drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23 #include "ecore_sp_commands.h"
  24 #include "ecore_cxt.h"
  25
  26 #define CHIP_MCP_RESP_ITER_US 10
  27 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  28
  29 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  30 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  31
  32 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  33         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  34                  _val)
  35
  36 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  37         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  38
  39 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  40         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  41                      OFFSETOF(struct public_drv_mb, _field), _val)
  42
  43 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  44         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  45                      OFFSETOF(struct public_drv_mb, _field))
  46
  47 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  48         DRV_ID_PDA_COMP_VER_OFFSET)
  49
  50 #define MCP_BYTES_PER_MBIT_OFFSET 17
  51
  52 #ifndef ASIC_ONLY
  53 static int loaded;
  54 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  55 #endif
  56
  57 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  58 {
  59         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  60                 return false;
  61         return true;
  62 }
  63
  64 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  65 {
  66         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  67                                         PUBLIC_PORT);
  68         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  69
  70         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  71                                                    MFW_PORT(p_hwfn));
  72         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  73                    "port_addr = 0x%x, port_id 0x%02x\n",
  74                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  75 }
  76
  77 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  78 {
  79         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  80         OSAL_BE32 tmp;
  81         u32 i;
  82
  83 #ifndef ASIC_ONLY
  84         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  85                 return;
  86 #endif
  87
  88         if (!p_hwfn->mcp_info->public_base)
  89                 return;
  90
  91         for (i = 0; i < length; i++) {
  92                 tmp = ecore_rd(p_hwfn, p_ptt,
  93                                p_hwfn->mcp_info->mfw_mb_addr +
  94                                (i << 2) + sizeof(u32));
  95
  96                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  97                     OSAL_BE32_TO_CPU(tmp);
  98         }
  99 }
 100
 101 struct ecore_mcp_cmd_elem {
 102         osal_list_entry_t list;
 103         struct ecore_mcp_mb_params *p_mb_params;
 104         u16 expected_seq_num;
 105         bool b_is_completed;
 106 };
 107
 108 /* Must be called while cmd_lock is acquired */
 109 static struct ecore_mcp_cmd_elem *
 110 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 111                        struct ecore_mcp_mb_params *p_mb_params,
 112                        u16 expected_seq_num)
 113 {
 114         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 115
 116         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 117                                  sizeof(*p_cmd_elem));
 118         if (!p_cmd_elem) {
 119                 DP_NOTICE(p_hwfn, false,
 120                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 121                 goto out;
 122         }
 123
 124         p_cmd_elem->p_mb_params = p_mb_params;
 125         p_cmd_elem->expected_seq_num = expected_seq_num;
 126         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 127 out:
 128         return p_cmd_elem;
 129 }
 130
 131 /* Must be called while cmd_lock is acquired */
 132 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 133                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 134 {
 135         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 136         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 137 }
 138
 139 /* Must be called while cmd_lock is acquired */
 140 static struct ecore_mcp_cmd_elem *
 141 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 142 {
 143         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 144
 145         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 146                                  struct ecore_mcp_cmd_elem) {
 147                 if (p_cmd_elem->expected_seq_num == seq_num)
 148                         return p_cmd_elem;
 149         }
 150
 151         return OSAL_NULL;
 152 }
 153
 154 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 155 {
 156         if (p_hwfn->mcp_info) {
 157                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 158
 159                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 160                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 161                                               &p_hwfn->mcp_info->cmd_list, list,
 162                                               struct ecore_mcp_cmd_elem) {
 163                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 164                 }
 165                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 166
 167                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 168                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 169 #ifdef CONFIG_ECORE_LOCK_ALLOC
 170                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 171                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 172 #endif
 173         }
 174
 175         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 176
 177         return ECORE_SUCCESS;
 178 }
 179
 180 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 181                                                    struct ecore_ptt *p_ptt)
 182 {
 183         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 184         u32 drv_mb_offsize, mfw_mb_offsize;
 185         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 186
 187 #ifndef ASIC_ONLY
 188         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 189                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 190                 p_info->public_base = 0;
 191                 return ECORE_INVAL;
 192         }
 193 #endif
 194
 195         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 196         if (!p_info->public_base)
 197                 return ECORE_INVAL;
 198
 199         p_info->public_base |= GRCBASE_MCP;
 200
 201         /* Calculate the driver and MFW mailbox address */
 202         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 203                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 204                                                        PUBLIC_DRV_MB));
 205         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 207                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 208                    " mcp_pf_id = 0x%x\n",
 209                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 210
 211         /* Set the MFW MB address */
 212         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 213                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 214                                                        PUBLIC_MFW_MB));
 215         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 216         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 217                                                p_info->mfw_mb_addr);
 218
 219         /* Get the current driver mailbox sequence before sending
 220          * the first command
 221          */
 222         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 223             DRV_MSG_SEQ_NUMBER_MASK;
 224
 225         /* Get current FW pulse sequence */
 226         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 227             DRV_PULSE_SEQ_MASK;
 228
 229         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 230
 231         return ECORE_SUCCESS;
 232 }
 233
 234 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 235                                         struct ecore_ptt *p_ptt)
 236 {
 237         struct ecore_mcp_info *p_info;
 238         u32 size;
 239
 240         /* Allocate mcp_info structure */
 241         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 242                                        sizeof(*p_hwfn->mcp_info));
 243         if (!p_hwfn->mcp_info)
 244                 goto err;
 245         p_info = p_hwfn->mcp_info;
 246
 247         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 248                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 249                 /* Do not free mcp_info here, since public_base indicate that
 250                  * the MCP is not initialized
 251                  */
 252                 return ECORE_SUCCESS;
 253         }
 254
 255         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 256         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 257         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 258         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 259                 goto err;
 260
 261         /* Initialize the MFW spinlocks */
 262 #ifdef CONFIG_ECORE_LOCK_ALLOC
 263         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 264         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 265 #endif
 266         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 267         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 268
 269         OSAL_LIST_INIT(&p_info->cmd_list);
 270
 271         return ECORE_SUCCESS;
 272
 273 err:
 274         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 275         ecore_mcp_free(p_hwfn);
 276         return ECORE_NOMEM;
 277 }
 278
 279 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 280                                      struct ecore_ptt *p_ptt)
 281 {
 282         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 283
 284         /* Use MCP history register to check if MCP reset occurred between init
 285          * time and now.
 286          */
 287         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 288                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 289                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 290                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 291
 292                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 293                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 294         }
 295 }
 296
 297 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 298                                      struct ecore_ptt *p_ptt)
 299 {
 300         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 301         enum _ecore_status_t rc = ECORE_SUCCESS;
 302
 303 #ifndef ASIC_ONLY
 304         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 305                 delay = EMUL_MCP_RESP_ITER_US;
 306 #endif
 307
 308         if (p_hwfn->mcp_info->b_block_cmd) {
 309                 DP_NOTICE(p_hwfn, false,
 310                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 311                 return ECORE_ABORTED;
 312         }
 313
 314         /* Ensure that only a single thread is accessing the mailbox */
 315         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 316
 317         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 318
 319         /* Set drv command along with the updated sequence */
 320         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 321         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 322         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 323
 324         do {
 325                 /* Wait for MFW response */
 326                 OSAL_UDELAY(delay);
 327                 /* Give the FW up to 500 second (50*1000*10usec) */
 328         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 329                                                 MISCS_REG_GENERIC_POR_0)) &&
 330                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 331
 332         if (org_mcp_reset_seq !=
 333             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 334                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 335                            "MCP was reset after %d usec\n", cnt * delay);
 336         } else {
 337                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 338                 rc = ECORE_AGAIN;
 339         }
 340
 341         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 342
 343         return rc;
 344 }
 345
 346 /* Must be called while cmd_lock is acquired */
 347 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 348 {
 349         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 350
 351         /* There is at most one pending command at a certain time, and if it
 352          * exists - it is placed at the HEAD of the list.
 353          */
 354         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 355                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 356                                                    struct ecore_mcp_cmd_elem,
 357                                                    list);
 358                 return !p_cmd_elem->b_is_completed;
 359         }
 360
 361         return false;
 362 }
 363
 364 /* Must be called while cmd_lock is acquired */
 365 static enum _ecore_status_t
 366 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 367 {
 368         struct ecore_mcp_mb_params *p_mb_params;
 369         struct ecore_mcp_cmd_elem *p_cmd_elem;
 370         u32 mcp_resp;
 371         u16 seq_num;
 372
 373         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 374         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 375
 376         /* Return if no new non-handled response has been received */
 377         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 378                 return ECORE_AGAIN;
 379
 380         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 381         if (!p_cmd_elem) {
 382                 DP_ERR(p_hwfn,
 383                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 384                        seq_num);
 385                 return ECORE_UNKNOWN_ERROR;
 386         }
 387
 388         p_mb_params = p_cmd_elem->p_mb_params;
 389
 390         /* Get the MFW response along with the sequence number */
 391         p_mb_params->mcp_resp = mcp_resp;
 392
 393         /* Get the MFW param */
 394         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 395
 396         /* Get the union data */
 397         if (p_mb_params->p_data_dst != OSAL_NULL &&
 398             p_mb_params->data_dst_size) {
 399                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 400                                       OFFSETOF(struct public_drv_mb,
 401                                                union_data);
 402                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 403                                   union_data_addr, p_mb_params->data_dst_size);
 404         }
 405
 406         p_cmd_elem->b_is_completed = true;
 407
 408         return ECORE_SUCCESS;
 409 }
 410
 411 /* Must be called while cmd_lock is acquired */
 412 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 413                                       struct ecore_ptt *p_ptt,
 414                                       struct ecore_mcp_mb_params *p_mb_params,
 415                                       u16 seq_num)
 416 {
 417         union drv_union_data union_data;
 418         u32 union_data_addr;
 419
 420         /* Set the union data */
 421         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 422                           OFFSETOF(struct public_drv_mb, union_data);
 423         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 424         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 425                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 426                             p_mb_params->data_src_size);
 427         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 428                         sizeof(union_data));
 429
 430         /* Set the drv param */
 431         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 432
 433         /* Set the drv command along with the sequence number */
 434         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 435
 436         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 437                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 438                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 439 }
 440
 441 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 442                                        bool block_cmd)
 443 {
 444         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 445
 446         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 447                 block_cmd ? "Block" : "Unblock");
 448 }
 449
 450 static enum _ecore_status_t
 451 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 452                          struct ecore_mcp_mb_params *p_mb_params,
 453                          u32 max_retries, u32 delay)
 454 {
 455         struct ecore_mcp_cmd_elem *p_cmd_elem;
 456         u32 cnt = 0;
 457         u16 seq_num;
 458         enum _ecore_status_t rc = ECORE_SUCCESS;
 459
 460         /* Wait until the mailbox is non-occupied */
 461         do {
 462                 /* Exit the loop if there is no pending command, or if the
 463                  * pending command is completed during this iteration.
 464                  * The spinlock stays locked until the command is sent.
 465                  */
 466
 467                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 468
 469                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 470                         break;
 471
 472                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 473                 if (rc == ECORE_SUCCESS)
 474                         break;
 475                 else if (rc != ECORE_AGAIN)
 476                         goto err;
 477
 478                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 479                 OSAL_UDELAY(delay);
 480         } while (++cnt < max_retries);
 481
 482         if (cnt >= max_retries) {
 483                 DP_NOTICE(p_hwfn, false,
 484                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 485                           p_mb_params->cmd, p_mb_params->param);
 486                 return ECORE_AGAIN;
 487         }
 488
 489         /* Send the mailbox command */
 490         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 491         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 492         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 493         if (!p_cmd_elem) {
 494                 rc = ECORE_NOMEM;
 495                 goto err;
 496         }
 497
 498         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 499         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 500
 501         /* Wait for the MFW response */
 502         do {
 503                 /* Exit the loop if the command is already completed, or if the
 504                  * command is completed during this iteration.
 505                  * The spinlock stays locked until the list element is removed.
 506                  */
 507
 508                 OSAL_UDELAY(delay);
 509                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 510
 511                 if (p_cmd_elem->b_is_completed)
 512                         break;
 513
 514                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 515                 if (rc == ECORE_SUCCESS)
 516                         break;
 517                 else if (rc != ECORE_AGAIN)
 518                         goto err;
 519
 520                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 521         } while (++cnt < max_retries);
 522
 523         if (cnt >= max_retries) {
 524                 DP_NOTICE(p_hwfn, false,
 525                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 526                           p_mb_params->cmd, p_mb_params->param);
 527
 528                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 529                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 530                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 531
 532                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 533                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 534                 return ECORE_AGAIN;
 535         }
 536
 537         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 538         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 539
 540         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 541                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 542                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 543                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 544
 545         /* Clear the sequence number from the MFW response */
 546         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 547
 548         return ECORE_SUCCESS;
 549
 550 err:
 551         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 552         return rc;
 553 }
 554
 555 static enum _ecore_status_t
 556 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 557                         struct ecore_ptt *p_ptt,
 558                         struct ecore_mcp_mb_params *p_mb_params)
 559 {
 560         osal_size_t union_data_size = sizeof(union drv_union_data);
 561         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 562         u32 delay = CHIP_MCP_RESP_ITER_US;
 563
 564 #ifndef ASIC_ONLY
 565         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 566                 delay = EMUL_MCP_RESP_ITER_US;
 567         /* There is a built-in delay of 100usec in each MFW response read */
 568         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 569                 max_retries /= 10;
 570 #endif
 571
 572         /* MCP not initialized */
 573         if (!ecore_mcp_is_init(p_hwfn)) {
 574                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 575                 return ECORE_BUSY;
 576         }
 577
 578         if (p_mb_params->data_src_size > union_data_size ||
 579             p_mb_params->data_dst_size > union_data_size) {
 580                 DP_ERR(p_hwfn,
 581                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 582                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 583                        union_data_size);
 584                 return ECORE_INVAL;
 585         }
 586
 587         if (p_hwfn->mcp_info->b_block_cmd) {
 588                 DP_NOTICE(p_hwfn, false,
 589                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 590                           p_mb_params->cmd, p_mb_params->param);
 591                 return ECORE_ABORTED;
 592         }
 593
 594         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 595                                         delay);
 596 }
 597
 598 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 599                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 600                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 601 {
 602         struct ecore_mcp_mb_params mb_params;
 603         enum _ecore_status_t rc;
 604
 605 #ifndef ASIC_ONLY
 606         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 607                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 608                         loaded--;
 609                         loaded_port[p_hwfn->port_id]--;
 610                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 611                                    loaded);
 612                 }
 613                 return ECORE_SUCCESS;
 614         }
 615 #endif
 616
 617         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 618         mb_params.cmd = cmd;
 619         mb_params.param = param;
 620         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 621         if (rc != ECORE_SUCCESS)
 622                 return rc;
 623
 624         *o_mcp_resp = mb_params.mcp_resp;
 625         *o_mcp_param = mb_params.mcp_param;
 626
 627         return ECORE_SUCCESS;
 628 }
 629
 630 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 631                                           struct ecore_ptt *p_ptt,
 632                                           u32 cmd,
 633                                           u32 param,
 634                                           u32 *o_mcp_resp,
 635                                           u32 *o_mcp_param,
 636                                           u32 i_txn_size, u32 *i_buf)
 637 {
 638         struct ecore_mcp_mb_params mb_params;
 639         enum _ecore_status_t rc;
 640
 641         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 642         mb_params.cmd = cmd;
 643         mb_params.param = param;
 644         mb_params.p_data_src = i_buf;
 645         mb_params.data_src_size = (u8)i_txn_size;
 646         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 647         if (rc != ECORE_SUCCESS)
 648                 return rc;
 649
 650         *o_mcp_resp = mb_params.mcp_resp;
 651         *o_mcp_param = mb_params.mcp_param;
 652
 653         return ECORE_SUCCESS;
 654 }
 655
 656 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 657                                           struct ecore_ptt *p_ptt,
 658                                           u32 cmd,
 659                                           u32 param,
 660                                           u32 *o_mcp_resp,
 661                                           u32 *o_mcp_param,
 662                                           u32 *o_txn_size, u32 *o_buf)
 663 {
 664         struct ecore_mcp_mb_params mb_params;
 665         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 666         enum _ecore_status_t rc;
 667
 668         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 669         mb_params.cmd = cmd;
 670         mb_params.param = param;
 671         mb_params.p_data_dst = raw_data;
 672
 673         /* Use the maximal value since the actual one is part of the response */
 674         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 675
 676         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 677         if (rc != ECORE_SUCCESS)
 678                 return rc;
 679
 680         *o_mcp_resp = mb_params.mcp_resp;
 681         *o_mcp_param = mb_params.mcp_param;
 682
 683         *o_txn_size = *o_mcp_param;
 684         /* @DPDK */
 685         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 686
 687         return ECORE_SUCCESS;
 688 }
 689
 690 #ifndef ASIC_ONLY
 691 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 692                                     u32 *p_load_code)
 693 {
 694         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 695
 696         if (!loaded)
 697                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 698         else if (!loaded_port[p_hwfn->port_id])
 699                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 700         else
 701                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 702
 703         /* On CMT, always tell that it's engine */
 704         if (ECORE_IS_CMT(p_hwfn->p_dev))
 705                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 706
 707         *p_load_code = load_phase;
 708         loaded++;
 709         loaded_port[p_hwfn->port_id]++;
 710
 711         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 712                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 713                    *p_load_code, loaded, p_hwfn->port_id,
 714                    loaded_port[p_hwfn->port_id]);
 715 }
 716 #endif
 717
 718 static bool
 719 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 720                          enum ecore_override_force_load override_force_load)
 721 {
 722         bool can_force_load = false;
 723
 724         switch (override_force_load) {
 725         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 726                 can_force_load = true;
 727                 break;
 728         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 729                 can_force_load = false;
 730                 break;
 731         default:
 732                 can_force_load = (drv_role == DRV_ROLE_OS &&
 733                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 734                                  (drv_role == DRV_ROLE_KDUMP &&
 735                                   exist_drv_role == DRV_ROLE_OS);
 736                 break;
 737         }
 738
 739         return can_force_load;
 740 }
 741
 742 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 743                                                       struct ecore_ptt *p_ptt)
 744 {
 745         u32 resp = 0, param = 0;
 746         enum _ecore_status_t rc;
 747
 748         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 749                            &resp, &param);
 750         if (rc != ECORE_SUCCESS)
 751                 DP_NOTICE(p_hwfn, false,
 752                           "Failed to send cancel load request, rc = %d\n", rc);
 753
 754         return rc;
 755 }
 756
 757 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 758 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 759 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 760 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 761 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 762 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 763 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 764
 765 static u32 ecore_get_config_bitmap(void)
 766 {
 767         u32 config_bitmap = 0x0;
 768
 769 #ifdef CONFIG_ECORE_L2
 770         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 771 #endif
 772 #ifdef CONFIG_ECORE_SRIOV
 773         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 774 #endif
 775 #ifdef CONFIG_ECORE_ROCE
 776         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 777 #endif
 778 #ifdef CONFIG_ECORE_IWARP
 779         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 780 #endif
 781 #ifdef CONFIG_ECORE_FCOE
 782         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 783 #endif
 784 #ifdef CONFIG_ECORE_ISCSI
 785         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 786 #endif
 787 #ifdef CONFIG_ECORE_LL2
 788         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 789 #endif
 790
 791         return config_bitmap;
 792 }
 793
 794 struct ecore_load_req_in_params {
 795         u8 hsi_ver;
 796 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 797 #define ECORE_LOAD_REQ_HSI_VER_1        1
 798         u32 drv_ver_0;
 799         u32 drv_ver_1;
 800         u32 fw_ver;
 801         u8 drv_role;
 802         u8 timeout_val;
 803         u8 force_cmd;
 804         bool avoid_eng_reset;
 805 };
 806
 807 struct ecore_load_req_out_params {
 808         u32 load_code;
 809         u32 exist_drv_ver_0;
 810         u32 exist_drv_ver_1;
 811         u32 exist_fw_ver;
 812         u8 exist_drv_role;
 813         u8 mfw_hsi_ver;
 814         bool drv_exists;
 815 };
 816
 817 static enum _ecore_status_t
 818 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 819                      struct ecore_load_req_in_params *p_in_params,
 820                      struct ecore_load_req_out_params *p_out_params)
 821 {
 822         struct ecore_mcp_mb_params mb_params;
 823         struct load_req_stc load_req;
 824         struct load_rsp_stc load_rsp;
 825         u32 hsi_ver;
 826         enum _ecore_status_t rc;
 827
 828         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 829         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 830         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 831         load_req.fw_ver = p_in_params->fw_ver;
 832         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 833         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 834                       p_in_params->timeout_val);
 835         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 836         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 837                       p_in_params->avoid_eng_reset);
 838
 839         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 840                   DRV_ID_MCP_HSI_VER_CURRENT :
 841                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 842
 843         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 844         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 845         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 846         mb_params.p_data_src = &load_req;
 847         mb_params.data_src_size = sizeof(load_req);
 848         mb_params.p_data_dst = &load_rsp;
 849         mb_params.data_dst_size = sizeof(load_rsp);
 850
 851         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 852                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 853                    mb_params.param,
 854                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 855                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 856                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 857                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 858
 859         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 860                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 861                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 862                            load_req.drv_ver_0, load_req.drv_ver_1,
 863                            load_req.fw_ver, load_req.misc0,
 864                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 865                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 866                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 867                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 868
 869         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 870         if (rc != ECORE_SUCCESS) {
 871                 DP_NOTICE(p_hwfn, false,
 872                           "Failed to send load request, rc = %d\n", rc);
 873                 return rc;
 874         }
 875
 876         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 877                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 878         p_out_params->load_code = mb_params.mcp_resp;
 879
 880         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 881             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 882                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 883                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 884                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 885                            load_rsp.fw_ver, load_rsp.misc0,
 886                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 887                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 888                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 889
 890                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 891                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 892                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 893                 p_out_params->exist_drv_role =
 894                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 895                 p_out_params->mfw_hsi_ver =
 896                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 897                 p_out_params->drv_exists =
 898                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 899                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 900         }
 901
 902         return ECORE_SUCCESS;
 903 }
 904
 905 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 906                                    u8 *p_mfw_drv_role)
 907 {
 908         switch (drv_role) {
 909         case ECORE_DRV_ROLE_OS:
 910                 *p_mfw_drv_role = DRV_ROLE_OS;
 911                 break;
 912         case ECORE_DRV_ROLE_KDUMP:
 913                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 914                 break;
 915         }
 916 }
 917
 918 enum ecore_load_req_force {
 919         ECORE_LOAD_REQ_FORCE_NONE,
 920         ECORE_LOAD_REQ_FORCE_PF,
 921         ECORE_LOAD_REQ_FORCE_ALL,
 922 };
 923
 924 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 925                                     u8 *p_mfw_force_cmd)
 926 {
 927         switch (force_cmd) {
 928         case ECORE_LOAD_REQ_FORCE_NONE:
 929                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 930                 break;
 931         case ECORE_LOAD_REQ_FORCE_PF:
 932                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 933                 break;
 934         case ECORE_LOAD_REQ_FORCE_ALL:
 935                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 936                 break;
 937         }
 938 }
 939
 940 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 941                                         struct ecore_ptt *p_ptt,
 942                                         struct ecore_load_req_params *p_params)
 943 {
 944         struct ecore_load_req_out_params out_params;
 945         struct ecore_load_req_in_params in_params;
 946         u8 mfw_drv_role = 0, mfw_force_cmd;
 947         enum _ecore_status_t rc;
 948
 949 #ifndef ASIC_ONLY
 950         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 951                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 952                 return ECORE_SUCCESS;
 953         }
 954 #endif
 955
 956         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 957         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 958         in_params.drv_ver_0 = ECORE_VERSION;
 959         in_params.drv_ver_1 = ecore_get_config_bitmap();
 960         in_params.fw_ver = STORM_FW_VERSION;
 961         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 962         in_params.drv_role = mfw_drv_role;
 963         in_params.timeout_val = p_params->timeout_val;
 964         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 965         in_params.force_cmd = mfw_force_cmd;
 966         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 967
 968         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 969         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 970         if (rc != ECORE_SUCCESS)
 971                 return rc;
 972
 973         /* First handle cases where another load request should/might be sent:
 974          * - MFW expects the old interface [HSI version = 1]
 975          * - MFW responds that a force load request is required
 976          */
 977         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 978                 DP_INFO(p_hwfn,
 979                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 980
 981                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 982                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 983                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 984                                           &out_params);
 985                 if (rc != ECORE_SUCCESS)
 986                         return rc;
 987         } else if (out_params.load_code ==
 988                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 989                 if (ecore_mcp_can_force_load(in_params.drv_role,
 990                                              out_params.exist_drv_role,
 991                                              p_params->override_force_load)) {
 992                         DP_INFO(p_hwfn,
 993                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 994                                 in_params.drv_role, in_params.fw_ver,
 995                                 in_params.drv_ver_0, in_params.drv_ver_1,
 996                                 out_params.exist_drv_role,
 997                                 out_params.exist_fw_ver,
 998                                 out_params.exist_drv_ver_0,
 999                                 out_params.exist_drv_ver_1);
1000
1001                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1002                                                 &mfw_force_cmd);
1003
1004                         in_params.force_cmd = mfw_force_cmd;
1005                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1006                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1007                                                   &out_params);
1008                         if (rc != ECORE_SUCCESS)
1009                                 return rc;
1010                 } else {
1011                         DP_NOTICE(p_hwfn, false,
1012                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1013                                   in_params.drv_role, in_params.fw_ver,
1014                                   in_params.drv_ver_0, in_params.drv_ver_1,
1015                                   out_params.exist_drv_role,
1016                                   out_params.exist_fw_ver,
1017                                   out_params.exist_drv_ver_0,
1018                                   out_params.exist_drv_ver_1);
1019
1020                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1021                         return ECORE_BUSY;
1022                 }
1023         }
1024
1025         /* Now handle the other types of responses.
1026          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1027          * expected here after the additional revised load requests were sent.
1028          */
1029         switch (out_params.load_code) {
1030         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1031         case FW_MSG_CODE_DRV_LOAD_PORT:
1032         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1033                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1034                     out_params.drv_exists) {
1035                         /* The role and fw/driver version match, but the PF is
1036                          * already loaded and has not been unloaded gracefully.
1037                          * This is unexpected since a quasi-FLR request was
1038                          * previously sent as part of ecore_hw_prepare().
1039                          */
1040                         DP_NOTICE(p_hwfn, false,
1041                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1042                         return ECORE_INVAL;
1043                 }
1044                 break;
1045         default:
1046                 DP_NOTICE(p_hwfn, false,
1047                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1048                           out_params.load_code);
1049                 return ECORE_BUSY;
1050         }
1051
1052         p_params->load_code = out_params.load_code;
1053
1054         return ECORE_SUCCESS;
1055 }
1056
1057 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1058                                          struct ecore_ptt *p_ptt)
1059 {
1060         u32 resp = 0, param = 0;
1061         enum _ecore_status_t rc;
1062
1063         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1064                            &param);
1065         if (rc != ECORE_SUCCESS) {
1066                 DP_NOTICE(p_hwfn, false,
1067                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1068                 return rc;
1069         }
1070
1071 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)
1072
1073         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1074         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1075                 DP_NOTICE(p_hwfn, false,
1076                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1077
1078         return ECORE_SUCCESS;
1079 }
1080
1081 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1082                                           struct ecore_ptt *p_ptt)
1083 {
1084         u32 wol_param, mcp_resp, mcp_param;
1085
1086         /* @DPDK */
1087         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1088
1089         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1090                              &mcp_resp, &mcp_param);
1091 }
1092
1093 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1094                                            struct ecore_ptt *p_ptt)
1095 {
1096         struct ecore_mcp_mb_params mb_params;
1097         struct mcp_mac wol_mac;
1098
1099         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1100         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1101
1102         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1103 }
1104
1105 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1106                                     struct ecore_ptt *p_ptt)
1107 {
1108         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1109                                         PUBLIC_PATH);
1110         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1111         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1112                                      ECORE_PATH_ID(p_hwfn));
1113         u32 disabled_vfs[VF_MAX_STATIC / 32];
1114         int i;
1115
1116         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1117                    "Reading Disabled VF information from [offset %08x],"
1118                    " path_addr %08x\n",
1119                    mfw_path_offsize, path_addr);
1120
1121         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1122                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1123                                            path_addr +
1124                                            OFFSETOF(struct public_path,
1125                                                     mcp_vf_disabled) +
1126                                            sizeof(u32) * i);
1127                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1128                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1129                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1130         }
1131
1132         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1133                 OSAL_VF_FLR_UPDATE(p_hwfn);
1134 }
1135
1136 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1137                                           struct ecore_ptt *p_ptt,
1138                                           u32 *vfs_to_ack)
1139 {
1140         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1141                                         PUBLIC_FUNC);
1142         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1143         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1144                                      MCP_PF_ID(p_hwfn));
1145         struct ecore_mcp_mb_params mb_params;
1146         enum _ecore_status_t rc;
1147         int i;
1148
1149         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1150                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1151                            "Acking VFs [%08x,...,%08x] - %08x\n",
1152                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1153
1154         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1155         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1156         mb_params.p_data_src = vfs_to_ack;
1157         mb_params.data_src_size = VF_MAX_STATIC / 8;
1158         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1159                                      &mb_params);
1160         if (rc != ECORE_SUCCESS) {
1161                 DP_NOTICE(p_hwfn, false,
1162                           "Failed to pass ACK for VF flr to MFW\n");
1163                 return ECORE_TIMEOUT;
1164         }
1165
1166         /* TMP - clear the ACK bits; should be done by MFW */
1167         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1168                 ecore_wr(p_hwfn, p_ptt,
1169                          func_addr +
1170                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1171                          i * sizeof(u32), 0);
1172
1173         return rc;
1174 }
1175
1176 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1177                                                 struct ecore_ptt *p_ptt)
1178 {
1179         u32 transceiver_state;
1180
1181         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1182                                      p_hwfn->mcp_info->port_addr +
1183                                      OFFSETOF(struct public_port,
1184                                               transceiver_data));
1185
1186         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1187                    "Received transceiver state update [0x%08x] from mfw"
1188                    " [Addr 0x%x]\n",
1189                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1190                                             OFFSETOF(struct public_port,
1191                                                      transceiver_data)));
1192
1193         transceiver_state = GET_MFW_FIELD(transceiver_state,
1194                                           ETH_TRANSCEIVER_STATE);
1195
1196         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1197                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1198         else
1199                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1200 }
1201
1202 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1203                                       struct ecore_ptt *p_ptt,
1204                                       struct ecore_mcp_link_state *p_link)
1205 {
1206         u32 eee_status, val;
1207
1208         p_link->eee_adv_caps = 0;
1209         p_link->eee_lp_adv_caps = 0;
1210         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1211                                      OFFSETOF(struct public_port, eee_status));
1212         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1213         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1214         if (val & EEE_1G_ADV)
1215                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1216         if (val & EEE_10G_ADV)
1217                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1218         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1219         if (val & EEE_1G_ADV)
1220                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1221         if (val & EEE_10G_ADV)
1222                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1223 }
1224
1225 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1226                                          struct ecore_ptt *p_ptt,
1227                                          bool b_reset)
1228 {
1229         struct ecore_mcp_link_state *p_link;
1230         u8 max_bw, min_bw;
1231         u32 status = 0;
1232
1233         /* Prevent SW/attentions from doing this at the same time */
1234         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1235
1236         p_link = &p_hwfn->mcp_info->link_output;
1237         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1238         if (!b_reset) {
1239                 status = ecore_rd(p_hwfn, p_ptt,
1240                                   p_hwfn->mcp_info->port_addr +
1241                                   OFFSETOF(struct public_port, link_status));
1242                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1243                            "Received link update [0x%08x] from mfw"
1244                            " [Addr 0x%x]\n",
1245                            status, (u32)(p_hwfn->mcp_info->port_addr +
1246                                           OFFSETOF(struct public_port,
1247                                                    link_status)));
1248         } else {
1249                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1250                            "Resetting link indications\n");
1251                 goto out;
1252         }
1253
1254         if (p_hwfn->b_drv_link_init)
1255                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1256         else
1257                 p_link->link_up = false;
1258
1259         p_link->full_duplex = true;
1260         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1261         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1262                 p_link->speed = 100000;
1263                 break;
1264         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1265                 p_link->speed = 50000;
1266                 break;
1267         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1268                 p_link->speed = 40000;
1269                 break;
1270         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1271                 p_link->speed = 25000;
1272                 break;
1273         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1274                 p_link->speed = 20000;
1275                 break;
1276         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1277                 p_link->speed = 10000;
1278                 break;
1279         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1280                 p_link->full_duplex = false;
1281                 /* Fall-through */
1282         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1283                 p_link->speed = 1000;
1284                 break;
1285         default:
1286                 p_link->speed = 0;
1287         }
1288
1289         /* We never store total line speed as p_link->speed is
1290          * again changes according to bandwidth allocation.
1291          */
1292         if (p_link->link_up && p_link->speed)
1293                 p_link->line_speed = p_link->speed;
1294         else
1295                 p_link->line_speed = 0;
1296
1297         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1298         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1299
1300         /* Max bandwidth configuration */
1301         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1302                                            p_link, max_bw);
1303
1304         /* Mintz bandwidth configuration */
1305         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1306                                            p_link, min_bw);
1307         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1308                                               p_link->min_pf_rate);
1309
1310         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1311         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1312         p_link->parallel_detection = !!(status &
1313                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1314         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1315
1316         p_link->partner_adv_speed |=
1317             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1318             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1319         p_link->partner_adv_speed |=
1320             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1321             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1322         p_link->partner_adv_speed |=
1323             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1324             ECORE_LINK_PARTNER_SPEED_10G : 0;
1325         p_link->partner_adv_speed |=
1326             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1327             ECORE_LINK_PARTNER_SPEED_20G : 0;
1328         p_link->partner_adv_speed |=
1329             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1330             ECORE_LINK_PARTNER_SPEED_25G : 0;
1331         p_link->partner_adv_speed |=
1332             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1333             ECORE_LINK_PARTNER_SPEED_40G : 0;
1334         p_link->partner_adv_speed |=
1335             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1336             ECORE_LINK_PARTNER_SPEED_50G : 0;
1337         p_link->partner_adv_speed |=
1338             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1339             ECORE_LINK_PARTNER_SPEED_100G : 0;
1340
1341         p_link->partner_tx_flow_ctrl_en =
1342             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1343         p_link->partner_rx_flow_ctrl_en =
1344             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1345
1346         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1347         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1348                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1349                 break;
1350         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1351                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1352                 break;
1353         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1354                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1355                 break;
1356         default:
1357                 p_link->partner_adv_pause = 0;
1358         }
1359
1360         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1361
1362         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1363                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1364
1365         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1366 out:
1367         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1368 }
1369
1370 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1371                                         struct ecore_ptt *p_ptt, bool b_up)
1372 {
1373         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1374         struct ecore_mcp_mb_params mb_params;
1375         struct eth_phy_cfg phy_cfg;
1376         enum _ecore_status_t rc = ECORE_SUCCESS;
1377         u32 cmd;
1378
1379 #ifndef ASIC_ONLY
1380         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1381                 return ECORE_SUCCESS;
1382 #endif
1383
1384         /* Set the shmem configuration according to params */
1385         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1386         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1387         if (!params->speed.autoneg)
1388                 phy_cfg.speed = params->speed.forced_speed;
1389         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1390         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1391         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1392         phy_cfg.adv_speed = params->speed.advertised_speeds;
1393         phy_cfg.loopback_mode = params->loopback_mode;
1394
1395         /* There are MFWs that share this capability regardless of whether
1396          * this is feasible or not. And given that at the very least adv_caps
1397          * would be set internally by ecore, we want to make sure LFA would
1398          * still work.
1399          */
1400         if ((p_hwfn->mcp_info->capabilities &
1401              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1402             params->eee.enable) {
1403                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1404                 if (params->eee.tx_lpi_enable)
1405                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1406                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1407                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1408                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1409                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1410                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1411                                     EEE_TX_TIMER_USEC_OFFSET) &
1412                                         EEE_TX_TIMER_USEC_MASK;
1413         }
1414
1415         p_hwfn->b_drv_link_init = b_up;
1416
1417         if (b_up)
1418                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1419                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1420                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1421                            phy_cfg.loopback_mode);
1422         else
1423                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1424
1425         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1426         mb_params.cmd = cmd;
1427         mb_params.p_data_src = &phy_cfg;
1428         mb_params.data_src_size = sizeof(phy_cfg);
1429         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1430
1431         /* if mcp fails to respond we must abort */
1432         if (rc != ECORE_SUCCESS) {
1433                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1434                 return rc;
1435         }
1436
1437         /* Mimic link-change attention, done for several reasons:
1438          *  - On reset, there's no guarantee MFW would trigger
1439          *    an attention.
1440          *  - On initialization, older MFWs might not indicate link change
1441          *    during LFA, so we'll never get an UP indication.
1442          */
1443         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1444
1445         return ECORE_SUCCESS;
1446 }
1447
1448 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1449                                    struct ecore_ptt *p_ptt)
1450 {
1451         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1452
1453         /* TODO - Add support for VFs */
1454         if (IS_VF(p_hwfn->p_dev))
1455                 return ECORE_INVAL;
1456
1457         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1458                                                  PUBLIC_PATH);
1459         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1460         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1461
1462         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1463                                  path_addr +
1464                                  OFFSETOF(struct public_path, process_kill)) &
1465             PROCESS_KILL_COUNTER_MASK;
1466
1467         return proc_kill_cnt;
1468 }
1469
1470 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1471                                           struct ecore_ptt *p_ptt)
1472 {
1473         struct ecore_dev *p_dev = p_hwfn->p_dev;
1474         u32 proc_kill_cnt;
1475
1476         /* Prevent possible attentions/interrupts during the recovery handling
1477          * and till its load phase, during which they will be re-enabled.
1478          */
1479         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1480
1481         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1482
1483         /* The following operations should be done once, and thus in CMT mode
1484          * are carried out by only the first HW function.
1485          */
1486         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1487                 return;
1488
1489         if (p_dev->recov_in_prog) {
1490                 DP_NOTICE(p_hwfn, false,
1491                           "Ignoring the indication since a recovery"
1492                           " process is already in progress\n");
1493                 return;
1494         }
1495
1496         p_dev->recov_in_prog = true;
1497
1498         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1499         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1500
1501         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1502 }
1503
1504 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1505                                           struct ecore_ptt *p_ptt,
1506                                           enum MFW_DRV_MSG_TYPE type)
1507 {
1508         enum ecore_mcp_protocol_type stats_type;
1509         union ecore_mcp_protocol_stats stats;
1510         struct ecore_mcp_mb_params mb_params;
1511         u32 hsi_param;
1512         enum _ecore_status_t rc;
1513
1514         switch (type) {
1515         case MFW_DRV_MSG_GET_LAN_STATS:
1516                 stats_type = ECORE_MCP_LAN_STATS;
1517                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1518                 break;
1519         default:
1520                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1521                 return;
1522         }
1523
1524         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1525
1526         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1527         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1528         mb_params.param = hsi_param;
1529         mb_params.p_data_src = &stats;
1530         mb_params.data_src_size = sizeof(stats);
1531         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1532         if (rc != ECORE_SUCCESS)
1533                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1534 }
1535
1536 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1537                                     struct public_func *p_shmem_info)
1538 {
1539         struct ecore_mcp_function_info *p_info;
1540
1541         p_info = &p_hwfn->mcp_info->func_info;
1542
1543         /* TODO - bandwidth min/max should have valid values of 1-100,
1544          * as well as some indication that the feature is disabled.
1545          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1546          * limit and correct value to min `1' and max `100' if limit isn't in
1547          * range.
1548          */
1549         p_info->bandwidth_min = (p_shmem_info->config &
1550                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1551             FUNC_MF_CFG_MIN_BW_OFFSET;
1552         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1553                 DP_INFO(p_hwfn,
1554                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1555                         p_info->bandwidth_min);
1556                 p_info->bandwidth_min = 1;
1557         }
1558
1559         p_info->bandwidth_max = (p_shmem_info->config &
1560                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1561             FUNC_MF_CFG_MAX_BW_OFFSET;
1562         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1563                 DP_INFO(p_hwfn,
1564                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1565                         p_info->bandwidth_max);
1566                 p_info->bandwidth_max = 100;
1567         }
1568 }
1569
1570 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1571                                     struct ecore_ptt *p_ptt,
1572                                     struct public_func *p_data,
1573                                     int pfid)
1574 {
1575         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1576                                         PUBLIC_FUNC);
1577         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1578         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1579         u32 i, size;
1580
1581         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1582
1583         size = OSAL_MIN_T(u32, sizeof(*p_data),
1584                           SECTION_SIZE(mfw_path_offsize));
1585         for (i = 0; i < size / sizeof(u32); i++)
1586                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1587                                               func_addr + (i << 2));
1588
1589         return size;
1590 }
1591
1592 static void
1593 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1594 {
1595         struct ecore_mcp_function_info *p_info;
1596         struct public_func shmem_info;
1597         u32 resp = 0, param = 0;
1598
1599         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1600
1601         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1602
1603         p_info = &p_hwfn->mcp_info->func_info;
1604
1605         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1606
1607         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1608
1609         /* Acknowledge the MFW */
1610         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1611                       &param);
1612 }
1613
1614 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1615 {
1616         /* A single notification should be sent to upper driver in CMT mode */
1617         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1618                 return;
1619
1620         DP_NOTICE(p_hwfn, false,
1621                   "Fan failure was detected on the network interface card"
1622                   " and it's going to be shut down.\n");
1623
1624         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1625 }
1626
1627 struct ecore_mdump_cmd_params {
1628         u32 cmd;
1629         void *p_data_src;
1630         u8 data_src_size;
1631         void *p_data_dst;
1632         u8 data_dst_size;
1633         u32 mcp_resp;
1634 };
1635
1636 static enum _ecore_status_t
1637 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1638                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1639 {
1640         struct ecore_mcp_mb_params mb_params;
1641         enum _ecore_status_t rc;
1642
1643         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1644         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1645         mb_params.param = p_mdump_cmd_params->cmd;
1646         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1647         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1648         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1649         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1650         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1651         if (rc != ECORE_SUCCESS)
1652                 return rc;
1653
1654         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1655
1656         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1657                 DP_INFO(p_hwfn,
1658                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1659                         p_mdump_cmd_params->cmd);
1660                 rc = ECORE_NOTIMPL;
1661         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1662                 DP_INFO(p_hwfn,
1663                         "The mdump command is not supported by the MFW\n");
1664                 rc = ECORE_NOTIMPL;
1665         }
1666
1667         return rc;
1668 }
1669
1670 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1671                                                 struct ecore_ptt *p_ptt)
1672 {
1673         struct ecore_mdump_cmd_params mdump_cmd_params;
1674
1675         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1676         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1677
1678         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1679 }
1680
1681 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1682                                                 struct ecore_ptt *p_ptt,
1683                                                 u32 epoch)
1684 {
1685         struct ecore_mdump_cmd_params mdump_cmd_params;
1686
1687         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1688         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1689         mdump_cmd_params.p_data_src = &epoch;
1690         mdump_cmd_params.data_src_size = sizeof(epoch);
1691
1692         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1693 }
1694
1695 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1696                                              struct ecore_ptt *p_ptt)
1697 {
1698         struct ecore_mdump_cmd_params mdump_cmd_params;
1699
1700         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1701         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1702
1703         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1704 }
1705
1706 static enum _ecore_status_t
1707 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1708                            struct mdump_config_stc *p_mdump_config)
1709 {
1710         struct ecore_mdump_cmd_params mdump_cmd_params;
1711         enum _ecore_status_t rc;
1712
1713         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1714         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1715         mdump_cmd_params.p_data_dst = p_mdump_config;
1716         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1717
1718         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1719         if (rc != ECORE_SUCCESS)
1720                 return rc;
1721
1722         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1723                 DP_INFO(p_hwfn,
1724                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1725                         mdump_cmd_params.mcp_resp);
1726                 rc = ECORE_UNKNOWN_ERROR;
1727         }
1728
1729         return rc;
1730 }
1731
1732 enum _ecore_status_t
1733 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1734                          struct ecore_mdump_info *p_mdump_info)
1735 {
1736         u32 addr, global_offsize, global_addr;
1737         struct mdump_config_stc mdump_config;
1738         enum _ecore_status_t rc;
1739
1740         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1741
1742         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1743                                     PUBLIC_GLOBAL);
1744         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1745         global_addr = SECTION_ADDR(global_offsize, 0);
1746         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1747                                         global_addr +
1748                                         OFFSETOF(struct public_global,
1749                                                  mdump_reason));
1750
1751         if (p_mdump_info->reason) {
1752                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1753                 if (rc != ECORE_SUCCESS)
1754                         return rc;
1755
1756                 p_mdump_info->version = mdump_config.version;
1757                 p_mdump_info->config = mdump_config.config;
1758                 p_mdump_info->epoch = mdump_config.epoc;
1759                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1760                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1761
1762                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1763                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1764                            p_mdump_info->reason, p_mdump_info->version,
1765                            p_mdump_info->config, p_mdump_info->epoch,
1766                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1767         } else {
1768                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1769                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1770         }
1771
1772         return ECORE_SUCCESS;
1773 }
1774
1775 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1776                                                 struct ecore_ptt *p_ptt)
1777 {
1778         struct ecore_mdump_cmd_params mdump_cmd_params;
1779
1780         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1781         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1782
1783         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1784 }
1785
1786 enum _ecore_status_t
1787 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1788                            struct ecore_mdump_retain_data *p_mdump_retain)
1789 {
1790         struct ecore_mdump_cmd_params mdump_cmd_params;
1791         struct mdump_retain_data_stc mfw_mdump_retain;
1792         enum _ecore_status_t rc;
1793
1794         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1795         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1796         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1797         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1798
1799         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1800         if (rc != ECORE_SUCCESS)
1801                 return rc;
1802
1803         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1804                 DP_INFO(p_hwfn,
1805                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1806                         mdump_cmd_params.mcp_resp);
1807                 return ECORE_UNKNOWN_ERROR;
1808         }
1809
1810         p_mdump_retain->valid = mfw_mdump_retain.valid;
1811         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1812         p_mdump_retain->pf = mfw_mdump_retain.pf;
1813         p_mdump_retain->status = mfw_mdump_retain.status;
1814
1815         return ECORE_SUCCESS;
1816 }
1817
1818 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1819                                                 struct ecore_ptt *p_ptt)
1820 {
1821         struct ecore_mdump_cmd_params mdump_cmd_params;
1822
1823         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1824         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1825
1826         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1827 }
1828
1829 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1830                                             struct ecore_ptt *p_ptt)
1831 {
1832         struct ecore_mdump_retain_data mdump_retain;
1833         enum _ecore_status_t rc;
1834
1835         /* In CMT mode - no need for more than a single acknowledgment to the
1836          * MFW, and no more than a single notification to the upper driver.
1837          */
1838         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1839                 return;
1840
1841         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1842         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1843                 DP_NOTICE(p_hwfn, false,
1844                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1845                           mdump_retain.epoch, mdump_retain.pf,
1846                           mdump_retain.status);
1847         } else {
1848                 DP_NOTICE(p_hwfn, false,
1849                           "The MFW notified that a critical error occurred in the device\n");
1850         }
1851
1852         if (p_hwfn->p_dev->allow_mdump) {
1853                 DP_NOTICE(p_hwfn, false,
1854                           "Not acknowledging the notification to allow the MFW crash dump\n");
1855                 return;
1856         }
1857
1858         DP_NOTICE(p_hwfn, false,
1859                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1860         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1861         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1862 }
1863
1864 void
1865 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1866 {
1867         struct public_func shmem_info;
1868         u32 port_cfg, val;
1869
1870         if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1871                 return;
1872
1873         OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1874         port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1875                             OFFSETOF(struct public_port, oem_cfg_port));
1876         val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1877         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1878                 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type  %d\n",
1879                           val);
1880
1881         val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1882         if (val == OEM_CFG_SCHED_TYPE_ETS)
1883                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1884         else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1885                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1886         else
1887                 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1888                           val);
1889
1890         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1891                                  MCP_PF_ID(p_hwfn));
1892         val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1893         p_hwfn->ufp_info.tc = (u8)val;
1894         val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1895                             OEM_CFG_FUNC_HOST_PRI_CTRL);
1896         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1897                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1898         else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1899                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1900         else
1901                 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1902                           val);
1903
1904         DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1905                    "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1906                    p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1907                    p_hwfn->ufp_info.pri_type);
1908 }
1909
1910 static enum _ecore_status_t
1911 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1912 {
1913         ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
1914
1915         if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
1916                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1917                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1918
1919                 ecore_qm_reconf(p_hwfn, p_ptt);
1920         } else {
1921                 /* Merge UFP TC with the dcbx TC data */
1922                 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1923                                             ECORE_DCBX_OPERATIONAL_MIB);
1924         }
1925
1926         /* update storm FW with negotiation results */
1927         ecore_sp_pf_update_ufp(p_hwfn);
1928
1929         return ECORE_SUCCESS;
1930 }
1931
1932 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1933                                              struct ecore_ptt *p_ptt)
1934 {
1935         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1936         enum _ecore_status_t rc = ECORE_SUCCESS;
1937         bool found = false;
1938         u16 i;
1939
1940         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1941
1942         /* Read Messages from MFW */
1943         ecore_mcp_read_mb(p_hwfn, p_ptt);
1944
1945         /* Compare current messages to old ones */
1946         for (i = 0; i < info->mfw_mb_length; i++) {
1947                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1948                         continue;
1949
1950                 found = true;
1951
1952                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1953                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1954                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1955
1956                 switch (i) {
1957                 case MFW_DRV_MSG_LINK_CHANGE:
1958                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1959                         break;
1960                 case MFW_DRV_MSG_VF_DISABLED:
1961                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1962                         break;
1963                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1964                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1965                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1966                         break;
1967                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1968                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1969                                                     ECORE_DCBX_REMOTE_MIB);
1970                         break;
1971                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1972                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1973                                                     ECORE_DCBX_OPERATIONAL_MIB);
1974                         break;
1975                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1976                         ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
1977                         break;
1978                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1979                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1980                         break;
1981                 case MFW_DRV_MSG_ERROR_RECOVERY:
1982                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1983                         break;
1984                 case MFW_DRV_MSG_GET_LAN_STATS:
1985                 case MFW_DRV_MSG_GET_FCOE_STATS:
1986                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1987                 case MFW_DRV_MSG_GET_RDMA_STATS:
1988                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1989                         break;
1990                 case MFW_DRV_MSG_BW_UPDATE:
1991                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1992                         break;
1993                 case MFW_DRV_MSG_FAILURE_DETECTED:
1994                         ecore_mcp_handle_fan_failure(p_hwfn);
1995                         break;
1996                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1997                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1998                         break;
1999                 default:
2000                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2001                         rc = ECORE_INVAL;
2002                 }
2003         }
2004
2005         /* ACK everything */
2006         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2007                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2008
2009                 /* MFW expect answer in BE, so we force write in that format */
2010                 ecore_wr(p_hwfn, p_ptt,
2011                          info->mfw_mb_addr + sizeof(u32) +
2012                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2013                          sizeof(u32) + i * sizeof(u32), val);
2014         }
2015
2016         if (!found) {
2017                 DP_NOTICE(p_hwfn, false,
2018                           "Received an MFW message indication but no"
2019                           " new message!\n");
2020                 rc = ECORE_INVAL;
2021         }
2022
2023         /* Copy the new mfw messages into the shadow */
2024         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2025
2026         return rc;
2027 }
2028
2029 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2030                                            struct ecore_ptt *p_ptt,
2031                                            u32 *p_mfw_ver,
2032                                            u32 *p_running_bundle_id)
2033 {
2034         u32 global_offsize;
2035
2036 #ifndef ASIC_ONLY
2037         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2038                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2039                 return ECORE_SUCCESS;
2040         }
2041 #endif
2042
2043         if (IS_VF(p_hwfn->p_dev)) {
2044                 if (p_hwfn->vf_iov_info) {
2045                         struct pfvf_acquire_resp_tlv *p_resp;
2046
2047                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2048                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2049                         return ECORE_SUCCESS;
2050                 } else {
2051                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2052                                    "VF requested MFW version prior to ACQUIRE\n");
2053                         return ECORE_INVAL;
2054                 }
2055         }
2056
2057         global_offsize = ecore_rd(p_hwfn, p_ptt,
2058                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2059                                                        public_base,
2060                                                        PUBLIC_GLOBAL));
2061         *p_mfw_ver =
2062             ecore_rd(p_hwfn, p_ptt,
2063                      SECTION_ADDR(global_offsize,
2064                                   0) + OFFSETOF(struct public_global, mfw_ver));
2065
2066         if (p_running_bundle_id != OSAL_NULL) {
2067                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2068                                                 SECTION_ADDR(global_offsize,
2069                                                              0) +
2070                                                 OFFSETOF(struct public_global,
2071                                                          running_bundle_id));
2072         }
2073
2074         return ECORE_SUCCESS;
2075 }
2076
2077 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2078                                               struct ecore_ptt *p_ptt,
2079                                               u32 *p_media_type)
2080 {
2081
2082         /* TODO - Add support for VFs */
2083         if (IS_VF(p_hwfn->p_dev))
2084                 return ECORE_INVAL;
2085
2086         if (!ecore_mcp_is_init(p_hwfn)) {
2087                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2088                 return ECORE_BUSY;
2089         }
2090
2091         if (!p_ptt) {
2092                 *p_media_type = MEDIA_UNSPECIFIED;
2093                 return ECORE_INVAL;
2094         } else {
2095                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2096                                          p_hwfn->mcp_info->port_addr +
2097                                          OFFSETOF(struct public_port,
2098                                                   media_type));
2099         }
2100
2101         return ECORE_SUCCESS;
2102 }
2103
2104 /* @DPDK */
2105 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2106 static void
2107 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2108                                  enum ecore_pci_personality *p_proto)
2109 {
2110         *p_proto = ECORE_PCI_ETH;
2111
2112         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2113                    "According to Legacy capabilities, L2 personality is %08x\n",
2114                    (u32)*p_proto);
2115 }
2116
2117 /* @DPDK */
2118 static enum _ecore_status_t
2119 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2120                               struct ecore_ptt *p_ptt,
2121                               enum ecore_pci_personality *p_proto)
2122 {
2123         u32 resp = 0, param = 0;
2124         enum _ecore_status_t rc;
2125
2126         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2127                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2128                    (u32)*p_proto, resp, param);
2129         return ECORE_SUCCESS;
2130 }
2131
2132 static enum _ecore_status_t
2133 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2134                           struct public_func *p_info,
2135                           struct ecore_ptt *p_ptt,
2136                           enum ecore_pci_personality *p_proto)
2137 {
2138         enum _ecore_status_t rc = ECORE_SUCCESS;
2139
2140         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2141         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2142                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2143                     ECORE_SUCCESS)
2144                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2145                 break;
2146         default:
2147                 rc = ECORE_INVAL;
2148         }
2149
2150         return rc;
2151 }
2152
2153 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2154                                                     struct ecore_ptt *p_ptt)
2155 {
2156         struct ecore_mcp_function_info *info;
2157         struct public_func shmem_info;
2158
2159         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2160         info = &p_hwfn->mcp_info->func_info;
2161
2162         info->pause_on_host = (shmem_info.config &
2163                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2164
2165         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2166                                       &info->protocol)) {
2167                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2168                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2169                 return ECORE_INVAL;
2170         }
2171
2172         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2173
2174         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2175                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2176                 info->mac[1] = (u8)(shmem_info.mac_upper);
2177                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2178                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2179                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2180                 info->mac[5] = (u8)(shmem_info.mac_lower);
2181         } else {
2182                 /* TODO - are there protocols for which there's no MAC? */
2183                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2184         }
2185
2186         /* TODO - are these calculations true for BE machine? */
2187         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2188                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2189         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2190                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2191
2192         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2193
2194         info->mtu = (u16)shmem_info.mtu_size;
2195
2196         if (info->mtu == 0)
2197                 info->mtu = 1500;
2198
2199         info->mtu = (u16)shmem_info.mtu_size;
2200
2201         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2202                    "Read configuration from shmem: pause_on_host %02x"
2203                     " protocol %02x BW [%02x - %02x]"
2204                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2205                     " node %lx ovlan %04x\n",
2206                    info->pause_on_host, info->protocol,
2207                    info->bandwidth_min, info->bandwidth_max,
2208                    info->mac[0], info->mac[1], info->mac[2],
2209                    info->mac[3], info->mac[4], info->mac[5],
2210                    (unsigned long)info->wwn_port,
2211                    (unsigned long)info->wwn_node, info->ovlan);
2212
2213         return ECORE_SUCCESS;
2214 }
2215
2216 struct ecore_mcp_link_params
2217 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2218 {
2219         if (!p_hwfn || !p_hwfn->mcp_info)
2220                 return OSAL_NULL;
2221         return &p_hwfn->mcp_info->link_input;
2222 }
2223
2224 struct ecore_mcp_link_state
2225 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2226 {
2227         if (!p_hwfn || !p_hwfn->mcp_info)
2228                 return OSAL_NULL;
2229
2230 #ifndef ASIC_ONLY
2231         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2232                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2233                 p_hwfn->mcp_info->link_output.link_up = true;
2234         }
2235 #endif
2236
2237         return &p_hwfn->mcp_info->link_output;
2238 }
2239
2240 struct ecore_mcp_link_capabilities
2241 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2242 {
2243         if (!p_hwfn || !p_hwfn->mcp_info)
2244                 return OSAL_NULL;
2245         return &p_hwfn->mcp_info->link_capabilities;
2246 }
2247
2248 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2249                                      struct ecore_ptt *p_ptt)
2250 {
2251         u32 resp = 0, param = 0;
2252         enum _ecore_status_t rc;
2253
2254         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2255                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2256
2257         /* Wait for the drain to complete before returning */
2258         OSAL_MSLEEP(1020);
2259
2260         return rc;
2261 }
2262
2263 const struct ecore_mcp_function_info
2264 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2265 {
2266         if (!p_hwfn || !p_hwfn->mcp_info)
2267                 return OSAL_NULL;
2268         return &p_hwfn->mcp_info->func_info;
2269 }
2270
2271 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2272                                   struct ecore_ptt *p_ptt, u32 personalities)
2273 {
2274         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2275         struct public_func shmem_info;
2276         int i, count = 0, num_pfs;
2277
2278         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2279
2280         for (i = 0; i < num_pfs; i++) {
2281                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2282                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2283                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2284                         continue;
2285
2286                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2287                                               &protocol) !=
2288                     ECORE_SUCCESS)
2289                         continue;
2290
2291                 if ((1 << ((u32)protocol)) & personalities)
2292                         count++;
2293         }
2294
2295         return count;
2296 }
2297
2298 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2299                                               struct ecore_ptt *p_ptt,
2300                                               u32 *p_flash_size)
2301 {
2302         u32 flash_size;
2303
2304 #ifndef ASIC_ONLY
2305         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2306                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2307                 return ECORE_INVAL;
2308         }
2309 #endif
2310
2311         if (IS_VF(p_hwfn->p_dev))
2312                 return ECORE_INVAL;
2313
2314         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2315         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2316                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2317         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2318
2319         *p_flash_size = flash_size;
2320
2321         return ECORE_SUCCESS;
2322 }
2323
2324 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2325                                                   struct ecore_ptt *p_ptt)
2326 {
2327         struct ecore_dev *p_dev = p_hwfn->p_dev;
2328
2329         if (p_dev->recov_in_prog) {
2330                 DP_NOTICE(p_hwfn, false,
2331                           "Avoid triggering a recovery since such a process"
2332                           " is already in progress\n");
2333                 return ECORE_AGAIN;
2334         }
2335
2336         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2337         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2338
2339         return ECORE_SUCCESS;
2340 }
2341
2342 static enum _ecore_status_t
2343 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2344                             struct ecore_ptt *p_ptt,
2345                             u8 vf_id, u8 num)
2346 {
2347         u32 resp = 0, param = 0, rc_param = 0;
2348         enum _ecore_status_t rc;
2349
2350 /* Only Leader can configure MSIX, and need to take CMT into account */
2351
2352         if (!IS_LEAD_HWFN(p_hwfn))
2353                 return ECORE_SUCCESS;
2354         num *= p_hwfn->p_dev->num_hwfns;
2355
2356         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2357             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2358         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2359             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2360
2361         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2362                            &resp, &rc_param);
2363
2364         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2365                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2366                           vf_id);
2367                 rc = ECORE_INVAL;
2368         } else {
2369                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2370                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2371                             num, vf_id);
2372         }
2373
2374         return rc;
2375 }
2376
2377 static enum _ecore_status_t
2378 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2379                             struct ecore_ptt *p_ptt,
2380                             u8 num)
2381 {
2382         u32 resp = 0, param = num, rc_param = 0;
2383         enum _ecore_status_t rc;
2384
2385         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2386                            param, &resp, &rc_param);
2387
2388         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2389                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2390                 rc = ECORE_INVAL;
2391         } else {
2392                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2393                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2394                            num);
2395         }
2396
2397         return rc;
2398 }
2399
2400 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2401                                               struct ecore_ptt *p_ptt,
2402                                               u8 vf_id, u8 num)
2403 {
2404         if (ECORE_IS_BB(p_hwfn->p_dev))
2405                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2406         else
2407                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2408 }
2409
2410 enum _ecore_status_t
2411 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2412                            struct ecore_mcp_drv_version *p_ver)
2413 {
2414         struct ecore_mcp_mb_params mb_params;
2415         struct drv_version_stc drv_version;
2416         u32 num_words, i;
2417         void *p_name;
2418         OSAL_BE32 val;
2419         enum _ecore_status_t rc;
2420
2421 #ifndef ASIC_ONLY
2422         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2423                 return ECORE_SUCCESS;
2424 #endif
2425
2426         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2427         drv_version.version = p_ver->version;
2428         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2429         for (i = 0; i < num_words; i++) {
2430                 /* The driver name is expected to be in a big-endian format */
2431                 p_name = &p_ver->name[i * sizeof(u32)];
2432                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2433                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2434         }
2435
2436         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2437         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2438         mb_params.p_data_src = &drv_version;
2439         mb_params.data_src_size = sizeof(drv_version);
2440         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2441         if (rc != ECORE_SUCCESS)
2442                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2443
2444         return rc;
2445 }
2446
2447 /* A maximal 100 msec waiting time for the MCP to halt */
2448 #define ECORE_MCP_HALT_SLEEP_MS         10
2449 #define ECORE_MCP_HALT_MAX_RETRIES      10
2450
2451 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2452                                     struct ecore_ptt *p_ptt)
2453 {
2454         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2455         enum _ecore_status_t rc;
2456
2457         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2458                            &param);
2459         if (rc != ECORE_SUCCESS) {
2460                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2461                 return rc;
2462         }
2463
2464         do {
2465                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2466                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2467                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2468                         break;
2469         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2470
2471         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2472                 DP_NOTICE(p_hwfn, false,
2473                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2474                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2475                 return ECORE_BUSY;
2476         }
2477
2478         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2479
2480         return ECORE_SUCCESS;
2481 }
2482
2483 #define ECORE_MCP_RESUME_SLEEP_MS       10
2484
2485 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2486                                       struct ecore_ptt *p_ptt)
2487 {
2488         u32 cpu_mode, cpu_state;
2489
2490         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2491
2492         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2493         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2494         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2495
2496         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2497         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2498
2499         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2500                 DP_NOTICE(p_hwfn, false,
2501                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2502                           cpu_mode, cpu_state);
2503                 return ECORE_BUSY;
2504         }
2505
2506         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2507
2508         return ECORE_SUCCESS;
2509 }
2510
2511 enum _ecore_status_t
2512 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2513                                    struct ecore_ptt *p_ptt,
2514                                    enum ecore_ov_client client)
2515 {
2516         enum _ecore_status_t rc;
2517         u32 resp = 0, param = 0;
2518         u32 drv_mb_param;
2519
2520         switch (client) {
2521         case ECORE_OV_CLIENT_DRV:
2522                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2523                 break;
2524         case ECORE_OV_CLIENT_USER:
2525                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2526                 break;
2527         case ECORE_OV_CLIENT_VENDOR_SPEC:
2528                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2529                 break;
2530         default:
2531                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2532                 return ECORE_INVAL;
2533         }
2534
2535         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2536                            drv_mb_param, &resp, &param);
2537         if (rc != ECORE_SUCCESS)
2538                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2539
2540         return rc;
2541 }
2542
2543 enum _ecore_status_t
2544 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2545                                  struct ecore_ptt *p_ptt,
2546                                  enum ecore_ov_driver_state drv_state)
2547 {
2548         enum _ecore_status_t rc;
2549         u32 resp = 0, param = 0;
2550         u32 drv_mb_param;
2551
2552         switch (drv_state) {
2553         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2554                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2555                 break;
2556         case ECORE_OV_DRIVER_STATE_DISABLED:
2557                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2558                 break;
2559         case ECORE_OV_DRIVER_STATE_ACTIVE:
2560                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2561                 break;
2562         default:
2563                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2564                 return ECORE_INVAL;
2565         }
2566
2567         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2568                            drv_mb_param, &resp, &param);
2569         if (rc != ECORE_SUCCESS)
2570                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2571
2572         return rc;
2573 }
2574
2575 enum _ecore_status_t
2576 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2577                          struct ecore_fc_npiv_tbl *p_table)
2578 {
2579         return 0;
2580 }
2581
2582 enum _ecore_status_t
2583 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2584                         struct ecore_ptt *p_ptt, u16 mtu)
2585 {
2586         return 0;
2587 }
2588
2589 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2590                                        struct ecore_ptt *p_ptt,
2591                                        enum ecore_led_mode mode)
2592 {
2593         u32 resp = 0, param = 0, drv_mb_param;
2594         enum _ecore_status_t rc;
2595
2596         switch (mode) {
2597         case ECORE_LED_MODE_ON:
2598                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2599                 break;
2600         case ECORE_LED_MODE_OFF:
2601                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2602                 break;
2603         case ECORE_LED_MODE_RESTORE:
2604                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2605                 break;
2606         default:
2607                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2608                 return ECORE_INVAL;
2609         }
2610
2611         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2612                            drv_mb_param, &resp, &param);
2613         if (rc != ECORE_SUCCESS)
2614                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2615
2616         return rc;
2617 }
2618
2619 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2620                                              struct ecore_ptt *p_ptt,
2621                                              u32 mask_parities)
2622 {
2623         u32 resp = 0, param = 0;
2624         enum _ecore_status_t rc;
2625
2626         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2627                            mask_parities, &resp, &param);
2628
2629         if (rc != ECORE_SUCCESS) {
2630                 DP_ERR(p_hwfn,
2631                        "MCP response failure for mask parities, aborting\n");
2632         } else if (resp != FW_MSG_CODE_OK) {
2633                 DP_ERR(p_hwfn,
2634                        "MCP did not ack mask parity request. Old MFW?\n");
2635                 rc = ECORE_INVAL;
2636         }
2637
2638         return rc;
2639 }
2640
2641 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2642                                         u8 *p_buf, u32 len)
2643 {
2644         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2645         u32 bytes_left, offset, bytes_to_copy, buf_size;
2646         u32 nvm_offset, resp, param;
2647         struct ecore_ptt *p_ptt;
2648         enum _ecore_status_t rc = ECORE_SUCCESS;
2649
2650         p_ptt = ecore_ptt_acquire(p_hwfn);
2651         if (!p_ptt)
2652                 return ECORE_BUSY;
2653
2654         bytes_left = len;
2655         offset = 0;
2656         while (bytes_left > 0) {
2657                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2658                                            MCP_DRV_NVM_BUF_LEN);
2659                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2660                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2661                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2662                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2663                                           nvm_offset, &resp, &param, &buf_size,
2664                                           (u32 *)(p_buf + offset));
2665                 if (rc != ECORE_SUCCESS) {
2666                         DP_NOTICE(p_dev, false,
2667                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2668                                   rc);
2669                         resp = FW_MSG_CODE_ERROR;
2670                         break;
2671                 }
2672
2673                 if (resp != FW_MSG_CODE_NVM_OK) {
2674                         DP_NOTICE(p_dev, false,
2675                                   "nvm read failed, resp = 0x%08x\n", resp);
2676                         rc = ECORE_UNKNOWN_ERROR;
2677                         break;
2678                 }
2679
2680                 /* This can be a lengthy process, and it's possible scheduler
2681                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2682                  */
2683                 if (bytes_left % 0x1000 <
2684                     (bytes_left - buf_size) % 0x1000)
2685                         OSAL_MSLEEP(1);
2686
2687                 offset += buf_size;
2688                 bytes_left -= buf_size;
2689         }
2690
2691         p_dev->mcp_nvm_resp = resp;
2692         ecore_ptt_release(p_hwfn, p_ptt);
2693
2694         return rc;
2695 }
2696
2697 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2698                                         u32 addr, u8 *p_buf, u32 len)
2699 {
2700         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2701         struct ecore_ptt *p_ptt;
2702         u32 resp, param;
2703         enum _ecore_status_t rc;
2704
2705         p_ptt = ecore_ptt_acquire(p_hwfn);
2706         if (!p_ptt)
2707                 return ECORE_BUSY;
2708
2709         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2710                                   (cmd == ECORE_PHY_CORE_READ) ?
2711                                   DRV_MSG_CODE_PHY_CORE_READ :
2712                                   DRV_MSG_CODE_PHY_RAW_READ,
2713                                   addr, &resp, &param, &len, (u32 *)p_buf);
2714         if (rc != ECORE_SUCCESS)
2715                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2716
2717         p_dev->mcp_nvm_resp = resp;
2718         ecore_ptt_release(p_hwfn, p_ptt);
2719
2720         return rc;
2721 }
2722
2723 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2724 {
2725         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2726         struct ecore_ptt *p_ptt;
2727
2728         p_ptt = ecore_ptt_acquire(p_hwfn);
2729         if (!p_ptt)
2730                 return ECORE_BUSY;
2731
2732         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2733         ecore_ptt_release(p_hwfn, p_ptt);
2734
2735         return ECORE_SUCCESS;
2736 }
2737
2738 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2739 {
2740         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2741         struct ecore_ptt *p_ptt;
2742         u32 resp, param;
2743         enum _ecore_status_t rc;
2744
2745         p_ptt = ecore_ptt_acquire(p_hwfn);
2746         if (!p_ptt)
2747                 return ECORE_BUSY;
2748         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2749                            &resp, &param);
2750         p_dev->mcp_nvm_resp = resp;
2751         ecore_ptt_release(p_hwfn, p_ptt);
2752
2753         return rc;
2754 }
2755
2756 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2757                                                   u32 addr)
2758 {
2759         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2760         struct ecore_ptt *p_ptt;
2761         u32 resp, param;
2762         enum _ecore_status_t rc;
2763
2764         p_ptt = ecore_ptt_acquire(p_hwfn);
2765         if (!p_ptt)
2766                 return ECORE_BUSY;
2767         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2768                            &resp, &param);
2769         p_dev->mcp_nvm_resp = resp;
2770         ecore_ptt_release(p_hwfn, p_ptt);
2771
2772         return rc;
2773 }
2774
2775 /* rc receives ECORE_INVAL as default parameter because
2776  * it might not enter the while loop if the len is 0
2777  */
2778 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2779                                          u32 addr, u8 *p_buf, u32 len)
2780 {
2781         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2782         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2783         enum _ecore_status_t rc = ECORE_INVAL;
2784         struct ecore_ptt *p_ptt;
2785
2786         p_ptt = ecore_ptt_acquire(p_hwfn);
2787         if (!p_ptt)
2788                 return ECORE_BUSY;
2789
2790         switch (cmd) {
2791         case ECORE_PUT_FILE_DATA:
2792                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2793                 break;
2794         case ECORE_NVM_WRITE_NVRAM:
2795                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2796                 break;
2797         case ECORE_EXT_PHY_FW_UPGRADE:
2798                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2799                 break;
2800         default:
2801                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2802                           cmd);
2803                 rc = ECORE_INVAL;
2804                 goto out;
2805         }
2806
2807         buf_idx = 0;
2808         while (buf_idx < len) {
2809                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2810                                       MCP_DRV_NVM_BUF_LEN);
2811                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2812                               addr) +
2813                              buf_idx;
2814                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2815                                           &resp, &param, buf_size,
2816                                           (u32 *)&p_buf[buf_idx]);
2817                 if (rc != ECORE_SUCCESS) {
2818                         DP_NOTICE(p_dev, false,
2819                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2820                                   rc);
2821                         resp = FW_MSG_CODE_ERROR;
2822                         break;
2823                 }
2824
2825                 if (resp != FW_MSG_CODE_OK &&
2826                     resp != FW_MSG_CODE_NVM_OK &&
2827                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2828                         DP_NOTICE(p_dev, false,
2829                                   "nvm write failed, resp = 0x%08x\n", resp);
2830                         rc = ECORE_UNKNOWN_ERROR;
2831                         break;
2832                 }
2833
2834                 /* This can be a lengthy process, and it's possible scheduler
2835                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2836                  */
2837                 if (buf_idx % 0x1000 >
2838                     (buf_idx + buf_size) % 0x1000)
2839                         OSAL_MSLEEP(1);
2840
2841                 buf_idx += buf_size;
2842         }
2843
2844         p_dev->mcp_nvm_resp = resp;
2845 out:
2846         ecore_ptt_release(p_hwfn, p_ptt);
2847
2848         return rc;
2849 }
2850
2851 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2852                                          u32 addr, u8 *p_buf, u32 len)
2853 {
2854         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2855         struct ecore_ptt *p_ptt;
2856         u32 resp, param, nvm_cmd;
2857         enum _ecore_status_t rc;
2858
2859         p_ptt = ecore_ptt_acquire(p_hwfn);
2860         if (!p_ptt)
2861                 return ECORE_BUSY;
2862
2863         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2864                         DRV_MSG_CODE_PHY_RAW_WRITE;
2865         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2866                                   &resp, &param, len, (u32 *)p_buf);
2867         if (rc != ECORE_SUCCESS)
2868                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2869         p_dev->mcp_nvm_resp = resp;
2870         ecore_ptt_release(p_hwfn, p_ptt);
2871
2872         return rc;
2873 }
2874
2875 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2876                                                    u32 addr)
2877 {
2878         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2879         struct ecore_ptt *p_ptt;
2880         u32 resp, param;
2881         enum _ecore_status_t rc;
2882
2883         p_ptt = ecore_ptt_acquire(p_hwfn);
2884         if (!p_ptt)
2885                 return ECORE_BUSY;
2886
2887         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2888                            &resp, &param);
2889         p_dev->mcp_nvm_resp = resp;
2890         ecore_ptt_release(p_hwfn, p_ptt);
2891
2892         return rc;
2893 }
2894
2895 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2896                                             struct ecore_ptt *p_ptt,
2897                                             u32 port, u32 addr, u32 offset,
2898                                             u32 len, u8 *p_buf)
2899 {
2900         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2901         u32 resp, param;
2902         enum _ecore_status_t rc;
2903
2904         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2905                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2906         addr = offset;
2907         offset = 0;
2908         bytes_left = len;
2909         while (bytes_left > 0) {
2910                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2911                                            MAX_I2C_TRANSACTION_SIZE);
2912                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2913                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2914                 nvm_offset |= ((addr + offset) <<
2915                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2916                 nvm_offset |= (bytes_to_copy <<
2917                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2918                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2919                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2920                                           nvm_offset, &resp, &param, &buf_size,
2921                                           (u32 *)(p_buf + offset));
2922                 if ((resp & FW_MSG_CODE_MASK) ==
2923                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2924                         return ECORE_NODEV;
2925                 } else if ((resp & FW_MSG_CODE_MASK) !=
2926                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2927                         return ECORE_UNKNOWN_ERROR;
2928
2929                 offset += buf_size;
2930                 bytes_left -= buf_size;
2931         }
2932
2933         return ECORE_SUCCESS;
2934 }
2935
2936 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2937                                              struct ecore_ptt *p_ptt,
2938                                              u32 port, u32 addr, u32 offset,
2939                                              u32 len, u8 *p_buf)
2940 {
2941         u32 buf_idx, buf_size, nvm_offset, resp, param;
2942         enum _ecore_status_t rc;
2943
2944         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2945                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2946         buf_idx = 0;
2947         while (buf_idx < len) {
2948                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2949                                       MAX_I2C_TRANSACTION_SIZE);
2950                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2951                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2952                 nvm_offset |= ((offset + buf_idx) <<
2953                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2954                 nvm_offset |= (buf_size <<
2955                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2956                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2957                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2958                                           nvm_offset, &resp, &param, buf_size,
2959                                           (u32 *)&p_buf[buf_idx]);
2960                 if ((resp & FW_MSG_CODE_MASK) ==
2961                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2962                         return ECORE_NODEV;
2963                 } else if ((resp & FW_MSG_CODE_MASK) !=
2964                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2965                         return ECORE_UNKNOWN_ERROR;
2966
2967                 buf_idx += buf_size;
2968         }
2969
2970         return ECORE_SUCCESS;
2971 }
2972
2973 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2974                                          struct ecore_ptt *p_ptt,
2975                                          u16 gpio, u32 *gpio_val)
2976 {
2977         enum _ecore_status_t rc = ECORE_SUCCESS;
2978         u32 drv_mb_param = 0, rsp;
2979
2980         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2981
2982         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2983                            drv_mb_param, &rsp, gpio_val);
2984
2985         if (rc != ECORE_SUCCESS)
2986                 return rc;
2987
2988         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2989                 return ECORE_UNKNOWN_ERROR;
2990
2991         return ECORE_SUCCESS;
2992 }
2993
2994 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2995                                           struct ecore_ptt *p_ptt,
2996                                           u16 gpio, u16 gpio_val)
2997 {
2998         enum _ecore_status_t rc = ECORE_SUCCESS;
2999         u32 drv_mb_param = 0, param, rsp;
3000
3001         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3002                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3003
3004         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3005                            drv_mb_param, &rsp, &param);
3006
3007         if (rc != ECORE_SUCCESS)
3008                 return rc;
3009
3010         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3011                 return ECORE_UNKNOWN_ERROR;
3012
3013         return ECORE_SUCCESS;
3014 }
3015
3016 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3017                                          struct ecore_ptt *p_ptt,
3018                                          u16 gpio, u32 *gpio_direction,
3019                                          u32 *gpio_ctrl)
3020 {
3021         u32 drv_mb_param = 0, rsp, val = 0;
3022         enum _ecore_status_t rc = ECORE_SUCCESS;
3023
3024         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3025
3026         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3027                            drv_mb_param, &rsp, &val);
3028         if (rc != ECORE_SUCCESS)
3029                 return rc;
3030
3031         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3032                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3033         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3034                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3035
3036         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3037                 return ECORE_UNKNOWN_ERROR;
3038
3039         return ECORE_SUCCESS;
3040 }
3041
3042 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3043                                                   struct ecore_ptt *p_ptt)
3044 {
3045         u32 drv_mb_param = 0, rsp, param;
3046         enum _ecore_status_t rc = ECORE_SUCCESS;
3047
3048         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3049                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3050
3051         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3052                            drv_mb_param, &rsp, &param);
3053
3054         if (rc != ECORE_SUCCESS)
3055                 return rc;
3056
3057         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3058             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3059                 rc = ECORE_UNKNOWN_ERROR;
3060
3061         return rc;
3062 }
3063
3064 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3065                                                struct ecore_ptt *p_ptt)
3066 {
3067         u32 drv_mb_param, rsp, param;
3068         enum _ecore_status_t rc = ECORE_SUCCESS;
3069
3070         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3071                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3072
3073         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3074                            drv_mb_param, &rsp, &param);
3075
3076         if (rc != ECORE_SUCCESS)
3077                 return rc;
3078
3079         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3080             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3081                 rc = ECORE_UNKNOWN_ERROR;
3082
3083         return rc;
3084 }
3085
3086 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3087         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3088 {
3089         u32 drv_mb_param = 0, rsp;
3090         enum _ecore_status_t rc = ECORE_SUCCESS;
3091
3092         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3093                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3094
3095         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3096                            drv_mb_param, &rsp, num_images);
3097
3098         if (rc != ECORE_SUCCESS)
3099                 return rc;
3100
3101         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3102                 rc = ECORE_UNKNOWN_ERROR;
3103
3104         return rc;
3105 }
3106
3107 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3108         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3109         struct bist_nvm_image_att *p_image_att, u32 image_index)
3110 {
3111         u32 buf_size, nvm_offset, resp, param;
3112         enum _ecore_status_t rc;
3113
3114         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3115                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3116         nvm_offset |= (image_index <<
3117                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3118         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3119                                   nvm_offset, &resp, &param, &buf_size,
3120                                   (u32 *)p_image_att);
3121         if (rc != ECORE_SUCCESS)
3122                 return rc;
3123
3124         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3125             (p_image_att->return_code != 1))
3126                 rc = ECORE_UNKNOWN_ERROR;
3127
3128         return rc;
3129 }
3130
3131 enum _ecore_status_t
3132 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3133                                struct ecore_ptt *p_ptt,
3134                                struct ecore_temperature_info *p_temp_info)
3135 {
3136         struct ecore_temperature_sensor *p_temp_sensor;
3137         struct temperature_status_stc mfw_temp_info;
3138         struct ecore_mcp_mb_params mb_params;
3139         u32 val;
3140         enum _ecore_status_t rc;
3141         u8 i;
3142
3143         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3144         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3145         mb_params.p_data_dst = &mfw_temp_info;
3146         mb_params.data_dst_size = sizeof(mfw_temp_info);
3147         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3148         if (rc != ECORE_SUCCESS)
3149                 return rc;
3150
3151         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3152         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3153                                               ECORE_MAX_NUM_OF_SENSORS);
3154         for (i = 0; i < p_temp_info->num_sensors; i++) {
3155                 val = mfw_temp_info.sensor[i];
3156                 p_temp_sensor = &p_temp_info->sensors[i];
3157                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3158                                                  SENSOR_LOCATION_OFFSET;
3159                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3160                                                 THRESHOLD_HIGH_OFFSET;
3161                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3162                                           CRITICAL_TEMPERATURE_OFFSET;
3163                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3164                                               CURRENT_TEMP_OFFSET;
3165         }
3166
3167         return ECORE_SUCCESS;
3168 }
3169
3170 enum _ecore_status_t ecore_mcp_get_mba_versions(
3171         struct ecore_hwfn *p_hwfn,
3172         struct ecore_ptt *p_ptt,
3173         struct ecore_mba_vers *p_mba_vers)
3174 {
3175         u32 buf_size, resp, param;
3176         enum _ecore_status_t rc;
3177
3178         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3179                                   0, &resp, &param, &buf_size,
3180                                   &p_mba_vers->mba_vers[0]);
3181
3182         if (rc != ECORE_SUCCESS)
3183                 return rc;
3184
3185         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3186                 rc = ECORE_UNKNOWN_ERROR;
3187
3188         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3189                 rc = ECORE_UNKNOWN_ERROR;
3190
3191         return rc;
3192 }
3193
3194 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3195                                               struct ecore_ptt *p_ptt,
3196                                               u64 *num_events)
3197 {
3198         u32 rsp;
3199
3200         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3201                              0, &rsp, (u32 *)num_events);
3202 }
3203
3204 static enum resource_id_enum
3205 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3206 {
3207         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3208
3209         switch (res_id) {
3210         case ECORE_SB:
3211                 mfw_res_id = RESOURCE_NUM_SB_E;
3212                 break;
3213         case ECORE_L2_QUEUE:
3214                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3215                 break;
3216         case ECORE_VPORT:
3217                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3218                 break;
3219         case ECORE_RSS_ENG:
3220                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3221                 break;
3222         case ECORE_PQ:
3223                 mfw_res_id = RESOURCE_NUM_PQ_E;
3224                 break;
3225         case ECORE_RL:
3226                 mfw_res_id = RESOURCE_NUM_RL_E;
3227                 break;
3228         case ECORE_MAC:
3229         case ECORE_VLAN:
3230                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3231                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3232                 break;
3233         case ECORE_ILT:
3234                 mfw_res_id = RESOURCE_ILT_E;
3235                 break;
3236         case ECORE_LL2_QUEUE:
3237                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3238                 break;
3239         case ECORE_RDMA_CNQ_RAM:
3240         case ECORE_CMDQS_CQS:
3241                 /* CNQ/CMDQS are the same resource */
3242                 mfw_res_id = RESOURCE_CQS_E;
3243                 break;
3244         case ECORE_RDMA_STATS_QUEUE:
3245                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3246                 break;
3247         case ECORE_BDQ:
3248                 mfw_res_id = RESOURCE_BDQ_E;
3249                 break;
3250         default:
3251                 break;
3252         }
3253
3254         return mfw_res_id;
3255 }
3256
3257 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3258 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3259 #define ECORE_RESC_ALLOC_VERSION                                \
3260         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3261           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3262          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3263           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3264
3265 struct ecore_resc_alloc_in_params {
3266         u32 cmd;
3267         enum ecore_resources res_id;
3268         u32 resc_max_val;
3269 };
3270
3271 struct ecore_resc_alloc_out_params {
3272         u32 mcp_resp;
3273         u32 mcp_param;
3274         u32 resc_num;
3275         u32 resc_start;
3276         u32 vf_resc_num;
3277         u32 vf_resc_start;
3278         u32 flags;
3279 };
3280
3281 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3282
3283 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3284 {
3285         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3286         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3287         enum _ecore_status_t rc;
3288
3289         /* Allow ongoing PCIe transactions to complete */
3290         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3291
3292         /* Clear the PF's internal FID_enable in the PXP */
3293         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3294         if (rc != ECORE_SUCCESS)
3295                 DP_NOTICE(p_hwfn, false,
3296                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3297                           rc);
3298
3299         return rc;
3300 }
3301
3302 static enum _ecore_status_t
3303 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3304                               struct ecore_ptt *p_ptt,
3305                               struct ecore_resc_alloc_in_params *p_in_params,
3306                               struct ecore_resc_alloc_out_params *p_out_params)
3307 {
3308         struct ecore_mcp_mb_params mb_params;
3309         struct resource_info mfw_resc_info;
3310         enum _ecore_status_t rc;
3311
3312         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3313
3314         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3315         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3316                 DP_ERR(p_hwfn,
3317                        "Failed to match resource %d [%s] with the MFW resources\n",
3318                        p_in_params->res_id,
3319                        ecore_hw_get_resc_name(p_in_params->res_id));
3320                 return ECORE_INVAL;
3321         }
3322
3323         switch (p_in_params->cmd) {
3324         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3325                 mfw_resc_info.size = p_in_params->resc_max_val;
3326                 /* Fallthrough */
3327         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3328                 break;
3329         default:
3330                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3331                        p_in_params->cmd);
3332                 return ECORE_INVAL;
3333         }
3334
3335         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3336         mb_params.cmd = p_in_params->cmd;
3337         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3338         mb_params.p_data_src = &mfw_resc_info;
3339         mb_params.data_src_size = sizeof(mfw_resc_info);
3340         mb_params.p_data_dst = mb_params.p_data_src;
3341         mb_params.data_dst_size = mb_params.data_src_size;
3342
3343         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3344                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3345                    p_in_params->cmd, p_in_params->res_id,
3346                    ecore_hw_get_resc_name(p_in_params->res_id),
3347                    GET_MFW_FIELD(mb_params.param,
3348                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3349                    GET_MFW_FIELD(mb_params.param,
3350                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3351                    p_in_params->resc_max_val);
3352
3353         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3354         if (rc != ECORE_SUCCESS)
3355                 return rc;
3356
3357         p_out_params->mcp_resp = mb_params.mcp_resp;
3358         p_out_params->mcp_param = mb_params.mcp_param;
3359         p_out_params->resc_num = mfw_resc_info.size;
3360         p_out_params->resc_start = mfw_resc_info.offset;
3361         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3362         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3363         p_out_params->flags = mfw_resc_info.flags;
3364
3365         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3366                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3367                    GET_MFW_FIELD(p_out_params->mcp_param,
3368                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3369                    GET_MFW_FIELD(p_out_params->mcp_param,
3370                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3371                    p_out_params->resc_num, p_out_params->resc_start,
3372                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3373                    p_out_params->flags);
3374
3375         return ECORE_SUCCESS;
3376 }
3377
3378 enum _ecore_status_t
3379 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3380                            enum ecore_resources res_id, u32 resc_max_val,
3381                            u32 *p_mcp_resp)
3382 {
3383         struct ecore_resc_alloc_out_params out_params;
3384         struct ecore_resc_alloc_in_params in_params;
3385         enum _ecore_status_t rc;
3386
3387         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3388         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3389         in_params.res_id = res_id;
3390         in_params.resc_max_val = resc_max_val;
3391         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3392         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3393                                            &out_params);
3394         if (rc != ECORE_SUCCESS)
3395                 return rc;
3396
3397         *p_mcp_resp = out_params.mcp_resp;
3398
3399         return ECORE_SUCCESS;
3400 }
3401
3402 enum _ecore_status_t
3403 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3404                         enum ecore_resources res_id, u32 *p_mcp_resp,
3405                         u32 *p_resc_num, u32 *p_resc_start)
3406 {
3407         struct ecore_resc_alloc_out_params out_params;
3408         struct ecore_resc_alloc_in_params in_params;
3409         enum _ecore_status_t rc;
3410
3411         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3412         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3413         in_params.res_id = res_id;
3414         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3415         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3416                                            &out_params);
3417         if (rc != ECORE_SUCCESS)
3418                 return rc;
3419
3420         *p_mcp_resp = out_params.mcp_resp;
3421
3422         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3423                 *p_resc_num = out_params.resc_num;
3424                 *p_resc_start = out_params.resc_start;
3425         }
3426
3427         return ECORE_SUCCESS;
3428 }
3429
3430 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3431                                                struct ecore_ptt *p_ptt)
3432 {
3433         u32 mcp_resp, mcp_param;
3434
3435         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3436                              &mcp_resp, &mcp_param);
3437 }
3438
3439 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3440                                                    struct ecore_ptt *p_ptt,
3441                                                    u32 param, u32 *p_mcp_resp,
3442                                                    u32 *p_mcp_param)
3443 {
3444         enum _ecore_status_t rc;
3445
3446         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3447                            p_mcp_resp, p_mcp_param);
3448         if (rc != ECORE_SUCCESS)
3449                 return rc;
3450
3451         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3452                 DP_INFO(p_hwfn,
3453                         "The resource command is unsupported by the MFW\n");
3454                 return ECORE_NOTIMPL;
3455         }
3456
3457         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3458                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3459
3460                 DP_NOTICE(p_hwfn, false,
3461                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3462                           param, opcode);
3463                 return ECORE_INVAL;
3464         }
3465
3466         return rc;
3467 }
3468
3469 enum _ecore_status_t
3470 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3471                       struct ecore_resc_lock_params *p_params)
3472 {
3473         u32 param = 0, mcp_resp, mcp_param;
3474         u8 opcode;
3475         enum _ecore_status_t rc;
3476
3477         switch (p_params->timeout) {
3478         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3479                 opcode = RESOURCE_OPCODE_REQ;
3480                 p_params->timeout = 0;
3481                 break;
3482         case ECORE_MCP_RESC_LOCK_TO_NONE:
3483                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3484                 p_params->timeout = 0;
3485                 break;
3486         default:
3487                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3488                 break;
3489         }
3490
3491         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3492         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3493         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3494
3495         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3496                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3497                    param, p_params->timeout, opcode, p_params->resource);
3498
3499         /* Attempt to acquire the resource */
3500         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3501                                     &mcp_param);
3502         if (rc != ECORE_SUCCESS)
3503                 return rc;
3504
3505         /* Analyze the response */
3506         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3507         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3508
3509         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3510                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3511                    mcp_param, opcode, p_params->owner);
3512
3513         switch (opcode) {
3514         case RESOURCE_OPCODE_GNT:
3515                 p_params->b_granted = true;
3516                 break;
3517         case RESOURCE_OPCODE_BUSY:
3518                 p_params->b_granted = false;
3519                 break;
3520         default:
3521                 DP_NOTICE(p_hwfn, false,
3522                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3523                           mcp_param, opcode);
3524                 return ECORE_INVAL;
3525         }
3526
3527         return ECORE_SUCCESS;
3528 }
3529
3530 enum _ecore_status_t
3531 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3532                     struct ecore_resc_lock_params *p_params)
3533 {
3534         u32 retry_cnt = 0;
3535         enum _ecore_status_t rc;
3536
3537         do {
3538                 /* No need for an interval before the first iteration */
3539                 if (retry_cnt) {
3540                         if (p_params->sleep_b4_retry) {
3541                                 u16 retry_interval_in_ms =
3542                                         DIV_ROUND_UP(p_params->retry_interval,
3543                                                      1000);
3544
3545                                 OSAL_MSLEEP(retry_interval_in_ms);
3546                         } else {
3547                                 OSAL_UDELAY(p_params->retry_interval);
3548                         }
3549                 }
3550
3551                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3552                 if (rc != ECORE_SUCCESS)
3553                         return rc;
3554
3555                 if (p_params->b_granted)
3556                         break;
3557         } while (retry_cnt++ < p_params->retry_num);
3558
3559         return ECORE_SUCCESS;
3560 }
3561
3562 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3563                                       struct ecore_resc_unlock_params *p_unlock,
3564                                       enum ecore_resc_lock resource,
3565                                       bool b_is_permanent)
3566 {
3567         if (p_lock != OSAL_NULL) {
3568                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3569
3570                 /* Permanent resources don't require aging, and there's no
3571                  * point in trying to acquire them more than once since it's
3572                  * unexpected another entity would release them.
3573                  */
3574                 if (b_is_permanent) {
3575                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3576                 } else {
3577                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3578                         p_lock->retry_interval =
3579                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3580                         p_lock->sleep_b4_retry = true;
3581                 }
3582
3583                 p_lock->resource = resource;
3584         }
3585
3586         if (p_unlock != OSAL_NULL) {
3587                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3588                 p_unlock->resource = resource;
3589         }
3590 }
3591
3592 enum _ecore_status_t
3593 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3594                       struct ecore_resc_unlock_params *p_params)
3595 {
3596         u32 param = 0, mcp_resp, mcp_param;
3597         u8 opcode;
3598         enum _ecore_status_t rc;
3599
3600         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3601                                    : RESOURCE_OPCODE_RELEASE;
3602         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3603         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3604
3605         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3606                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3607                    param, opcode, p_params->resource);
3608
3609         /* Attempt to release the resource */
3610         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3611                                     &mcp_param);
3612         if (rc != ECORE_SUCCESS)
3613                 return rc;
3614
3615         /* Analyze the response */
3616         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3617
3618         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3619                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3620                    mcp_param, opcode);
3621
3622         switch (opcode) {
3623         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3624                 DP_INFO(p_hwfn,
3625                         "Resource unlock request for an already released resource [%d]\n",
3626                         p_params->resource);
3627                 /* Fallthrough */
3628         case RESOURCE_OPCODE_RELEASED:
3629                 p_params->b_released = true;
3630                 break;
3631         case RESOURCE_OPCODE_WRONG_OWNER:
3632                 p_params->b_released = false;
3633                 break;
3634         default:
3635                 DP_NOTICE(p_hwfn, false,
3636                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3637                           mcp_param, opcode);
3638                 return ECORE_INVAL;
3639         }
3640
3641         return ECORE_SUCCESS;
3642 }
3643
3644 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3645 {
3646         return !!(p_hwfn->mcp_info->capabilities &
3647                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3648 }
3649
3650 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3651                                                 struct ecore_ptt *p_ptt)
3652 {
3653         u32 mcp_resp;
3654         enum _ecore_status_t rc;
3655
3656         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3657                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3658         if (rc == ECORE_SUCCESS)
3659                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3660                            "MFW supported features: %08x\n",
3661                            p_hwfn->mcp_info->capabilities);
3662
3663         return rc;
3664 }
3665
3666 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3667                                                 struct ecore_ptt *p_ptt)
3668 {
3669         u32 mcp_resp, mcp_param, features;
3670
3671         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3672                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3673
3674         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3675                              features, &mcp_resp, &mcp_param);
3676 }
3677
3678 enum _ecore_status_t
3679 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3680                         struct ecore_mcp_drv_attr *p_drv_attr)
3681 {
3682         struct attribute_cmd_write_stc attr_cmd_write;
3683         enum _attribute_commands_e mfw_attr_cmd;
3684         struct ecore_mcp_mb_params mb_params;
3685         enum _ecore_status_t rc;
3686
3687         switch (p_drv_attr->attr_cmd) {
3688         case ECORE_MCP_DRV_ATTR_CMD_READ:
3689                 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
3690                 break;
3691         case ECORE_MCP_DRV_ATTR_CMD_WRITE:
3692                 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
3693                 break;
3694         case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
3695                 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
3696                 break;
3697         case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
3698                 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
3699                 break;
3700         default:
3701                 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
3702                           p_drv_attr->attr_cmd);
3703                 return ECORE_INVAL;
3704         }
3705
3706         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3707         mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
3708         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
3709                       p_drv_attr->attr_num);
3710         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
3711                       mfw_attr_cmd);
3712         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
3713                 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
3714                 attr_cmd_write.val = p_drv_attr->val;
3715                 attr_cmd_write.mask = p_drv_attr->mask;
3716                 attr_cmd_write.offset = p_drv_attr->offset;
3717
3718                 mb_params.p_data_src = &attr_cmd_write;
3719                 mb_params.data_src_size = sizeof(attr_cmd_write);
3720         }
3721
3722         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3723         if (rc != ECORE_SUCCESS)
3724                 return rc;
3725
3726         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3727                 DP_INFO(p_hwfn,
3728                         "The attribute command is not supported by the MFW\n");
3729                 return ECORE_NOTIMPL;
3730         } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
3731                 DP_INFO(p_hwfn,
3732                         "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
3733                         mb_params.mcp_resp, p_drv_attr->attr_cmd,
3734                         p_drv_attr->attr_num);
3735                 return ECORE_INVAL;
3736         }
3737
3738         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3739                    "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
3740                    p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
3741                    p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
3742                    mb_params.mcp_param);
3743
3744         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
3745             p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
3746                 p_drv_attr->val = mb_params.mcp_param;
3747
3748         return ECORE_SUCCESS;
3749 }