drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23 #include "ecore_sp_commands.h"
  24
  25 #define CHIP_MCP_RESP_ITER_US 10
  26 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  27
  28 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  29 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  30
  31 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  32         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  33                  _val)
  34
  35 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  36         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  37
  38 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  39         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  40                      OFFSETOF(struct public_drv_mb, _field), _val)
  41
  42 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  43         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  44                      OFFSETOF(struct public_drv_mb, _field))
  45
  46 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  47         DRV_ID_PDA_COMP_VER_OFFSET)
  48
  49 #define MCP_BYTES_PER_MBIT_OFFSET 17
  50
  51 #ifndef ASIC_ONLY
  52 static int loaded;
  53 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  54 #endif
  55
  56 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  57 {
  58         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  59                 return false;
  60         return true;
  61 }
  62
  63 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  64 {
  65         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  66                                         PUBLIC_PORT);
  67         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  68
  69         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  70                                                    MFW_PORT(p_hwfn));
  71         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  72                    "port_addr = 0x%x, port_id 0x%02x\n",
  73                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  74 }
  75
  76 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  77 {
  78         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  79         OSAL_BE32 tmp;
  80         u32 i;
  81
  82 #ifndef ASIC_ONLY
  83         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  84                 return;
  85 #endif
  86
  87         if (!p_hwfn->mcp_info->public_base)
  88                 return;
  89
  90         for (i = 0; i < length; i++) {
  91                 tmp = ecore_rd(p_hwfn, p_ptt,
  92                                p_hwfn->mcp_info->mfw_mb_addr +
  93                                (i << 2) + sizeof(u32));
  94
  95                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  96                     OSAL_BE32_TO_CPU(tmp);
  97         }
  98 }
  99
 100 struct ecore_mcp_cmd_elem {
 101         osal_list_entry_t list;
 102         struct ecore_mcp_mb_params *p_mb_params;
 103         u16 expected_seq_num;
 104         bool b_is_completed;
 105 };
 106
 107 /* Must be called while cmd_lock is acquired */
 108 static struct ecore_mcp_cmd_elem *
 109 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 110                        struct ecore_mcp_mb_params *p_mb_params,
 111                        u16 expected_seq_num)
 112 {
 113         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 114
 115         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 116                                  sizeof(*p_cmd_elem));
 117         if (!p_cmd_elem) {
 118                 DP_NOTICE(p_hwfn, false,
 119                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 120                 goto out;
 121         }
 122
 123         p_cmd_elem->p_mb_params = p_mb_params;
 124         p_cmd_elem->expected_seq_num = expected_seq_num;
 125         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 126 out:
 127         return p_cmd_elem;
 128 }
 129
 130 /* Must be called while cmd_lock is acquired */
 131 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 132                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 133 {
 134         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 135         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 136 }
 137
 138 /* Must be called while cmd_lock is acquired */
 139 static struct ecore_mcp_cmd_elem *
 140 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 141 {
 142         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 143
 144         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 145                                  struct ecore_mcp_cmd_elem) {
 146                 if (p_cmd_elem->expected_seq_num == seq_num)
 147                         return p_cmd_elem;
 148         }
 149
 150         return OSAL_NULL;
 151 }
 152
 153 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 154 {
 155         if (p_hwfn->mcp_info) {
 156                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 157
 158                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 159                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 160                                               &p_hwfn->mcp_info->cmd_list, list,
 161                                               struct ecore_mcp_cmd_elem) {
 162                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 163                 }
 164                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 165
 166                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 167                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 168 #ifdef CONFIG_ECORE_LOCK_ALLOC
 169                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 170                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 171 #endif
 172         }
 173
 174         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 175
 176         return ECORE_SUCCESS;
 177 }
 178
 179 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 180                                                    struct ecore_ptt *p_ptt)
 181 {
 182         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 183         u32 drv_mb_offsize, mfw_mb_offsize;
 184         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 185
 186 #ifndef ASIC_ONLY
 187         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 188                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 189                 p_info->public_base = 0;
 190                 return ECORE_INVAL;
 191         }
 192 #endif
 193
 194         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 195         if (!p_info->public_base)
 196                 return ECORE_INVAL;
 197
 198         p_info->public_base |= GRCBASE_MCP;
 199
 200         /* Calculate the driver and MFW mailbox address */
 201         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 202                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 203                                                        PUBLIC_DRV_MB));
 204         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 205         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 206                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 207                    " mcp_pf_id = 0x%x\n",
 208                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 209
 210         /* Set the MFW MB address */
 211         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 212                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 213                                                        PUBLIC_MFW_MB));
 214         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 215         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 216                                                p_info->mfw_mb_addr);
 217
 218         /* Get the current driver mailbox sequence before sending
 219          * the first command
 220          */
 221         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 222             DRV_MSG_SEQ_NUMBER_MASK;
 223
 224         /* Get current FW pulse sequence */
 225         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 226             DRV_PULSE_SEQ_MASK;
 227
 228         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 229
 230         return ECORE_SUCCESS;
 231 }
 232
 233 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 234                                         struct ecore_ptt *p_ptt)
 235 {
 236         struct ecore_mcp_info *p_info;
 237         u32 size;
 238
 239         /* Allocate mcp_info structure */
 240         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 241                                        sizeof(*p_hwfn->mcp_info));
 242         if (!p_hwfn->mcp_info)
 243                 goto err;
 244         p_info = p_hwfn->mcp_info;
 245
 246         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 247                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 248                 /* Do not free mcp_info here, since public_base indicate that
 249                  * the MCP is not initialized
 250                  */
 251                 return ECORE_SUCCESS;
 252         }
 253
 254         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 255         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 256         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 257         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 258                 goto err;
 259
 260         /* Initialize the MFW spinlocks */
 261 #ifdef CONFIG_ECORE_LOCK_ALLOC
 262         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 263         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 264 #endif
 265         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 266         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 267
 268         OSAL_LIST_INIT(&p_info->cmd_list);
 269
 270         return ECORE_SUCCESS;
 271
 272 err:
 273         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 274         ecore_mcp_free(p_hwfn);
 275         return ECORE_NOMEM;
 276 }
 277
 278 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 279                                      struct ecore_ptt *p_ptt)
 280 {
 281         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 282
 283         /* Use MCP history register to check if MCP reset occurred between init
 284          * time and now.
 285          */
 286         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 287                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 288                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 289                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 290
 291                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 292                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 293         }
 294 }
 295
 296 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 297                                      struct ecore_ptt *p_ptt)
 298 {
 299         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 300         enum _ecore_status_t rc = ECORE_SUCCESS;
 301
 302 #ifndef ASIC_ONLY
 303         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 304                 delay = EMUL_MCP_RESP_ITER_US;
 305 #endif
 306
 307         if (p_hwfn->mcp_info->b_block_cmd) {
 308                 DP_NOTICE(p_hwfn, false,
 309                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 310                 return ECORE_ABORTED;
 311         }
 312
 313         /* Ensure that only a single thread is accessing the mailbox */
 314         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 315
 316         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 317
 318         /* Set drv command along with the updated sequence */
 319         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 320         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 321         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 322
 323         do {
 324                 /* Wait for MFW response */
 325                 OSAL_UDELAY(delay);
 326                 /* Give the FW up to 500 second (50*1000*10usec) */
 327         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 328                                                 MISCS_REG_GENERIC_POR_0)) &&
 329                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 330
 331         if (org_mcp_reset_seq !=
 332             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 333                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 334                            "MCP was reset after %d usec\n", cnt * delay);
 335         } else {
 336                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 337                 rc = ECORE_AGAIN;
 338         }
 339
 340         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 341
 342         return rc;
 343 }
 344
 345 /* Must be called while cmd_lock is acquired */
 346 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 347 {
 348         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 349
 350         /* There is at most one pending command at a certain time, and if it
 351          * exists - it is placed at the HEAD of the list.
 352          */
 353         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 354                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 355                                                    struct ecore_mcp_cmd_elem,
 356                                                    list);
 357                 return !p_cmd_elem->b_is_completed;
 358         }
 359
 360         return false;
 361 }
 362
 363 /* Must be called while cmd_lock is acquired */
 364 static enum _ecore_status_t
 365 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 366 {
 367         struct ecore_mcp_mb_params *p_mb_params;
 368         struct ecore_mcp_cmd_elem *p_cmd_elem;
 369         u32 mcp_resp;
 370         u16 seq_num;
 371
 372         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 373         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 374
 375         /* Return if no new non-handled response has been received */
 376         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 377                 return ECORE_AGAIN;
 378
 379         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 380         if (!p_cmd_elem) {
 381                 DP_ERR(p_hwfn,
 382                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 383                        seq_num);
 384                 return ECORE_UNKNOWN_ERROR;
 385         }
 386
 387         p_mb_params = p_cmd_elem->p_mb_params;
 388
 389         /* Get the MFW response along with the sequence number */
 390         p_mb_params->mcp_resp = mcp_resp;
 391
 392         /* Get the MFW param */
 393         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 394
 395         /* Get the union data */
 396         if (p_mb_params->p_data_dst != OSAL_NULL &&
 397             p_mb_params->data_dst_size) {
 398                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 399                                       OFFSETOF(struct public_drv_mb,
 400                                                union_data);
 401                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 402                                   union_data_addr, p_mb_params->data_dst_size);
 403         }
 404
 405         p_cmd_elem->b_is_completed = true;
 406
 407         return ECORE_SUCCESS;
 408 }
 409
 410 /* Must be called while cmd_lock is acquired */
 411 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 412                                       struct ecore_ptt *p_ptt,
 413                                       struct ecore_mcp_mb_params *p_mb_params,
 414                                       u16 seq_num)
 415 {
 416         union drv_union_data union_data;
 417         u32 union_data_addr;
 418
 419         /* Set the union data */
 420         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 421                           OFFSETOF(struct public_drv_mb, union_data);
 422         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 423         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 424                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 425                             p_mb_params->data_src_size);
 426         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 427                         sizeof(union_data));
 428
 429         /* Set the drv param */
 430         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 431
 432         /* Set the drv command along with the sequence number */
 433         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 434
 435         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 436                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 437                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 438 }
 439
 440 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 441                                        bool block_cmd)
 442 {
 443         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 444
 445         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 446                 block_cmd ? "Block" : "Unblock");
 447 }
 448
 449 static enum _ecore_status_t
 450 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 451                          struct ecore_mcp_mb_params *p_mb_params,
 452                          u32 max_retries, u32 delay)
 453 {
 454         struct ecore_mcp_cmd_elem *p_cmd_elem;
 455         u32 cnt = 0;
 456         u16 seq_num;
 457         enum _ecore_status_t rc = ECORE_SUCCESS;
 458
 459         /* Wait until the mailbox is non-occupied */
 460         do {
 461                 /* Exit the loop if there is no pending command, or if the
 462                  * pending command is completed during this iteration.
 463                  * The spinlock stays locked until the command is sent.
 464                  */
 465
 466                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 467
 468                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 469                         break;
 470
 471                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 472                 if (rc == ECORE_SUCCESS)
 473                         break;
 474                 else if (rc != ECORE_AGAIN)
 475                         goto err;
 476
 477                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 478                 OSAL_UDELAY(delay);
 479         } while (++cnt < max_retries);
 480
 481         if (cnt >= max_retries) {
 482                 DP_NOTICE(p_hwfn, false,
 483                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 484                           p_mb_params->cmd, p_mb_params->param);
 485                 return ECORE_AGAIN;
 486         }
 487
 488         /* Send the mailbox command */
 489         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 490         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 491         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 492         if (!p_cmd_elem) {
 493                 rc = ECORE_NOMEM;
 494                 goto err;
 495         }
 496
 497         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 498         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 499
 500         /* Wait for the MFW response */
 501         do {
 502                 /* Exit the loop if the command is already completed, or if the
 503                  * command is completed during this iteration.
 504                  * The spinlock stays locked until the list element is removed.
 505                  */
 506
 507                 OSAL_UDELAY(delay);
 508                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 509
 510                 if (p_cmd_elem->b_is_completed)
 511                         break;
 512
 513                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 514                 if (rc == ECORE_SUCCESS)
 515                         break;
 516                 else if (rc != ECORE_AGAIN)
 517                         goto err;
 518
 519                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 520         } while (++cnt < max_retries);
 521
 522         if (cnt >= max_retries) {
 523                 DP_NOTICE(p_hwfn, false,
 524                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 525                           p_mb_params->cmd, p_mb_params->param);
 526
 527                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 528                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 529                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 530
 531                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 532                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 533                 return ECORE_AGAIN;
 534         }
 535
 536         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 537         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 538
 539         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 540                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 541                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 542                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 543
 544         /* Clear the sequence number from the MFW response */
 545         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 546
 547         return ECORE_SUCCESS;
 548
 549 err:
 550         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 551         return rc;
 552 }
 553
 554 static enum _ecore_status_t
 555 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 556                         struct ecore_ptt *p_ptt,
 557                         struct ecore_mcp_mb_params *p_mb_params)
 558 {
 559         osal_size_t union_data_size = sizeof(union drv_union_data);
 560         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 561         u32 delay = CHIP_MCP_RESP_ITER_US;
 562
 563 #ifndef ASIC_ONLY
 564         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 565                 delay = EMUL_MCP_RESP_ITER_US;
 566         /* There is a built-in delay of 100usec in each MFW response read */
 567         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 568                 max_retries /= 10;
 569 #endif
 570
 571         /* MCP not initialized */
 572         if (!ecore_mcp_is_init(p_hwfn)) {
 573                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 574                 return ECORE_BUSY;
 575         }
 576
 577         if (p_mb_params->data_src_size > union_data_size ||
 578             p_mb_params->data_dst_size > union_data_size) {
 579                 DP_ERR(p_hwfn,
 580                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 581                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 582                        union_data_size);
 583                 return ECORE_INVAL;
 584         }
 585
 586         if (p_hwfn->mcp_info->b_block_cmd) {
 587                 DP_NOTICE(p_hwfn, false,
 588                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 589                           p_mb_params->cmd, p_mb_params->param);
 590                 return ECORE_ABORTED;
 591         }
 592
 593         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 594                                         delay);
 595 }
 596
 597 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 598                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 599                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 600 {
 601         struct ecore_mcp_mb_params mb_params;
 602         enum _ecore_status_t rc;
 603
 604 #ifndef ASIC_ONLY
 605         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 606                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 607                         loaded--;
 608                         loaded_port[p_hwfn->port_id]--;
 609                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 610                                    loaded);
 611                 }
 612                 return ECORE_SUCCESS;
 613         }
 614 #endif
 615
 616         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 617         mb_params.cmd = cmd;
 618         mb_params.param = param;
 619         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 620         if (rc != ECORE_SUCCESS)
 621                 return rc;
 622
 623         *o_mcp_resp = mb_params.mcp_resp;
 624         *o_mcp_param = mb_params.mcp_param;
 625
 626         return ECORE_SUCCESS;
 627 }
 628
 629 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 630                                           struct ecore_ptt *p_ptt,
 631                                           u32 cmd,
 632                                           u32 param,
 633                                           u32 *o_mcp_resp,
 634                                           u32 *o_mcp_param,
 635                                           u32 i_txn_size, u32 *i_buf)
 636 {
 637         struct ecore_mcp_mb_params mb_params;
 638         enum _ecore_status_t rc;
 639
 640         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 641         mb_params.cmd = cmd;
 642         mb_params.param = param;
 643         mb_params.p_data_src = i_buf;
 644         mb_params.data_src_size = (u8)i_txn_size;
 645         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 646         if (rc != ECORE_SUCCESS)
 647                 return rc;
 648
 649         *o_mcp_resp = mb_params.mcp_resp;
 650         *o_mcp_param = mb_params.mcp_param;
 651
 652         return ECORE_SUCCESS;
 653 }
 654
 655 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 656                                           struct ecore_ptt *p_ptt,
 657                                           u32 cmd,
 658                                           u32 param,
 659                                           u32 *o_mcp_resp,
 660                                           u32 *o_mcp_param,
 661                                           u32 *o_txn_size, u32 *o_buf)
 662 {
 663         struct ecore_mcp_mb_params mb_params;
 664         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 665         enum _ecore_status_t rc;
 666
 667         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 668         mb_params.cmd = cmd;
 669         mb_params.param = param;
 670         mb_params.p_data_dst = raw_data;
 671
 672         /* Use the maximal value since the actual one is part of the response */
 673         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 674
 675         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 676         if (rc != ECORE_SUCCESS)
 677                 return rc;
 678
 679         *o_mcp_resp = mb_params.mcp_resp;
 680         *o_mcp_param = mb_params.mcp_param;
 681
 682         *o_txn_size = *o_mcp_param;
 683         /* @DPDK */
 684         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 685
 686         return ECORE_SUCCESS;
 687 }
 688
 689 #ifndef ASIC_ONLY
 690 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 691                                     u32 *p_load_code)
 692 {
 693         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 694
 695         if (!loaded)
 696                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 697         else if (!loaded_port[p_hwfn->port_id])
 698                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 699         else
 700                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 701
 702         /* On CMT, always tell that it's engine */
 703         if (ECORE_IS_CMT(p_hwfn->p_dev))
 704                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 705
 706         *p_load_code = load_phase;
 707         loaded++;
 708         loaded_port[p_hwfn->port_id]++;
 709
 710         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 711                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 712                    *p_load_code, loaded, p_hwfn->port_id,
 713                    loaded_port[p_hwfn->port_id]);
 714 }
 715 #endif
 716
 717 static bool
 718 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 719                          enum ecore_override_force_load override_force_load)
 720 {
 721         bool can_force_load = false;
 722
 723         switch (override_force_load) {
 724         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 725                 can_force_load = true;
 726                 break;
 727         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 728                 can_force_load = false;
 729                 break;
 730         default:
 731                 can_force_load = (drv_role == DRV_ROLE_OS &&
 732                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 733                                  (drv_role == DRV_ROLE_KDUMP &&
 734                                   exist_drv_role == DRV_ROLE_OS);
 735                 break;
 736         }
 737
 738         return can_force_load;
 739 }
 740
 741 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 742                                                       struct ecore_ptt *p_ptt)
 743 {
 744         u32 resp = 0, param = 0;
 745         enum _ecore_status_t rc;
 746
 747         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 748                            &resp, &param);
 749         if (rc != ECORE_SUCCESS)
 750                 DP_NOTICE(p_hwfn, false,
 751                           "Failed to send cancel load request, rc = %d\n", rc);
 752
 753         return rc;
 754 }
 755
 756 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 757 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 758 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 759 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 760 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 761 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 762 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 763
 764 static u32 ecore_get_config_bitmap(void)
 765 {
 766         u32 config_bitmap = 0x0;
 767
 768 #ifdef CONFIG_ECORE_L2
 769         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 770 #endif
 771 #ifdef CONFIG_ECORE_SRIOV
 772         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 773 #endif
 774 #ifdef CONFIG_ECORE_ROCE
 775         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 776 #endif
 777 #ifdef CONFIG_ECORE_IWARP
 778         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 779 #endif
 780 #ifdef CONFIG_ECORE_FCOE
 781         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 782 #endif
 783 #ifdef CONFIG_ECORE_ISCSI
 784         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 785 #endif
 786 #ifdef CONFIG_ECORE_LL2
 787         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 788 #endif
 789
 790         return config_bitmap;
 791 }
 792
 793 struct ecore_load_req_in_params {
 794         u8 hsi_ver;
 795 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 796 #define ECORE_LOAD_REQ_HSI_VER_1        1
 797         u32 drv_ver_0;
 798         u32 drv_ver_1;
 799         u32 fw_ver;
 800         u8 drv_role;
 801         u8 timeout_val;
 802         u8 force_cmd;
 803         bool avoid_eng_reset;
 804 };
 805
 806 struct ecore_load_req_out_params {
 807         u32 load_code;
 808         u32 exist_drv_ver_0;
 809         u32 exist_drv_ver_1;
 810         u32 exist_fw_ver;
 811         u8 exist_drv_role;
 812         u8 mfw_hsi_ver;
 813         bool drv_exists;
 814 };
 815
 816 static enum _ecore_status_t
 817 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 818                      struct ecore_load_req_in_params *p_in_params,
 819                      struct ecore_load_req_out_params *p_out_params)
 820 {
 821         struct ecore_mcp_mb_params mb_params;
 822         struct load_req_stc load_req;
 823         struct load_rsp_stc load_rsp;
 824         u32 hsi_ver;
 825         enum _ecore_status_t rc;
 826
 827         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 828         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 829         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 830         load_req.fw_ver = p_in_params->fw_ver;
 831         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 832         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 833                       p_in_params->timeout_val);
 834         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 835         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 836                       p_in_params->avoid_eng_reset);
 837
 838         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 839                   DRV_ID_MCP_HSI_VER_CURRENT :
 840                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 841
 842         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 843         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 844         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 845         mb_params.p_data_src = &load_req;
 846         mb_params.data_src_size = sizeof(load_req);
 847         mb_params.p_data_dst = &load_rsp;
 848         mb_params.data_dst_size = sizeof(load_rsp);
 849
 850         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 851                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 852                    mb_params.param,
 853                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 854                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 855                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 856                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 857
 858         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 859                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 860                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 861                            load_req.drv_ver_0, load_req.drv_ver_1,
 862                            load_req.fw_ver, load_req.misc0,
 863                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 864                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 865                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 866                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 867
 868         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 869         if (rc != ECORE_SUCCESS) {
 870                 DP_NOTICE(p_hwfn, false,
 871                           "Failed to send load request, rc = %d\n", rc);
 872                 return rc;
 873         }
 874
 875         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 876                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 877         p_out_params->load_code = mb_params.mcp_resp;
 878
 879         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 880             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 881                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 882                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 883                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 884                            load_rsp.fw_ver, load_rsp.misc0,
 885                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 886                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 887                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 888
 889                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 890                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 891                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 892                 p_out_params->exist_drv_role =
 893                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 894                 p_out_params->mfw_hsi_ver =
 895                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 896                 p_out_params->drv_exists =
 897                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 898                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 899         }
 900
 901         return ECORE_SUCCESS;
 902 }
 903
 904 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 905                                    u8 *p_mfw_drv_role)
 906 {
 907         switch (drv_role) {
 908         case ECORE_DRV_ROLE_OS:
 909                 *p_mfw_drv_role = DRV_ROLE_OS;
 910                 break;
 911         case ECORE_DRV_ROLE_KDUMP:
 912                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 913                 break;
 914         }
 915 }
 916
 917 enum ecore_load_req_force {
 918         ECORE_LOAD_REQ_FORCE_NONE,
 919         ECORE_LOAD_REQ_FORCE_PF,
 920         ECORE_LOAD_REQ_FORCE_ALL,
 921 };
 922
 923 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 924                                     u8 *p_mfw_force_cmd)
 925 {
 926         switch (force_cmd) {
 927         case ECORE_LOAD_REQ_FORCE_NONE:
 928                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 929                 break;
 930         case ECORE_LOAD_REQ_FORCE_PF:
 931                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 932                 break;
 933         case ECORE_LOAD_REQ_FORCE_ALL:
 934                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 935                 break;
 936         }
 937 }
 938
 939 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 940                                         struct ecore_ptt *p_ptt,
 941                                         struct ecore_load_req_params *p_params)
 942 {
 943         struct ecore_load_req_out_params out_params;
 944         struct ecore_load_req_in_params in_params;
 945         u8 mfw_drv_role = 0, mfw_force_cmd;
 946         enum _ecore_status_t rc;
 947
 948 #ifndef ASIC_ONLY
 949         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 950                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 951                 return ECORE_SUCCESS;
 952         }
 953 #endif
 954
 955         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 956         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 957         in_params.drv_ver_0 = ECORE_VERSION;
 958         in_params.drv_ver_1 = ecore_get_config_bitmap();
 959         in_params.fw_ver = STORM_FW_VERSION;
 960         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 961         in_params.drv_role = mfw_drv_role;
 962         in_params.timeout_val = p_params->timeout_val;
 963         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 964         in_params.force_cmd = mfw_force_cmd;
 965         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 966
 967         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 968         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 969         if (rc != ECORE_SUCCESS)
 970                 return rc;
 971
 972         /* First handle cases where another load request should/might be sent:
 973          * - MFW expects the old interface [HSI version = 1]
 974          * - MFW responds that a force load request is required
 975          */
 976         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 977                 DP_INFO(p_hwfn,
 978                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 979
 980                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 981                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 982                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 983                                           &out_params);
 984                 if (rc != ECORE_SUCCESS)
 985                         return rc;
 986         } else if (out_params.load_code ==
 987                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 988                 if (ecore_mcp_can_force_load(in_params.drv_role,
 989                                              out_params.exist_drv_role,
 990                                              p_params->override_force_load)) {
 991                         DP_INFO(p_hwfn,
 992                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 993                                 in_params.drv_role, in_params.fw_ver,
 994                                 in_params.drv_ver_0, in_params.drv_ver_1,
 995                                 out_params.exist_drv_role,
 996                                 out_params.exist_fw_ver,
 997                                 out_params.exist_drv_ver_0,
 998                                 out_params.exist_drv_ver_1);
 999
1000                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1001                                                 &mfw_force_cmd);
1002
1003                         in_params.force_cmd = mfw_force_cmd;
1004                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1005                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1006                                                   &out_params);
1007                         if (rc != ECORE_SUCCESS)
1008                                 return rc;
1009                 } else {
1010                         DP_NOTICE(p_hwfn, false,
1011                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1012                                   in_params.drv_role, in_params.fw_ver,
1013                                   in_params.drv_ver_0, in_params.drv_ver_1,
1014                                   out_params.exist_drv_role,
1015                                   out_params.exist_fw_ver,
1016                                   out_params.exist_drv_ver_0,
1017                                   out_params.exist_drv_ver_1);
1018
1019                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1020                         return ECORE_BUSY;
1021                 }
1022         }
1023
1024         /* Now handle the other types of responses.
1025          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1026          * expected here after the additional revised load requests were sent.
1027          */
1028         switch (out_params.load_code) {
1029         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1030         case FW_MSG_CODE_DRV_LOAD_PORT:
1031         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1032                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1033                     out_params.drv_exists) {
1034                         /* The role and fw/driver version match, but the PF is
1035                          * already loaded and has not been unloaded gracefully.
1036                          * This is unexpected since a quasi-FLR request was
1037                          * previously sent as part of ecore_hw_prepare().
1038                          */
1039                         DP_NOTICE(p_hwfn, false,
1040                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1041                         return ECORE_INVAL;
1042                 }
1043                 break;
1044         default:
1045                 DP_NOTICE(p_hwfn, false,
1046                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1047                           out_params.load_code);
1048                 return ECORE_BUSY;
1049         }
1050
1051         p_params->load_code = out_params.load_code;
1052
1053         return ECORE_SUCCESS;
1054 }
1055
1056 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1057                                          struct ecore_ptt *p_ptt)
1058 {
1059         u32 resp = 0, param = 0;
1060         enum _ecore_status_t rc;
1061
1062         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1063                            &param);
1064         if (rc != ECORE_SUCCESS) {
1065                 DP_NOTICE(p_hwfn, false,
1066                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1067                 return rc;
1068         }
1069
1070 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR     (1 << 0)
1071
1072         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1073         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1074                 DP_NOTICE(p_hwfn, false,
1075                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1076
1077         return ECORE_SUCCESS;
1078 }
1079
1080 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1081                                           struct ecore_ptt *p_ptt)
1082 {
1083         u32 wol_param, mcp_resp, mcp_param;
1084
1085         /* @DPDK */
1086         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1087
1088         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1089                              &mcp_resp, &mcp_param);
1090 }
1091
1092 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1093                                            struct ecore_ptt *p_ptt)
1094 {
1095         struct ecore_mcp_mb_params mb_params;
1096         struct mcp_mac wol_mac;
1097
1098         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1099         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1100
1101         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1102 }
1103
1104 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1105                                     struct ecore_ptt *p_ptt)
1106 {
1107         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1108                                         PUBLIC_PATH);
1109         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1110         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1111                                      ECORE_PATH_ID(p_hwfn));
1112         u32 disabled_vfs[VF_MAX_STATIC / 32];
1113         int i;
1114
1115         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1116                    "Reading Disabled VF information from [offset %08x],"
1117                    " path_addr %08x\n",
1118                    mfw_path_offsize, path_addr);
1119
1120         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1121                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1122                                            path_addr +
1123                                            OFFSETOF(struct public_path,
1124                                                     mcp_vf_disabled) +
1125                                            sizeof(u32) * i);
1126                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1127                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1128                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1129         }
1130
1131         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1132                 OSAL_VF_FLR_UPDATE(p_hwfn);
1133 }
1134
1135 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1136                                           struct ecore_ptt *p_ptt,
1137                                           u32 *vfs_to_ack)
1138 {
1139         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1140                                         PUBLIC_FUNC);
1141         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1142         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1143                                      MCP_PF_ID(p_hwfn));
1144         struct ecore_mcp_mb_params mb_params;
1145         enum _ecore_status_t rc;
1146         int i;
1147
1148         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1149                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1150                            "Acking VFs [%08x,...,%08x] - %08x\n",
1151                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1152
1153         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1154         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1155         mb_params.p_data_src = vfs_to_ack;
1156         mb_params.data_src_size = VF_MAX_STATIC / 8;
1157         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1158                                      &mb_params);
1159         if (rc != ECORE_SUCCESS) {
1160                 DP_NOTICE(p_hwfn, false,
1161                           "Failed to pass ACK for VF flr to MFW\n");
1162                 return ECORE_TIMEOUT;
1163         }
1164
1165         /* TMP - clear the ACK bits; should be done by MFW */
1166         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1167                 ecore_wr(p_hwfn, p_ptt,
1168                          func_addr +
1169                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1170                          i * sizeof(u32), 0);
1171
1172         return rc;
1173 }
1174
1175 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1176                                                 struct ecore_ptt *p_ptt)
1177 {
1178         u32 transceiver_state;
1179
1180         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1181                                      p_hwfn->mcp_info->port_addr +
1182                                      OFFSETOF(struct public_port,
1183                                               transceiver_data));
1184
1185         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1186                    "Received transceiver state update [0x%08x] from mfw"
1187                    " [Addr 0x%x]\n",
1188                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1189                                             OFFSETOF(struct public_port,
1190                                                      transceiver_data)));
1191
1192         transceiver_state = GET_MFW_FIELD(transceiver_state,
1193                                           ETH_TRANSCEIVER_STATE);
1194
1195         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1196                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1197         else
1198                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1199 }
1200
1201 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1202                                       struct ecore_ptt *p_ptt,
1203                                       struct ecore_mcp_link_state *p_link)
1204 {
1205         u32 eee_status, val;
1206
1207         p_link->eee_adv_caps = 0;
1208         p_link->eee_lp_adv_caps = 0;
1209         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1210                                      OFFSETOF(struct public_port, eee_status));
1211         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1212         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1213         if (val & EEE_1G_ADV)
1214                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1215         if (val & EEE_10G_ADV)
1216                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1217         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1218         if (val & EEE_1G_ADV)
1219                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1220         if (val & EEE_10G_ADV)
1221                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1222 }
1223
1224 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1225                                          struct ecore_ptt *p_ptt,
1226                                          bool b_reset)
1227 {
1228         struct ecore_mcp_link_state *p_link;
1229         u8 max_bw, min_bw;
1230         u32 status = 0;
1231
1232         /* Prevent SW/attentions from doing this at the same time */
1233         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1234
1235         p_link = &p_hwfn->mcp_info->link_output;
1236         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1237         if (!b_reset) {
1238                 status = ecore_rd(p_hwfn, p_ptt,
1239                                   p_hwfn->mcp_info->port_addr +
1240                                   OFFSETOF(struct public_port, link_status));
1241                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1242                            "Received link update [0x%08x] from mfw"
1243                            " [Addr 0x%x]\n",
1244                            status, (u32)(p_hwfn->mcp_info->port_addr +
1245                                           OFFSETOF(struct public_port,
1246                                                    link_status)));
1247         } else {
1248                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1249                            "Resetting link indications\n");
1250                 goto out;
1251         }
1252
1253         if (p_hwfn->b_drv_link_init)
1254                 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1255         else
1256                 p_link->link_up = false;
1257
1258         p_link->full_duplex = true;
1259         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1260         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1261                 p_link->speed = 100000;
1262                 break;
1263         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1264                 p_link->speed = 50000;
1265                 break;
1266         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1267                 p_link->speed = 40000;
1268                 break;
1269         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1270                 p_link->speed = 25000;
1271                 break;
1272         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1273                 p_link->speed = 20000;
1274                 break;
1275         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1276                 p_link->speed = 10000;
1277                 break;
1278         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1279                 p_link->full_duplex = false;
1280                 /* Fall-through */
1281         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1282                 p_link->speed = 1000;
1283                 break;
1284         default:
1285                 p_link->speed = 0;
1286         }
1287
1288         /* We never store total line speed as p_link->speed is
1289          * again changes according to bandwidth allocation.
1290          */
1291         if (p_link->link_up && p_link->speed)
1292                 p_link->line_speed = p_link->speed;
1293         else
1294                 p_link->line_speed = 0;
1295
1296         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1297         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1298
1299         /* Max bandwidth configuration */
1300         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1301                                            p_link, max_bw);
1302
1303         /* Mintz bandwidth configuration */
1304         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1305                                            p_link, min_bw);
1306         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1307                                               p_link->min_pf_rate);
1308
1309         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1310         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1311         p_link->parallel_detection = !!(status &
1312                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1313         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1314
1315         p_link->partner_adv_speed |=
1316             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1317             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1318         p_link->partner_adv_speed |=
1319             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1320             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1321         p_link->partner_adv_speed |=
1322             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1323             ECORE_LINK_PARTNER_SPEED_10G : 0;
1324         p_link->partner_adv_speed |=
1325             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1326             ECORE_LINK_PARTNER_SPEED_20G : 0;
1327         p_link->partner_adv_speed |=
1328             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1329             ECORE_LINK_PARTNER_SPEED_25G : 0;
1330         p_link->partner_adv_speed |=
1331             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1332             ECORE_LINK_PARTNER_SPEED_40G : 0;
1333         p_link->partner_adv_speed |=
1334             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1335             ECORE_LINK_PARTNER_SPEED_50G : 0;
1336         p_link->partner_adv_speed |=
1337             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1338             ECORE_LINK_PARTNER_SPEED_100G : 0;
1339
1340         p_link->partner_tx_flow_ctrl_en =
1341             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1342         p_link->partner_rx_flow_ctrl_en =
1343             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1344
1345         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1346         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1347                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1348                 break;
1349         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1350                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1351                 break;
1352         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1353                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1354                 break;
1355         default:
1356                 p_link->partner_adv_pause = 0;
1357         }
1358
1359         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1360
1361         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1362                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1363
1364         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1365 out:
1366         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1367 }
1368
1369 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1370                                         struct ecore_ptt *p_ptt, bool b_up)
1371 {
1372         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1373         struct ecore_mcp_mb_params mb_params;
1374         struct eth_phy_cfg phy_cfg;
1375         enum _ecore_status_t rc = ECORE_SUCCESS;
1376         u32 cmd;
1377
1378 #ifndef ASIC_ONLY
1379         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1380                 return ECORE_SUCCESS;
1381 #endif
1382
1383         /* Set the shmem configuration according to params */
1384         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1385         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1386         if (!params->speed.autoneg)
1387                 phy_cfg.speed = params->speed.forced_speed;
1388         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1389         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1390         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1391         phy_cfg.adv_speed = params->speed.advertised_speeds;
1392         phy_cfg.loopback_mode = params->loopback_mode;
1393
1394         /* There are MFWs that share this capability regardless of whether
1395          * this is feasible or not. And given that at the very least adv_caps
1396          * would be set internally by ecore, we want to make sure LFA would
1397          * still work.
1398          */
1399         if ((p_hwfn->mcp_info->capabilities &
1400              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1401             params->eee.enable) {
1402                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1403                 if (params->eee.tx_lpi_enable)
1404                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1405                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1406                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1407                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1408                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1409                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1410                                     EEE_TX_TIMER_USEC_OFFSET) &
1411                                         EEE_TX_TIMER_USEC_MASK;
1412         }
1413
1414         p_hwfn->b_drv_link_init = b_up;
1415
1416         if (b_up)
1417                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1418                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1419                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1420                            phy_cfg.loopback_mode);
1421         else
1422                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1423
1424         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1425         mb_params.cmd = cmd;
1426         mb_params.p_data_src = &phy_cfg;
1427         mb_params.data_src_size = sizeof(phy_cfg);
1428         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1429
1430         /* if mcp fails to respond we must abort */
1431         if (rc != ECORE_SUCCESS) {
1432                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1433                 return rc;
1434         }
1435
1436         /* Mimic link-change attention, done for several reasons:
1437          *  - On reset, there's no guarantee MFW would trigger
1438          *    an attention.
1439          *  - On initialization, older MFWs might not indicate link change
1440          *    during LFA, so we'll never get an UP indication.
1441          */
1442         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1443
1444         return ECORE_SUCCESS;
1445 }
1446
1447 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1448                                    struct ecore_ptt *p_ptt)
1449 {
1450         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1451
1452         /* TODO - Add support for VFs */
1453         if (IS_VF(p_hwfn->p_dev))
1454                 return ECORE_INVAL;
1455
1456         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1457                                                  PUBLIC_PATH);
1458         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1459         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1460
1461         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1462                                  path_addr +
1463                                  OFFSETOF(struct public_path, process_kill)) &
1464             PROCESS_KILL_COUNTER_MASK;
1465
1466         return proc_kill_cnt;
1467 }
1468
1469 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1470                                           struct ecore_ptt *p_ptt)
1471 {
1472         struct ecore_dev *p_dev = p_hwfn->p_dev;
1473         u32 proc_kill_cnt;
1474
1475         /* Prevent possible attentions/interrupts during the recovery handling
1476          * and till its load phase, during which they will be re-enabled.
1477          */
1478         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1479
1480         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1481
1482         /* The following operations should be done once, and thus in CMT mode
1483          * are carried out by only the first HW function.
1484          */
1485         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1486                 return;
1487
1488         if (p_dev->recov_in_prog) {
1489                 DP_NOTICE(p_hwfn, false,
1490                           "Ignoring the indication since a recovery"
1491                           " process is already in progress\n");
1492                 return;
1493         }
1494
1495         p_dev->recov_in_prog = true;
1496
1497         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1498         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1499
1500         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1501 }
1502
1503 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1504                                           struct ecore_ptt *p_ptt,
1505                                           enum MFW_DRV_MSG_TYPE type)
1506 {
1507         enum ecore_mcp_protocol_type stats_type;
1508         union ecore_mcp_protocol_stats stats;
1509         struct ecore_mcp_mb_params mb_params;
1510         u32 hsi_param;
1511         enum _ecore_status_t rc;
1512
1513         switch (type) {
1514         case MFW_DRV_MSG_GET_LAN_STATS:
1515                 stats_type = ECORE_MCP_LAN_STATS;
1516                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1517                 break;
1518         default:
1519                 DP_INFO(p_hwfn, "Invalid protocol type %d\n", type);
1520                 return;
1521         }
1522
1523         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1524
1525         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1526         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1527         mb_params.param = hsi_param;
1528         mb_params.p_data_src = &stats;
1529         mb_params.data_src_size = sizeof(stats);
1530         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1531         if (rc != ECORE_SUCCESS)
1532                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1533 }
1534
1535 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1536                                     struct public_func *p_shmem_info)
1537 {
1538         struct ecore_mcp_function_info *p_info;
1539
1540         p_info = &p_hwfn->mcp_info->func_info;
1541
1542         /* TODO - bandwidth min/max should have valid values of 1-100,
1543          * as well as some indication that the feature is disabled.
1544          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1545          * limit and correct value to min `1' and max `100' if limit isn't in
1546          * range.
1547          */
1548         p_info->bandwidth_min = (p_shmem_info->config &
1549                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1550             FUNC_MF_CFG_MIN_BW_OFFSET;
1551         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1552                 DP_INFO(p_hwfn,
1553                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1554                         p_info->bandwidth_min);
1555                 p_info->bandwidth_min = 1;
1556         }
1557
1558         p_info->bandwidth_max = (p_shmem_info->config &
1559                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1560             FUNC_MF_CFG_MAX_BW_OFFSET;
1561         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1562                 DP_INFO(p_hwfn,
1563                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1564                         p_info->bandwidth_max);
1565                 p_info->bandwidth_max = 100;
1566         }
1567 }
1568
1569 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1570                                     struct ecore_ptt *p_ptt,
1571                                     struct public_func *p_data,
1572                                     int pfid)
1573 {
1574         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1575                                         PUBLIC_FUNC);
1576         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1577         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1578         u32 i, size;
1579
1580         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1581
1582         size = OSAL_MIN_T(u32, sizeof(*p_data),
1583                           SECTION_SIZE(mfw_path_offsize));
1584         for (i = 0; i < size / sizeof(u32); i++)
1585                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1586                                               func_addr + (i << 2));
1587
1588         return size;
1589 }
1590
1591 static void
1592 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1593 {
1594         struct ecore_mcp_function_info *p_info;
1595         struct public_func shmem_info;
1596         u32 resp = 0, param = 0;
1597
1598         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1599
1600         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1601
1602         p_info = &p_hwfn->mcp_info->func_info;
1603
1604         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1605
1606         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1607
1608         /* Acknowledge the MFW */
1609         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1610                       &param);
1611 }
1612
1613 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1614 {
1615         /* A single notification should be sent to upper driver in CMT mode */
1616         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1617                 return;
1618
1619         DP_NOTICE(p_hwfn, false,
1620                   "Fan failure was detected on the network interface card"
1621                   " and it's going to be shut down.\n");
1622
1623         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1624 }
1625
1626 struct ecore_mdump_cmd_params {
1627         u32 cmd;
1628         void *p_data_src;
1629         u8 data_src_size;
1630         void *p_data_dst;
1631         u8 data_dst_size;
1632         u32 mcp_resp;
1633 };
1634
1635 static enum _ecore_status_t
1636 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1637                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1638 {
1639         struct ecore_mcp_mb_params mb_params;
1640         enum _ecore_status_t rc;
1641
1642         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1643         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1644         mb_params.param = p_mdump_cmd_params->cmd;
1645         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1646         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1647         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1648         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1649         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1650         if (rc != ECORE_SUCCESS)
1651                 return rc;
1652
1653         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1654
1655         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1656                 DP_INFO(p_hwfn,
1657                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1658                         p_mdump_cmd_params->cmd);
1659                 rc = ECORE_NOTIMPL;
1660         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1661                 DP_INFO(p_hwfn,
1662                         "The mdump command is not supported by the MFW\n");
1663                 rc = ECORE_NOTIMPL;
1664         }
1665
1666         return rc;
1667 }
1668
1669 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1670                                                 struct ecore_ptt *p_ptt)
1671 {
1672         struct ecore_mdump_cmd_params mdump_cmd_params;
1673
1674         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1675         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1676
1677         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1678 }
1679
1680 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1681                                                 struct ecore_ptt *p_ptt,
1682                                                 u32 epoch)
1683 {
1684         struct ecore_mdump_cmd_params mdump_cmd_params;
1685
1686         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1687         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1688         mdump_cmd_params.p_data_src = &epoch;
1689         mdump_cmd_params.data_src_size = sizeof(epoch);
1690
1691         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1692 }
1693
1694 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1695                                              struct ecore_ptt *p_ptt)
1696 {
1697         struct ecore_mdump_cmd_params mdump_cmd_params;
1698
1699         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1700         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1701
1702         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1703 }
1704
1705 static enum _ecore_status_t
1706 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1707                            struct mdump_config_stc *p_mdump_config)
1708 {
1709         struct ecore_mdump_cmd_params mdump_cmd_params;
1710         enum _ecore_status_t rc;
1711
1712         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1713         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1714         mdump_cmd_params.p_data_dst = p_mdump_config;
1715         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1716
1717         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1718         if (rc != ECORE_SUCCESS)
1719                 return rc;
1720
1721         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1722                 DP_INFO(p_hwfn,
1723                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1724                         mdump_cmd_params.mcp_resp);
1725                 rc = ECORE_UNKNOWN_ERROR;
1726         }
1727
1728         return rc;
1729 }
1730
1731 enum _ecore_status_t
1732 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1733                          struct ecore_mdump_info *p_mdump_info)
1734 {
1735         u32 addr, global_offsize, global_addr;
1736         struct mdump_config_stc mdump_config;
1737         enum _ecore_status_t rc;
1738
1739         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1740
1741         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1742                                     PUBLIC_GLOBAL);
1743         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1744         global_addr = SECTION_ADDR(global_offsize, 0);
1745         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1746                                         global_addr +
1747                                         OFFSETOF(struct public_global,
1748                                                  mdump_reason));
1749
1750         if (p_mdump_info->reason) {
1751                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1752                 if (rc != ECORE_SUCCESS)
1753                         return rc;
1754
1755                 p_mdump_info->version = mdump_config.version;
1756                 p_mdump_info->config = mdump_config.config;
1757                 p_mdump_info->epoch = mdump_config.epoc;
1758                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1759                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1760
1761                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1762                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1763                            p_mdump_info->reason, p_mdump_info->version,
1764                            p_mdump_info->config, p_mdump_info->epoch,
1765                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1766         } else {
1767                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1768                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1769         }
1770
1771         return ECORE_SUCCESS;
1772 }
1773
1774 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1775                                                 struct ecore_ptt *p_ptt)
1776 {
1777         struct ecore_mdump_cmd_params mdump_cmd_params;
1778
1779         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1780         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1781
1782         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1783 }
1784
1785 enum _ecore_status_t
1786 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1787                            struct ecore_mdump_retain_data *p_mdump_retain)
1788 {
1789         struct ecore_mdump_cmd_params mdump_cmd_params;
1790         struct mdump_retain_data_stc mfw_mdump_retain;
1791         enum _ecore_status_t rc;
1792
1793         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1794         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1795         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1796         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1797
1798         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1799         if (rc != ECORE_SUCCESS)
1800                 return rc;
1801
1802         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1803                 DP_INFO(p_hwfn,
1804                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1805                         mdump_cmd_params.mcp_resp);
1806                 return ECORE_UNKNOWN_ERROR;
1807         }
1808
1809         p_mdump_retain->valid = mfw_mdump_retain.valid;
1810         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1811         p_mdump_retain->pf = mfw_mdump_retain.pf;
1812         p_mdump_retain->status = mfw_mdump_retain.status;
1813
1814         return ECORE_SUCCESS;
1815 }
1816
1817 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1818                                                 struct ecore_ptt *p_ptt)
1819 {
1820         struct ecore_mdump_cmd_params mdump_cmd_params;
1821
1822         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1823         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1824
1825         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1826 }
1827
1828 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1829                                             struct ecore_ptt *p_ptt)
1830 {
1831         struct ecore_mdump_retain_data mdump_retain;
1832         enum _ecore_status_t rc;
1833
1834         /* In CMT mode - no need for more than a single acknowledgment to the
1835          * MFW, and no more than a single notification to the upper driver.
1836          */
1837         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1838                 return;
1839
1840         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1841         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1842                 DP_NOTICE(p_hwfn, false,
1843                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1844                           mdump_retain.epoch, mdump_retain.pf,
1845                           mdump_retain.status);
1846         } else {
1847                 DP_NOTICE(p_hwfn, false,
1848                           "The MFW notified that a critical error occurred in the device\n");
1849         }
1850
1851         if (p_hwfn->p_dev->allow_mdump) {
1852                 DP_NOTICE(p_hwfn, false,
1853                           "Not acknowledging the notification to allow the MFW crash dump\n");
1854                 return;
1855         }
1856
1857         DP_NOTICE(p_hwfn, false,
1858                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1859         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1860         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1861 }
1862
1863 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1864                                              struct ecore_ptt *p_ptt)
1865 {
1866         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1867         enum _ecore_status_t rc = ECORE_SUCCESS;
1868         bool found = false;
1869         u16 i;
1870
1871         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1872
1873         /* Read Messages from MFW */
1874         ecore_mcp_read_mb(p_hwfn, p_ptt);
1875
1876         /* Compare current messages to old ones */
1877         for (i = 0; i < info->mfw_mb_length; i++) {
1878                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1879                         continue;
1880
1881                 found = true;
1882
1883                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1884                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1885                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1886
1887                 switch (i) {
1888                 case MFW_DRV_MSG_LINK_CHANGE:
1889                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1890                         break;
1891                 case MFW_DRV_MSG_VF_DISABLED:
1892                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1893                         break;
1894                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1895                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1896                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1897                         break;
1898                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1899                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1900                                                     ECORE_DCBX_REMOTE_MIB);
1901                         break;
1902                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1903                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1904                                                     ECORE_DCBX_OPERATIONAL_MIB);
1905                         break;
1906                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1907                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1908                         break;
1909                 case MFW_DRV_MSG_ERROR_RECOVERY:
1910                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
1911                         break;
1912                 case MFW_DRV_MSG_GET_LAN_STATS:
1913                 case MFW_DRV_MSG_GET_FCOE_STATS:
1914                 case MFW_DRV_MSG_GET_ISCSI_STATS:
1915                 case MFW_DRV_MSG_GET_RDMA_STATS:
1916                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1917                         break;
1918                 case MFW_DRV_MSG_BW_UPDATE:
1919                         ecore_mcp_update_bw(p_hwfn, p_ptt);
1920                         break;
1921                 case MFW_DRV_MSG_FAILURE_DETECTED:
1922                         ecore_mcp_handle_fan_failure(p_hwfn);
1923                         break;
1924                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
1925                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
1926                         break;
1927                 default:
1928                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1929                         rc = ECORE_INVAL;
1930                 }
1931         }
1932
1933         /* ACK everything */
1934         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1935                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
1936
1937                 /* MFW expect answer in BE, so we force write in that format */
1938                 ecore_wr(p_hwfn, p_ptt,
1939                          info->mfw_mb_addr + sizeof(u32) +
1940                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1941                          sizeof(u32) + i * sizeof(u32), val);
1942         }
1943
1944         if (!found) {
1945                 DP_NOTICE(p_hwfn, false,
1946                           "Received an MFW message indication but no"
1947                           " new message!\n");
1948                 rc = ECORE_INVAL;
1949         }
1950
1951         /* Copy the new mfw messages into the shadow */
1952         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1953
1954         return rc;
1955 }
1956
1957 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
1958                                            struct ecore_ptt *p_ptt,
1959                                            u32 *p_mfw_ver,
1960                                            u32 *p_running_bundle_id)
1961 {
1962         u32 global_offsize;
1963
1964 #ifndef ASIC_ONLY
1965         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
1966                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
1967                 return ECORE_SUCCESS;
1968         }
1969 #endif
1970
1971         if (IS_VF(p_hwfn->p_dev)) {
1972                 if (p_hwfn->vf_iov_info) {
1973                         struct pfvf_acquire_resp_tlv *p_resp;
1974
1975                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1976                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1977                         return ECORE_SUCCESS;
1978                 } else {
1979                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
1980                                    "VF requested MFW version prior to ACQUIRE\n");
1981                         return ECORE_INVAL;
1982                 }
1983         }
1984
1985         global_offsize = ecore_rd(p_hwfn, p_ptt,
1986                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
1987                                                        public_base,
1988                                                        PUBLIC_GLOBAL));
1989         *p_mfw_ver =
1990             ecore_rd(p_hwfn, p_ptt,
1991                      SECTION_ADDR(global_offsize,
1992                                   0) + OFFSETOF(struct public_global, mfw_ver));
1993
1994         if (p_running_bundle_id != OSAL_NULL) {
1995                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
1996                                                 SECTION_ADDR(global_offsize,
1997                                                              0) +
1998                                                 OFFSETOF(struct public_global,
1999                                                          running_bundle_id));
2000         }
2001
2002         return ECORE_SUCCESS;
2003 }
2004
2005 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2006                                               struct ecore_ptt *p_ptt,
2007                                               u32 *p_media_type)
2008 {
2009
2010         /* TODO - Add support for VFs */
2011         if (IS_VF(p_hwfn->p_dev))
2012                 return ECORE_INVAL;
2013
2014         if (!ecore_mcp_is_init(p_hwfn)) {
2015                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2016                 return ECORE_BUSY;
2017         }
2018
2019         if (!p_ptt) {
2020                 *p_media_type = MEDIA_UNSPECIFIED;
2021                 return ECORE_INVAL;
2022         } else {
2023                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2024                                          p_hwfn->mcp_info->port_addr +
2025                                          OFFSETOF(struct public_port,
2026                                                   media_type));
2027         }
2028
2029         return ECORE_SUCCESS;
2030 }
2031
2032 /* @DPDK */
2033 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2034 static void
2035 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2036                                  enum ecore_pci_personality *p_proto)
2037 {
2038         *p_proto = ECORE_PCI_ETH;
2039
2040         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2041                    "According to Legacy capabilities, L2 personality is %08x\n",
2042                    (u32)*p_proto);
2043 }
2044
2045 /* @DPDK */
2046 static enum _ecore_status_t
2047 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2048                               struct ecore_ptt *p_ptt,
2049                               enum ecore_pci_personality *p_proto)
2050 {
2051         u32 resp = 0, param = 0;
2052         enum _ecore_status_t rc;
2053
2054         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2055                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2056                    (u32)*p_proto, resp, param);
2057         return ECORE_SUCCESS;
2058 }
2059
2060 static enum _ecore_status_t
2061 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2062                           struct public_func *p_info,
2063                           struct ecore_ptt *p_ptt,
2064                           enum ecore_pci_personality *p_proto)
2065 {
2066         enum _ecore_status_t rc = ECORE_SUCCESS;
2067
2068         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2069         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2070                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2071                     ECORE_SUCCESS)
2072                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2073                 break;
2074         default:
2075                 rc = ECORE_INVAL;
2076         }
2077
2078         return rc;
2079 }
2080
2081 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2082                                                     struct ecore_ptt *p_ptt)
2083 {
2084         struct ecore_mcp_function_info *info;
2085         struct public_func shmem_info;
2086
2087         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2088         info = &p_hwfn->mcp_info->func_info;
2089
2090         info->pause_on_host = (shmem_info.config &
2091                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2092
2093         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2094                                       &info->protocol)) {
2095                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2096                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2097                 return ECORE_INVAL;
2098         }
2099
2100         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2101
2102         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2103                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2104                 info->mac[1] = (u8)(shmem_info.mac_upper);
2105                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2106                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2107                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2108                 info->mac[5] = (u8)(shmem_info.mac_lower);
2109         } else {
2110                 /* TODO - are there protocols for which there's no MAC? */
2111                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2112         }
2113
2114         /* TODO - are these calculations true for BE machine? */
2115         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2116                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2117         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2118                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2119
2120         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2121
2122         info->mtu = (u16)shmem_info.mtu_size;
2123
2124         if (info->mtu == 0)
2125                 info->mtu = 1500;
2126
2127         info->mtu = (u16)shmem_info.mtu_size;
2128
2129         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2130                    "Read configuration from shmem: pause_on_host %02x"
2131                     " protocol %02x BW [%02x - %02x]"
2132                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2133                     " node %lx ovlan %04x\n",
2134                    info->pause_on_host, info->protocol,
2135                    info->bandwidth_min, info->bandwidth_max,
2136                    info->mac[0], info->mac[1], info->mac[2],
2137                    info->mac[3], info->mac[4], info->mac[5],
2138                    (unsigned long)info->wwn_port,
2139                    (unsigned long)info->wwn_node, info->ovlan);
2140
2141         return ECORE_SUCCESS;
2142 }
2143
2144 struct ecore_mcp_link_params
2145 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2146 {
2147         if (!p_hwfn || !p_hwfn->mcp_info)
2148                 return OSAL_NULL;
2149         return &p_hwfn->mcp_info->link_input;
2150 }
2151
2152 struct ecore_mcp_link_state
2153 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2154 {
2155         if (!p_hwfn || !p_hwfn->mcp_info)
2156                 return OSAL_NULL;
2157
2158 #ifndef ASIC_ONLY
2159         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2160                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2161                 p_hwfn->mcp_info->link_output.link_up = true;
2162         }
2163 #endif
2164
2165         return &p_hwfn->mcp_info->link_output;
2166 }
2167
2168 struct ecore_mcp_link_capabilities
2169 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2170 {
2171         if (!p_hwfn || !p_hwfn->mcp_info)
2172                 return OSAL_NULL;
2173         return &p_hwfn->mcp_info->link_capabilities;
2174 }
2175
2176 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2177                                      struct ecore_ptt *p_ptt)
2178 {
2179         u32 resp = 0, param = 0;
2180         enum _ecore_status_t rc;
2181
2182         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2183                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2184
2185         /* Wait for the drain to complete before returning */
2186         OSAL_MSLEEP(1020);
2187
2188         return rc;
2189 }
2190
2191 const struct ecore_mcp_function_info
2192 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2193 {
2194         if (!p_hwfn || !p_hwfn->mcp_info)
2195                 return OSAL_NULL;
2196         return &p_hwfn->mcp_info->func_info;
2197 }
2198
2199 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2200                                   struct ecore_ptt *p_ptt, u32 personalities)
2201 {
2202         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2203         struct public_func shmem_info;
2204         int i, count = 0, num_pfs;
2205
2206         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2207
2208         for (i = 0; i < num_pfs; i++) {
2209                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2210                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2211                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2212                         continue;
2213
2214                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2215                                               &protocol) !=
2216                     ECORE_SUCCESS)
2217                         continue;
2218
2219                 if ((1 << ((u32)protocol)) & personalities)
2220                         count++;
2221         }
2222
2223         return count;
2224 }
2225
2226 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2227                                               struct ecore_ptt *p_ptt,
2228                                               u32 *p_flash_size)
2229 {
2230         u32 flash_size;
2231
2232 #ifndef ASIC_ONLY
2233         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2234                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2235                 return ECORE_INVAL;
2236         }
2237 #endif
2238
2239         if (IS_VF(p_hwfn->p_dev))
2240                 return ECORE_INVAL;
2241
2242         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2243         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2244                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2245         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2246
2247         *p_flash_size = flash_size;
2248
2249         return ECORE_SUCCESS;
2250 }
2251
2252 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2253                                                   struct ecore_ptt *p_ptt)
2254 {
2255         struct ecore_dev *p_dev = p_hwfn->p_dev;
2256
2257         if (p_dev->recov_in_prog) {
2258                 DP_NOTICE(p_hwfn, false,
2259                           "Avoid triggering a recovery since such a process"
2260                           " is already in progress\n");
2261                 return ECORE_AGAIN;
2262         }
2263
2264         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2265         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2266
2267         return ECORE_SUCCESS;
2268 }
2269
2270 static enum _ecore_status_t
2271 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2272                             struct ecore_ptt *p_ptt,
2273                             u8 vf_id, u8 num)
2274 {
2275         u32 resp = 0, param = 0, rc_param = 0;
2276         enum _ecore_status_t rc;
2277
2278 /* Only Leader can configure MSIX, and need to take CMT into account */
2279
2280         if (!IS_LEAD_HWFN(p_hwfn))
2281                 return ECORE_SUCCESS;
2282         num *= p_hwfn->p_dev->num_hwfns;
2283
2284         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2285             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2286         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2287             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2288
2289         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2290                            &resp, &rc_param);
2291
2292         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2293                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2294                           vf_id);
2295                 rc = ECORE_INVAL;
2296         } else {
2297                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2298                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2299                             num, vf_id);
2300         }
2301
2302         return rc;
2303 }
2304
2305 static enum _ecore_status_t
2306 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2307                             struct ecore_ptt *p_ptt,
2308                             u8 num)
2309 {
2310         u32 resp = 0, param = num, rc_param = 0;
2311         enum _ecore_status_t rc;
2312
2313         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2314                            param, &resp, &rc_param);
2315
2316         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2317                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2318                 rc = ECORE_INVAL;
2319         } else {
2320                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2321                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2322                            num);
2323         }
2324
2325         return rc;
2326 }
2327
2328 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2329                                               struct ecore_ptt *p_ptt,
2330                                               u8 vf_id, u8 num)
2331 {
2332         if (ECORE_IS_BB(p_hwfn->p_dev))
2333                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2334         else
2335                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2336 }
2337
2338 enum _ecore_status_t
2339 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2340                            struct ecore_mcp_drv_version *p_ver)
2341 {
2342         struct ecore_mcp_mb_params mb_params;
2343         struct drv_version_stc drv_version;
2344         u32 num_words, i;
2345         void *p_name;
2346         OSAL_BE32 val;
2347         enum _ecore_status_t rc;
2348
2349 #ifndef ASIC_ONLY
2350         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2351                 return ECORE_SUCCESS;
2352 #endif
2353
2354         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2355         drv_version.version = p_ver->version;
2356         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2357         for (i = 0; i < num_words; i++) {
2358                 /* The driver name is expected to be in a big-endian format */
2359                 p_name = &p_ver->name[i * sizeof(u32)];
2360                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2361                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2362         }
2363
2364         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2365         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2366         mb_params.p_data_src = &drv_version;
2367         mb_params.data_src_size = sizeof(drv_version);
2368         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2369         if (rc != ECORE_SUCCESS)
2370                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2371
2372         return rc;
2373 }
2374
2375 /* A maximal 100 msec waiting time for the MCP to halt */
2376 #define ECORE_MCP_HALT_SLEEP_MS         10
2377 #define ECORE_MCP_HALT_MAX_RETRIES      10
2378
2379 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2380                                     struct ecore_ptt *p_ptt)
2381 {
2382         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2383         enum _ecore_status_t rc;
2384
2385         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2386                            &param);
2387         if (rc != ECORE_SUCCESS) {
2388                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2389                 return rc;
2390         }
2391
2392         do {
2393                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2394                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2395                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2396                         break;
2397         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2398
2399         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2400                 DP_NOTICE(p_hwfn, false,
2401                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2402                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2403                 return ECORE_BUSY;
2404         }
2405
2406         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2407
2408         return ECORE_SUCCESS;
2409 }
2410
2411 #define ECORE_MCP_RESUME_SLEEP_MS       10
2412
2413 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2414                                       struct ecore_ptt *p_ptt)
2415 {
2416         u32 cpu_mode, cpu_state;
2417
2418         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2419
2420         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2421         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2422         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2423
2424         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2425         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2426
2427         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2428                 DP_NOTICE(p_hwfn, false,
2429                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2430                           cpu_mode, cpu_state);
2431                 return ECORE_BUSY;
2432         }
2433
2434         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2435
2436         return ECORE_SUCCESS;
2437 }
2438
2439 enum _ecore_status_t
2440 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2441                                    struct ecore_ptt *p_ptt,
2442                                    enum ecore_ov_client client)
2443 {
2444         enum _ecore_status_t rc;
2445         u32 resp = 0, param = 0;
2446         u32 drv_mb_param;
2447
2448         switch (client) {
2449         case ECORE_OV_CLIENT_DRV:
2450                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2451                 break;
2452         case ECORE_OV_CLIENT_USER:
2453                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2454                 break;
2455         case ECORE_OV_CLIENT_VENDOR_SPEC:
2456                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2457                 break;
2458         default:
2459                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2460                 return ECORE_INVAL;
2461         }
2462
2463         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2464                            drv_mb_param, &resp, &param);
2465         if (rc != ECORE_SUCCESS)
2466                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2467
2468         return rc;
2469 }
2470
2471 enum _ecore_status_t
2472 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2473                                  struct ecore_ptt *p_ptt,
2474                                  enum ecore_ov_driver_state drv_state)
2475 {
2476         enum _ecore_status_t rc;
2477         u32 resp = 0, param = 0;
2478         u32 drv_mb_param;
2479
2480         switch (drv_state) {
2481         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2482                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2483                 break;
2484         case ECORE_OV_DRIVER_STATE_DISABLED:
2485                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2486                 break;
2487         case ECORE_OV_DRIVER_STATE_ACTIVE:
2488                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2489                 break;
2490         default:
2491                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2492                 return ECORE_INVAL;
2493         }
2494
2495         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2496                            drv_mb_param, &resp, &param);
2497         if (rc != ECORE_SUCCESS)
2498                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2499
2500         return rc;
2501 }
2502
2503 enum _ecore_status_t
2504 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2505                          struct ecore_fc_npiv_tbl *p_table)
2506 {
2507         return 0;
2508 }
2509
2510 enum _ecore_status_t
2511 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2512                         struct ecore_ptt *p_ptt, u16 mtu)
2513 {
2514         return 0;
2515 }
2516
2517 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2518                                        struct ecore_ptt *p_ptt,
2519                                        enum ecore_led_mode mode)
2520 {
2521         u32 resp = 0, param = 0, drv_mb_param;
2522         enum _ecore_status_t rc;
2523
2524         switch (mode) {
2525         case ECORE_LED_MODE_ON:
2526                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2527                 break;
2528         case ECORE_LED_MODE_OFF:
2529                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2530                 break;
2531         case ECORE_LED_MODE_RESTORE:
2532                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2533                 break;
2534         default:
2535                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2536                 return ECORE_INVAL;
2537         }
2538
2539         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2540                            drv_mb_param, &resp, &param);
2541         if (rc != ECORE_SUCCESS)
2542                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2543
2544         return rc;
2545 }
2546
2547 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2548                                              struct ecore_ptt *p_ptt,
2549                                              u32 mask_parities)
2550 {
2551         u32 resp = 0, param = 0;
2552         enum _ecore_status_t rc;
2553
2554         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2555                            mask_parities, &resp, &param);
2556
2557         if (rc != ECORE_SUCCESS) {
2558                 DP_ERR(p_hwfn,
2559                        "MCP response failure for mask parities, aborting\n");
2560         } else if (resp != FW_MSG_CODE_OK) {
2561                 DP_ERR(p_hwfn,
2562                        "MCP did not ack mask parity request. Old MFW?\n");
2563                 rc = ECORE_INVAL;
2564         }
2565
2566         return rc;
2567 }
2568
2569 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2570                                         u8 *p_buf, u32 len)
2571 {
2572         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2573         u32 bytes_left, offset, bytes_to_copy, buf_size;
2574         u32 nvm_offset, resp, param;
2575         struct ecore_ptt *p_ptt;
2576         enum _ecore_status_t rc = ECORE_SUCCESS;
2577
2578         p_ptt = ecore_ptt_acquire(p_hwfn);
2579         if (!p_ptt)
2580                 return ECORE_BUSY;
2581
2582         bytes_left = len;
2583         offset = 0;
2584         while (bytes_left > 0) {
2585                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2586                                            MCP_DRV_NVM_BUF_LEN);
2587                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2588                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2589                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2590                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2591                                           nvm_offset, &resp, &param, &buf_size,
2592                                           (u32 *)(p_buf + offset));
2593                 if (rc != ECORE_SUCCESS) {
2594                         DP_NOTICE(p_dev, false,
2595                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2596                                   rc);
2597                         resp = FW_MSG_CODE_ERROR;
2598                         break;
2599                 }
2600
2601                 if (resp != FW_MSG_CODE_NVM_OK) {
2602                         DP_NOTICE(p_dev, false,
2603                                   "nvm read failed, resp = 0x%08x\n", resp);
2604                         rc = ECORE_UNKNOWN_ERROR;
2605                         break;
2606                 }
2607
2608                 /* This can be a lengthy process, and it's possible scheduler
2609                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2610                  */
2611                 if (bytes_left % 0x1000 <
2612                     (bytes_left - buf_size) % 0x1000)
2613                         OSAL_MSLEEP(1);
2614
2615                 offset += buf_size;
2616                 bytes_left -= buf_size;
2617         }
2618
2619         p_dev->mcp_nvm_resp = resp;
2620         ecore_ptt_release(p_hwfn, p_ptt);
2621
2622         return rc;
2623 }
2624
2625 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2626                                         u32 addr, u8 *p_buf, u32 len)
2627 {
2628         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2629         struct ecore_ptt *p_ptt;
2630         u32 resp, param;
2631         enum _ecore_status_t rc;
2632
2633         p_ptt = ecore_ptt_acquire(p_hwfn);
2634         if (!p_ptt)
2635                 return ECORE_BUSY;
2636
2637         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2638                                   (cmd == ECORE_PHY_CORE_READ) ?
2639                                   DRV_MSG_CODE_PHY_CORE_READ :
2640                                   DRV_MSG_CODE_PHY_RAW_READ,
2641                                   addr, &resp, &param, &len, (u32 *)p_buf);
2642         if (rc != ECORE_SUCCESS)
2643                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2644
2645         p_dev->mcp_nvm_resp = resp;
2646         ecore_ptt_release(p_hwfn, p_ptt);
2647
2648         return rc;
2649 }
2650
2651 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2652 {
2653         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2654         struct ecore_ptt *p_ptt;
2655
2656         p_ptt = ecore_ptt_acquire(p_hwfn);
2657         if (!p_ptt)
2658                 return ECORE_BUSY;
2659
2660         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2661         ecore_ptt_release(p_hwfn, p_ptt);
2662
2663         return ECORE_SUCCESS;
2664 }
2665
2666 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2667 {
2668         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2669         struct ecore_ptt *p_ptt;
2670         u32 resp, param;
2671         enum _ecore_status_t rc;
2672
2673         p_ptt = ecore_ptt_acquire(p_hwfn);
2674         if (!p_ptt)
2675                 return ECORE_BUSY;
2676         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2677                            &resp, &param);
2678         p_dev->mcp_nvm_resp = resp;
2679         ecore_ptt_release(p_hwfn, p_ptt);
2680
2681         return rc;
2682 }
2683
2684 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2685                                                   u32 addr)
2686 {
2687         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2688         struct ecore_ptt *p_ptt;
2689         u32 resp, param;
2690         enum _ecore_status_t rc;
2691
2692         p_ptt = ecore_ptt_acquire(p_hwfn);
2693         if (!p_ptt)
2694                 return ECORE_BUSY;
2695         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2696                            &resp, &param);
2697         p_dev->mcp_nvm_resp = resp;
2698         ecore_ptt_release(p_hwfn, p_ptt);
2699
2700         return rc;
2701 }
2702
2703 /* rc receives ECORE_INVAL as default parameter because
2704  * it might not enter the while loop if the len is 0
2705  */
2706 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2707                                          u32 addr, u8 *p_buf, u32 len)
2708 {
2709         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2710         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2711         enum _ecore_status_t rc = ECORE_INVAL;
2712         struct ecore_ptt *p_ptt;
2713
2714         p_ptt = ecore_ptt_acquire(p_hwfn);
2715         if (!p_ptt)
2716                 return ECORE_BUSY;
2717
2718         switch (cmd) {
2719         case ECORE_PUT_FILE_DATA:
2720                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2721                 break;
2722         case ECORE_NVM_WRITE_NVRAM:
2723                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2724                 break;
2725         case ECORE_EXT_PHY_FW_UPGRADE:
2726                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2727                 break;
2728         default:
2729                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2730                           cmd);
2731                 rc = ECORE_INVAL;
2732                 goto out;
2733         }
2734
2735         buf_idx = 0;
2736         while (buf_idx < len) {
2737                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2738                                       MCP_DRV_NVM_BUF_LEN);
2739                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2740                               addr) +
2741                              buf_idx;
2742                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2743                                           &resp, &param, buf_size,
2744                                           (u32 *)&p_buf[buf_idx]);
2745                 if (rc != ECORE_SUCCESS) {
2746                         DP_NOTICE(p_dev, false,
2747                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2748                                   rc);
2749                         resp = FW_MSG_CODE_ERROR;
2750                         break;
2751                 }
2752
2753                 if (resp != FW_MSG_CODE_OK &&
2754                     resp != FW_MSG_CODE_NVM_OK &&
2755                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2756                         DP_NOTICE(p_dev, false,
2757                                   "nvm write failed, resp = 0x%08x\n", resp);
2758                         rc = ECORE_UNKNOWN_ERROR;
2759                         break;
2760                 }
2761
2762                 /* This can be a lengthy process, and it's possible scheduler
2763                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2764                  */
2765                 if (buf_idx % 0x1000 >
2766                     (buf_idx + buf_size) % 0x1000)
2767                         OSAL_MSLEEP(1);
2768
2769                 buf_idx += buf_size;
2770         }
2771
2772         p_dev->mcp_nvm_resp = resp;
2773 out:
2774         ecore_ptt_release(p_hwfn, p_ptt);
2775
2776         return rc;
2777 }
2778
2779 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2780                                          u32 addr, u8 *p_buf, u32 len)
2781 {
2782         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2783         struct ecore_ptt *p_ptt;
2784         u32 resp, param, nvm_cmd;
2785         enum _ecore_status_t rc;
2786
2787         p_ptt = ecore_ptt_acquire(p_hwfn);
2788         if (!p_ptt)
2789                 return ECORE_BUSY;
2790
2791         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2792                         DRV_MSG_CODE_PHY_RAW_WRITE;
2793         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2794                                   &resp, &param, len, (u32 *)p_buf);
2795         if (rc != ECORE_SUCCESS)
2796                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2797         p_dev->mcp_nvm_resp = resp;
2798         ecore_ptt_release(p_hwfn, p_ptt);
2799
2800         return rc;
2801 }
2802
2803 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2804                                                    u32 addr)
2805 {
2806         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2807         struct ecore_ptt *p_ptt;
2808         u32 resp, param;
2809         enum _ecore_status_t rc;
2810
2811         p_ptt = ecore_ptt_acquire(p_hwfn);
2812         if (!p_ptt)
2813                 return ECORE_BUSY;
2814
2815         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2816                            &resp, &param);
2817         p_dev->mcp_nvm_resp = resp;
2818         ecore_ptt_release(p_hwfn, p_ptt);
2819
2820         return rc;
2821 }
2822
2823 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2824                                             struct ecore_ptt *p_ptt,
2825                                             u32 port, u32 addr, u32 offset,
2826                                             u32 len, u8 *p_buf)
2827 {
2828         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2829         u32 resp, param;
2830         enum _ecore_status_t rc;
2831
2832         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2833                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2834         addr = offset;
2835         offset = 0;
2836         bytes_left = len;
2837         while (bytes_left > 0) {
2838                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2839                                            MAX_I2C_TRANSACTION_SIZE);
2840                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2841                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2842                 nvm_offset |= ((addr + offset) <<
2843                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2844                 nvm_offset |= (bytes_to_copy <<
2845                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2846                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2847                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2848                                           nvm_offset, &resp, &param, &buf_size,
2849                                           (u32 *)(p_buf + offset));
2850                 if ((resp & FW_MSG_CODE_MASK) ==
2851                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2852                         return ECORE_NODEV;
2853                 } else if ((resp & FW_MSG_CODE_MASK) !=
2854                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2855                         return ECORE_UNKNOWN_ERROR;
2856
2857                 offset += buf_size;
2858                 bytes_left -= buf_size;
2859         }
2860
2861         return ECORE_SUCCESS;
2862 }
2863
2864 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2865                                              struct ecore_ptt *p_ptt,
2866                                              u32 port, u32 addr, u32 offset,
2867                                              u32 len, u8 *p_buf)
2868 {
2869         u32 buf_idx, buf_size, nvm_offset, resp, param;
2870         enum _ecore_status_t rc;
2871
2872         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2873                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2874         buf_idx = 0;
2875         while (buf_idx < len) {
2876                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2877                                       MAX_I2C_TRANSACTION_SIZE);
2878                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2879                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2880                 nvm_offset |= ((offset + buf_idx) <<
2881                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2882                 nvm_offset |= (buf_size <<
2883                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2884                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2885                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2886                                           nvm_offset, &resp, &param, buf_size,
2887                                           (u32 *)&p_buf[buf_idx]);
2888                 if ((resp & FW_MSG_CODE_MASK) ==
2889                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2890                         return ECORE_NODEV;
2891                 } else if ((resp & FW_MSG_CODE_MASK) !=
2892                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2893                         return ECORE_UNKNOWN_ERROR;
2894
2895                 buf_idx += buf_size;
2896         }
2897
2898         return ECORE_SUCCESS;
2899 }
2900
2901 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2902                                          struct ecore_ptt *p_ptt,
2903                                          u16 gpio, u32 *gpio_val)
2904 {
2905         enum _ecore_status_t rc = ECORE_SUCCESS;
2906         u32 drv_mb_param = 0, rsp;
2907
2908         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
2909
2910         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
2911                            drv_mb_param, &rsp, gpio_val);
2912
2913         if (rc != ECORE_SUCCESS)
2914                 return rc;
2915
2916         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2917                 return ECORE_UNKNOWN_ERROR;
2918
2919         return ECORE_SUCCESS;
2920 }
2921
2922 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
2923                                           struct ecore_ptt *p_ptt,
2924                                           u16 gpio, u16 gpio_val)
2925 {
2926         enum _ecore_status_t rc = ECORE_SUCCESS;
2927         u32 drv_mb_param = 0, param, rsp;
2928
2929         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
2930                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
2931
2932         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
2933                            drv_mb_param, &rsp, &param);
2934
2935         if (rc != ECORE_SUCCESS)
2936                 return rc;
2937
2938         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2939                 return ECORE_UNKNOWN_ERROR;
2940
2941         return ECORE_SUCCESS;
2942 }
2943
2944 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
2945                                          struct ecore_ptt *p_ptt,
2946                                          u16 gpio, u32 *gpio_direction,
2947                                          u32 *gpio_ctrl)
2948 {
2949         u32 drv_mb_param = 0, rsp, val = 0;
2950         enum _ecore_status_t rc = ECORE_SUCCESS;
2951
2952         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
2953
2954         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
2955                            drv_mb_param, &rsp, &val);
2956         if (rc != ECORE_SUCCESS)
2957                 return rc;
2958
2959         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
2960                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
2961         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
2962                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
2963
2964         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
2965                 return ECORE_UNKNOWN_ERROR;
2966
2967         return ECORE_SUCCESS;
2968 }
2969
2970 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
2971                                                   struct ecore_ptt *p_ptt)
2972 {
2973         u32 drv_mb_param = 0, rsp, param;
2974         enum _ecore_status_t rc = ECORE_SUCCESS;
2975
2976         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2977                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
2978
2979         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2980                            drv_mb_param, &rsp, &param);
2981
2982         if (rc != ECORE_SUCCESS)
2983                 return rc;
2984
2985         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2986             (param != DRV_MB_PARAM_BIST_RC_PASSED))
2987                 rc = ECORE_UNKNOWN_ERROR;
2988
2989         return rc;
2990 }
2991
2992 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
2993                                                struct ecore_ptt *p_ptt)
2994 {
2995         u32 drv_mb_param, rsp, param;
2996         enum _ecore_status_t rc = ECORE_SUCCESS;
2997
2998         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2999                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3000
3001         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3002                            drv_mb_param, &rsp, &param);
3003
3004         if (rc != ECORE_SUCCESS)
3005                 return rc;
3006
3007         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3008             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3009                 rc = ECORE_UNKNOWN_ERROR;
3010
3011         return rc;
3012 }
3013
3014 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3015         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3016 {
3017         u32 drv_mb_param = 0, rsp;
3018         enum _ecore_status_t rc = ECORE_SUCCESS;
3019
3020         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3021                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3022
3023         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3024                            drv_mb_param, &rsp, num_images);
3025
3026         if (rc != ECORE_SUCCESS)
3027                 return rc;
3028
3029         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3030                 rc = ECORE_UNKNOWN_ERROR;
3031
3032         return rc;
3033 }
3034
3035 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3036         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3037         struct bist_nvm_image_att *p_image_att, u32 image_index)
3038 {
3039         u32 buf_size, nvm_offset, resp, param;
3040         enum _ecore_status_t rc;
3041
3042         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3043                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3044         nvm_offset |= (image_index <<
3045                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3046         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3047                                   nvm_offset, &resp, &param, &buf_size,
3048                                   (u32 *)p_image_att);
3049         if (rc != ECORE_SUCCESS)
3050                 return rc;
3051
3052         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3053             (p_image_att->return_code != 1))
3054                 rc = ECORE_UNKNOWN_ERROR;
3055
3056         return rc;
3057 }
3058
3059 enum _ecore_status_t
3060 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3061                                struct ecore_ptt *p_ptt,
3062                                struct ecore_temperature_info *p_temp_info)
3063 {
3064         struct ecore_temperature_sensor *p_temp_sensor;
3065         struct temperature_status_stc mfw_temp_info;
3066         struct ecore_mcp_mb_params mb_params;
3067         u32 val;
3068         enum _ecore_status_t rc;
3069         u8 i;
3070
3071         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3072         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3073         mb_params.p_data_dst = &mfw_temp_info;
3074         mb_params.data_dst_size = sizeof(mfw_temp_info);
3075         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3076         if (rc != ECORE_SUCCESS)
3077                 return rc;
3078
3079         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3080         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3081                                               ECORE_MAX_NUM_OF_SENSORS);
3082         for (i = 0; i < p_temp_info->num_sensors; i++) {
3083                 val = mfw_temp_info.sensor[i];
3084                 p_temp_sensor = &p_temp_info->sensors[i];
3085                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3086                                                  SENSOR_LOCATION_OFFSET;
3087                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3088                                                 THRESHOLD_HIGH_OFFSET;
3089                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3090                                           CRITICAL_TEMPERATURE_OFFSET;
3091                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3092                                               CURRENT_TEMP_OFFSET;
3093         }
3094
3095         return ECORE_SUCCESS;
3096 }
3097
3098 enum _ecore_status_t ecore_mcp_get_mba_versions(
3099         struct ecore_hwfn *p_hwfn,
3100         struct ecore_ptt *p_ptt,
3101         struct ecore_mba_vers *p_mba_vers)
3102 {
3103         u32 buf_size, resp, param;
3104         enum _ecore_status_t rc;
3105
3106         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3107                                   0, &resp, &param, &buf_size,
3108                                   &p_mba_vers->mba_vers[0]);
3109
3110         if (rc != ECORE_SUCCESS)
3111                 return rc;
3112
3113         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3114                 rc = ECORE_UNKNOWN_ERROR;
3115
3116         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3117                 rc = ECORE_UNKNOWN_ERROR;
3118
3119         return rc;
3120 }
3121
3122 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3123                                               struct ecore_ptt *p_ptt,
3124                                               u64 *num_events)
3125 {
3126         u32 rsp;
3127
3128         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3129                              0, &rsp, (u32 *)num_events);
3130 }
3131
3132 static enum resource_id_enum
3133 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3134 {
3135         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3136
3137         switch (res_id) {
3138         case ECORE_SB:
3139                 mfw_res_id = RESOURCE_NUM_SB_E;
3140                 break;
3141         case ECORE_L2_QUEUE:
3142                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3143                 break;
3144         case ECORE_VPORT:
3145                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3146                 break;
3147         case ECORE_RSS_ENG:
3148                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3149                 break;
3150         case ECORE_PQ:
3151                 mfw_res_id = RESOURCE_NUM_PQ_E;
3152                 break;
3153         case ECORE_RL:
3154                 mfw_res_id = RESOURCE_NUM_RL_E;
3155                 break;
3156         case ECORE_MAC:
3157         case ECORE_VLAN:
3158                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3159                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3160                 break;
3161         case ECORE_ILT:
3162                 mfw_res_id = RESOURCE_ILT_E;
3163                 break;
3164         case ECORE_LL2_QUEUE:
3165                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3166                 break;
3167         case ECORE_RDMA_CNQ_RAM:
3168         case ECORE_CMDQS_CQS:
3169                 /* CNQ/CMDQS are the same resource */
3170                 mfw_res_id = RESOURCE_CQS_E;
3171                 break;
3172         case ECORE_RDMA_STATS_QUEUE:
3173                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3174                 break;
3175         case ECORE_BDQ:
3176                 mfw_res_id = RESOURCE_BDQ_E;
3177                 break;
3178         default:
3179                 break;
3180         }
3181
3182         return mfw_res_id;
3183 }
3184
3185 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3186 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3187 #define ECORE_RESC_ALLOC_VERSION                                \
3188         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3189           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3190          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3191           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3192
3193 struct ecore_resc_alloc_in_params {
3194         u32 cmd;
3195         enum ecore_resources res_id;
3196         u32 resc_max_val;
3197 };
3198
3199 struct ecore_resc_alloc_out_params {
3200         u32 mcp_resp;
3201         u32 mcp_param;
3202         u32 resc_num;
3203         u32 resc_start;
3204         u32 vf_resc_num;
3205         u32 vf_resc_start;
3206         u32 flags;
3207 };
3208
3209 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3210
3211 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3212 {
3213         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3214         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3215         enum _ecore_status_t rc;
3216
3217         /* Allow ongoing PCIe transactions to complete */
3218         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3219
3220         /* Clear the PF's internal FID_enable in the PXP */
3221         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3222         if (rc != ECORE_SUCCESS)
3223                 DP_NOTICE(p_hwfn, false,
3224                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3225                           rc);
3226
3227         return rc;
3228 }
3229
3230 static enum _ecore_status_t
3231 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3232                               struct ecore_ptt *p_ptt,
3233                               struct ecore_resc_alloc_in_params *p_in_params,
3234                               struct ecore_resc_alloc_out_params *p_out_params)
3235 {
3236         struct ecore_mcp_mb_params mb_params;
3237         struct resource_info mfw_resc_info;
3238         enum _ecore_status_t rc;
3239
3240         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3241
3242         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3243         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3244                 DP_ERR(p_hwfn,
3245                        "Failed to match resource %d [%s] with the MFW resources\n",
3246                        p_in_params->res_id,
3247                        ecore_hw_get_resc_name(p_in_params->res_id));
3248                 return ECORE_INVAL;
3249         }
3250
3251         switch (p_in_params->cmd) {
3252         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3253                 mfw_resc_info.size = p_in_params->resc_max_val;
3254                 /* Fallthrough */
3255         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3256                 break;
3257         default:
3258                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3259                        p_in_params->cmd);
3260                 return ECORE_INVAL;
3261         }
3262
3263         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3264         mb_params.cmd = p_in_params->cmd;
3265         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3266         mb_params.p_data_src = &mfw_resc_info;
3267         mb_params.data_src_size = sizeof(mfw_resc_info);
3268         mb_params.p_data_dst = mb_params.p_data_src;
3269         mb_params.data_dst_size = mb_params.data_src_size;
3270
3271         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3272                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3273                    p_in_params->cmd, p_in_params->res_id,
3274                    ecore_hw_get_resc_name(p_in_params->res_id),
3275                    GET_MFW_FIELD(mb_params.param,
3276                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3277                    GET_MFW_FIELD(mb_params.param,
3278                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3279                    p_in_params->resc_max_val);
3280
3281         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3282         if (rc != ECORE_SUCCESS)
3283                 return rc;
3284
3285         p_out_params->mcp_resp = mb_params.mcp_resp;
3286         p_out_params->mcp_param = mb_params.mcp_param;
3287         p_out_params->resc_num = mfw_resc_info.size;
3288         p_out_params->resc_start = mfw_resc_info.offset;
3289         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3290         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3291         p_out_params->flags = mfw_resc_info.flags;
3292
3293         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3294                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3295                    GET_MFW_FIELD(p_out_params->mcp_param,
3296                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3297                    GET_MFW_FIELD(p_out_params->mcp_param,
3298                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3299                    p_out_params->resc_num, p_out_params->resc_start,
3300                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3301                    p_out_params->flags);
3302
3303         return ECORE_SUCCESS;
3304 }
3305
3306 enum _ecore_status_t
3307 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3308                            enum ecore_resources res_id, u32 resc_max_val,
3309                            u32 *p_mcp_resp)
3310 {
3311         struct ecore_resc_alloc_out_params out_params;
3312         struct ecore_resc_alloc_in_params in_params;
3313         enum _ecore_status_t rc;
3314
3315         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3316         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3317         in_params.res_id = res_id;
3318         in_params.resc_max_val = resc_max_val;
3319         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3320         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3321                                            &out_params);
3322         if (rc != ECORE_SUCCESS)
3323                 return rc;
3324
3325         *p_mcp_resp = out_params.mcp_resp;
3326
3327         return ECORE_SUCCESS;
3328 }
3329
3330 enum _ecore_status_t
3331 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3332                         enum ecore_resources res_id, u32 *p_mcp_resp,
3333                         u32 *p_resc_num, u32 *p_resc_start)
3334 {
3335         struct ecore_resc_alloc_out_params out_params;
3336         struct ecore_resc_alloc_in_params in_params;
3337         enum _ecore_status_t rc;
3338
3339         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3340         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3341         in_params.res_id = res_id;
3342         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3343         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3344                                            &out_params);
3345         if (rc != ECORE_SUCCESS)
3346                 return rc;
3347
3348         *p_mcp_resp = out_params.mcp_resp;
3349
3350         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3351                 *p_resc_num = out_params.resc_num;
3352                 *p_resc_start = out_params.resc_start;
3353         }
3354
3355         return ECORE_SUCCESS;
3356 }
3357
3358 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3359                                                struct ecore_ptt *p_ptt)
3360 {
3361         u32 mcp_resp, mcp_param;
3362
3363         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3364                              &mcp_resp, &mcp_param);
3365 }
3366
3367 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3368                                                    struct ecore_ptt *p_ptt,
3369                                                    u32 param, u32 *p_mcp_resp,
3370                                                    u32 *p_mcp_param)
3371 {
3372         enum _ecore_status_t rc;
3373
3374         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3375                            p_mcp_resp, p_mcp_param);
3376         if (rc != ECORE_SUCCESS)
3377                 return rc;
3378
3379         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3380                 DP_INFO(p_hwfn,
3381                         "The resource command is unsupported by the MFW\n");
3382                 return ECORE_NOTIMPL;
3383         }
3384
3385         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3386                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3387
3388                 DP_NOTICE(p_hwfn, false,
3389                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3390                           param, opcode);
3391                 return ECORE_INVAL;
3392         }
3393
3394         return rc;
3395 }
3396
3397 enum _ecore_status_t
3398 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3399                       struct ecore_resc_lock_params *p_params)
3400 {
3401         u32 param = 0, mcp_resp, mcp_param;
3402         u8 opcode;
3403         enum _ecore_status_t rc;
3404
3405         switch (p_params->timeout) {
3406         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3407                 opcode = RESOURCE_OPCODE_REQ;
3408                 p_params->timeout = 0;
3409                 break;
3410         case ECORE_MCP_RESC_LOCK_TO_NONE:
3411                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3412                 p_params->timeout = 0;
3413                 break;
3414         default:
3415                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3416                 break;
3417         }
3418
3419         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3420         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3421         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3422
3423         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3424                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3425                    param, p_params->timeout, opcode, p_params->resource);
3426
3427         /* Attempt to acquire the resource */
3428         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3429                                     &mcp_param);
3430         if (rc != ECORE_SUCCESS)
3431                 return rc;
3432
3433         /* Analyze the response */
3434         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3435         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3436
3437         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3438                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3439                    mcp_param, opcode, p_params->owner);
3440
3441         switch (opcode) {
3442         case RESOURCE_OPCODE_GNT:
3443                 p_params->b_granted = true;
3444                 break;
3445         case RESOURCE_OPCODE_BUSY:
3446                 p_params->b_granted = false;
3447                 break;
3448         default:
3449                 DP_NOTICE(p_hwfn, false,
3450                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3451                           mcp_param, opcode);
3452                 return ECORE_INVAL;
3453         }
3454
3455         return ECORE_SUCCESS;
3456 }
3457
3458 enum _ecore_status_t
3459 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3460                     struct ecore_resc_lock_params *p_params)
3461 {
3462         u32 retry_cnt = 0;
3463         enum _ecore_status_t rc;
3464
3465         do {
3466                 /* No need for an interval before the first iteration */
3467                 if (retry_cnt) {
3468                         if (p_params->sleep_b4_retry) {
3469                                 u16 retry_interval_in_ms =
3470                                         DIV_ROUND_UP(p_params->retry_interval,
3471                                                      1000);
3472
3473                                 OSAL_MSLEEP(retry_interval_in_ms);
3474                         } else {
3475                                 OSAL_UDELAY(p_params->retry_interval);
3476                         }
3477                 }
3478
3479                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3480                 if (rc != ECORE_SUCCESS)
3481                         return rc;
3482
3483                 if (p_params->b_granted)
3484                         break;
3485         } while (retry_cnt++ < p_params->retry_num);
3486
3487         return ECORE_SUCCESS;
3488 }
3489
3490 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3491                                       struct ecore_resc_unlock_params *p_unlock,
3492                                       enum ecore_resc_lock resource,
3493                                       bool b_is_permanent)
3494 {
3495         if (p_lock != OSAL_NULL) {
3496                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3497
3498                 /* Permanent resources don't require aging, and there's no
3499                  * point in trying to acquire them more than once since it's
3500                  * unexpected another entity would release them.
3501                  */
3502                 if (b_is_permanent) {
3503                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3504                 } else {
3505                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3506                         p_lock->retry_interval =
3507                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3508                         p_lock->sleep_b4_retry = true;
3509                 }
3510
3511                 p_lock->resource = resource;
3512         }
3513
3514         if (p_unlock != OSAL_NULL) {
3515                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3516                 p_unlock->resource = resource;
3517         }
3518 }
3519
3520 enum _ecore_status_t
3521 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3522                       struct ecore_resc_unlock_params *p_params)
3523 {
3524         u32 param = 0, mcp_resp, mcp_param;
3525         u8 opcode;
3526         enum _ecore_status_t rc;
3527
3528         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3529                                    : RESOURCE_OPCODE_RELEASE;
3530         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3531         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3532
3533         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3534                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3535                    param, opcode, p_params->resource);
3536
3537         /* Attempt to release the resource */
3538         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3539                                     &mcp_param);
3540         if (rc != ECORE_SUCCESS)
3541                 return rc;
3542
3543         /* Analyze the response */
3544         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3545
3546         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3547                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3548                    mcp_param, opcode);
3549
3550         switch (opcode) {
3551         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3552                 DP_INFO(p_hwfn,
3553                         "Resource unlock request for an already released resource [%d]\n",
3554                         p_params->resource);
3555                 /* Fallthrough */
3556         case RESOURCE_OPCODE_RELEASED:
3557                 p_params->b_released = true;
3558                 break;
3559         case RESOURCE_OPCODE_WRONG_OWNER:
3560                 p_params->b_released = false;
3561                 break;
3562         default:
3563                 DP_NOTICE(p_hwfn, false,
3564                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3565                           mcp_param, opcode);
3566                 return ECORE_INVAL;
3567         }
3568
3569         return ECORE_SUCCESS;
3570 }
3571
3572 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3573 {
3574         return !!(p_hwfn->mcp_info->capabilities &
3575                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3576 }
3577
3578 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3579                                                 struct ecore_ptt *p_ptt)
3580 {
3581         u32 mcp_resp;
3582         enum _ecore_status_t rc;
3583
3584         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3585                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3586         if (rc == ECORE_SUCCESS)
3587                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3588                            "MFW supported features: %08x\n",
3589                            p_hwfn->mcp_info->capabilities);
3590
3591         return rc;
3592 }
3593
3594 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3595                                                 struct ecore_ptt *p_ptt)
3596 {
3597         u32 mcp_resp, mcp_param, features;
3598
3599         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3600                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3601
3602         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3603                              features, &mcp_resp, &mcp_param);
3604 }