drivers/net/qede/base/ecore_mcp.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "bcm_osal.h"
  10 #include "ecore.h"
  11 #include "ecore_status.h"
  12 #include "ecore_mcp.h"
  13 #include "mcp_public.h"
  14 #include "reg_addr.h"
  15 #include "ecore_hw.h"
  16 #include "ecore_init_fw_funcs.h"
  17 #include "ecore_sriov.h"
  18 #include "ecore_vf.h"
  19 #include "ecore_iov_api.h"
  20 #include "ecore_gtt_reg_addr.h"
  21 #include "ecore_iro.h"
  22 #include "ecore_dcbx.h"
  23 #include "ecore_sp_commands.h"
  24 #include "ecore_cxt.h"
  25
  26 #define CHIP_MCP_RESP_ITER_US 10
  27 #define EMUL_MCP_RESP_ITER_US (1000 * 1000)
  28
  29 #define ECORE_DRV_MB_MAX_RETRIES (500 * 1000)   /* Account for 5 sec */
  30 #define ECORE_MCP_RESET_RETRIES (50 * 1000)     /* Account for 500 msec */
  31
  32 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
  33         ecore_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
  34                  _val)
  35
  36 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
  37         ecore_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
  38
  39 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
  40         DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
  41                      OFFSETOF(struct public_drv_mb, _field), _val)
  42
  43 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
  44         DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
  45                      OFFSETOF(struct public_drv_mb, _field))
  46
  47 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
  48         DRV_ID_PDA_COMP_VER_OFFSET)
  49
  50 #define MCP_BYTES_PER_MBIT_OFFSET 17
  51
  52 #ifndef ASIC_ONLY
  53 static int loaded;
  54 static int loaded_port[MAX_NUM_PORTS] = { 0 };
  55 #endif
  56
  57 bool ecore_mcp_is_init(struct ecore_hwfn *p_hwfn)
  58 {
  59         if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
  60                 return false;
  61         return true;
  62 }
  63
  64 void ecore_mcp_cmd_port_init(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  65 {
  66         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
  67                                         PUBLIC_PORT);
  68         u32 mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt, addr);
  69
  70         p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
  71                                                    MFW_PORT(p_hwfn));
  72         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
  73                    "port_addr = 0x%x, port_id 0x%02x\n",
  74                    p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
  75 }
  76
  77 void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
  78 {
  79         u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
  80         OSAL_BE32 tmp;
  81         u32 i;
  82
  83 #ifndef ASIC_ONLY
  84         if (CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
  85                 return;
  86 #endif
  87
  88         if (!p_hwfn->mcp_info->public_base)
  89                 return;
  90
  91         for (i = 0; i < length; i++) {
  92                 tmp = ecore_rd(p_hwfn, p_ptt,
  93                                p_hwfn->mcp_info->mfw_mb_addr +
  94                                (i << 2) + sizeof(u32));
  95
  96                 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
  97                     OSAL_BE32_TO_CPU(tmp);
  98         }
  99 }
 100
 101 struct ecore_mcp_cmd_elem {
 102         osal_list_entry_t list;
 103         struct ecore_mcp_mb_params *p_mb_params;
 104         u16 expected_seq_num;
 105         bool b_is_completed;
 106 };
 107
 108 /* Must be called while cmd_lock is acquired */
 109 static struct ecore_mcp_cmd_elem *
 110 ecore_mcp_cmd_add_elem(struct ecore_hwfn *p_hwfn,
 111                        struct ecore_mcp_mb_params *p_mb_params,
 112                        u16 expected_seq_num)
 113 {
 114         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 115
 116         p_cmd_elem = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
 117                                  sizeof(*p_cmd_elem));
 118         if (!p_cmd_elem) {
 119                 DP_NOTICE(p_hwfn, false,
 120                           "Failed to allocate `struct ecore_mcp_cmd_elem'\n");
 121                 goto out;
 122         }
 123
 124         p_cmd_elem->p_mb_params = p_mb_params;
 125         p_cmd_elem->expected_seq_num = expected_seq_num;
 126         OSAL_LIST_PUSH_HEAD(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 127 out:
 128         return p_cmd_elem;
 129 }
 130
 131 /* Must be called while cmd_lock is acquired */
 132 static void ecore_mcp_cmd_del_elem(struct ecore_hwfn *p_hwfn,
 133                                    struct ecore_mcp_cmd_elem *p_cmd_elem)
 134 {
 135         OSAL_LIST_REMOVE_ENTRY(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
 136         OSAL_FREE(p_hwfn->p_dev, p_cmd_elem);
 137 }
 138
 139 /* Must be called while cmd_lock is acquired */
 140 static struct ecore_mcp_cmd_elem *
 141 ecore_mcp_cmd_get_elem(struct ecore_hwfn *p_hwfn, u16 seq_num)
 142 {
 143         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 144
 145         OSAL_LIST_FOR_EACH_ENTRY(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list,
 146                                  struct ecore_mcp_cmd_elem) {
 147                 if (p_cmd_elem->expected_seq_num == seq_num)
 148                         return p_cmd_elem;
 149         }
 150
 151         return OSAL_NULL;
 152 }
 153
 154 enum _ecore_status_t ecore_mcp_free(struct ecore_hwfn *p_hwfn)
 155 {
 156         if (p_hwfn->mcp_info) {
 157                 struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL, *p_tmp;
 158
 159                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 160                 OSAL_LIST_FOR_EACH_ENTRY_SAFE(p_cmd_elem, p_tmp,
 161                                               &p_hwfn->mcp_info->cmd_list, list,
 162                                               struct ecore_mcp_cmd_elem) {
 163                         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 164                 }
 165                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 166
 167                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_cur);
 168                 OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info->mfw_mb_shadow);
 169 #ifdef CONFIG_ECORE_LOCK_ALLOC
 170                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->cmd_lock);
 171                 OSAL_SPIN_LOCK_DEALLOC(&p_hwfn->mcp_info->link_lock);
 172 #endif
 173         }
 174
 175         OSAL_FREE(p_hwfn->p_dev, p_hwfn->mcp_info);
 176
 177         return ECORE_SUCCESS;
 178 }
 179
 180 static enum _ecore_status_t ecore_load_mcp_offsets(struct ecore_hwfn *p_hwfn,
 181                                                    struct ecore_ptt *p_ptt)
 182 {
 183         struct ecore_mcp_info *p_info = p_hwfn->mcp_info;
 184         u32 drv_mb_offsize, mfw_mb_offsize;
 185         u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
 186
 187 #ifndef ASIC_ONLY
 188         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 189                 DP_NOTICE(p_hwfn, false, "Emulation - assume no MFW\n");
 190                 p_info->public_base = 0;
 191                 return ECORE_INVAL;
 192         }
 193 #endif
 194
 195         p_info->public_base = ecore_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
 196         if (!p_info->public_base)
 197                 return ECORE_INVAL;
 198
 199         p_info->public_base |= GRCBASE_MCP;
 200
 201         /* Calculate the driver and MFW mailbox address */
 202         drv_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 203                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 204                                                        PUBLIC_DRV_MB));
 205         p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
 206         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 207                    "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x"
 208                    " mcp_pf_id = 0x%x\n",
 209                    drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
 210
 211         /* Set the MFW MB address */
 212         mfw_mb_offsize = ecore_rd(p_hwfn, p_ptt,
 213                                   SECTION_OFFSIZE_ADDR(p_info->public_base,
 214                                                        PUBLIC_MFW_MB));
 215         p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
 216         p_info->mfw_mb_length = (u16)ecore_rd(p_hwfn, p_ptt,
 217                                                p_info->mfw_mb_addr);
 218
 219         /* Get the current driver mailbox sequence before sending
 220          * the first command
 221          */
 222         p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
 223             DRV_MSG_SEQ_NUMBER_MASK;
 224
 225         /* Get current FW pulse sequence */
 226         p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
 227             DRV_PULSE_SEQ_MASK;
 228
 229         p_info->mcp_hist = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 230
 231         return ECORE_SUCCESS;
 232 }
 233
 234 enum _ecore_status_t ecore_mcp_cmd_init(struct ecore_hwfn *p_hwfn,
 235                                         struct ecore_ptt *p_ptt)
 236 {
 237         struct ecore_mcp_info *p_info;
 238         u32 size;
 239
 240         /* Allocate mcp_info structure */
 241         p_hwfn->mcp_info = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 242                                        sizeof(*p_hwfn->mcp_info));
 243         if (!p_hwfn->mcp_info)
 244                 goto err;
 245         p_info = p_hwfn->mcp_info;
 246
 247         if (ecore_load_mcp_offsets(p_hwfn, p_ptt) != ECORE_SUCCESS) {
 248                 DP_NOTICE(p_hwfn, false, "MCP is not initialized\n");
 249                 /* Do not free mcp_info here, since public_base indicate that
 250                  * the MCP is not initialized
 251                  */
 252                 return ECORE_SUCCESS;
 253         }
 254
 255         size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
 256         p_info->mfw_mb_cur = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 257         p_info->mfw_mb_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
 258         if (!p_info->mfw_mb_shadow || !p_info->mfw_mb_addr)
 259                 goto err;
 260
 261         /* Initialize the MFW spinlocks */
 262 #ifdef CONFIG_ECORE_LOCK_ALLOC
 263         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->cmd_lock);
 264         OSAL_SPIN_LOCK_ALLOC(p_hwfn, &p_info->link_lock);
 265 #endif
 266         OSAL_SPIN_LOCK_INIT(&p_info->cmd_lock);
 267         OSAL_SPIN_LOCK_INIT(&p_info->link_lock);
 268
 269         OSAL_LIST_INIT(&p_info->cmd_list);
 270
 271         return ECORE_SUCCESS;
 272
 273 err:
 274         DP_NOTICE(p_hwfn, true, "Failed to allocate mcp memory\n");
 275         ecore_mcp_free(p_hwfn);
 276         return ECORE_NOMEM;
 277 }
 278
 279 static void ecore_mcp_reread_offsets(struct ecore_hwfn *p_hwfn,
 280                                      struct ecore_ptt *p_ptt)
 281 {
 282         u32 generic_por_0 = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 283
 284         /* Use MCP history register to check if MCP reset occurred between init
 285          * time and now.
 286          */
 287         if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
 288                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 289                            "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
 290                            p_hwfn->mcp_info->mcp_hist, generic_por_0);
 291
 292                 ecore_load_mcp_offsets(p_hwfn, p_ptt);
 293                 ecore_mcp_cmd_port_init(p_hwfn, p_ptt);
 294         }
 295 }
 296
 297 enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
 298                                      struct ecore_ptt *p_ptt)
 299 {
 300         u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
 301         enum _ecore_status_t rc = ECORE_SUCCESS;
 302
 303 #ifndef ASIC_ONLY
 304         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 305                 delay = EMUL_MCP_RESP_ITER_US;
 306 #endif
 307
 308         if (p_hwfn->mcp_info->b_block_cmd) {
 309                 DP_NOTICE(p_hwfn, false,
 310                           "The MFW is not responsive. Avoid sending MCP_RESET mailbox command.\n");
 311                 return ECORE_ABORTED;
 312         }
 313
 314         /* Ensure that only a single thread is accessing the mailbox */
 315         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 316
 317         org_mcp_reset_seq = ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
 318
 319         /* Set drv command along with the updated sequence */
 320         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 321         seq = ++p_hwfn->mcp_info->drv_mb_seq;
 322         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
 323
 324         do {
 325                 /* Wait for MFW response */
 326                 OSAL_UDELAY(delay);
 327                 /* Give the FW up to 500 second (50*1000*10usec) */
 328         } while ((org_mcp_reset_seq == ecore_rd(p_hwfn, p_ptt,
 329                                                 MISCS_REG_GENERIC_POR_0)) &&
 330                  (cnt++ < ECORE_MCP_RESET_RETRIES));
 331
 332         if (org_mcp_reset_seq !=
 333             ecore_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
 334                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 335                            "MCP was reset after %d usec\n", cnt * delay);
 336         } else {
 337                 DP_ERR(p_hwfn, "Failed to reset MCP\n");
 338                 rc = ECORE_AGAIN;
 339         }
 340
 341         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 342
 343         return rc;
 344 }
 345
 346 /* Must be called while cmd_lock is acquired */
 347 static bool ecore_mcp_has_pending_cmd(struct ecore_hwfn *p_hwfn)
 348 {
 349         struct ecore_mcp_cmd_elem *p_cmd_elem = OSAL_NULL;
 350
 351         /* There is at most one pending command at a certain time, and if it
 352          * exists - it is placed at the HEAD of the list.
 353          */
 354         if (!OSAL_LIST_IS_EMPTY(&p_hwfn->mcp_info->cmd_list)) {
 355                 p_cmd_elem = OSAL_LIST_FIRST_ENTRY(&p_hwfn->mcp_info->cmd_list,
 356                                                    struct ecore_mcp_cmd_elem,
 357                                                    list);
 358                 return !p_cmd_elem->b_is_completed;
 359         }
 360
 361         return false;
 362 }
 363
 364 /* Must be called while cmd_lock is acquired */
 365 static enum _ecore_status_t
 366 ecore_mcp_update_pending_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
 367 {
 368         struct ecore_mcp_mb_params *p_mb_params;
 369         struct ecore_mcp_cmd_elem *p_cmd_elem;
 370         u32 mcp_resp;
 371         u16 seq_num;
 372
 373         mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
 374         seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
 375
 376         /* Return if no new non-handled response has been received */
 377         if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
 378                 return ECORE_AGAIN;
 379
 380         p_cmd_elem = ecore_mcp_cmd_get_elem(p_hwfn, seq_num);
 381         if (!p_cmd_elem) {
 382                 DP_ERR(p_hwfn,
 383                        "Failed to find a pending mailbox cmd that expects sequence number %d\n",
 384                        seq_num);
 385                 return ECORE_UNKNOWN_ERROR;
 386         }
 387
 388         p_mb_params = p_cmd_elem->p_mb_params;
 389
 390         /* Get the MFW response along with the sequence number */
 391         p_mb_params->mcp_resp = mcp_resp;
 392
 393         /* Get the MFW param */
 394         p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
 395
 396         /* Get the union data */
 397         if (p_mb_params->p_data_dst != OSAL_NULL &&
 398             p_mb_params->data_dst_size) {
 399                 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 400                                       OFFSETOF(struct public_drv_mb,
 401                                                union_data);
 402                 ecore_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
 403                                   union_data_addr, p_mb_params->data_dst_size);
 404         }
 405
 406         p_cmd_elem->b_is_completed = true;
 407
 408         return ECORE_SUCCESS;
 409 }
 410
 411 /* Must be called while cmd_lock is acquired */
 412 static void __ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 413                                       struct ecore_ptt *p_ptt,
 414                                       struct ecore_mcp_mb_params *p_mb_params,
 415                                       u16 seq_num)
 416 {
 417         union drv_union_data union_data;
 418         u32 union_data_addr;
 419
 420         /* Set the union data */
 421         union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
 422                           OFFSETOF(struct public_drv_mb, union_data);
 423         OSAL_MEM_ZERO(&union_data, sizeof(union_data));
 424         if (p_mb_params->p_data_src != OSAL_NULL && p_mb_params->data_src_size)
 425                 OSAL_MEMCPY(&union_data, p_mb_params->p_data_src,
 426                             p_mb_params->data_src_size);
 427         ecore_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
 428                         sizeof(union_data));
 429
 430         /* Set the drv param */
 431         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
 432
 433         /* Set the drv command along with the sequence number */
 434         DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
 435
 436         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 437                    "MFW mailbox: command 0x%08x param 0x%08x\n",
 438                    (p_mb_params->cmd | seq_num), p_mb_params->param);
 439 }
 440
 441 static void ecore_mcp_cmd_set_blocking(struct ecore_hwfn *p_hwfn,
 442                                        bool block_cmd)
 443 {
 444         p_hwfn->mcp_info->b_block_cmd = block_cmd;
 445
 446         DP_INFO(p_hwfn, "%s sending of mailbox commands to the MFW\n",
 447                 block_cmd ? "Block" : "Unblock");
 448 }
 449
 450 static enum _ecore_status_t
 451 _ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 452                          struct ecore_mcp_mb_params *p_mb_params,
 453                          u32 max_retries, u32 delay)
 454 {
 455         struct ecore_mcp_cmd_elem *p_cmd_elem;
 456         u32 cnt = 0;
 457         u16 seq_num;
 458         enum _ecore_status_t rc = ECORE_SUCCESS;
 459
 460         /* Wait until the mailbox is non-occupied */
 461         do {
 462                 /* Exit the loop if there is no pending command, or if the
 463                  * pending command is completed during this iteration.
 464                  * The spinlock stays locked until the command is sent.
 465                  */
 466
 467                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 468
 469                 if (!ecore_mcp_has_pending_cmd(p_hwfn))
 470                         break;
 471
 472                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 473                 if (rc == ECORE_SUCCESS)
 474                         break;
 475                 else if (rc != ECORE_AGAIN)
 476                         goto err;
 477
 478                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 479                 OSAL_UDELAY(delay);
 480         } while (++cnt < max_retries);
 481
 482         if (cnt >= max_retries) {
 483                 DP_NOTICE(p_hwfn, false,
 484                           "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
 485                           p_mb_params->cmd, p_mb_params->param);
 486                 return ECORE_AGAIN;
 487         }
 488
 489         /* Send the mailbox command */
 490         ecore_mcp_reread_offsets(p_hwfn, p_ptt);
 491         seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
 492         p_cmd_elem = ecore_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
 493         if (!p_cmd_elem) {
 494                 rc = ECORE_NOMEM;
 495                 goto err;
 496         }
 497
 498         __ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
 499         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 500
 501         /* Wait for the MFW response */
 502         do {
 503                 /* Exit the loop if the command is already completed, or if the
 504                  * command is completed during this iteration.
 505                  * The spinlock stays locked until the list element is removed.
 506                  */
 507
 508                 OSAL_UDELAY(delay);
 509                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 510
 511                 if (p_cmd_elem->b_is_completed)
 512                         break;
 513
 514                 rc = ecore_mcp_update_pending_cmd(p_hwfn, p_ptt);
 515                 if (rc == ECORE_SUCCESS)
 516                         break;
 517                 else if (rc != ECORE_AGAIN)
 518                         goto err;
 519
 520                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 521         } while (++cnt < max_retries);
 522
 523         if (cnt >= max_retries) {
 524                 DP_NOTICE(p_hwfn, false,
 525                           "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
 526                           p_mb_params->cmd, p_mb_params->param);
 527
 528                 OSAL_SPIN_LOCK(&p_hwfn->mcp_info->cmd_lock);
 529                 ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 530                 OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 531
 532                 ecore_mcp_cmd_set_blocking(p_hwfn, true);
 533                 ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_MFW_RESP_FAIL);
 534                 return ECORE_AGAIN;
 535         }
 536
 537         ecore_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
 538         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 539
 540         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 541                    "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
 542                    p_mb_params->mcp_resp, p_mb_params->mcp_param,
 543                    (cnt * delay) / 1000, (cnt * delay) % 1000);
 544
 545         /* Clear the sequence number from the MFW response */
 546         p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
 547
 548         return ECORE_SUCCESS;
 549
 550 err:
 551         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->cmd_lock);
 552         return rc;
 553 }
 554
 555 static enum _ecore_status_t
 556 ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
 557                         struct ecore_ptt *p_ptt,
 558                         struct ecore_mcp_mb_params *p_mb_params)
 559 {
 560         osal_size_t union_data_size = sizeof(union drv_union_data);
 561         u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
 562         u32 delay = CHIP_MCP_RESP_ITER_US;
 563
 564 #ifndef ASIC_ONLY
 565         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
 566                 delay = EMUL_MCP_RESP_ITER_US;
 567         /* There is a built-in delay of 100usec in each MFW response read */
 568         if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
 569                 max_retries /= 10;
 570 #endif
 571
 572         /* MCP not initialized */
 573         if (!ecore_mcp_is_init(p_hwfn)) {
 574                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
 575                 return ECORE_BUSY;
 576         }
 577
 578         if (p_mb_params->data_src_size > union_data_size ||
 579             p_mb_params->data_dst_size > union_data_size) {
 580                 DP_ERR(p_hwfn,
 581                        "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
 582                        p_mb_params->data_src_size, p_mb_params->data_dst_size,
 583                        union_data_size);
 584                 return ECORE_INVAL;
 585         }
 586
 587         if (p_hwfn->mcp_info->b_block_cmd) {
 588                 DP_NOTICE(p_hwfn, false,
 589                           "The MFW is not responsive. Avoid sending mailbox command 0x%08x [param 0x%08x].\n",
 590                           p_mb_params->cmd, p_mb_params->param);
 591                 return ECORE_ABORTED;
 592         }
 593
 594         return _ecore_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
 595                                         delay);
 596 }
 597
 598 enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
 599                                    struct ecore_ptt *p_ptt, u32 cmd, u32 param,
 600                                    u32 *o_mcp_resp, u32 *o_mcp_param)
 601 {
 602         struct ecore_mcp_mb_params mb_params;
 603         enum _ecore_status_t rc;
 604
 605 #ifndef ASIC_ONLY
 606         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 607                 if (cmd == DRV_MSG_CODE_UNLOAD_REQ) {
 608                         loaded--;
 609                         loaded_port[p_hwfn->port_id]--;
 610                         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Unload cnt: 0x%x\n",
 611                                    loaded);
 612                 }
 613                 return ECORE_SUCCESS;
 614         }
 615 #endif
 616
 617         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 618         mb_params.cmd = cmd;
 619         mb_params.param = param;
 620         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 621         if (rc != ECORE_SUCCESS)
 622                 return rc;
 623
 624         *o_mcp_resp = mb_params.mcp_resp;
 625         *o_mcp_param = mb_params.mcp_param;
 626
 627         return ECORE_SUCCESS;
 628 }
 629
 630 enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
 631                                           struct ecore_ptt *p_ptt,
 632                                           u32 cmd,
 633                                           u32 param,
 634                                           u32 *o_mcp_resp,
 635                                           u32 *o_mcp_param,
 636                                           u32 i_txn_size, u32 *i_buf)
 637 {
 638         struct ecore_mcp_mb_params mb_params;
 639         enum _ecore_status_t rc;
 640
 641         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 642         mb_params.cmd = cmd;
 643         mb_params.param = param;
 644         mb_params.p_data_src = i_buf;
 645         mb_params.data_src_size = (u8)i_txn_size;
 646         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 647         if (rc != ECORE_SUCCESS)
 648                 return rc;
 649
 650         *o_mcp_resp = mb_params.mcp_resp;
 651         *o_mcp_param = mb_params.mcp_param;
 652
 653         return ECORE_SUCCESS;
 654 }
 655
 656 enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
 657                                           struct ecore_ptt *p_ptt,
 658                                           u32 cmd,
 659                                           u32 param,
 660                                           u32 *o_mcp_resp,
 661                                           u32 *o_mcp_param,
 662                                           u32 *o_txn_size, u32 *o_buf)
 663 {
 664         struct ecore_mcp_mb_params mb_params;
 665         u8 raw_data[MCP_DRV_NVM_BUF_LEN];
 666         enum _ecore_status_t rc;
 667
 668         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 669         mb_params.cmd = cmd;
 670         mb_params.param = param;
 671         mb_params.p_data_dst = raw_data;
 672
 673         /* Use the maximal value since the actual one is part of the response */
 674         mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
 675
 676         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 677         if (rc != ECORE_SUCCESS)
 678                 return rc;
 679
 680         *o_mcp_resp = mb_params.mcp_resp;
 681         *o_mcp_param = mb_params.mcp_param;
 682
 683         *o_txn_size = *o_mcp_param;
 684         /* @DPDK */
 685         OSAL_MEMCPY(o_buf, raw_data, RTE_MIN(*o_txn_size, MCP_DRV_NVM_BUF_LEN));
 686
 687         return ECORE_SUCCESS;
 688 }
 689
 690 #ifndef ASIC_ONLY
 691 static void ecore_mcp_mf_workaround(struct ecore_hwfn *p_hwfn,
 692                                     u32 *p_load_code)
 693 {
 694         static int load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 695
 696         if (!loaded)
 697                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 698         else if (!loaded_port[p_hwfn->port_id])
 699                 load_phase = FW_MSG_CODE_DRV_LOAD_PORT;
 700         else
 701                 load_phase = FW_MSG_CODE_DRV_LOAD_FUNCTION;
 702
 703         /* On CMT, always tell that it's engine */
 704         if (ECORE_IS_CMT(p_hwfn->p_dev))
 705                 load_phase = FW_MSG_CODE_DRV_LOAD_ENGINE;
 706
 707         *p_load_code = load_phase;
 708         loaded++;
 709         loaded_port[p_hwfn->port_id]++;
 710
 711         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 712                    "Load phase: %x load cnt: 0x%x port id=%d port_load=%d\n",
 713                    *p_load_code, loaded, p_hwfn->port_id,
 714                    loaded_port[p_hwfn->port_id]);
 715 }
 716 #endif
 717
 718 static bool
 719 ecore_mcp_can_force_load(u8 drv_role, u8 exist_drv_role,
 720                          enum ecore_override_force_load override_force_load)
 721 {
 722         bool can_force_load = false;
 723
 724         switch (override_force_load) {
 725         case ECORE_OVERRIDE_FORCE_LOAD_ALWAYS:
 726                 can_force_load = true;
 727                 break;
 728         case ECORE_OVERRIDE_FORCE_LOAD_NEVER:
 729                 can_force_load = false;
 730                 break;
 731         default:
 732                 can_force_load = (drv_role == DRV_ROLE_OS &&
 733                                   exist_drv_role == DRV_ROLE_PREBOOT) ||
 734                                  (drv_role == DRV_ROLE_KDUMP &&
 735                                   exist_drv_role == DRV_ROLE_OS);
 736                 break;
 737         }
 738
 739         return can_force_load;
 740 }
 741
 742 static enum _ecore_status_t ecore_mcp_cancel_load_req(struct ecore_hwfn *p_hwfn,
 743                                                       struct ecore_ptt *p_ptt)
 744 {
 745         u32 resp = 0, param = 0;
 746         enum _ecore_status_t rc;
 747
 748         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
 749                            &resp, &param);
 750         if (rc != ECORE_SUCCESS)
 751                 DP_NOTICE(p_hwfn, false,
 752                           "Failed to send cancel load request, rc = %d\n", rc);
 753
 754         return rc;
 755 }
 756
 757 #define CONFIG_ECORE_L2_BITMAP_IDX      (0x1 << 0)
 758 #define CONFIG_ECORE_SRIOV_BITMAP_IDX   (0x1 << 1)
 759 #define CONFIG_ECORE_ROCE_BITMAP_IDX    (0x1 << 2)
 760 #define CONFIG_ECORE_IWARP_BITMAP_IDX   (0x1 << 3)
 761 #define CONFIG_ECORE_FCOE_BITMAP_IDX    (0x1 << 4)
 762 #define CONFIG_ECORE_ISCSI_BITMAP_IDX   (0x1 << 5)
 763 #define CONFIG_ECORE_LL2_BITMAP_IDX     (0x1 << 6)
 764
 765 static u32 ecore_get_config_bitmap(void)
 766 {
 767         u32 config_bitmap = 0x0;
 768
 769 #ifdef CONFIG_ECORE_L2
 770         config_bitmap |= CONFIG_ECORE_L2_BITMAP_IDX;
 771 #endif
 772 #ifdef CONFIG_ECORE_SRIOV
 773         config_bitmap |= CONFIG_ECORE_SRIOV_BITMAP_IDX;
 774 #endif
 775 #ifdef CONFIG_ECORE_ROCE
 776         config_bitmap |= CONFIG_ECORE_ROCE_BITMAP_IDX;
 777 #endif
 778 #ifdef CONFIG_ECORE_IWARP
 779         config_bitmap |= CONFIG_ECORE_IWARP_BITMAP_IDX;
 780 #endif
 781 #ifdef CONFIG_ECORE_FCOE
 782         config_bitmap |= CONFIG_ECORE_FCOE_BITMAP_IDX;
 783 #endif
 784 #ifdef CONFIG_ECORE_ISCSI
 785         config_bitmap |= CONFIG_ECORE_ISCSI_BITMAP_IDX;
 786 #endif
 787 #ifdef CONFIG_ECORE_LL2
 788         config_bitmap |= CONFIG_ECORE_LL2_BITMAP_IDX;
 789 #endif
 790
 791         return config_bitmap;
 792 }
 793
 794 struct ecore_load_req_in_params {
 795         u8 hsi_ver;
 796 #define ECORE_LOAD_REQ_HSI_VER_DEFAULT  0
 797 #define ECORE_LOAD_REQ_HSI_VER_1        1
 798         u32 drv_ver_0;
 799         u32 drv_ver_1;
 800         u32 fw_ver;
 801         u8 drv_role;
 802         u8 timeout_val;
 803         u8 force_cmd;
 804         bool avoid_eng_reset;
 805 };
 806
 807 struct ecore_load_req_out_params {
 808         u32 load_code;
 809         u32 exist_drv_ver_0;
 810         u32 exist_drv_ver_1;
 811         u32 exist_fw_ver;
 812         u8 exist_drv_role;
 813         u8 mfw_hsi_ver;
 814         bool drv_exists;
 815 };
 816
 817 static enum _ecore_status_t
 818 __ecore_mcp_load_req(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 819                      struct ecore_load_req_in_params *p_in_params,
 820                      struct ecore_load_req_out_params *p_out_params)
 821 {
 822         struct ecore_mcp_mb_params mb_params;
 823         struct load_req_stc load_req;
 824         struct load_rsp_stc load_rsp;
 825         u32 hsi_ver;
 826         enum _ecore_status_t rc;
 827
 828         OSAL_MEM_ZERO(&load_req, sizeof(load_req));
 829         load_req.drv_ver_0 = p_in_params->drv_ver_0;
 830         load_req.drv_ver_1 = p_in_params->drv_ver_1;
 831         load_req.fw_ver = p_in_params->fw_ver;
 832         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
 833         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
 834                       p_in_params->timeout_val);
 835         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE, p_in_params->force_cmd);
 836         SET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
 837                       p_in_params->avoid_eng_reset);
 838
 839         hsi_ver = (p_in_params->hsi_ver == ECORE_LOAD_REQ_HSI_VER_DEFAULT) ?
 840                   DRV_ID_MCP_HSI_VER_CURRENT :
 841                   (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_OFFSET);
 842
 843         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
 844         mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
 845         mb_params.param = PDA_COMP | hsi_ver | p_hwfn->p_dev->drv_type;
 846         mb_params.p_data_src = &load_req;
 847         mb_params.data_src_size = sizeof(load_req);
 848         mb_params.p_data_dst = &load_rsp;
 849         mb_params.data_dst_size = sizeof(load_rsp);
 850
 851         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 852                    "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
 853                    mb_params.param,
 854                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
 855                    GET_MFW_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
 856                    GET_MFW_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
 857                    GET_MFW_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
 858
 859         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1)
 860                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 861                            "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
 862                            load_req.drv_ver_0, load_req.drv_ver_1,
 863                            load_req.fw_ver, load_req.misc0,
 864                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_ROLE),
 865                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO),
 866                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FORCE),
 867                            GET_MFW_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
 868
 869         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
 870         if (rc != ECORE_SUCCESS) {
 871                 DP_NOTICE(p_hwfn, false,
 872                           "Failed to send load request, rc = %d\n", rc);
 873                 return rc;
 874         }
 875
 876         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 877                    "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
 878         p_out_params->load_code = mb_params.mcp_resp;
 879
 880         if (p_in_params->hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
 881             p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 882                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
 883                            "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
 884                            load_rsp.drv_ver_0, load_rsp.drv_ver_1,
 885                            load_rsp.fw_ver, load_rsp.misc0,
 886                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
 887                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
 888                            GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
 889
 890                 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
 891                 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
 892                 p_out_params->exist_fw_ver = load_rsp.fw_ver;
 893                 p_out_params->exist_drv_role =
 894                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
 895                 p_out_params->mfw_hsi_ver =
 896                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
 897                 p_out_params->drv_exists =
 898                         GET_MFW_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
 899                         LOAD_RSP_FLAGS0_DRV_EXISTS;
 900         }
 901
 902         return ECORE_SUCCESS;
 903 }
 904
 905 static void ecore_get_mfw_drv_role(enum ecore_drv_role drv_role,
 906                                    u8 *p_mfw_drv_role)
 907 {
 908         switch (drv_role) {
 909         case ECORE_DRV_ROLE_OS:
 910                 *p_mfw_drv_role = DRV_ROLE_OS;
 911                 break;
 912         case ECORE_DRV_ROLE_KDUMP:
 913                 *p_mfw_drv_role = DRV_ROLE_KDUMP;
 914                 break;
 915         }
 916 }
 917
 918 enum ecore_load_req_force {
 919         ECORE_LOAD_REQ_FORCE_NONE,
 920         ECORE_LOAD_REQ_FORCE_PF,
 921         ECORE_LOAD_REQ_FORCE_ALL,
 922 };
 923
 924 static void ecore_get_mfw_force_cmd(enum ecore_load_req_force force_cmd,
 925                                     u8 *p_mfw_force_cmd)
 926 {
 927         switch (force_cmd) {
 928         case ECORE_LOAD_REQ_FORCE_NONE:
 929                 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
 930                 break;
 931         case ECORE_LOAD_REQ_FORCE_PF:
 932                 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
 933                 break;
 934         case ECORE_LOAD_REQ_FORCE_ALL:
 935                 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
 936                 break;
 937         }
 938 }
 939
 940 enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
 941                                         struct ecore_ptt *p_ptt,
 942                                         struct ecore_load_req_params *p_params)
 943 {
 944         struct ecore_load_req_out_params out_params;
 945         struct ecore_load_req_in_params in_params;
 946         u8 mfw_drv_role = 0, mfw_force_cmd;
 947         enum _ecore_status_t rc;
 948
 949 #ifndef ASIC_ONLY
 950         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
 951                 ecore_mcp_mf_workaround(p_hwfn, &p_params->load_code);
 952                 return ECORE_SUCCESS;
 953         }
 954 #endif
 955
 956         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
 957         in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_DEFAULT;
 958         in_params.drv_ver_0 = ECORE_VERSION;
 959         in_params.drv_ver_1 = ecore_get_config_bitmap();
 960         in_params.fw_ver = STORM_FW_VERSION;
 961         ecore_get_mfw_drv_role(p_params->drv_role, &mfw_drv_role);
 962         in_params.drv_role = mfw_drv_role;
 963         in_params.timeout_val = p_params->timeout_val;
 964         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
 965         in_params.force_cmd = mfw_force_cmd;
 966         in_params.avoid_eng_reset = p_params->avoid_eng_reset;
 967
 968         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 969         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
 970         if (rc != ECORE_SUCCESS)
 971                 return rc;
 972
 973         /* First handle cases where another load request should/might be sent:
 974          * - MFW expects the old interface [HSI version = 1]
 975          * - MFW responds that a force load request is required
 976          */
 977         if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
 978                 DP_INFO(p_hwfn,
 979                         "MFW refused a load request due to HSI > 1. Resending with HSI = 1.\n");
 980
 981                 in_params.hsi_ver = ECORE_LOAD_REQ_HSI_VER_1;
 982                 OSAL_MEM_ZERO(&out_params, sizeof(out_params));
 983                 rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
 984                                           &out_params);
 985                 if (rc != ECORE_SUCCESS)
 986                         return rc;
 987         } else if (out_params.load_code ==
 988                    FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
 989                 if (ecore_mcp_can_force_load(in_params.drv_role,
 990                                              out_params.exist_drv_role,
 991                                              p_params->override_force_load)) {
 992                         DP_INFO(p_hwfn,
 993                                 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, 0x%08x_%08x}, existing={%d, 0x%08x, 0x%08x_%08x}]\n",
 994                                 in_params.drv_role, in_params.fw_ver,
 995                                 in_params.drv_ver_0, in_params.drv_ver_1,
 996                                 out_params.exist_drv_role,
 997                                 out_params.exist_fw_ver,
 998                                 out_params.exist_drv_ver_0,
 999                                 out_params.exist_drv_ver_1);
1000
1001                         ecore_get_mfw_force_cmd(ECORE_LOAD_REQ_FORCE_ALL,
1002                                                 &mfw_force_cmd);
1003
1004                         in_params.force_cmd = mfw_force_cmd;
1005                         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
1006                         rc = __ecore_mcp_load_req(p_hwfn, p_ptt, &in_params,
1007                                                   &out_params);
1008                         if (rc != ECORE_SUCCESS)
1009                                 return rc;
1010                 } else {
1011                         DP_NOTICE(p_hwfn, false,
1012                                   "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
1013                                   in_params.drv_role, in_params.fw_ver,
1014                                   in_params.drv_ver_0, in_params.drv_ver_1,
1015                                   out_params.exist_drv_role,
1016                                   out_params.exist_fw_ver,
1017                                   out_params.exist_drv_ver_0,
1018                                   out_params.exist_drv_ver_1);
1019
1020                         ecore_mcp_cancel_load_req(p_hwfn, p_ptt);
1021                         return ECORE_BUSY;
1022                 }
1023         }
1024
1025         /* Now handle the other types of responses.
1026          * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
1027          * expected here after the additional revised load requests were sent.
1028          */
1029         switch (out_params.load_code) {
1030         case FW_MSG_CODE_DRV_LOAD_ENGINE:
1031         case FW_MSG_CODE_DRV_LOAD_PORT:
1032         case FW_MSG_CODE_DRV_LOAD_FUNCTION:
1033                 if (out_params.mfw_hsi_ver != ECORE_LOAD_REQ_HSI_VER_1 &&
1034                     out_params.drv_exists) {
1035                         /* The role and fw/driver version match, but the PF is
1036                          * already loaded and has not been unloaded gracefully.
1037                          * This is unexpected since a quasi-FLR request was
1038                          * previously sent as part of ecore_hw_prepare().
1039                          */
1040                         DP_NOTICE(p_hwfn, false,
1041                                   "PF is already loaded - shouldn't have got here since a quasi-FLR request was previously sent!\n");
1042                         return ECORE_INVAL;
1043                 }
1044                 break;
1045         default:
1046                 DP_NOTICE(p_hwfn, false,
1047                           "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
1048                           out_params.load_code);
1049                 return ECORE_BUSY;
1050         }
1051
1052         p_params->load_code = out_params.load_code;
1053
1054         return ECORE_SUCCESS;
1055 }
1056
1057 enum _ecore_status_t ecore_mcp_load_done(struct ecore_hwfn *p_hwfn,
1058                                          struct ecore_ptt *p_ptt)
1059 {
1060         u32 resp = 0, param = 0;
1061         enum _ecore_status_t rc;
1062
1063         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_LOAD_DONE, 0, &resp,
1064                            &param);
1065         if (rc != ECORE_SUCCESS) {
1066                 DP_NOTICE(p_hwfn, false,
1067                           "Failed to send a LOAD_DONE command, rc = %d\n", rc);
1068                 return rc;
1069         }
1070
1071         /* Check if there is a DID mismatch between nvm-cfg/efuse */
1072         if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR)
1073                 DP_NOTICE(p_hwfn, false,
1074                           "warning: device configuration is not supported on this board type. The device may not function as expected.\n");
1075
1076         return ECORE_SUCCESS;
1077 }
1078
1079 enum _ecore_status_t ecore_mcp_unload_req(struct ecore_hwfn *p_hwfn,
1080                                           struct ecore_ptt *p_ptt)
1081 {
1082         u32 wol_param, mcp_resp, mcp_param;
1083
1084         /* @DPDK */
1085         wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
1086
1087         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
1088                              &mcp_resp, &mcp_param);
1089 }
1090
1091 enum _ecore_status_t ecore_mcp_unload_done(struct ecore_hwfn *p_hwfn,
1092                                            struct ecore_ptt *p_ptt)
1093 {
1094         struct ecore_mcp_mb_params mb_params;
1095         struct mcp_mac wol_mac;
1096
1097         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1098         mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1099
1100         return ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1101 }
1102
1103 static void ecore_mcp_handle_vf_flr(struct ecore_hwfn *p_hwfn,
1104                                     struct ecore_ptt *p_ptt)
1105 {
1106         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1107                                         PUBLIC_PATH);
1108         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1109         u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1110                                      ECORE_PATH_ID(p_hwfn));
1111         u32 disabled_vfs[VF_MAX_STATIC / 32];
1112         int i;
1113
1114         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1115                    "Reading Disabled VF information from [offset %08x],"
1116                    " path_addr %08x\n",
1117                    mfw_path_offsize, path_addr);
1118
1119         for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1120                 disabled_vfs[i] = ecore_rd(p_hwfn, p_ptt,
1121                                            path_addr +
1122                                            OFFSETOF(struct public_path,
1123                                                     mcp_vf_disabled) +
1124                                            sizeof(u32) * i);
1125                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1126                            "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1127                            i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1128         }
1129
1130         if (ecore_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1131                 OSAL_VF_FLR_UPDATE(p_hwfn);
1132 }
1133
1134 enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
1135                                           struct ecore_ptt *p_ptt,
1136                                           u32 *vfs_to_ack)
1137 {
1138         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1139                                         PUBLIC_FUNC);
1140         u32 mfw_func_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1141         u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1142                                      MCP_PF_ID(p_hwfn));
1143         struct ecore_mcp_mb_params mb_params;
1144         enum _ecore_status_t rc;
1145         int i;
1146
1147         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1148                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
1149                            "Acking VFs [%08x,...,%08x] - %08x\n",
1150                            i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1151
1152         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1153         mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1154         mb_params.p_data_src = vfs_to_ack;
1155         mb_params.data_src_size = VF_MAX_STATIC / 8;
1156         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
1157                                      &mb_params);
1158         if (rc != ECORE_SUCCESS) {
1159                 DP_NOTICE(p_hwfn, false,
1160                           "Failed to pass ACK for VF flr to MFW\n");
1161                 return ECORE_TIMEOUT;
1162         }
1163
1164         /* TMP - clear the ACK bits; should be done by MFW */
1165         for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1166                 ecore_wr(p_hwfn, p_ptt,
1167                          func_addr +
1168                          OFFSETOF(struct public_func, drv_ack_vf_disabled) +
1169                          i * sizeof(u32), 0);
1170
1171         return rc;
1172 }
1173
1174 static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
1175                                                 struct ecore_ptt *p_ptt)
1176 {
1177         u32 transceiver_state;
1178
1179         transceiver_state = ecore_rd(p_hwfn, p_ptt,
1180                                      p_hwfn->mcp_info->port_addr +
1181                                      OFFSETOF(struct public_port,
1182                                               transceiver_data));
1183
1184         DP_VERBOSE(p_hwfn, (ECORE_MSG_HW | ECORE_MSG_SP),
1185                    "Received transceiver state update [0x%08x] from mfw"
1186                    " [Addr 0x%x]\n",
1187                    transceiver_state, (u32)(p_hwfn->mcp_info->port_addr +
1188                                             OFFSETOF(struct public_port,
1189                                                      transceiver_data)));
1190
1191         transceiver_state = GET_MFW_FIELD(transceiver_state,
1192                                           ETH_TRANSCEIVER_STATE);
1193
1194         if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1195                 DP_NOTICE(p_hwfn, false, "Transceiver is present.\n");
1196         else
1197                 DP_NOTICE(p_hwfn, false, "Transceiver is unplugged.\n");
1198 }
1199
1200 static void ecore_mcp_read_eee_config(struct ecore_hwfn *p_hwfn,
1201                                       struct ecore_ptt *p_ptt,
1202                                       struct ecore_mcp_link_state *p_link)
1203 {
1204         u32 eee_status, val;
1205
1206         p_link->eee_adv_caps = 0;
1207         p_link->eee_lp_adv_caps = 0;
1208         eee_status = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1209                                      OFFSETOF(struct public_port, eee_status));
1210         p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1211         val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1212         if (val & EEE_1G_ADV)
1213                 p_link->eee_adv_caps |= ECORE_EEE_1G_ADV;
1214         if (val & EEE_10G_ADV)
1215                 p_link->eee_adv_caps |= ECORE_EEE_10G_ADV;
1216         val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1217         if (val & EEE_1G_ADV)
1218                 p_link->eee_lp_adv_caps |= ECORE_EEE_1G_ADV;
1219         if (val & EEE_10G_ADV)
1220                 p_link->eee_lp_adv_caps |= ECORE_EEE_10G_ADV;
1221 }
1222
1223 static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
1224                                     struct ecore_ptt *p_ptt,
1225                                     struct public_func *p_data,
1226                                     int pfid)
1227 {
1228         u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1229                                         PUBLIC_FUNC);
1230         u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1231         u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1232         u32 i, size;
1233
1234         OSAL_MEM_ZERO(p_data, sizeof(*p_data));
1235
1236         size = OSAL_MIN_T(u32, sizeof(*p_data),
1237                           SECTION_SIZE(mfw_path_offsize));
1238         for (i = 0; i < size / sizeof(u32); i++)
1239                 ((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
1240                                               func_addr + (i << 2));
1241
1242         return size;
1243 }
1244
1245 static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
1246                                          struct ecore_ptt *p_ptt,
1247                                          bool b_reset)
1248 {
1249         struct ecore_mcp_link_state *p_link;
1250         u8 max_bw, min_bw;
1251         u32 status = 0;
1252
1253         /* Prevent SW/attentions from doing this at the same time */
1254         OSAL_SPIN_LOCK(&p_hwfn->mcp_info->link_lock);
1255
1256         p_link = &p_hwfn->mcp_info->link_output;
1257         OSAL_MEMSET(p_link, 0, sizeof(*p_link));
1258         if (!b_reset) {
1259                 status = ecore_rd(p_hwfn, p_ptt,
1260                                   p_hwfn->mcp_info->port_addr +
1261                                   OFFSETOF(struct public_port, link_status));
1262                 DP_VERBOSE(p_hwfn, (ECORE_MSG_LINK | ECORE_MSG_SP),
1263                            "Received link update [0x%08x] from mfw"
1264                            " [Addr 0x%x]\n",
1265                            status, (u32)(p_hwfn->mcp_info->port_addr +
1266                                           OFFSETOF(struct public_port,
1267                                                    link_status)));
1268         } else {
1269                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1270                            "Resetting link indications\n");
1271                 goto out;
1272         }
1273
1274         if (p_hwfn->b_drv_link_init) {
1275                 /* Link indication with modern MFW arrives as per-PF
1276                  * indication.
1277                  */
1278                 if (p_hwfn->mcp_info->capabilities &
1279                     FW_MB_PARAM_FEATURE_SUPPORT_VLINK) {
1280                         struct public_func shmem_info;
1281
1282                         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1283                                                  MCP_PF_ID(p_hwfn));
1284                         p_link->link_up = !!(shmem_info.status &
1285                                              FUNC_STATUS_VIRTUAL_LINK_UP);
1286                 } else {
1287                         p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1288                 }
1289         } else {
1290                 p_link->link_up = false;
1291         }
1292
1293         p_link->full_duplex = true;
1294         switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1295         case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1296                 p_link->speed = 100000;
1297                 break;
1298         case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1299                 p_link->speed = 50000;
1300                 break;
1301         case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1302                 p_link->speed = 40000;
1303                 break;
1304         case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1305                 p_link->speed = 25000;
1306                 break;
1307         case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1308                 p_link->speed = 20000;
1309                 break;
1310         case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1311                 p_link->speed = 10000;
1312                 break;
1313         case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1314                 p_link->full_duplex = false;
1315                 /* Fall-through */
1316         case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1317                 p_link->speed = 1000;
1318                 break;
1319         default:
1320                 p_link->speed = 0;
1321         }
1322
1323         /* We never store total line speed as p_link->speed is
1324          * again changes according to bandwidth allocation.
1325          */
1326         if (p_link->link_up && p_link->speed)
1327                 p_link->line_speed = p_link->speed;
1328         else
1329                 p_link->line_speed = 0;
1330
1331         max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1332         min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1333
1334         /* Max bandwidth configuration */
1335         __ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
1336                                            p_link, max_bw);
1337
1338         /* Mintz bandwidth configuration */
1339         __ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
1340                                            p_link, min_bw);
1341         ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev, p_ptt,
1342                                               p_link->min_pf_rate);
1343
1344         p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1345         p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1346         p_link->parallel_detection = !!(status &
1347                                          LINK_STATUS_PARALLEL_DETECTION_USED);
1348         p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1349
1350         p_link->partner_adv_speed |=
1351             (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1352             ECORE_LINK_PARTNER_SPEED_1G_FD : 0;
1353         p_link->partner_adv_speed |=
1354             (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1355             ECORE_LINK_PARTNER_SPEED_1G_HD : 0;
1356         p_link->partner_adv_speed |=
1357             (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1358             ECORE_LINK_PARTNER_SPEED_10G : 0;
1359         p_link->partner_adv_speed |=
1360             (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1361             ECORE_LINK_PARTNER_SPEED_20G : 0;
1362         p_link->partner_adv_speed |=
1363             (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1364             ECORE_LINK_PARTNER_SPEED_25G : 0;
1365         p_link->partner_adv_speed |=
1366             (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1367             ECORE_LINK_PARTNER_SPEED_40G : 0;
1368         p_link->partner_adv_speed |=
1369             (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1370             ECORE_LINK_PARTNER_SPEED_50G : 0;
1371         p_link->partner_adv_speed |=
1372             (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1373             ECORE_LINK_PARTNER_SPEED_100G : 0;
1374
1375         p_link->partner_tx_flow_ctrl_en =
1376             !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1377         p_link->partner_rx_flow_ctrl_en =
1378             !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1379
1380         switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1381         case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1382                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_SYMMETRIC_PAUSE;
1383                 break;
1384         case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1385                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_ASYMMETRIC_PAUSE;
1386                 break;
1387         case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1388                 p_link->partner_adv_pause = ECORE_LINK_PARTNER_BOTH_PAUSE;
1389                 break;
1390         default:
1391                 p_link->partner_adv_pause = 0;
1392         }
1393
1394         p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1395
1396         if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1397                 ecore_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1398
1399         OSAL_LINK_UPDATE(p_hwfn, p_ptt);
1400 out:
1401         OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->link_lock);
1402 }
1403
1404 enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
1405                                         struct ecore_ptt *p_ptt, bool b_up)
1406 {
1407         struct ecore_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1408         struct ecore_mcp_mb_params mb_params;
1409         struct eth_phy_cfg phy_cfg;
1410         enum _ecore_status_t rc = ECORE_SUCCESS;
1411         u32 cmd;
1412
1413 #ifndef ASIC_ONLY
1414         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
1415                 return ECORE_SUCCESS;
1416 #endif
1417
1418         /* Set the shmem configuration according to params */
1419         OSAL_MEM_ZERO(&phy_cfg, sizeof(phy_cfg));
1420         cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1421         if (!params->speed.autoneg)
1422                 phy_cfg.speed = params->speed.forced_speed;
1423         phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1424         phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1425         phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1426         phy_cfg.adv_speed = params->speed.advertised_speeds;
1427         phy_cfg.loopback_mode = params->loopback_mode;
1428
1429         /* There are MFWs that share this capability regardless of whether
1430          * this is feasible or not. And given that at the very least adv_caps
1431          * would be set internally by ecore, we want to make sure LFA would
1432          * still work.
1433          */
1434         if ((p_hwfn->mcp_info->capabilities &
1435              FW_MB_PARAM_FEATURE_SUPPORT_EEE) &&
1436             params->eee.enable) {
1437                 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1438                 if (params->eee.tx_lpi_enable)
1439                         phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1440                 if (params->eee.adv_caps & ECORE_EEE_1G_ADV)
1441                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1442                 if (params->eee.adv_caps & ECORE_EEE_10G_ADV)
1443                         phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1444                 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1445                                     EEE_TX_TIMER_USEC_OFFSET) &
1446                                         EEE_TX_TIMER_USEC_MASK;
1447         }
1448
1449         p_hwfn->b_drv_link_init = b_up;
1450
1451         if (b_up)
1452                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1453                            "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x\n",
1454                            phy_cfg.speed, phy_cfg.pause, phy_cfg.adv_speed,
1455                            phy_cfg.loopback_mode);
1456         else
1457                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK, "Resetting link\n");
1458
1459         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1460         mb_params.cmd = cmd;
1461         mb_params.p_data_src = &phy_cfg;
1462         mb_params.data_src_size = sizeof(phy_cfg);
1463         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1464
1465         /* if mcp fails to respond we must abort */
1466         if (rc != ECORE_SUCCESS) {
1467                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1468                 return rc;
1469         }
1470
1471         /* Mimic link-change attention, done for several reasons:
1472          *  - On reset, there's no guarantee MFW would trigger
1473          *    an attention.
1474          *  - On initialization, older MFWs might not indicate link change
1475          *    during LFA, so we'll never get an UP indication.
1476          */
1477         ecore_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1478
1479         return ECORE_SUCCESS;
1480 }
1481
1482 u32 ecore_get_process_kill_counter(struct ecore_hwfn *p_hwfn,
1483                                    struct ecore_ptt *p_ptt)
1484 {
1485         u32 path_offsize_addr, path_offsize, path_addr, proc_kill_cnt;
1486
1487         /* TODO - Add support for VFs */
1488         if (IS_VF(p_hwfn->p_dev))
1489                 return ECORE_INVAL;
1490
1491         path_offsize_addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1492                                                  PUBLIC_PATH);
1493         path_offsize = ecore_rd(p_hwfn, p_ptt, path_offsize_addr);
1494         path_addr = SECTION_ADDR(path_offsize, ECORE_PATH_ID(p_hwfn));
1495
1496         proc_kill_cnt = ecore_rd(p_hwfn, p_ptt,
1497                                  path_addr +
1498                                  OFFSETOF(struct public_path, process_kill)) &
1499             PROCESS_KILL_COUNTER_MASK;
1500
1501         return proc_kill_cnt;
1502 }
1503
1504 static void ecore_mcp_handle_process_kill(struct ecore_hwfn *p_hwfn,
1505                                           struct ecore_ptt *p_ptt)
1506 {
1507         struct ecore_dev *p_dev = p_hwfn->p_dev;
1508         u32 proc_kill_cnt;
1509
1510         /* Prevent possible attentions/interrupts during the recovery handling
1511          * and till its load phase, during which they will be re-enabled.
1512          */
1513         ecore_int_igu_disable_int(p_hwfn, p_ptt);
1514
1515         DP_NOTICE(p_hwfn, false, "Received a process kill indication\n");
1516
1517         /* The following operations should be done once, and thus in CMT mode
1518          * are carried out by only the first HW function.
1519          */
1520         if (p_hwfn != ECORE_LEADING_HWFN(p_dev))
1521                 return;
1522
1523         if (p_dev->recov_in_prog) {
1524                 DP_NOTICE(p_hwfn, false,
1525                           "Ignoring the indication since a recovery"
1526                           " process is already in progress\n");
1527                 return;
1528         }
1529
1530         p_dev->recov_in_prog = true;
1531
1532         proc_kill_cnt = ecore_get_process_kill_counter(p_hwfn, p_ptt);
1533         DP_NOTICE(p_hwfn, false, "Process kill counter: %d\n", proc_kill_cnt);
1534
1535         OSAL_SCHEDULE_RECOVERY_HANDLER(p_hwfn);
1536 }
1537
1538 static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
1539                                           struct ecore_ptt *p_ptt,
1540                                           enum MFW_DRV_MSG_TYPE type)
1541 {
1542         enum ecore_mcp_protocol_type stats_type;
1543         union ecore_mcp_protocol_stats stats;
1544         struct ecore_mcp_mb_params mb_params;
1545         u32 hsi_param;
1546         enum _ecore_status_t rc;
1547
1548         switch (type) {
1549         case MFW_DRV_MSG_GET_LAN_STATS:
1550                 stats_type = ECORE_MCP_LAN_STATS;
1551                 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1552                 break;
1553         default:
1554                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1555                            "Invalid protocol type %d\n", type);
1556                 return;
1557         }
1558
1559         OSAL_GET_PROTOCOL_STATS(p_hwfn->p_dev, stats_type, &stats);
1560
1561         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1562         mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1563         mb_params.param = hsi_param;
1564         mb_params.p_data_src = &stats;
1565         mb_params.data_src_size = sizeof(stats);
1566         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1567         if (rc != ECORE_SUCCESS)
1568                 DP_ERR(p_hwfn, "Failed to send protocol stats, rc = %d\n", rc);
1569 }
1570
1571 static void ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
1572                                     struct public_func *p_shmem_info)
1573 {
1574         struct ecore_mcp_function_info *p_info;
1575
1576         p_info = &p_hwfn->mcp_info->func_info;
1577
1578         /* TODO - bandwidth min/max should have valid values of 1-100,
1579          * as well as some indication that the feature is disabled.
1580          * Until MFW/qlediag enforce those limitations, Assume THERE IS ALWAYS
1581          * limit and correct value to min `1' and max `100' if limit isn't in
1582          * range.
1583          */
1584         p_info->bandwidth_min = (p_shmem_info->config &
1585                                  FUNC_MF_CFG_MIN_BW_MASK) >>
1586             FUNC_MF_CFG_MIN_BW_OFFSET;
1587         if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1588                 DP_INFO(p_hwfn,
1589                         "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1590                         p_info->bandwidth_min);
1591                 p_info->bandwidth_min = 1;
1592         }
1593
1594         p_info->bandwidth_max = (p_shmem_info->config &
1595                                  FUNC_MF_CFG_MAX_BW_MASK) >>
1596             FUNC_MF_CFG_MAX_BW_OFFSET;
1597         if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1598                 DP_INFO(p_hwfn,
1599                         "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1600                         p_info->bandwidth_max);
1601                 p_info->bandwidth_max = 100;
1602         }
1603 }
1604
1605 static void
1606 ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1607 {
1608         struct ecore_mcp_function_info *p_info;
1609         struct public_func shmem_info;
1610         u32 resp = 0, param = 0;
1611
1612         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1613
1614         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
1615
1616         p_info = &p_hwfn->mcp_info->func_info;
1617
1618         ecore_configure_pf_min_bandwidth(p_hwfn->p_dev, p_info->bandwidth_min);
1619
1620         ecore_configure_pf_max_bandwidth(p_hwfn->p_dev, p_info->bandwidth_max);
1621
1622         /* Acknowledge the MFW */
1623         ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1624                       &param);
1625 }
1626
1627 static void ecore_mcp_handle_fan_failure(struct ecore_hwfn *p_hwfn)
1628 {
1629         /* A single notification should be sent to upper driver in CMT mode */
1630         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1631                 return;
1632
1633         DP_NOTICE(p_hwfn, false,
1634                   "Fan failure was detected on the network interface card"
1635                   " and it's going to be shut down.\n");
1636
1637         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_FAN_FAIL);
1638 }
1639
1640 struct ecore_mdump_cmd_params {
1641         u32 cmd;
1642         void *p_data_src;
1643         u8 data_src_size;
1644         void *p_data_dst;
1645         u8 data_dst_size;
1646         u32 mcp_resp;
1647 };
1648
1649 static enum _ecore_status_t
1650 ecore_mcp_mdump_cmd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1651                     struct ecore_mdump_cmd_params *p_mdump_cmd_params)
1652 {
1653         struct ecore_mcp_mb_params mb_params;
1654         enum _ecore_status_t rc;
1655
1656         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
1657         mb_params.cmd = DRV_MSG_CODE_MDUMP_CMD;
1658         mb_params.param = p_mdump_cmd_params->cmd;
1659         mb_params.p_data_src = p_mdump_cmd_params->p_data_src;
1660         mb_params.data_src_size = p_mdump_cmd_params->data_src_size;
1661         mb_params.p_data_dst = p_mdump_cmd_params->p_data_dst;
1662         mb_params.data_dst_size = p_mdump_cmd_params->data_dst_size;
1663         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1664         if (rc != ECORE_SUCCESS)
1665                 return rc;
1666
1667         p_mdump_cmd_params->mcp_resp = mb_params.mcp_resp;
1668
1669         if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_MDUMP_INVALID_CMD) {
1670                 DP_INFO(p_hwfn,
1671                         "The mdump sub command is unsupported by the MFW [mdump_cmd 0x%x]\n",
1672                         p_mdump_cmd_params->cmd);
1673                 rc = ECORE_NOTIMPL;
1674         } else if (p_mdump_cmd_params->mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
1675                 DP_INFO(p_hwfn,
1676                         "The mdump command is not supported by the MFW\n");
1677                 rc = ECORE_NOTIMPL;
1678         }
1679
1680         return rc;
1681 }
1682
1683 static enum _ecore_status_t ecore_mcp_mdump_ack(struct ecore_hwfn *p_hwfn,
1684                                                 struct ecore_ptt *p_ptt)
1685 {
1686         struct ecore_mdump_cmd_params mdump_cmd_params;
1687
1688         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1689         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_ACK;
1690
1691         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1692 }
1693
1694 enum _ecore_status_t ecore_mcp_mdump_set_values(struct ecore_hwfn *p_hwfn,
1695                                                 struct ecore_ptt *p_ptt,
1696                                                 u32 epoch)
1697 {
1698         struct ecore_mdump_cmd_params mdump_cmd_params;
1699
1700         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1701         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_SET_VALUES;
1702         mdump_cmd_params.p_data_src = &epoch;
1703         mdump_cmd_params.data_src_size = sizeof(epoch);
1704
1705         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1706 }
1707
1708 enum _ecore_status_t ecore_mcp_mdump_trigger(struct ecore_hwfn *p_hwfn,
1709                                              struct ecore_ptt *p_ptt)
1710 {
1711         struct ecore_mdump_cmd_params mdump_cmd_params;
1712
1713         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1714         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_TRIGGER;
1715
1716         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1717 }
1718
1719 static enum _ecore_status_t
1720 ecore_mcp_mdump_get_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1721                            struct mdump_config_stc *p_mdump_config)
1722 {
1723         struct ecore_mdump_cmd_params mdump_cmd_params;
1724         enum _ecore_status_t rc;
1725
1726         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1727         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_CONFIG;
1728         mdump_cmd_params.p_data_dst = p_mdump_config;
1729         mdump_cmd_params.data_dst_size = sizeof(*p_mdump_config);
1730
1731         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1732         if (rc != ECORE_SUCCESS)
1733                 return rc;
1734
1735         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1736                 DP_INFO(p_hwfn,
1737                         "Failed to get the mdump configuration and logs info [mcp_resp 0x%x]\n",
1738                         mdump_cmd_params.mcp_resp);
1739                 rc = ECORE_UNKNOWN_ERROR;
1740         }
1741
1742         return rc;
1743 }
1744
1745 enum _ecore_status_t
1746 ecore_mcp_mdump_get_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1747                          struct ecore_mdump_info *p_mdump_info)
1748 {
1749         u32 addr, global_offsize, global_addr;
1750         struct mdump_config_stc mdump_config;
1751         enum _ecore_status_t rc;
1752
1753         OSAL_MEMSET(p_mdump_info, 0, sizeof(*p_mdump_info));
1754
1755         addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1756                                     PUBLIC_GLOBAL);
1757         global_offsize = ecore_rd(p_hwfn, p_ptt, addr);
1758         global_addr = SECTION_ADDR(global_offsize, 0);
1759         p_mdump_info->reason = ecore_rd(p_hwfn, p_ptt,
1760                                         global_addr +
1761                                         OFFSETOF(struct public_global,
1762                                                  mdump_reason));
1763
1764         if (p_mdump_info->reason) {
1765                 rc = ecore_mcp_mdump_get_config(p_hwfn, p_ptt, &mdump_config);
1766                 if (rc != ECORE_SUCCESS)
1767                         return rc;
1768
1769                 p_mdump_info->version = mdump_config.version;
1770                 p_mdump_info->config = mdump_config.config;
1771                 p_mdump_info->epoch = mdump_config.epoc;
1772                 p_mdump_info->num_of_logs = mdump_config.num_of_logs;
1773                 p_mdump_info->valid_logs = mdump_config.valid_logs;
1774
1775                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1776                            "MFW mdump info: reason %d, version 0x%x, config 0x%x, epoch 0x%x, num_of_logs 0x%x, valid_logs 0x%x\n",
1777                            p_mdump_info->reason, p_mdump_info->version,
1778                            p_mdump_info->config, p_mdump_info->epoch,
1779                            p_mdump_info->num_of_logs, p_mdump_info->valid_logs);
1780         } else {
1781                 DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
1782                            "MFW mdump info: reason %d\n", p_mdump_info->reason);
1783         }
1784
1785         return ECORE_SUCCESS;
1786 }
1787
1788 enum _ecore_status_t ecore_mcp_mdump_clear_logs(struct ecore_hwfn *p_hwfn,
1789                                                 struct ecore_ptt *p_ptt)
1790 {
1791         struct ecore_mdump_cmd_params mdump_cmd_params;
1792
1793         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1794         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLEAR_LOGS;
1795
1796         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1797 }
1798
1799 enum _ecore_status_t
1800 ecore_mcp_mdump_get_retain(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
1801                            struct ecore_mdump_retain_data *p_mdump_retain)
1802 {
1803         struct ecore_mdump_cmd_params mdump_cmd_params;
1804         struct mdump_retain_data_stc mfw_mdump_retain;
1805         enum _ecore_status_t rc;
1806
1807         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1808         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_GET_RETAIN;
1809         mdump_cmd_params.p_data_dst = &mfw_mdump_retain;
1810         mdump_cmd_params.data_dst_size = sizeof(mfw_mdump_retain);
1811
1812         rc = ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1813         if (rc != ECORE_SUCCESS)
1814                 return rc;
1815
1816         if (mdump_cmd_params.mcp_resp != FW_MSG_CODE_OK) {
1817                 DP_INFO(p_hwfn,
1818                         "Failed to get the mdump retained data [mcp_resp 0x%x]\n",
1819                         mdump_cmd_params.mcp_resp);
1820                 return ECORE_UNKNOWN_ERROR;
1821         }
1822
1823         p_mdump_retain->valid = mfw_mdump_retain.valid;
1824         p_mdump_retain->epoch = mfw_mdump_retain.epoch;
1825         p_mdump_retain->pf = mfw_mdump_retain.pf;
1826         p_mdump_retain->status = mfw_mdump_retain.status;
1827
1828         return ECORE_SUCCESS;
1829 }
1830
1831 enum _ecore_status_t ecore_mcp_mdump_clr_retain(struct ecore_hwfn *p_hwfn,
1832                                                 struct ecore_ptt *p_ptt)
1833 {
1834         struct ecore_mdump_cmd_params mdump_cmd_params;
1835
1836         OSAL_MEM_ZERO(&mdump_cmd_params, sizeof(mdump_cmd_params));
1837         mdump_cmd_params.cmd = DRV_MSG_CODE_MDUMP_CLR_RETAIN;
1838
1839         return ecore_mcp_mdump_cmd(p_hwfn, p_ptt, &mdump_cmd_params);
1840 }
1841
1842 static void ecore_mcp_handle_critical_error(struct ecore_hwfn *p_hwfn,
1843                                             struct ecore_ptt *p_ptt)
1844 {
1845         struct ecore_mdump_retain_data mdump_retain;
1846         enum _ecore_status_t rc;
1847
1848         /* In CMT mode - no need for more than a single acknowledgment to the
1849          * MFW, and no more than a single notification to the upper driver.
1850          */
1851         if (p_hwfn != ECORE_LEADING_HWFN(p_hwfn->p_dev))
1852                 return;
1853
1854         rc = ecore_mcp_mdump_get_retain(p_hwfn, p_ptt, &mdump_retain);
1855         if (rc == ECORE_SUCCESS && mdump_retain.valid) {
1856                 DP_NOTICE(p_hwfn, false,
1857                           "The MFW notified that a critical error occurred in the device [epoch 0x%08x, pf 0x%x, status 0x%08x]\n",
1858                           mdump_retain.epoch, mdump_retain.pf,
1859                           mdump_retain.status);
1860         } else {
1861                 DP_NOTICE(p_hwfn, false,
1862                           "The MFW notified that a critical error occurred in the device\n");
1863         }
1864
1865         if (p_hwfn->p_dev->allow_mdump) {
1866                 DP_NOTICE(p_hwfn, false,
1867                           "Not acknowledging the notification to allow the MFW crash dump\n");
1868                 return;
1869         }
1870
1871         DP_NOTICE(p_hwfn, false,
1872                   "Acknowledging the notification to not allow the MFW crash dump [driver debug data collection is preferable]\n");
1873         ecore_mcp_mdump_ack(p_hwfn, p_ptt);
1874         ecore_hw_err_notify(p_hwfn, ECORE_HW_ERR_HW_ATTN);
1875 }
1876
1877 void
1878 ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1879 {
1880         struct public_func shmem_info;
1881         u32 port_cfg, val;
1882
1883         if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
1884                 return;
1885
1886         OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));
1887         port_cfg = ecore_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1888                             OFFSETOF(struct public_port, oem_cfg_port));
1889         val = GET_MFW_FIELD(port_cfg, OEM_CFG_CHANNEL_TYPE);
1890         if (val != OEM_CFG_CHANNEL_TYPE_STAGGED)
1891                 DP_NOTICE(p_hwfn, false, "Incorrect UFP Channel type  %d\n",
1892                           val);
1893
1894         val = GET_MFW_FIELD(port_cfg, OEM_CFG_SCHED_TYPE);
1895         if (val == OEM_CFG_SCHED_TYPE_ETS)
1896                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_ETS;
1897         else if (val == OEM_CFG_SCHED_TYPE_VNIC_BW)
1898                 p_hwfn->ufp_info.mode = ECORE_UFP_MODE_VNIC_BW;
1899         else
1900                 DP_NOTICE(p_hwfn, false, "Unknown UFP scheduling mode %d\n",
1901                           val);
1902
1903         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
1904                                  MCP_PF_ID(p_hwfn));
1905         val = GET_MFW_FIELD(shmem_info.oem_cfg_func, OEM_CFG_FUNC_TC);
1906         p_hwfn->ufp_info.tc = (u8)val;
1907         val = GET_MFW_FIELD(shmem_info.oem_cfg_func,
1908                             OEM_CFG_FUNC_HOST_PRI_CTRL);
1909         if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC)
1910                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_VNIC;
1911         else if (val == OEM_CFG_FUNC_HOST_PRI_CTRL_OS)
1912                 p_hwfn->ufp_info.pri_type = ECORE_UFP_PRI_OS;
1913         else
1914                 DP_NOTICE(p_hwfn, false, "Unknown Host priority control %d\n",
1915                           val);
1916
1917         DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
1918                    "UFP shmem config: mode = %d tc = %d pri_type = %d\n",
1919                    p_hwfn->ufp_info.mode, p_hwfn->ufp_info.tc,
1920                    p_hwfn->ufp_info.pri_type);
1921 }
1922
1923 static enum _ecore_status_t
1924 ecore_mcp_handle_ufp_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
1925 {
1926         ecore_mcp_read_ufp_config(p_hwfn, p_ptt);
1927
1928         if (p_hwfn->ufp_info.mode == ECORE_UFP_MODE_VNIC_BW) {
1929                 p_hwfn->qm_info.ooo_tc = p_hwfn->ufp_info.tc;
1930                 p_hwfn->hw_info.offload_tc = p_hwfn->ufp_info.tc;
1931
1932                 ecore_qm_reconf(p_hwfn, p_ptt);
1933         } else {
1934                 /* Merge UFP TC with the dcbx TC data */
1935                 ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1936                                             ECORE_DCBX_OPERATIONAL_MIB);
1937         }
1938
1939         /* update storm FW with negotiation results */
1940         ecore_sp_pf_update_ufp(p_hwfn);
1941
1942         return ECORE_SUCCESS;
1943 }
1944
1945 enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
1946                                              struct ecore_ptt *p_ptt)
1947 {
1948         struct ecore_mcp_info *info = p_hwfn->mcp_info;
1949         enum _ecore_status_t rc = ECORE_SUCCESS;
1950         bool found = false;
1951         u16 i;
1952
1953         DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Received message from MFW\n");
1954
1955         /* Read Messages from MFW */
1956         ecore_mcp_read_mb(p_hwfn, p_ptt);
1957
1958         /* Compare current messages to old ones */
1959         for (i = 0; i < info->mfw_mb_length; i++) {
1960                 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1961                         continue;
1962
1963                 found = true;
1964
1965                 DP_VERBOSE(p_hwfn, ECORE_MSG_LINK,
1966                            "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1967                            i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1968
1969                 switch (i) {
1970                 case MFW_DRV_MSG_LINK_CHANGE:
1971                         ecore_mcp_handle_link_change(p_hwfn, p_ptt, false);
1972                         break;
1973                 case MFW_DRV_MSG_VF_DISABLED:
1974                         ecore_mcp_handle_vf_flr(p_hwfn, p_ptt);
1975                         break;
1976                 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1977                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1978                                                     ECORE_DCBX_REMOTE_LLDP_MIB);
1979                         break;
1980                 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1981                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1982                                                     ECORE_DCBX_REMOTE_MIB);
1983                         break;
1984                 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1985                         ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
1986                                                     ECORE_DCBX_OPERATIONAL_MIB);
1987                         /* clear the user-config cache */
1988                         OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
1989                                     sizeof(struct ecore_dcbx_set));
1990                         break;
1991                 case MFW_DRV_MSG_LLDP_RECEIVED_TLVS_UPDATED:
1992                         ecore_lldp_mib_update_event(p_hwfn, p_ptt);
1993                         break;
1994                 case MFW_DRV_MSG_OEM_CFG_UPDATE:
1995                         ecore_mcp_handle_ufp_event(p_hwfn, p_ptt);
1996                         break;
1997                 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1998                         ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1999                         break;
2000                 case MFW_DRV_MSG_ERROR_RECOVERY:
2001                         ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
2002                         break;
2003                 case MFW_DRV_MSG_GET_LAN_STATS:
2004                 case MFW_DRV_MSG_GET_FCOE_STATS:
2005                 case MFW_DRV_MSG_GET_ISCSI_STATS:
2006                 case MFW_DRV_MSG_GET_RDMA_STATS:
2007                         ecore_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
2008                         break;
2009                 case MFW_DRV_MSG_BW_UPDATE:
2010                         ecore_mcp_update_bw(p_hwfn, p_ptt);
2011                         break;
2012                 case MFW_DRV_MSG_FAILURE_DETECTED:
2013                         ecore_mcp_handle_fan_failure(p_hwfn);
2014                         break;
2015                 case MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED:
2016                         ecore_mcp_handle_critical_error(p_hwfn, p_ptt);
2017                         break;
2018                 default:
2019                         DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
2020                         rc = ECORE_INVAL;
2021                 }
2022         }
2023
2024         /* ACK everything */
2025         for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
2026                 OSAL_BE32 val = OSAL_CPU_TO_BE32(((u32 *)info->mfw_mb_cur)[i]);
2027
2028                 /* MFW expect answer in BE, so we force write in that format */
2029                 ecore_wr(p_hwfn, p_ptt,
2030                          info->mfw_mb_addr + sizeof(u32) +
2031                          MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
2032                          sizeof(u32) + i * sizeof(u32), val);
2033         }
2034
2035         if (!found) {
2036                 DP_NOTICE(p_hwfn, false,
2037                           "Received an MFW message indication but no"
2038                           " new message!\n");
2039                 rc = ECORE_INVAL;
2040         }
2041
2042         /* Copy the new mfw messages into the shadow */
2043         OSAL_MEMCPY(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
2044
2045         return rc;
2046 }
2047
2048 enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
2049                                            struct ecore_ptt *p_ptt,
2050                                            u32 *p_mfw_ver,
2051                                            u32 *p_running_bundle_id)
2052 {
2053         u32 global_offsize;
2054
2055 #ifndef ASIC_ONLY
2056         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2057                 DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
2058                 return ECORE_SUCCESS;
2059         }
2060 #endif
2061
2062         if (IS_VF(p_hwfn->p_dev)) {
2063                 if (p_hwfn->vf_iov_info) {
2064                         struct pfvf_acquire_resp_tlv *p_resp;
2065
2066                         p_resp = &p_hwfn->vf_iov_info->acquire_resp;
2067                         *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
2068                         return ECORE_SUCCESS;
2069                 } else {
2070                         DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2071                                    "VF requested MFW version prior to ACQUIRE\n");
2072                         return ECORE_INVAL;
2073                 }
2074         }
2075
2076         global_offsize = ecore_rd(p_hwfn, p_ptt,
2077                                   SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
2078                                                        public_base,
2079                                                        PUBLIC_GLOBAL));
2080         *p_mfw_ver =
2081             ecore_rd(p_hwfn, p_ptt,
2082                      SECTION_ADDR(global_offsize,
2083                                   0) + OFFSETOF(struct public_global, mfw_ver));
2084
2085         if (p_running_bundle_id != OSAL_NULL) {
2086                 *p_running_bundle_id = ecore_rd(p_hwfn, p_ptt,
2087                                                 SECTION_ADDR(global_offsize,
2088                                                              0) +
2089                                                 OFFSETOF(struct public_global,
2090                                                          running_bundle_id));
2091         }
2092
2093         return ECORE_SUCCESS;
2094 }
2095
2096 enum _ecore_status_t ecore_mcp_get_media_type(struct ecore_hwfn *p_hwfn,
2097                                               struct ecore_ptt *p_ptt,
2098                                               u32 *p_media_type)
2099 {
2100
2101         /* TODO - Add support for VFs */
2102         if (IS_VF(p_hwfn->p_dev))
2103                 return ECORE_INVAL;
2104
2105         if (!ecore_mcp_is_init(p_hwfn)) {
2106                 DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
2107                 return ECORE_BUSY;
2108         }
2109
2110         if (!p_ptt) {
2111                 *p_media_type = MEDIA_UNSPECIFIED;
2112                 return ECORE_INVAL;
2113         } else {
2114                 *p_media_type = ecore_rd(p_hwfn, p_ptt,
2115                                          p_hwfn->mcp_info->port_addr +
2116                                          OFFSETOF(struct public_port,
2117                                                   media_type));
2118         }
2119
2120         return ECORE_SUCCESS;
2121 }
2122
2123 /* @DPDK */
2124 /* Old MFW has a global configuration for all PFs regarding RDMA support */
2125 static void
2126 ecore_mcp_get_shmem_proto_legacy(struct ecore_hwfn *p_hwfn,
2127                                  enum ecore_pci_personality *p_proto)
2128 {
2129         *p_proto = ECORE_PCI_ETH;
2130
2131         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2132                    "According to Legacy capabilities, L2 personality is %08x\n",
2133                    (u32)*p_proto);
2134 }
2135
2136 /* @DPDK */
2137 static enum _ecore_status_t
2138 ecore_mcp_get_shmem_proto_mfw(struct ecore_hwfn *p_hwfn,
2139                               struct ecore_ptt *p_ptt,
2140                               enum ecore_pci_personality *p_proto)
2141 {
2142         u32 resp = 0, param = 0;
2143         enum _ecore_status_t rc;
2144
2145         DP_VERBOSE(p_hwfn, ECORE_MSG_IFUP,
2146                    "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
2147                    (u32)*p_proto, resp, param);
2148         return ECORE_SUCCESS;
2149 }
2150
2151 static enum _ecore_status_t
2152 ecore_mcp_get_shmem_proto(struct ecore_hwfn *p_hwfn,
2153                           struct public_func *p_info,
2154                           struct ecore_ptt *p_ptt,
2155                           enum ecore_pci_personality *p_proto)
2156 {
2157         enum _ecore_status_t rc = ECORE_SUCCESS;
2158
2159         switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
2160         case FUNC_MF_CFG_PROTOCOL_ETHERNET:
2161                 if (ecore_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto) !=
2162                     ECORE_SUCCESS)
2163                         ecore_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
2164                 break;
2165         default:
2166                 rc = ECORE_INVAL;
2167         }
2168
2169         return rc;
2170 }
2171
2172 enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
2173                                                     struct ecore_ptt *p_ptt)
2174 {
2175         struct ecore_mcp_function_info *info;
2176         struct public_func shmem_info;
2177
2178         ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
2179         info = &p_hwfn->mcp_info->func_info;
2180
2181         info->pause_on_host = (shmem_info.config &
2182                                FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
2183
2184         if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2185                                       &info->protocol)) {
2186                 DP_ERR(p_hwfn, "Unknown personality %08x\n",
2187                        (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
2188                 return ECORE_INVAL;
2189         }
2190
2191         ecore_read_pf_bandwidth(p_hwfn, &shmem_info);
2192
2193         if (shmem_info.mac_upper || shmem_info.mac_lower) {
2194                 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
2195                 info->mac[1] = (u8)(shmem_info.mac_upper);
2196                 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
2197                 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
2198                 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
2199                 info->mac[5] = (u8)(shmem_info.mac_lower);
2200         } else {
2201                 /* TODO - are there protocols for which there's no MAC? */
2202                 DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
2203         }
2204
2205         /* TODO - are these calculations true for BE machine? */
2206         info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
2207                          (((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
2208         info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
2209                          (((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
2210
2211         info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
2212
2213         info->mtu = (u16)shmem_info.mtu_size;
2214
2215         if (info->mtu == 0)
2216                 info->mtu = 1500;
2217
2218         info->mtu = (u16)shmem_info.mtu_size;
2219
2220         DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
2221                    "Read configuration from shmem: pause_on_host %02x"
2222                     " protocol %02x BW [%02x - %02x]"
2223                     " MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
2224                     " node %lx ovlan %04x\n",
2225                    info->pause_on_host, info->protocol,
2226                    info->bandwidth_min, info->bandwidth_max,
2227                    info->mac[0], info->mac[1], info->mac[2],
2228                    info->mac[3], info->mac[4], info->mac[5],
2229                    (unsigned long)info->wwn_port,
2230                    (unsigned long)info->wwn_node, info->ovlan);
2231
2232         return ECORE_SUCCESS;
2233 }
2234
2235 struct ecore_mcp_link_params
2236 *ecore_mcp_get_link_params(struct ecore_hwfn *p_hwfn)
2237 {
2238         if (!p_hwfn || !p_hwfn->mcp_info)
2239                 return OSAL_NULL;
2240         return &p_hwfn->mcp_info->link_input;
2241 }
2242
2243 struct ecore_mcp_link_state
2244 *ecore_mcp_get_link_state(struct ecore_hwfn *p_hwfn)
2245 {
2246         if (!p_hwfn || !p_hwfn->mcp_info)
2247                 return OSAL_NULL;
2248
2249 #ifndef ASIC_ONLY
2250         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev)) {
2251                 DP_INFO(p_hwfn, "Non-ASIC - always notify that link is up\n");
2252                 p_hwfn->mcp_info->link_output.link_up = true;
2253         }
2254 #endif
2255
2256         return &p_hwfn->mcp_info->link_output;
2257 }
2258
2259 struct ecore_mcp_link_capabilities
2260 *ecore_mcp_get_link_capabilities(struct ecore_hwfn *p_hwfn)
2261 {
2262         if (!p_hwfn || !p_hwfn->mcp_info)
2263                 return OSAL_NULL;
2264         return &p_hwfn->mcp_info->link_capabilities;
2265 }
2266
2267 enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
2268                                      struct ecore_ptt *p_ptt)
2269 {
2270         u32 resp = 0, param = 0;
2271         enum _ecore_status_t rc;
2272
2273         rc = ecore_mcp_cmd(p_hwfn, p_ptt,
2274                            DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
2275
2276         /* Wait for the drain to complete before returning */
2277         OSAL_MSLEEP(1020);
2278
2279         return rc;
2280 }
2281
2282 const struct ecore_mcp_function_info
2283 *ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn)
2284 {
2285         if (!p_hwfn || !p_hwfn->mcp_info)
2286                 return OSAL_NULL;
2287         return &p_hwfn->mcp_info->func_info;
2288 }
2289
2290 int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
2291                                   struct ecore_ptt *p_ptt, u32 personalities)
2292 {
2293         enum ecore_pci_personality protocol = ECORE_PCI_DEFAULT;
2294         struct public_func shmem_info;
2295         int i, count = 0, num_pfs;
2296
2297         num_pfs = NUM_OF_ENG_PFS(p_hwfn->p_dev);
2298
2299         for (i = 0; i < num_pfs; i++) {
2300                 ecore_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info,
2301                                          MCP_PF_ID_BY_REL(p_hwfn, i));
2302                 if (shmem_info.config & FUNC_MF_CFG_FUNC_HIDE)
2303                         continue;
2304
2305                 if (ecore_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
2306                                               &protocol) !=
2307                     ECORE_SUCCESS)
2308                         continue;
2309
2310                 if ((1 << ((u32)protocol)) & personalities)
2311                         count++;
2312         }
2313
2314         return count;
2315 }
2316
2317 enum _ecore_status_t ecore_mcp_get_flash_size(struct ecore_hwfn *p_hwfn,
2318                                               struct ecore_ptt *p_ptt,
2319                                               u32 *p_flash_size)
2320 {
2321         u32 flash_size;
2322
2323 #ifndef ASIC_ONLY
2324         if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
2325                 DP_NOTICE(p_hwfn, false, "Emulation - can't get flash size\n");
2326                 return ECORE_INVAL;
2327         }
2328 #endif
2329
2330         if (IS_VF(p_hwfn->p_dev))
2331                 return ECORE_INVAL;
2332
2333         flash_size = ecore_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
2334         flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
2335                      MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
2336         flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_OFFSET));
2337
2338         *p_flash_size = flash_size;
2339
2340         return ECORE_SUCCESS;
2341 }
2342
2343 enum _ecore_status_t ecore_start_recovery_process(struct ecore_hwfn *p_hwfn,
2344                                                   struct ecore_ptt *p_ptt)
2345 {
2346         struct ecore_dev *p_dev = p_hwfn->p_dev;
2347
2348         if (p_dev->recov_in_prog) {
2349                 DP_NOTICE(p_hwfn, false,
2350                           "Avoid triggering a recovery since such a process"
2351                           " is already in progress\n");
2352                 return ECORE_AGAIN;
2353         }
2354
2355         DP_NOTICE(p_hwfn, false, "Triggering a recovery process\n");
2356         ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_GENERAL_ATTN_35, 0x1);
2357
2358         return ECORE_SUCCESS;
2359 }
2360
2361 static enum _ecore_status_t
2362 ecore_mcp_config_vf_msix_bb(struct ecore_hwfn *p_hwfn,
2363                             struct ecore_ptt *p_ptt,
2364                             u8 vf_id, u8 num)
2365 {
2366         u32 resp = 0, param = 0, rc_param = 0;
2367         enum _ecore_status_t rc;
2368
2369 /* Only Leader can configure MSIX, and need to take CMT into account */
2370
2371         if (!IS_LEAD_HWFN(p_hwfn))
2372                 return ECORE_SUCCESS;
2373         num *= p_hwfn->p_dev->num_hwfns;
2374
2375         param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_OFFSET) &
2376             DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
2377         param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_OFFSET) &
2378             DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
2379
2380         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
2381                            &resp, &rc_param);
2382
2383         if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
2384                 DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
2385                           vf_id);
2386                 rc = ECORE_INVAL;
2387         } else {
2388                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2389                            "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
2390                             num, vf_id);
2391         }
2392
2393         return rc;
2394 }
2395
2396 static enum _ecore_status_t
2397 ecore_mcp_config_vf_msix_ah(struct ecore_hwfn *p_hwfn,
2398                             struct ecore_ptt *p_ptt,
2399                             u8 num)
2400 {
2401         u32 resp = 0, param = num, rc_param = 0;
2402         enum _ecore_status_t rc;
2403
2404         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
2405                            param, &resp, &rc_param);
2406
2407         if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
2408                 DP_NOTICE(p_hwfn, true, "MFW failed to set MSI-X for VFs\n");
2409                 rc = ECORE_INVAL;
2410         } else {
2411                 DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
2412                            "Requested 0x%02x MSI-x interrupts for VFs\n",
2413                            num);
2414         }
2415
2416         return rc;
2417 }
2418
2419 enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
2420                                               struct ecore_ptt *p_ptt,
2421                                               u8 vf_id, u8 num)
2422 {
2423         if (ECORE_IS_BB(p_hwfn->p_dev))
2424                 return ecore_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
2425         else
2426                 return ecore_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
2427 }
2428
2429 enum _ecore_status_t
2430 ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2431                            struct ecore_mcp_drv_version *p_ver)
2432 {
2433         struct ecore_mcp_mb_params mb_params;
2434         struct drv_version_stc drv_version;
2435         u32 num_words, i;
2436         void *p_name;
2437         OSAL_BE32 val;
2438         enum _ecore_status_t rc;
2439
2440 #ifndef ASIC_ONLY
2441         if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
2442                 return ECORE_SUCCESS;
2443 #endif
2444
2445         OSAL_MEM_ZERO(&drv_version, sizeof(drv_version));
2446         drv_version.version = p_ver->version;
2447         num_words = (MCP_DRV_VER_STR_SIZE - 4) / 4;
2448         for (i = 0; i < num_words; i++) {
2449                 /* The driver name is expected to be in a big-endian format */
2450                 p_name = &p_ver->name[i * sizeof(u32)];
2451                 val = OSAL_CPU_TO_BE32(*(u32 *)p_name);
2452                 *(u32 *)&drv_version.name[i * sizeof(u32)] = val;
2453         }
2454
2455         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
2456         mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
2457         mb_params.p_data_src = &drv_version;
2458         mb_params.data_src_size = sizeof(drv_version);
2459         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2460         if (rc != ECORE_SUCCESS)
2461                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2462
2463         return rc;
2464 }
2465
2466 /* A maximal 100 msec waiting time for the MCP to halt */
2467 #define ECORE_MCP_HALT_SLEEP_MS         10
2468 #define ECORE_MCP_HALT_MAX_RETRIES      10
2469
2470 enum _ecore_status_t ecore_mcp_halt(struct ecore_hwfn *p_hwfn,
2471                                     struct ecore_ptt *p_ptt)
2472 {
2473         u32 resp = 0, param = 0, cpu_state, cnt = 0;
2474         enum _ecore_status_t rc;
2475
2476         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
2477                            &param);
2478         if (rc != ECORE_SUCCESS) {
2479                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2480                 return rc;
2481         }
2482
2483         do {
2484                 OSAL_MSLEEP(ECORE_MCP_HALT_SLEEP_MS);
2485                 cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2486                 if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED)
2487                         break;
2488         } while (++cnt < ECORE_MCP_HALT_MAX_RETRIES);
2489
2490         if (cnt == ECORE_MCP_HALT_MAX_RETRIES) {
2491                 DP_NOTICE(p_hwfn, false,
2492                           "Failed to halt the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2493                           ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE), cpu_state);
2494                 return ECORE_BUSY;
2495         }
2496
2497         ecore_mcp_cmd_set_blocking(p_hwfn, true);
2498
2499         return ECORE_SUCCESS;
2500 }
2501
2502 #define ECORE_MCP_RESUME_SLEEP_MS       10
2503
2504 enum _ecore_status_t ecore_mcp_resume(struct ecore_hwfn *p_hwfn,
2505                                       struct ecore_ptt *p_ptt)
2506 {
2507         u32 cpu_mode, cpu_state;
2508
2509         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2510
2511         cpu_mode = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2512         cpu_mode &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2513         ecore_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, cpu_mode);
2514
2515         OSAL_MSLEEP(ECORE_MCP_RESUME_SLEEP_MS);
2516         cpu_state = ecore_rd(p_hwfn, p_ptt, MCP_REG_CPU_STATE);
2517
2518         if (cpu_state & MCP_REG_CPU_STATE_SOFT_HALTED) {
2519                 DP_NOTICE(p_hwfn, false,
2520                           "Failed to resume the MCP [CPU_MODE = 0x%08x, CPU_STATE = 0x%08x]\n",
2521                           cpu_mode, cpu_state);
2522                 return ECORE_BUSY;
2523         }
2524
2525         ecore_mcp_cmd_set_blocking(p_hwfn, false);
2526
2527         return ECORE_SUCCESS;
2528 }
2529
2530 enum _ecore_status_t
2531 ecore_mcp_ov_update_current_config(struct ecore_hwfn *p_hwfn,
2532                                    struct ecore_ptt *p_ptt,
2533                                    enum ecore_ov_client client)
2534 {
2535         enum _ecore_status_t rc;
2536         u32 resp = 0, param = 0;
2537         u32 drv_mb_param;
2538
2539         switch (client) {
2540         case ECORE_OV_CLIENT_DRV:
2541                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2542                 break;
2543         case ECORE_OV_CLIENT_USER:
2544                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2545                 break;
2546         case ECORE_OV_CLIENT_VENDOR_SPEC:
2547                 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2548                 break;
2549         default:
2550                 DP_NOTICE(p_hwfn, true, "Invalid client type %d\n", client);
2551                 return ECORE_INVAL;
2552         }
2553
2554         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2555                            drv_mb_param, &resp, &param);
2556         if (rc != ECORE_SUCCESS)
2557                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2558
2559         return rc;
2560 }
2561
2562 enum _ecore_status_t
2563 ecore_mcp_ov_update_driver_state(struct ecore_hwfn *p_hwfn,
2564                                  struct ecore_ptt *p_ptt,
2565                                  enum ecore_ov_driver_state drv_state)
2566 {
2567         enum _ecore_status_t rc;
2568         u32 resp = 0, param = 0;
2569         u32 drv_mb_param;
2570
2571         switch (drv_state) {
2572         case ECORE_OV_DRIVER_STATE_NOT_LOADED:
2573                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2574                 break;
2575         case ECORE_OV_DRIVER_STATE_DISABLED:
2576                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2577                 break;
2578         case ECORE_OV_DRIVER_STATE_ACTIVE:
2579                 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2580                 break;
2581         default:
2582                 DP_NOTICE(p_hwfn, true, "Invalid driver state %d\n", drv_state);
2583                 return ECORE_INVAL;
2584         }
2585
2586         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2587                            drv_mb_param, &resp, &param);
2588         if (rc != ECORE_SUCCESS)
2589                 DP_ERR(p_hwfn, "Failed to send driver state\n");
2590
2591         return rc;
2592 }
2593
2594 enum _ecore_status_t
2595 ecore_mcp_ov_get_fc_npiv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
2596                          struct ecore_fc_npiv_tbl *p_table)
2597 {
2598         return 0;
2599 }
2600
2601 enum _ecore_status_t
2602 ecore_mcp_ov_update_mtu(struct ecore_hwfn *p_hwfn,
2603                         struct ecore_ptt *p_ptt, u16 mtu)
2604 {
2605         return 0;
2606 }
2607
2608 enum _ecore_status_t ecore_mcp_set_led(struct ecore_hwfn *p_hwfn,
2609                                        struct ecore_ptt *p_ptt,
2610                                        enum ecore_led_mode mode)
2611 {
2612         u32 resp = 0, param = 0, drv_mb_param;
2613         enum _ecore_status_t rc;
2614
2615         switch (mode) {
2616         case ECORE_LED_MODE_ON:
2617                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2618                 break;
2619         case ECORE_LED_MODE_OFF:
2620                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2621                 break;
2622         case ECORE_LED_MODE_RESTORE:
2623                 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2624                 break;
2625         default:
2626                 DP_NOTICE(p_hwfn, true, "Invalid LED mode %d\n", mode);
2627                 return ECORE_INVAL;
2628         }
2629
2630         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2631                            drv_mb_param, &resp, &param);
2632         if (rc != ECORE_SUCCESS)
2633                 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2634
2635         return rc;
2636 }
2637
2638 enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
2639                                              struct ecore_ptt *p_ptt,
2640                                              u32 mask_parities)
2641 {
2642         u32 resp = 0, param = 0;
2643         enum _ecore_status_t rc;
2644
2645         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2646                            mask_parities, &resp, &param);
2647
2648         if (rc != ECORE_SUCCESS) {
2649                 DP_ERR(p_hwfn,
2650                        "MCP response failure for mask parities, aborting\n");
2651         } else if (resp != FW_MSG_CODE_OK) {
2652                 DP_ERR(p_hwfn,
2653                        "MCP did not ack mask parity request. Old MFW?\n");
2654                 rc = ECORE_INVAL;
2655         }
2656
2657         return rc;
2658 }
2659
2660 enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
2661                                         u8 *p_buf, u32 len)
2662 {
2663         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2664         u32 bytes_left, offset, bytes_to_copy, buf_size;
2665         u32 nvm_offset, resp, param;
2666         struct ecore_ptt *p_ptt;
2667         enum _ecore_status_t rc = ECORE_SUCCESS;
2668
2669         p_ptt = ecore_ptt_acquire(p_hwfn);
2670         if (!p_ptt)
2671                 return ECORE_BUSY;
2672
2673         bytes_left = len;
2674         offset = 0;
2675         while (bytes_left > 0) {
2676                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2677                                            MCP_DRV_NVM_BUF_LEN);
2678                 nvm_offset = (addr + offset) | (bytes_to_copy <<
2679                                                 DRV_MB_PARAM_NVM_LEN_OFFSET);
2680                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2681                                           DRV_MSG_CODE_NVM_READ_NVRAM,
2682                                           nvm_offset, &resp, &param, &buf_size,
2683                                           (u32 *)(p_buf + offset));
2684                 if (rc != ECORE_SUCCESS) {
2685                         DP_NOTICE(p_dev, false,
2686                                   "ecore_mcp_nvm_rd_cmd() failed, rc = %d\n",
2687                                   rc);
2688                         resp = FW_MSG_CODE_ERROR;
2689                         break;
2690                 }
2691
2692                 if (resp != FW_MSG_CODE_NVM_OK) {
2693                         DP_NOTICE(p_dev, false,
2694                                   "nvm read failed, resp = 0x%08x\n", resp);
2695                         rc = ECORE_UNKNOWN_ERROR;
2696                         break;
2697                 }
2698
2699                 /* This can be a lengthy process, and it's possible scheduler
2700                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2701                  */
2702                 if (bytes_left % 0x1000 <
2703                     (bytes_left - buf_size) % 0x1000)
2704                         OSAL_MSLEEP(1);
2705
2706                 offset += buf_size;
2707                 bytes_left -= buf_size;
2708         }
2709
2710         p_dev->mcp_nvm_resp = resp;
2711         ecore_ptt_release(p_hwfn, p_ptt);
2712
2713         return rc;
2714 }
2715
2716 enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
2717                                         u32 addr, u8 *p_buf, u32 len)
2718 {
2719         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2720         struct ecore_ptt *p_ptt;
2721         u32 resp, param;
2722         enum _ecore_status_t rc;
2723
2724         p_ptt = ecore_ptt_acquire(p_hwfn);
2725         if (!p_ptt)
2726                 return ECORE_BUSY;
2727
2728         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2729                                   (cmd == ECORE_PHY_CORE_READ) ?
2730                                   DRV_MSG_CODE_PHY_CORE_READ :
2731                                   DRV_MSG_CODE_PHY_RAW_READ,
2732                                   addr, &resp, &param, &len, (u32 *)p_buf);
2733         if (rc != ECORE_SUCCESS)
2734                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2735
2736         p_dev->mcp_nvm_resp = resp;
2737         ecore_ptt_release(p_hwfn, p_ptt);
2738
2739         return rc;
2740 }
2741
2742 enum _ecore_status_t ecore_mcp_nvm_resp(struct ecore_dev *p_dev, u8 *p_buf)
2743 {
2744         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2745         struct ecore_ptt *p_ptt;
2746
2747         p_ptt = ecore_ptt_acquire(p_hwfn);
2748         if (!p_ptt)
2749                 return ECORE_BUSY;
2750
2751         OSAL_MEMCPY(p_buf, &p_dev->mcp_nvm_resp, sizeof(p_dev->mcp_nvm_resp));
2752         ecore_ptt_release(p_hwfn, p_ptt);
2753
2754         return ECORE_SUCCESS;
2755 }
2756
2757 enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr)
2758 {
2759         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2760         struct ecore_ptt *p_ptt;
2761         u32 resp, param;
2762         enum _ecore_status_t rc;
2763
2764         p_ptt = ecore_ptt_acquire(p_hwfn);
2765         if (!p_ptt)
2766                 return ECORE_BUSY;
2767         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_DEL_FILE, addr,
2768                            &resp, &param);
2769         p_dev->mcp_nvm_resp = resp;
2770         ecore_ptt_release(p_hwfn, p_ptt);
2771
2772         return rc;
2773 }
2774
2775 enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
2776                                                   u32 addr)
2777 {
2778         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2779         struct ecore_ptt *p_ptt;
2780         u32 resp, param;
2781         enum _ecore_status_t rc;
2782
2783         p_ptt = ecore_ptt_acquire(p_hwfn);
2784         if (!p_ptt)
2785                 return ECORE_BUSY;
2786         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2787                            &resp, &param);
2788         p_dev->mcp_nvm_resp = resp;
2789         ecore_ptt_release(p_hwfn, p_ptt);
2790
2791         return rc;
2792 }
2793
2794 /* rc receives ECORE_INVAL as default parameter because
2795  * it might not enter the while loop if the len is 0
2796  */
2797 enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
2798                                          u32 addr, u8 *p_buf, u32 len)
2799 {
2800         u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param;
2801         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2802         enum _ecore_status_t rc = ECORE_INVAL;
2803         struct ecore_ptt *p_ptt;
2804
2805         p_ptt = ecore_ptt_acquire(p_hwfn);
2806         if (!p_ptt)
2807                 return ECORE_BUSY;
2808
2809         switch (cmd) {
2810         case ECORE_PUT_FILE_DATA:
2811                 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2812                 break;
2813         case ECORE_NVM_WRITE_NVRAM:
2814                 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2815                 break;
2816         case ECORE_EXT_PHY_FW_UPGRADE:
2817                 nvm_cmd = DRV_MSG_CODE_EXT_PHY_FW_UPGRADE;
2818                 break;
2819         default:
2820                 DP_NOTICE(p_hwfn, true, "Invalid nvm write command 0x%x\n",
2821                           cmd);
2822                 rc = ECORE_INVAL;
2823                 goto out;
2824         }
2825
2826         buf_idx = 0;
2827         while (buf_idx < len) {
2828                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2829                                       MCP_DRV_NVM_BUF_LEN);
2830                 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2831                               addr) +
2832                              buf_idx;
2833                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2834                                           &resp, &param, buf_size,
2835                                           (u32 *)&p_buf[buf_idx]);
2836                 if (rc != ECORE_SUCCESS) {
2837                         DP_NOTICE(p_dev, false,
2838                                   "ecore_mcp_nvm_write() failed, rc = %d\n",
2839                                   rc);
2840                         resp = FW_MSG_CODE_ERROR;
2841                         break;
2842                 }
2843
2844                 if (resp != FW_MSG_CODE_OK &&
2845                     resp != FW_MSG_CODE_NVM_OK &&
2846                     resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2847                         DP_NOTICE(p_dev, false,
2848                                   "nvm write failed, resp = 0x%08x\n", resp);
2849                         rc = ECORE_UNKNOWN_ERROR;
2850                         break;
2851                 }
2852
2853                 /* This can be a lengthy process, and it's possible scheduler
2854                  * isn't preemptible. Sleep a bit to prevent CPU hogging.
2855                  */
2856                 if (buf_idx % 0x1000 >
2857                     (buf_idx + buf_size) % 0x1000)
2858                         OSAL_MSLEEP(1);
2859
2860                 buf_idx += buf_size;
2861         }
2862
2863         p_dev->mcp_nvm_resp = resp;
2864 out:
2865         ecore_ptt_release(p_hwfn, p_ptt);
2866
2867         return rc;
2868 }
2869
2870 enum _ecore_status_t ecore_mcp_phy_write(struct ecore_dev *p_dev, u32 cmd,
2871                                          u32 addr, u8 *p_buf, u32 len)
2872 {
2873         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2874         struct ecore_ptt *p_ptt;
2875         u32 resp, param, nvm_cmd;
2876         enum _ecore_status_t rc;
2877
2878         p_ptt = ecore_ptt_acquire(p_hwfn);
2879         if (!p_ptt)
2880                 return ECORE_BUSY;
2881
2882         nvm_cmd = (cmd == ECORE_PHY_CORE_WRITE) ?  DRV_MSG_CODE_PHY_CORE_WRITE :
2883                         DRV_MSG_CODE_PHY_RAW_WRITE;
2884         rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, addr,
2885                                   &resp, &param, len, (u32 *)p_buf);
2886         if (rc != ECORE_SUCCESS)
2887                 DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
2888         p_dev->mcp_nvm_resp = resp;
2889         ecore_ptt_release(p_hwfn, p_ptt);
2890
2891         return rc;
2892 }
2893
2894 enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev,
2895                                                    u32 addr)
2896 {
2897         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
2898         struct ecore_ptt *p_ptt;
2899         u32 resp, param;
2900         enum _ecore_status_t rc;
2901
2902         p_ptt = ecore_ptt_acquire(p_hwfn);
2903         if (!p_ptt)
2904                 return ECORE_BUSY;
2905
2906         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_SECURE_MODE, addr,
2907                            &resp, &param);
2908         p_dev->mcp_nvm_resp = resp;
2909         ecore_ptt_release(p_hwfn, p_ptt);
2910
2911         return rc;
2912 }
2913
2914 enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
2915                                             struct ecore_ptt *p_ptt,
2916                                             u32 port, u32 addr, u32 offset,
2917                                             u32 len, u8 *p_buf)
2918 {
2919         u32 bytes_left, bytes_to_copy, buf_size, nvm_offset;
2920         u32 resp, param;
2921         enum _ecore_status_t rc;
2922
2923         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2924                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2925         addr = offset;
2926         offset = 0;
2927         bytes_left = len;
2928         while (bytes_left > 0) {
2929                 bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
2930                                            MAX_I2C_TRANSACTION_SIZE);
2931                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2932                                DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2933                 nvm_offset |= ((addr + offset) <<
2934                                 DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2935                 nvm_offset |= (bytes_to_copy <<
2936                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2937                 rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2938                                           DRV_MSG_CODE_TRANSCEIVER_READ,
2939                                           nvm_offset, &resp, &param, &buf_size,
2940                                           (u32 *)(p_buf + offset));
2941                 if ((resp & FW_MSG_CODE_MASK) ==
2942                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2943                         return ECORE_NODEV;
2944                 } else if ((resp & FW_MSG_CODE_MASK) !=
2945                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2946                         return ECORE_UNKNOWN_ERROR;
2947
2948                 offset += buf_size;
2949                 bytes_left -= buf_size;
2950         }
2951
2952         return ECORE_SUCCESS;
2953 }
2954
2955 enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
2956                                              struct ecore_ptt *p_ptt,
2957                                              u32 port, u32 addr, u32 offset,
2958                                              u32 len, u8 *p_buf)
2959 {
2960         u32 buf_idx, buf_size, nvm_offset, resp, param;
2961         enum _ecore_status_t rc;
2962
2963         nvm_offset = (port << DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET) |
2964                         (addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET);
2965         buf_idx = 0;
2966         while (buf_idx < len) {
2967                 buf_size = OSAL_MIN_T(u32, (len - buf_idx),
2968                                       MAX_I2C_TRANSACTION_SIZE);
2969                 nvm_offset &= (DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
2970                                  DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
2971                 nvm_offset |= ((offset + buf_idx) <<
2972                                  DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET);
2973                 nvm_offset |= (buf_size <<
2974                                DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET);
2975                 rc = ecore_mcp_nvm_wr_cmd(p_hwfn, p_ptt,
2976                                           DRV_MSG_CODE_TRANSCEIVER_WRITE,
2977                                           nvm_offset, &resp, &param, buf_size,
2978                                           (u32 *)&p_buf[buf_idx]);
2979                 if ((resp & FW_MSG_CODE_MASK) ==
2980                     FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
2981                         return ECORE_NODEV;
2982                 } else if ((resp & FW_MSG_CODE_MASK) !=
2983                            FW_MSG_CODE_TRANSCEIVER_DIAG_OK)
2984                         return ECORE_UNKNOWN_ERROR;
2985
2986                 buf_idx += buf_size;
2987         }
2988
2989         return ECORE_SUCCESS;
2990 }
2991
2992 enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
2993                                          struct ecore_ptt *p_ptt,
2994                                          u16 gpio, u32 *gpio_val)
2995 {
2996         enum _ecore_status_t rc = ECORE_SUCCESS;
2997         u32 drv_mb_param = 0, rsp;
2998
2999         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET);
3000
3001         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
3002                            drv_mb_param, &rsp, gpio_val);
3003
3004         if (rc != ECORE_SUCCESS)
3005                 return rc;
3006
3007         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3008                 return ECORE_UNKNOWN_ERROR;
3009
3010         return ECORE_SUCCESS;
3011 }
3012
3013 enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
3014                                           struct ecore_ptt *p_ptt,
3015                                           u16 gpio, u16 gpio_val)
3016 {
3017         enum _ecore_status_t rc = ECORE_SUCCESS;
3018         u32 drv_mb_param = 0, param, rsp;
3019
3020         drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) |
3021                 (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET);
3022
3023         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
3024                            drv_mb_param, &rsp, &param);
3025
3026         if (rc != ECORE_SUCCESS)
3027                 return rc;
3028
3029         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3030                 return ECORE_UNKNOWN_ERROR;
3031
3032         return ECORE_SUCCESS;
3033 }
3034
3035 enum _ecore_status_t ecore_mcp_gpio_info(struct ecore_hwfn *p_hwfn,
3036                                          struct ecore_ptt *p_ptt,
3037                                          u16 gpio, u32 *gpio_direction,
3038                                          u32 *gpio_ctrl)
3039 {
3040         u32 drv_mb_param = 0, rsp, val = 0;
3041         enum _ecore_status_t rc = ECORE_SUCCESS;
3042
3043         drv_mb_param = gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET;
3044
3045         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_INFO,
3046                            drv_mb_param, &rsp, &val);
3047         if (rc != ECORE_SUCCESS)
3048                 return rc;
3049
3050         *gpio_direction = (val & DRV_MB_PARAM_GPIO_DIRECTION_MASK) >>
3051                            DRV_MB_PARAM_GPIO_DIRECTION_OFFSET;
3052         *gpio_ctrl = (val & DRV_MB_PARAM_GPIO_CTRL_MASK) >>
3053                       DRV_MB_PARAM_GPIO_CTRL_OFFSET;
3054
3055         if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
3056                 return ECORE_UNKNOWN_ERROR;
3057
3058         return ECORE_SUCCESS;
3059 }
3060
3061 enum _ecore_status_t ecore_mcp_bist_register_test(struct ecore_hwfn *p_hwfn,
3062                                                   struct ecore_ptt *p_ptt)
3063 {
3064         u32 drv_mb_param = 0, rsp, param;
3065         enum _ecore_status_t rc = ECORE_SUCCESS;
3066
3067         drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
3068                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3069
3070         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3071                            drv_mb_param, &rsp, &param);
3072
3073         if (rc != ECORE_SUCCESS)
3074                 return rc;
3075
3076         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3077             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3078                 rc = ECORE_UNKNOWN_ERROR;
3079
3080         return rc;
3081 }
3082
3083 enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
3084                                                struct ecore_ptt *p_ptt)
3085 {
3086         u32 drv_mb_param, rsp, param;
3087         enum _ecore_status_t rc = ECORE_SUCCESS;
3088
3089         drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
3090                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3091
3092         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3093                            drv_mb_param, &rsp, &param);
3094
3095         if (rc != ECORE_SUCCESS)
3096                 return rc;
3097
3098         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3099             (param != DRV_MB_PARAM_BIST_RC_PASSED))
3100                 rc = ECORE_UNKNOWN_ERROR;
3101
3102         return rc;
3103 }
3104
3105 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
3106         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images)
3107 {
3108         u32 drv_mb_param = 0, rsp;
3109         enum _ecore_status_t rc = ECORE_SUCCESS;
3110
3111         drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
3112                         DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3113
3114         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3115                            drv_mb_param, &rsp, num_images);
3116
3117         if (rc != ECORE_SUCCESS)
3118                 return rc;
3119
3120         if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
3121                 rc = ECORE_UNKNOWN_ERROR;
3122
3123         return rc;
3124 }
3125
3126 enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
3127         struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3128         struct bist_nvm_image_att *p_image_att, u32 image_index)
3129 {
3130         u32 buf_size, nvm_offset, resp, param;
3131         enum _ecore_status_t rc;
3132
3133         nvm_offset = (DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
3134                                     DRV_MB_PARAM_BIST_TEST_INDEX_OFFSET);
3135         nvm_offset |= (image_index <<
3136                        DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_OFFSET);
3137         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
3138                                   nvm_offset, &resp, &param, &buf_size,
3139                                   (u32 *)p_image_att);
3140         if (rc != ECORE_SUCCESS)
3141                 return rc;
3142
3143         if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
3144             (p_image_att->return_code != 1))
3145                 rc = ECORE_UNKNOWN_ERROR;
3146
3147         return rc;
3148 }
3149
3150 enum _ecore_status_t
3151 ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
3152                                struct ecore_ptt *p_ptt,
3153                                struct ecore_temperature_info *p_temp_info)
3154 {
3155         struct ecore_temperature_sensor *p_temp_sensor;
3156         struct temperature_status_stc mfw_temp_info;
3157         struct ecore_mcp_mb_params mb_params;
3158         u32 val;
3159         enum _ecore_status_t rc;
3160         u8 i;
3161
3162         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3163         mb_params.cmd = DRV_MSG_CODE_GET_TEMPERATURE;
3164         mb_params.p_data_dst = &mfw_temp_info;
3165         mb_params.data_dst_size = sizeof(mfw_temp_info);
3166         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3167         if (rc != ECORE_SUCCESS)
3168                 return rc;
3169
3170         OSAL_BUILD_BUG_ON(ECORE_MAX_NUM_OF_SENSORS != MAX_NUM_OF_SENSORS);
3171         p_temp_info->num_sensors = OSAL_MIN_T(u32, mfw_temp_info.num_of_sensors,
3172                                               ECORE_MAX_NUM_OF_SENSORS);
3173         for (i = 0; i < p_temp_info->num_sensors; i++) {
3174                 val = mfw_temp_info.sensor[i];
3175                 p_temp_sensor = &p_temp_info->sensors[i];
3176                 p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
3177                                                  SENSOR_LOCATION_OFFSET;
3178                 p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
3179                                                 THRESHOLD_HIGH_OFFSET;
3180                 p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
3181                                           CRITICAL_TEMPERATURE_OFFSET;
3182                 p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
3183                                               CURRENT_TEMP_OFFSET;
3184         }
3185
3186         return ECORE_SUCCESS;
3187 }
3188
3189 enum _ecore_status_t ecore_mcp_get_mba_versions(
3190         struct ecore_hwfn *p_hwfn,
3191         struct ecore_ptt *p_ptt,
3192         struct ecore_mba_vers *p_mba_vers)
3193 {
3194         u32 buf_size, resp, param;
3195         enum _ecore_status_t rc;
3196
3197         rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MBA_VERSION,
3198                                   0, &resp, &param, &buf_size,
3199                                   &p_mba_vers->mba_vers[0]);
3200
3201         if (rc != ECORE_SUCCESS)
3202                 return rc;
3203
3204         if ((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK)
3205                 rc = ECORE_UNKNOWN_ERROR;
3206
3207         if (buf_size != MCP_DRV_NVM_BUF_LEN)
3208                 rc = ECORE_UNKNOWN_ERROR;
3209
3210         return rc;
3211 }
3212
3213 enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
3214                                               struct ecore_ptt *p_ptt,
3215                                               u64 *num_events)
3216 {
3217         u32 rsp;
3218
3219         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MEM_ECC_EVENTS,
3220                              0, &rsp, (u32 *)num_events);
3221 }
3222
3223 static enum resource_id_enum
3224 ecore_mcp_get_mfw_res_id(enum ecore_resources res_id)
3225 {
3226         enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
3227
3228         switch (res_id) {
3229         case ECORE_SB:
3230                 mfw_res_id = RESOURCE_NUM_SB_E;
3231                 break;
3232         case ECORE_L2_QUEUE:
3233                 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
3234                 break;
3235         case ECORE_VPORT:
3236                 mfw_res_id = RESOURCE_NUM_VPORT_E;
3237                 break;
3238         case ECORE_RSS_ENG:
3239                 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
3240                 break;
3241         case ECORE_PQ:
3242                 mfw_res_id = RESOURCE_NUM_PQ_E;
3243                 break;
3244         case ECORE_RL:
3245                 mfw_res_id = RESOURCE_NUM_RL_E;
3246                 break;
3247         case ECORE_MAC:
3248         case ECORE_VLAN:
3249                 /* Each VFC resource can accommodate both a MAC and a VLAN */
3250                 mfw_res_id = RESOURCE_VFC_FILTER_E;
3251                 break;
3252         case ECORE_ILT:
3253                 mfw_res_id = RESOURCE_ILT_E;
3254                 break;
3255         case ECORE_LL2_QUEUE:
3256                 mfw_res_id = RESOURCE_LL2_QUEUE_E;
3257                 break;
3258         case ECORE_RDMA_CNQ_RAM:
3259         case ECORE_CMDQS_CQS:
3260                 /* CNQ/CMDQS are the same resource */
3261                 mfw_res_id = RESOURCE_CQS_E;
3262                 break;
3263         case ECORE_RDMA_STATS_QUEUE:
3264                 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
3265                 break;
3266         case ECORE_BDQ:
3267                 mfw_res_id = RESOURCE_BDQ_E;
3268                 break;
3269         default:
3270                 break;
3271         }
3272
3273         return mfw_res_id;
3274 }
3275
3276 #define ECORE_RESC_ALLOC_VERSION_MAJOR  2
3277 #define ECORE_RESC_ALLOC_VERSION_MINOR  0
3278 #define ECORE_RESC_ALLOC_VERSION                                \
3279         ((ECORE_RESC_ALLOC_VERSION_MAJOR <<                     \
3280           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_OFFSET) |   \
3281          (ECORE_RESC_ALLOC_VERSION_MINOR <<                     \
3282           DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_OFFSET))
3283
3284 struct ecore_resc_alloc_in_params {
3285         u32 cmd;
3286         enum ecore_resources res_id;
3287         u32 resc_max_val;
3288 };
3289
3290 struct ecore_resc_alloc_out_params {
3291         u32 mcp_resp;
3292         u32 mcp_param;
3293         u32 resc_num;
3294         u32 resc_start;
3295         u32 vf_resc_num;
3296         u32 vf_resc_start;
3297         u32 flags;
3298 };
3299
3300 #define ECORE_RECOVERY_PROLOG_SLEEP_MS  100
3301
3302 enum _ecore_status_t ecore_recovery_prolog(struct ecore_dev *p_dev)
3303 {
3304         struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
3305         struct ecore_ptt *p_ptt = p_hwfn->p_main_ptt;
3306         enum _ecore_status_t rc;
3307
3308         /* Allow ongoing PCIe transactions to complete */
3309         OSAL_MSLEEP(ECORE_RECOVERY_PROLOG_SLEEP_MS);
3310
3311         /* Clear the PF's internal FID_enable in the PXP */
3312         rc = ecore_pglueb_set_pfid_enable(p_hwfn, p_ptt, false);
3313         if (rc != ECORE_SUCCESS)
3314                 DP_NOTICE(p_hwfn, false,
3315                           "ecore_pglueb_set_pfid_enable() failed. rc = %d.\n",
3316                           rc);
3317
3318         return rc;
3319 }
3320
3321 static enum _ecore_status_t
3322 ecore_mcp_resc_allocation_msg(struct ecore_hwfn *p_hwfn,
3323                               struct ecore_ptt *p_ptt,
3324                               struct ecore_resc_alloc_in_params *p_in_params,
3325                               struct ecore_resc_alloc_out_params *p_out_params)
3326 {
3327         struct ecore_mcp_mb_params mb_params;
3328         struct resource_info mfw_resc_info;
3329         enum _ecore_status_t rc;
3330
3331         OSAL_MEM_ZERO(&mfw_resc_info, sizeof(mfw_resc_info));
3332
3333         mfw_resc_info.res_id = ecore_mcp_get_mfw_res_id(p_in_params->res_id);
3334         if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
3335                 DP_ERR(p_hwfn,
3336                        "Failed to match resource %d [%s] with the MFW resources\n",
3337                        p_in_params->res_id,
3338                        ecore_hw_get_resc_name(p_in_params->res_id));
3339                 return ECORE_INVAL;
3340         }
3341
3342         switch (p_in_params->cmd) {
3343         case DRV_MSG_SET_RESOURCE_VALUE_MSG:
3344                 mfw_resc_info.size = p_in_params->resc_max_val;
3345                 /* Fallthrough */
3346         case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
3347                 break;
3348         default:
3349                 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
3350                        p_in_params->cmd);
3351                 return ECORE_INVAL;
3352         }
3353
3354         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3355         mb_params.cmd = p_in_params->cmd;
3356         mb_params.param = ECORE_RESC_ALLOC_VERSION;
3357         mb_params.p_data_src = &mfw_resc_info;
3358         mb_params.data_src_size = sizeof(mfw_resc_info);
3359         mb_params.p_data_dst = mb_params.p_data_src;
3360         mb_params.data_dst_size = mb_params.data_src_size;
3361
3362         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3363                    "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
3364                    p_in_params->cmd, p_in_params->res_id,
3365                    ecore_hw_get_resc_name(p_in_params->res_id),
3366                    GET_MFW_FIELD(mb_params.param,
3367                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3368                    GET_MFW_FIELD(mb_params.param,
3369                                  DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3370                    p_in_params->resc_max_val);
3371
3372         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3373         if (rc != ECORE_SUCCESS)
3374                 return rc;
3375
3376         p_out_params->mcp_resp = mb_params.mcp_resp;
3377         p_out_params->mcp_param = mb_params.mcp_param;
3378         p_out_params->resc_num = mfw_resc_info.size;
3379         p_out_params->resc_start = mfw_resc_info.offset;
3380         p_out_params->vf_resc_num = mfw_resc_info.vf_size;
3381         p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
3382         p_out_params->flags = mfw_resc_info.flags;
3383
3384         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3385                    "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
3386                    GET_MFW_FIELD(p_out_params->mcp_param,
3387                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
3388                    GET_MFW_FIELD(p_out_params->mcp_param,
3389                                  FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
3390                    p_out_params->resc_num, p_out_params->resc_start,
3391                    p_out_params->vf_resc_num, p_out_params->vf_resc_start,
3392                    p_out_params->flags);
3393
3394         return ECORE_SUCCESS;
3395 }
3396
3397 enum _ecore_status_t
3398 ecore_mcp_set_resc_max_val(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3399                            enum ecore_resources res_id, u32 resc_max_val,
3400                            u32 *p_mcp_resp)
3401 {
3402         struct ecore_resc_alloc_out_params out_params;
3403         struct ecore_resc_alloc_in_params in_params;
3404         enum _ecore_status_t rc;
3405
3406         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3407         in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
3408         in_params.res_id = res_id;
3409         in_params.resc_max_val = resc_max_val;
3410         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3411         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3412                                            &out_params);
3413         if (rc != ECORE_SUCCESS)
3414                 return rc;
3415
3416         *p_mcp_resp = out_params.mcp_resp;
3417
3418         return ECORE_SUCCESS;
3419 }
3420
3421 enum _ecore_status_t
3422 ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3423                         enum ecore_resources res_id, u32 *p_mcp_resp,
3424                         u32 *p_resc_num, u32 *p_resc_start)
3425 {
3426         struct ecore_resc_alloc_out_params out_params;
3427         struct ecore_resc_alloc_in_params in_params;
3428         enum _ecore_status_t rc;
3429
3430         OSAL_MEM_ZERO(&in_params, sizeof(in_params));
3431         in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
3432         in_params.res_id = res_id;
3433         OSAL_MEM_ZERO(&out_params, sizeof(out_params));
3434         rc = ecore_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
3435                                            &out_params);
3436         if (rc != ECORE_SUCCESS)
3437                 return rc;
3438
3439         *p_mcp_resp = out_params.mcp_resp;
3440
3441         if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
3442                 *p_resc_num = out_params.resc_num;
3443                 *p_resc_start = out_params.resc_start;
3444         }
3445
3446         return ECORE_SUCCESS;
3447 }
3448
3449 enum _ecore_status_t ecore_mcp_initiate_pf_flr(struct ecore_hwfn *p_hwfn,
3450                                                struct ecore_ptt *p_ptt)
3451 {
3452         u32 mcp_resp, mcp_param;
3453
3454         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
3455                              &mcp_resp, &mcp_param);
3456 }
3457
3458 static enum _ecore_status_t ecore_mcp_resource_cmd(struct ecore_hwfn *p_hwfn,
3459                                                    struct ecore_ptt *p_ptt,
3460                                                    u32 param, u32 *p_mcp_resp,
3461                                                    u32 *p_mcp_param)
3462 {
3463         enum _ecore_status_t rc;
3464
3465         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
3466                            p_mcp_resp, p_mcp_param);
3467         if (rc != ECORE_SUCCESS)
3468                 return rc;
3469
3470         if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3471                 DP_INFO(p_hwfn,
3472                         "The resource command is unsupported by the MFW\n");
3473                 return ECORE_NOTIMPL;
3474         }
3475
3476         if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
3477                 u8 opcode = GET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
3478
3479                 DP_NOTICE(p_hwfn, false,
3480                           "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
3481                           param, opcode);
3482                 return ECORE_INVAL;
3483         }
3484
3485         return rc;
3486 }
3487
3488 enum _ecore_status_t
3489 __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3490                       struct ecore_resc_lock_params *p_params)
3491 {
3492         u32 param = 0, mcp_resp, mcp_param;
3493         u8 opcode;
3494         enum _ecore_status_t rc;
3495
3496         switch (p_params->timeout) {
3497         case ECORE_MCP_RESC_LOCK_TO_DEFAULT:
3498                 opcode = RESOURCE_OPCODE_REQ;
3499                 p_params->timeout = 0;
3500                 break;
3501         case ECORE_MCP_RESC_LOCK_TO_NONE:
3502                 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
3503                 p_params->timeout = 0;
3504                 break;
3505         default:
3506                 opcode = RESOURCE_OPCODE_REQ_W_AGING;
3507                 break;
3508         }
3509
3510         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3511         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3512         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
3513
3514         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3515                    "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
3516                    param, p_params->timeout, opcode, p_params->resource);
3517
3518         /* Attempt to acquire the resource */
3519         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3520                                     &mcp_param);
3521         if (rc != ECORE_SUCCESS)
3522                 return rc;
3523
3524         /* Analyze the response */
3525         p_params->owner = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
3526         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3527
3528         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3529                    "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
3530                    mcp_param, opcode, p_params->owner);
3531
3532         switch (opcode) {
3533         case RESOURCE_OPCODE_GNT:
3534                 p_params->b_granted = true;
3535                 break;
3536         case RESOURCE_OPCODE_BUSY:
3537                 p_params->b_granted = false;
3538                 break;
3539         default:
3540                 DP_NOTICE(p_hwfn, false,
3541                           "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
3542                           mcp_param, opcode);
3543                 return ECORE_INVAL;
3544         }
3545
3546         return ECORE_SUCCESS;
3547 }
3548
3549 enum _ecore_status_t
3550 ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3551                     struct ecore_resc_lock_params *p_params)
3552 {
3553         u32 retry_cnt = 0;
3554         enum _ecore_status_t rc;
3555
3556         do {
3557                 /* No need for an interval before the first iteration */
3558                 if (retry_cnt) {
3559                         if (p_params->sleep_b4_retry) {
3560                                 u16 retry_interval_in_ms =
3561                                         DIV_ROUND_UP(p_params->retry_interval,
3562                                                      1000);
3563
3564                                 OSAL_MSLEEP(retry_interval_in_ms);
3565                         } else {
3566                                 OSAL_UDELAY(p_params->retry_interval);
3567                         }
3568                 }
3569
3570                 rc = __ecore_mcp_resc_lock(p_hwfn, p_ptt, p_params);
3571                 if (rc != ECORE_SUCCESS)
3572                         return rc;
3573
3574                 if (p_params->b_granted)
3575                         break;
3576         } while (retry_cnt++ < p_params->retry_num);
3577
3578         return ECORE_SUCCESS;
3579 }
3580
3581 void ecore_mcp_resc_lock_default_init(struct ecore_resc_lock_params *p_lock,
3582                                       struct ecore_resc_unlock_params *p_unlock,
3583                                       enum ecore_resc_lock resource,
3584                                       bool b_is_permanent)
3585 {
3586         if (p_lock != OSAL_NULL) {
3587                 OSAL_MEM_ZERO(p_lock, sizeof(*p_lock));
3588
3589                 /* Permanent resources don't require aging, and there's no
3590                  * point in trying to acquire them more than once since it's
3591                  * unexpected another entity would release them.
3592                  */
3593                 if (b_is_permanent) {
3594                         p_lock->timeout = ECORE_MCP_RESC_LOCK_TO_NONE;
3595                 } else {
3596                         p_lock->retry_num = ECORE_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3597                         p_lock->retry_interval =
3598                                         ECORE_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3599                         p_lock->sleep_b4_retry = true;
3600                 }
3601
3602                 p_lock->resource = resource;
3603         }
3604
3605         if (p_unlock != OSAL_NULL) {
3606                 OSAL_MEM_ZERO(p_unlock, sizeof(*p_unlock));
3607                 p_unlock->resource = resource;
3608         }
3609 }
3610
3611 enum _ecore_status_t
3612 ecore_mcp_resc_unlock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3613                       struct ecore_resc_unlock_params *p_params)
3614 {
3615         u32 param = 0, mcp_resp, mcp_param;
3616         u8 opcode;
3617         enum _ecore_status_t rc;
3618
3619         opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
3620                                    : RESOURCE_OPCODE_RELEASE;
3621         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
3622         SET_MFW_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
3623
3624         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3625                    "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
3626                    param, opcode, p_params->resource);
3627
3628         /* Attempt to release the resource */
3629         rc = ecore_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp,
3630                                     &mcp_param);
3631         if (rc != ECORE_SUCCESS)
3632                 return rc;
3633
3634         /* Analyze the response */
3635         opcode = GET_MFW_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
3636
3637         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3638                    "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
3639                    mcp_param, opcode);
3640
3641         switch (opcode) {
3642         case RESOURCE_OPCODE_RELEASED_PREVIOUS:
3643                 DP_INFO(p_hwfn,
3644                         "Resource unlock request for an already released resource [%d]\n",
3645                         p_params->resource);
3646                 /* Fallthrough */
3647         case RESOURCE_OPCODE_RELEASED:
3648                 p_params->b_released = true;
3649                 break;
3650         case RESOURCE_OPCODE_WRONG_OWNER:
3651                 p_params->b_released = false;
3652                 break;
3653         default:
3654                 DP_NOTICE(p_hwfn, false,
3655                           "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
3656                           mcp_param, opcode);
3657                 return ECORE_INVAL;
3658         }
3659
3660         return ECORE_SUCCESS;
3661 }
3662
3663 bool ecore_mcp_is_smart_an_supported(struct ecore_hwfn *p_hwfn)
3664 {
3665         return !!(p_hwfn->mcp_info->capabilities &
3666                   FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ);
3667 }
3668
3669 enum _ecore_status_t ecore_mcp_get_capabilities(struct ecore_hwfn *p_hwfn,
3670                                                 struct ecore_ptt *p_ptt)
3671 {
3672         u32 mcp_resp;
3673         enum _ecore_status_t rc;
3674
3675         rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3676                            0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3677         if (rc == ECORE_SUCCESS)
3678                 DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_PROBE),
3679                            "MFW supported features: %08x\n",
3680                            p_hwfn->mcp_info->capabilities);
3681
3682         return rc;
3683 }
3684
3685 enum _ecore_status_t ecore_mcp_set_capabilities(struct ecore_hwfn *p_hwfn,
3686                                                 struct ecore_ptt *p_ptt)
3687 {
3688         u32 mcp_resp, mcp_param, features;
3689
3690         features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_SMARTLINQ |
3691                    DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE |
3692                    DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK;
3693
3694         return ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3695                              features, &mcp_resp, &mcp_param);
3696 }
3697
3698 enum _ecore_status_t
3699 ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3700                         struct ecore_mcp_drv_attr *p_drv_attr)
3701 {
3702         struct attribute_cmd_write_stc attr_cmd_write;
3703         enum _attribute_commands_e mfw_attr_cmd;
3704         struct ecore_mcp_mb_params mb_params;
3705         enum _ecore_status_t rc;
3706
3707         switch (p_drv_attr->attr_cmd) {
3708         case ECORE_MCP_DRV_ATTR_CMD_READ:
3709                 mfw_attr_cmd = ATTRIBUTE_CMD_READ;
3710                 break;
3711         case ECORE_MCP_DRV_ATTR_CMD_WRITE:
3712                 mfw_attr_cmd = ATTRIBUTE_CMD_WRITE;
3713                 break;
3714         case ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR:
3715                 mfw_attr_cmd = ATTRIBUTE_CMD_READ_CLEAR;
3716                 break;
3717         case ECORE_MCP_DRV_ATTR_CMD_CLEAR:
3718                 mfw_attr_cmd = ATTRIBUTE_CMD_CLEAR;
3719                 break;
3720         default:
3721                 DP_NOTICE(p_hwfn, false, "Unknown attribute command %d\n",
3722                           p_drv_attr->attr_cmd);
3723                 return ECORE_INVAL;
3724         }
3725
3726         OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
3727         mb_params.cmd = DRV_MSG_CODE_ATTRIBUTE;
3728         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_KEY,
3729                       p_drv_attr->attr_num);
3730         SET_MFW_FIELD(mb_params.param, DRV_MB_PARAM_ATTRIBUTE_CMD,
3731                       mfw_attr_cmd);
3732         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_WRITE) {
3733                 OSAL_MEM_ZERO(&attr_cmd_write, sizeof(attr_cmd_write));
3734                 attr_cmd_write.val = p_drv_attr->val;
3735                 attr_cmd_write.mask = p_drv_attr->mask;
3736                 attr_cmd_write.offset = p_drv_attr->offset;
3737
3738                 mb_params.p_data_src = &attr_cmd_write;
3739                 mb_params.data_src_size = sizeof(attr_cmd_write);
3740         }
3741
3742         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3743         if (rc != ECORE_SUCCESS)
3744                 return rc;
3745
3746         if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
3747                 DP_INFO(p_hwfn,
3748                         "The attribute command is not supported by the MFW\n");
3749                 return ECORE_NOTIMPL;
3750         } else if (mb_params.mcp_resp != FW_MSG_CODE_OK) {
3751                 DP_INFO(p_hwfn,
3752                         "Failed to send an attribute command [mcp_resp 0x%x, attr_cmd %d, attr_num %d]\n",
3753                         mb_params.mcp_resp, p_drv_attr->attr_cmd,
3754                         p_drv_attr->attr_num);
3755                 return ECORE_INVAL;
3756         }
3757
3758         DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
3759                    "Attribute Command: cmd %d [mfw_cmd %d], num %d, in={val 0x%08x, mask 0x%08x, offset 0x%08x}, out={val 0x%08x}\n",
3760                    p_drv_attr->attr_cmd, mfw_attr_cmd, p_drv_attr->attr_num,
3761                    p_drv_attr->val, p_drv_attr->mask, p_drv_attr->offset,
3762                    mb_params.mcp_param);
3763
3764         if (p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ ||
3765             p_drv_attr->attr_cmd == ECORE_MCP_DRV_ATTR_CMD_READ_CLEAR)
3766                 p_drv_attr->val = mb_params.mcp_param;
3767
3768         return ECORE_SUCCESS;
3769 }
3770
3771 void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
3772                       u32 offset, u32 val)
3773 {
3774         struct ecore_mcp_mb_params mb_params = {0};
3775         enum _ecore_status_t       rc = ECORE_SUCCESS;
3776         u32                        dword = val;
3777
3778         mb_params.cmd = DRV_MSG_CODE_WRITE_WOL_REG;
3779         mb_params.param = offset;
3780         mb_params.p_data_src = &dword;
3781         mb_params.data_src_size = sizeof(dword);
3782
3783         rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
3784         if (rc != ECORE_SUCCESS) {
3785                 DP_NOTICE(p_hwfn, false,
3786                           "Failed to wol write request, rc = %d\n", rc);
3787         }
3788
3789         if (mb_params.mcp_resp != FW_MSG_CODE_WOL_READ_WRITE_OK) {
3790                 DP_NOTICE(p_hwfn, false,
3791                           "Failed to write value 0x%x to offset 0x%x [mcp_resp 0x%x]\n",
3792                           val, offset, mb_params.mcp_resp);
3793                 rc = ECORE_UNKNOWN_ERROR;
3794         }
3795 }