2 * Copyright (c) 2016 QLogic Corporation.
6 * See LICENSE.qede_pmd for copyright and licensing details.
12 /* Runtime array offsets */
13 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0
14 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1
15 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2
16 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3
17 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4
18 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5
19 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6
20 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7
21 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8
22 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9
23 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10
24 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11
25 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12
26 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13
27 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14
28 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
29 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
30 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
31 #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18
32 #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19
33 #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20
34 #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21
35 #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22
36 #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23
37 #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24
38 #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25
39 #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26
40 #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27
41 #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28
42 #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29
43 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30
44 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31
45 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32
46 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33
47 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34
48 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35
49 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36
50 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37
51 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38
52 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39
53 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40
54 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41
55 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42
56 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43
57 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44
58 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45
59 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024
60 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069
61 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024
62 #define CAU_REG_PI_MEMORY_RT_OFFSET 2093
63 #define CAU_REG_PI_MEMORY_RT_SIZE 4416
64 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509
65 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510
66 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511
67 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512
68 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513
69 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6514
70 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515
71 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516
72 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517
73 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518
74 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519
75 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520
76 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521
77 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522
78 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523
79 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524
80 #define SRC_REG_FIRSTFREE_RT_OFFSET 6525
81 #define SRC_REG_FIRSTFREE_RT_SIZE 2
82 #define SRC_REG_LASTFREE_RT_OFFSET 6527
83 #define SRC_REG_LASTFREE_RT_SIZE 2
84 #define SRC_REG_COUNTFREE_RT_OFFSET 6529
85 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530
86 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531
87 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532
88 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533
89 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534
90 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535
91 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536
92 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537
93 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538
94 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539
95 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540
96 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541
97 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542
98 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543
99 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544
100 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545
101 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546
102 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547
103 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548
104 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549
105 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550
106 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551
107 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552
108 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553
109 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554
110 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555
111 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556
112 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557
113 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558
114 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559
115 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560
116 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561
117 #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562
118 #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563
119 #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564
120 #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565
121 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566
122 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414
123 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980
124 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981
125 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982
126 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983
127 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984
128 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985
129 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986
130 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987
131 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988
132 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989
133 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990
134 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991
135 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992
136 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
137 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408
138 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
139 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016
140 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017
141 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018
142 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019
143 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020
144 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021
145 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022
146 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023
147 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024
148 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025
149 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026
150 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027
151 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028
152 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029
153 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030
154 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031
155 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032
156 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033
157 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034
158 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035
159 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036
160 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037
161 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038
162 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039
163 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040
164 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041
165 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042
166 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043
167 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044
168 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045
169 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046
170 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047
171 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048
172 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049
173 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050
174 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051
175 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052
176 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053
177 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054
178 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055
179 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056
180 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057
181 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058
182 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059
183 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060
184 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061
185 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062
186 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063
187 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064
188 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065
189 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066
190 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067
191 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068
192 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069
193 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070
194 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071
195 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072
196 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073
197 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074
198 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075
199 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076
200 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077
201 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078
202 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079
203 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080
204 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081
205 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082
206 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083
207 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
208 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34211
209 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34212
210 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34213
211 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34214
212 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34215
213 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34216
214 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34217
215 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34218
216 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34219
217 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34220
218 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34221
219 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34222
220 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34223
221 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34224
222 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34225
223 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34226
224 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34227
225 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34228
226 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34229
227 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34230
228 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34231
229 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34232
230 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34233
231 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34234
232 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34235
233 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34236
234 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34237
235 #define QM_REG_PQTX2PF_0_RT_OFFSET 34238
236 #define QM_REG_PQTX2PF_1_RT_OFFSET 34239
237 #define QM_REG_PQTX2PF_2_RT_OFFSET 34240
238 #define QM_REG_PQTX2PF_3_RT_OFFSET 34241
239 #define QM_REG_PQTX2PF_4_RT_OFFSET 34242
240 #define QM_REG_PQTX2PF_5_RT_OFFSET 34243
241 #define QM_REG_PQTX2PF_6_RT_OFFSET 34244
242 #define QM_REG_PQTX2PF_7_RT_OFFSET 34245
243 #define QM_REG_PQTX2PF_8_RT_OFFSET 34246
244 #define QM_REG_PQTX2PF_9_RT_OFFSET 34247
245 #define QM_REG_PQTX2PF_10_RT_OFFSET 34248
246 #define QM_REG_PQTX2PF_11_RT_OFFSET 34249
247 #define QM_REG_PQTX2PF_12_RT_OFFSET 34250
248 #define QM_REG_PQTX2PF_13_RT_OFFSET 34251
249 #define QM_REG_PQTX2PF_14_RT_OFFSET 34252
250 #define QM_REG_PQTX2PF_15_RT_OFFSET 34253
251 #define QM_REG_PQTX2PF_16_RT_OFFSET 34254
252 #define QM_REG_PQTX2PF_17_RT_OFFSET 34255
253 #define QM_REG_PQTX2PF_18_RT_OFFSET 34256
254 #define QM_REG_PQTX2PF_19_RT_OFFSET 34257
255 #define QM_REG_PQTX2PF_20_RT_OFFSET 34258
256 #define QM_REG_PQTX2PF_21_RT_OFFSET 34259
257 #define QM_REG_PQTX2PF_22_RT_OFFSET 34260
258 #define QM_REG_PQTX2PF_23_RT_OFFSET 34261
259 #define QM_REG_PQTX2PF_24_RT_OFFSET 34262
260 #define QM_REG_PQTX2PF_25_RT_OFFSET 34263
261 #define QM_REG_PQTX2PF_26_RT_OFFSET 34264
262 #define QM_REG_PQTX2PF_27_RT_OFFSET 34265
263 #define QM_REG_PQTX2PF_28_RT_OFFSET 34266
264 #define QM_REG_PQTX2PF_29_RT_OFFSET 34267
265 #define QM_REG_PQTX2PF_30_RT_OFFSET 34268
266 #define QM_REG_PQTX2PF_31_RT_OFFSET 34269
267 #define QM_REG_PQTX2PF_32_RT_OFFSET 34270
268 #define QM_REG_PQTX2PF_33_RT_OFFSET 34271
269 #define QM_REG_PQTX2PF_34_RT_OFFSET 34272
270 #define QM_REG_PQTX2PF_35_RT_OFFSET 34273
271 #define QM_REG_PQTX2PF_36_RT_OFFSET 34274
272 #define QM_REG_PQTX2PF_37_RT_OFFSET 34275
273 #define QM_REG_PQTX2PF_38_RT_OFFSET 34276
274 #define QM_REG_PQTX2PF_39_RT_OFFSET 34277
275 #define QM_REG_PQTX2PF_40_RT_OFFSET 34278
276 #define QM_REG_PQTX2PF_41_RT_OFFSET 34279
277 #define QM_REG_PQTX2PF_42_RT_OFFSET 34280
278 #define QM_REG_PQTX2PF_43_RT_OFFSET 34281
279 #define QM_REG_PQTX2PF_44_RT_OFFSET 34282
280 #define QM_REG_PQTX2PF_45_RT_OFFSET 34283
281 #define QM_REG_PQTX2PF_46_RT_OFFSET 34284
282 #define QM_REG_PQTX2PF_47_RT_OFFSET 34285
283 #define QM_REG_PQTX2PF_48_RT_OFFSET 34286
284 #define QM_REG_PQTX2PF_49_RT_OFFSET 34287
285 #define QM_REG_PQTX2PF_50_RT_OFFSET 34288
286 #define QM_REG_PQTX2PF_51_RT_OFFSET 34289
287 #define QM_REG_PQTX2PF_52_RT_OFFSET 34290
288 #define QM_REG_PQTX2PF_53_RT_OFFSET 34291
289 #define QM_REG_PQTX2PF_54_RT_OFFSET 34292
290 #define QM_REG_PQTX2PF_55_RT_OFFSET 34293
291 #define QM_REG_PQTX2PF_56_RT_OFFSET 34294
292 #define QM_REG_PQTX2PF_57_RT_OFFSET 34295
293 #define QM_REG_PQTX2PF_58_RT_OFFSET 34296
294 #define QM_REG_PQTX2PF_59_RT_OFFSET 34297
295 #define QM_REG_PQTX2PF_60_RT_OFFSET 34298
296 #define QM_REG_PQTX2PF_61_RT_OFFSET 34299
297 #define QM_REG_PQTX2PF_62_RT_OFFSET 34300
298 #define QM_REG_PQTX2PF_63_RT_OFFSET 34301
299 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 34302
300 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 34303
301 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 34304
302 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 34305
303 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 34306
304 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 34307
305 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 34308
306 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 34309
307 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 34310
308 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 34311
309 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 34312
310 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 34313
311 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 34314
312 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 34315
313 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 34316
314 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 34317
315 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34318
316 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34319
317 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34320
318 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34321
319 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34322
320 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34323
321 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34324
322 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34325
323 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34326
324 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34327
325 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34328
326 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34329
327 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 34330
328 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256
329 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34586
330 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
331 #define QM_REG_RLGLBLCRD_RT_OFFSET 34842
332 #define QM_REG_RLGLBLCRD_RT_SIZE 256
333 #define QM_REG_RLGLBLENABLE_RT_OFFSET 35098
334 #define QM_REG_RLPFPERIOD_RT_OFFSET 35099
335 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35100
336 #define QM_REG_RLPFINCVAL_RT_OFFSET 35101
337 #define QM_REG_RLPFINCVAL_RT_SIZE 16
338 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35117
339 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
340 #define QM_REG_RLPFCRD_RT_OFFSET 35133
341 #define QM_REG_RLPFCRD_RT_SIZE 16
342 #define QM_REG_RLPFENABLE_RT_OFFSET 35149
343 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 35150
344 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 35151
345 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16
346 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35167
347 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
348 #define QM_REG_WFQPFCRD_RT_OFFSET 35183
349 #define QM_REG_WFQPFCRD_RT_SIZE 256
350 #define QM_REG_WFQPFENABLE_RT_OFFSET 35439
351 #define QM_REG_WFQVPENABLE_RT_OFFSET 35440
352 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 35441
353 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512
354 #define QM_REG_TXPQMAP_RT_OFFSET 35953
355 #define QM_REG_TXPQMAP_RT_SIZE 512
356 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 36465
357 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512
358 #define QM_REG_WFQVPCRD_RT_OFFSET 36977
359 #define QM_REG_WFQVPCRD_RT_SIZE 512
360 #define QM_REG_WFQVPMAP_RT_OFFSET 37489
361 #define QM_REG_WFQVPMAP_RT_SIZE 512
362 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 38001
363 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
364 #define QM_REG_VOQCRDLINE_RT_OFFSET 38321
365 #define QM_REG_VOQCRDLINE_RT_SIZE 36
366 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 38357
367 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36
368 #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 38393
369 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 38394
370 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 38395
371 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 38396
372 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 38397
373 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 38398
374 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 38399
375 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 38400
376 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 38401
377 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
378 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 38405
379 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
380 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 38409
381 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
382 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 38441
383 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
384 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 38457
385 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
386 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 38473
387 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
388 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 38489
389 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
390 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 38505
391 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 38506
392 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 38507
393 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
394 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 38515
395 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024
396 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 39539
397 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512
398 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 40051
399 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512
400 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 40563
401 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512
402 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 41075
403 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512
404 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 41587
405 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32
406 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 41619
407 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 41620
408 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 41621
409 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 41622
410 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 41623
411 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 41624
412 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 41625
413 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 41626
414 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 41627
415 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 41628
416 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 41629
417 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 41630
418 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 41631
419 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 41632
420 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 41633
421 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 41634
422 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 41635
423 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 41636
424 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 41637
425 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 41638
426 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 41639
427 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 41640
428 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 41641
429 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 41642
430 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 41643
431 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 41644
432 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 41645
433 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 41646
434 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 41647
435 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 41648
436 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 41649
437 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 41650
438 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 41651
439 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 41652
440 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 41653
441 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 41654
442 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 41655
443 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 41656
444 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 41657
445 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 41658
446 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 41659
447 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 41660
448 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 41661
449 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 41662
450 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 41663
451 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 41664
452 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 41665
453 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 41666
454 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 41667
455 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 41668
456 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 41669
457 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 41670
458 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 41671
459 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 41672
460 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 41673
461 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 41674
462 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 41675
463 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 41676
464 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 41677
465 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 41678
466 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 41679
467 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 41680
468 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 41681
469 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 41682
470 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 41683
471 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 41684
472 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 41685
473 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 41686
474 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 41687
475 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 41688
476 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 41689
477 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 41690
478 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 41691
479 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 41692
480 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 41693
481 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 41694
482 #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 41695
483 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 41696
484 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 41697
485 #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 41698
486 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 41699
487 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 41700
488 #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 41701
489 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 41702
490 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 41703
491 #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 41704
492 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 41705
493 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 41706
494 #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 41707
495 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 41708
496 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 41709
497 #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 41710
498 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 41711
499 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 41712
500 #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 41713
501 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 41714
502 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 41715
503 #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 41716
504 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 41717
505 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 41718
506 #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 41719
507 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 41720
508 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 41721
509 #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 41722
510 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 41723
511 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 41724
512 #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 41725
513 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 41726
514 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 41727
515 #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 41728
516 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 41729
517 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 41730
518 #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 41731
519 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 41732
520 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 41733
521 #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 41734
522 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 41735
523 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 41736
524 #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 41737
525 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 41738
526 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 41739
527 #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 41740
528 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 41741
529 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 41742
531 #define RUNTIME_ARRAY_SIZE 41743
533 #endif /* __RT_DEFS_H__ */