drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_kvargs.h>
  11
  12 static const struct qed_eth_ops *qed_ops;
  13 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  14 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  15
  16 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  17
  18 struct rte_qede_xstats_name_off {
  19         char name[RTE_ETH_XSTATS_NAME_SIZE];
  20         uint64_t offset;
  21 };
  22
  23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  24         {"rx_unicast_bytes",
  25                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  26         {"rx_multicast_bytes",
  27                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  28         {"rx_broadcast_bytes",
  29                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  30         {"rx_unicast_packets",
  31                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  32         {"rx_multicast_packets",
  33                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  34         {"rx_broadcast_packets",
  35                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  36
  37         {"tx_unicast_bytes",
  38                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  39         {"tx_multicast_bytes",
  40                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  41         {"tx_broadcast_bytes",
  42                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  43         {"tx_unicast_packets",
  44                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  45         {"tx_multicast_packets",
  46                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  47         {"tx_broadcast_packets",
  48                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  49
  50         {"rx_64_byte_packets",
  51                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  52         {"rx_65_to_127_byte_packets",
  53                 offsetof(struct ecore_eth_stats_common,
  54                          rx_65_to_127_byte_packets)},
  55         {"rx_128_to_255_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common,
  57                          rx_128_to_255_byte_packets)},
  58         {"rx_256_to_511_byte_packets",
  59                 offsetof(struct ecore_eth_stats_common,
  60                          rx_256_to_511_byte_packets)},
  61         {"rx_512_to_1023_byte_packets",
  62                 offsetof(struct ecore_eth_stats_common,
  63                          rx_512_to_1023_byte_packets)},
  64         {"rx_1024_to_1518_byte_packets",
  65                 offsetof(struct ecore_eth_stats_common,
  66                          rx_1024_to_1518_byte_packets)},
  67         {"tx_64_byte_packets",
  68                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  69         {"tx_65_to_127_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          tx_65_to_127_byte_packets)},
  72         {"tx_128_to_255_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common,
  74                          tx_128_to_255_byte_packets)},
  75         {"tx_256_to_511_byte_packets",
  76                 offsetof(struct ecore_eth_stats_common,
  77                          tx_256_to_511_byte_packets)},
  78         {"tx_512_to_1023_byte_packets",
  79                 offsetof(struct ecore_eth_stats_common,
  80                          tx_512_to_1023_byte_packets)},
  81         {"tx_1024_to_1518_byte_packets",
  82                 offsetof(struct ecore_eth_stats_common,
  83                          tx_1024_to_1518_byte_packets)},
  84
  85         {"rx_mac_crtl_frames",
  86                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  87         {"tx_mac_control_frames",
  88                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  89         {"rx_pause_frames",
  90                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  91         {"tx_pause_frames",
  92                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  93         {"rx_priority_flow_control_frames",
  94                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
  95         {"tx_priority_flow_control_frames",
  96                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
  97
  98         {"rx_crc_errors",
  99                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 100         {"rx_align_errors",
 101                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 102         {"rx_carrier_errors",
 103                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 104         {"rx_oversize_packet_errors",
 105                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 106         {"rx_jabber_errors",
 107                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 108         {"rx_undersize_packet_errors",
 109                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 110         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 111         {"rx_host_buffer_not_available",
 112                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 113         /* Number of packets discarded because they are bigger than MTU */
 114         {"rx_packet_too_big_discards",
 115                 offsetof(struct ecore_eth_stats_common,
 116                          packet_too_big_discard)},
 117         {"rx_ttl_zero_discards",
 118                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 119         {"rx_multi_function_tag_filter_discards",
 120                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 121         {"rx_mac_filter_discards",
 122                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 123         {"rx_gft_filter_drop",
 124                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 125         {"rx_hw_buffer_truncates",
 126                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 127         {"rx_hw_buffer_discards",
 128                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 129         {"tx_error_drop_packets",
 130                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 131
 132         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 133         {"rx_mac_unicast_packets",
 134                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 135         {"rx_mac_multicast_packets",
 136                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 137         {"rx_mac_broadcast_packets",
 138                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 139         {"rx_mac_frames_ok",
 140                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 141         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 142         {"tx_mac_unicast_packets",
 143                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 144         {"tx_mac_multicast_packets",
 145                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 146         {"tx_mac_broadcast_packets",
 147                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 148
 149         {"lro_coalesced_packets",
 150                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 151         {"lro_coalesced_events",
 152                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 153         {"lro_aborts_num",
 154                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 155         {"lro_not_coalesced_packets",
 156                 offsetof(struct ecore_eth_stats_common,
 157                          tpa_not_coalesced_pkts)},
 158         {"lro_coalesced_bytes",
 159                 offsetof(struct ecore_eth_stats_common,
 160                          tpa_coalesced_bytes)},
 161 };
 162
 163 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 164         {"rx_1519_to_1522_byte_packets",
 165                 offsetof(struct ecore_eth_stats, bb) +
 166                 offsetof(struct ecore_eth_stats_bb,
 167                          rx_1519_to_1522_byte_packets)},
 168         {"rx_1519_to_2047_byte_packets",
 169                 offsetof(struct ecore_eth_stats, bb) +
 170                 offsetof(struct ecore_eth_stats_bb,
 171                          rx_1519_to_2047_byte_packets)},
 172         {"rx_2048_to_4095_byte_packets",
 173                 offsetof(struct ecore_eth_stats, bb) +
 174                 offsetof(struct ecore_eth_stats_bb,
 175                          rx_2048_to_4095_byte_packets)},
 176         {"rx_4096_to_9216_byte_packets",
 177                 offsetof(struct ecore_eth_stats, bb) +
 178                 offsetof(struct ecore_eth_stats_bb,
 179                          rx_4096_to_9216_byte_packets)},
 180         {"rx_9217_to_16383_byte_packets",
 181                 offsetof(struct ecore_eth_stats, bb) +
 182                 offsetof(struct ecore_eth_stats_bb,
 183                          rx_9217_to_16383_byte_packets)},
 184
 185         {"tx_1519_to_2047_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          tx_1519_to_2047_byte_packets)},
 189         {"tx_2048_to_4095_byte_packets",
 190                 offsetof(struct ecore_eth_stats, bb) +
 191                 offsetof(struct ecore_eth_stats_bb,
 192                          tx_2048_to_4095_byte_packets)},
 193         {"tx_4096_to_9216_byte_packets",
 194                 offsetof(struct ecore_eth_stats, bb) +
 195                 offsetof(struct ecore_eth_stats_bb,
 196                          tx_4096_to_9216_byte_packets)},
 197         {"tx_9217_to_16383_byte_packets",
 198                 offsetof(struct ecore_eth_stats, bb) +
 199                 offsetof(struct ecore_eth_stats_bb,
 200                          tx_9217_to_16383_byte_packets)},
 201
 202         {"tx_lpi_entry_count",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 205         {"tx_total_collisions",
 206                 offsetof(struct ecore_eth_stats, bb) +
 207                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 208 };
 209
 210 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 211         {"rx_1519_to_max_byte_packets",
 212                 offsetof(struct ecore_eth_stats, ah) +
 213                 offsetof(struct ecore_eth_stats_ah,
 214                          rx_1519_to_max_byte_packets)},
 215         {"tx_1519_to_max_byte_packets",
 216                 offsetof(struct ecore_eth_stats, ah) +
 217                 offsetof(struct ecore_eth_stats_ah,
 218                          tx_1519_to_max_byte_packets)},
 219 };
 220
 221 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 222         {"rx_q_segments",
 223                 offsetof(struct qede_rx_queue, rx_segs)},
 224         {"rx_q_hw_errors",
 225                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 226         {"rx_q_allocation_errors",
 227                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 228 };
 229
 230 /* Get FW version string based on fw_size */
 231 static int
 232 qede_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size)
 233 {
 234         struct qede_dev *qdev = dev->data->dev_private;
 235         struct ecore_dev *edev = &qdev->edev;
 236         struct qed_dev_info *info = &qdev->dev_info.common;
 237         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 238         size_t size;
 239
 240         if (fw_ver == NULL)
 241                 return 0;
 242
 243         if (IS_PF(edev))
 244                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 245                          QEDE_PMD_FW_VERSION);
 246         else
 247                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 248                          info->fw_major, info->fw_minor,
 249                          info->fw_rev, info->fw_eng);
 250         size = strlen(ver_str);
 251         if (size + 1 <= fw_size) /* Add 1 byte for "\0" */
 252                 strlcpy(fw_ver, ver_str, fw_size);
 253         else
 254                 return (size + 1);
 255
 256         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 257                  " MFW: %d.%d.%d.%d",
 258                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_3),
 259                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_2),
 260                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_1),
 261                  GET_MFW_FIELD(info->mfw_rev, QED_MFW_VERSION_0));
 262         size = strlen(ver_str);
 263         if (size + 1 <= fw_size)
 264                 strlcpy(fw_ver, ver_str, fw_size);
 265
 266         if (fw_size <= 32)
 267                 goto out;
 268
 269         snprintf(ver_str + size, (QEDE_PMD_DRV_VER_STR_SIZE - size),
 270                  " MBI: %d.%d.%d",
 271                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_2),
 272                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_1),
 273                  GET_MFW_FIELD(info->mbi_version, QED_MBI_VERSION_0));
 274         size = strlen(ver_str);
 275         if (size + 1 <= fw_size)
 276                 strlcpy(fw_ver, ver_str, fw_size);
 277
 278 out:
 279         return 0;
 280 }
 281
 282 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 283 {
 284         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 285 }
 286
 287 static void
 288 qede_interrupt_handler_intx(void *param)
 289 {
 290         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 291         struct qede_dev *qdev = eth_dev->data->dev_private;
 292         struct ecore_dev *edev = &qdev->edev;
 293         u64 status;
 294
 295         /* Check if our device actually raised an interrupt */
 296         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 297         if (status & 0x1) {
 298                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 299
 300                 if (rte_intr_ack(eth_dev->intr_handle))
 301                         DP_ERR(edev, "rte_intr_ack failed\n");
 302         }
 303 }
 304
 305 static void
 306 qede_interrupt_handler(void *param)
 307 {
 308         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 309         struct qede_dev *qdev = eth_dev->data->dev_private;
 310         struct ecore_dev *edev = &qdev->edev;
 311
 312         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 313         if (rte_intr_ack(eth_dev->intr_handle))
 314                 DP_ERR(edev, "rte_intr_ack failed\n");
 315 }
 316
 317 static void
 318 qede_assign_rxtx_handlers(struct rte_eth_dev *dev, bool is_dummy)
 319 {
 320         uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
 321         struct qede_dev *qdev = dev->data->dev_private;
 322         struct ecore_dev *edev = &qdev->edev;
 323         bool use_tx_offload = false;
 324
 325         if (is_dummy) {
 326                 dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
 327                 dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
 328                 return;
 329         }
 330
 331         if (ECORE_IS_CMT(edev)) {
 332                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
 333                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
 334                 return;
 335         }
 336
 337         if (dev->data->lro || dev->data->scattered_rx) {
 338                 DP_INFO(edev, "Assigning qede_recv_pkts\n");
 339                 dev->rx_pkt_burst = qede_recv_pkts;
 340         } else {
 341                 DP_INFO(edev, "Assigning qede_recv_pkts_regular\n");
 342                 dev->rx_pkt_burst = qede_recv_pkts_regular;
 343         }
 344
 345         use_tx_offload = !!(tx_offloads &
 346                             (DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | /* tunnel */
 347                              DEV_TX_OFFLOAD_TCP_TSO | /* tso */
 348                              DEV_TX_OFFLOAD_VLAN_INSERT)); /* vlan insert */
 349
 350         if (use_tx_offload) {
 351                 DP_INFO(edev, "Assigning qede_xmit_pkts\n");
 352                 dev->tx_pkt_burst = qede_xmit_pkts;
 353         } else {
 354                 DP_INFO(edev, "Assigning qede_xmit_pkts_regular\n");
 355                 dev->tx_pkt_burst = qede_xmit_pkts_regular;
 356         }
 357 }
 358
 359 static void
 360 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 361 {
 362         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 363         qdev->ops = qed_ops;
 364 }
 365
 366 static void qede_print_adapter_info(struct rte_eth_dev *dev)
 367 {
 368         struct qede_dev *qdev = dev->data->dev_private;
 369         struct ecore_dev *edev = &qdev->edev;
 370         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 371
 372         DP_INFO(edev, "**************************************************\n");
 373         DP_INFO(edev, " %-20s: %s\n", "DPDK version", rte_version());
 374         DP_INFO(edev, " %-20s: %s %c%d\n", "Chip details",
 375                   ECORE_IS_BB(edev) ? "BB" : "AH",
 376                   'A' + edev->chip_rev,
 377                   (int)edev->chip_metal);
 378         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 379                  QEDE_PMD_DRV_VERSION);
 380         DP_INFO(edev, " %-20s: %s\n", "Driver version", ver_str);
 381         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 382                  QEDE_PMD_BASE_VERSION);
 383         DP_INFO(edev, " %-20s: %s\n", "Base version", ver_str);
 384         qede_fw_version_get(dev, ver_str, sizeof(ver_str));
 385         DP_INFO(edev, " %-20s: %s\n", "Firmware version", ver_str);
 386         DP_INFO(edev, " %-20s: %s\n", "Firmware file", qede_fw_file);
 387         DP_INFO(edev, "**************************************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 393         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 394         unsigned int i = 0, j = 0, qid;
 395         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 396         struct qede_tx_queue *txq;
 397
 398         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 399
 400         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 401                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 402         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 403                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 404
 405         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 406                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 407                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 408                             sizeof(uint64_t));
 409                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 410                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 411                             sizeof(uint64_t));
 412                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 413                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 414                             sizeof(uint64_t));
 415
 416                 if (xstats)
 417                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 418                                 OSAL_MEMSET((((char *)
 419                                               (qdev->fp_array[qid].rxq)) +
 420                                              qede_rxq_xstats_strings[j].offset),
 421                                             0,
 422                                             sizeof(uint64_t));
 423
 424                 i++;
 425                 if (i == rxq_stat_cntrs)
 426                         break;
 427         }
 428
 429         i = 0;
 430
 431         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 432                 txq = qdev->fp_array[qid].txq;
 433
 434                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 435                                 (((uint64_t)(uintptr_t)(txq)) +
 436                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 437                             sizeof(uint64_t));
 438
 439                 i++;
 440                 if (i == txq_stat_cntrs)
 441                         break;
 442         }
 443 }
 444
 445 static int
 446 qede_stop_vport(struct ecore_dev *edev)
 447 {
 448         struct ecore_hwfn *p_hwfn;
 449         uint8_t vport_id;
 450         int rc;
 451         int i;
 452
 453         vport_id = 0;
 454         for_each_hwfn(edev, i) {
 455                 p_hwfn = &edev->hwfns[i];
 456                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 457                                          vport_id);
 458                 if (rc != ECORE_SUCCESS) {
 459                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 460                         return rc;
 461                 }
 462         }
 463
 464         DP_INFO(edev, "vport stopped\n");
 465
 466         return 0;
 467 }
 468
 469 static int
 470 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 471 {
 472         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 473         struct ecore_sp_vport_start_params params;
 474         struct ecore_hwfn *p_hwfn;
 475         int rc;
 476         int i;
 477
 478         if (qdev->vport_started)
 479                 qede_stop_vport(edev);
 480
 481         memset(&params, 0, sizeof(params));
 482         params.vport_id = 0;
 483         params.mtu = mtu;
 484         /* @DPDK - Disable FW placement */
 485         params.zero_placement_offset = 1;
 486         for_each_hwfn(edev, i) {
 487                 p_hwfn = &edev->hwfns[i];
 488                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 489                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 490                 rc = ecore_sp_vport_start(p_hwfn, &params);
 491                 if (rc != ECORE_SUCCESS) {
 492                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 493                         return rc;
 494                 }
 495         }
 496         ecore_reset_vport_stats(edev);
 497         qdev->vport_started = true;
 498         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 499
 500         return 0;
 501 }
 502
 503 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 504 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 505
 506 /* Activate or deactivate vport via vport-update */
 507 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 508 {
 509         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 510         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 511         struct ecore_sp_vport_update_params params;
 512         struct ecore_hwfn *p_hwfn;
 513         uint8_t i;
 514         int rc = -1;
 515
 516         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 517         params.vport_id = 0;
 518         params.update_vport_active_rx_flg = 1;
 519         params.update_vport_active_tx_flg = 1;
 520         params.vport_active_rx_flg = flg;
 521         params.vport_active_tx_flg = flg;
 522         if ((qdev->enable_tx_switching == false) && (flg == true)) {
 523                 params.update_tx_switching_flg = 1;
 524                 params.tx_switching_flg = !flg;
 525         }
 526         for_each_hwfn(edev, i) {
 527                 p_hwfn = &edev->hwfns[i];
 528                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 529                 rc = ecore_sp_vport_update(p_hwfn, &params,
 530                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 531                 if (rc != ECORE_SUCCESS) {
 532                         DP_ERR(edev, "Failed to update vport\n");
 533                         break;
 534                 }
 535         }
 536         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 537
 538         return rc;
 539 }
 540
 541 static void
 542 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 543                            uint16_t mtu, bool enable)
 544 {
 545         /* Enable LRO in split mode */
 546         sge_tpa_params->tpa_ipv4_en_flg = enable;
 547         sge_tpa_params->tpa_ipv6_en_flg = enable;
 548         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 549         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 550         /* set if tpa enable changes */
 551         sge_tpa_params->update_tpa_en_flg = 1;
 552         /* set if tpa parameters should be handled */
 553         sge_tpa_params->update_tpa_param_flg = enable;
 554
 555         sge_tpa_params->max_buffers_per_cqe = 20;
 556         /* Enable TPA in split mode. In this mode each TPA segment
 557          * starts on the new BD, so there is one BD per segment.
 558          */
 559         sge_tpa_params->tpa_pkt_split_flg = 1;
 560         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 561         sge_tpa_params->tpa_gro_consistent_flg = 0;
 562         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 563         sge_tpa_params->tpa_max_size = 0x7FFF;
 564         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 565         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 566 }
 567
 568 /* Enable/disable LRO via vport-update */
 569 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 570 {
 571         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 572         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 573         struct ecore_sp_vport_update_params params;
 574         struct ecore_sge_tpa_params tpa_params;
 575         struct ecore_hwfn *p_hwfn;
 576         int rc;
 577         int i;
 578
 579         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 580         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 581         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 582         params.vport_id = 0;
 583         params.sge_tpa_params = &tpa_params;
 584         for_each_hwfn(edev, i) {
 585                 p_hwfn = &edev->hwfns[i];
 586                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 587                 rc = ecore_sp_vport_update(p_hwfn, &params,
 588                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 589                 if (rc != ECORE_SUCCESS) {
 590                         DP_ERR(edev, "Failed to update LRO\n");
 591                         return -1;
 592                 }
 593         }
 594         qdev->enable_lro = flg;
 595         eth_dev->data->lro = flg;
 596
 597         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 598
 599         return 0;
 600 }
 601
 602 static int
 603 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 604                              enum qed_filter_rx_mode_type type)
 605 {
 606         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 607         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 608         struct ecore_filter_accept_flags flags;
 609
 610         memset(&flags, 0, sizeof(flags));
 611
 612         flags.update_rx_mode_config = 1;
 613         flags.update_tx_mode_config = 1;
 614         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 615                 ECORE_ACCEPT_MCAST_MATCHED |
 616                 ECORE_ACCEPT_BCAST;
 617
 618         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 619                 ECORE_ACCEPT_MCAST_MATCHED |
 620                 ECORE_ACCEPT_BCAST;
 621
 622         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 623                 flags.rx_accept_filter |= (ECORE_ACCEPT_UCAST_UNMATCHED |
 624                                            ECORE_ACCEPT_MCAST_UNMATCHED);
 625                 if (IS_VF(edev)) {
 626                         flags.tx_accept_filter |=
 627                                                 (ECORE_ACCEPT_UCAST_UNMATCHED |
 628                                                  ECORE_ACCEPT_MCAST_UNMATCHED);
 629                         DP_INFO(edev, "Enabling Tx unmatched flags for VF\n");
 630                 }
 631         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 632                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 633         }
 634
 635         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 636                         ECORE_SPQ_MODE_CB, NULL);
 637 }
 638
 639 int
 640 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 641                   bool add)
 642 {
 643         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 644         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 645         struct qede_ucast_entry *tmp = NULL;
 646         struct qede_ucast_entry *u;
 647         struct rte_ether_addr *mac_addr;
 648
 649         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 650         if (add) {
 651                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 652                         if ((memcmp(mac_addr, &tmp->mac,
 653                                     RTE_ETHER_ADDR_LEN) == 0) &&
 654                              ucast->vni == tmp->vni &&
 655                              ucast->vlan == tmp->vlan) {
 656                                 DP_INFO(edev, "Unicast MAC is already added"
 657                                         " with vlan = %u, vni = %u\n",
 658                                         ucast->vlan,  ucast->vni);
 659                                         return 0;
 660                         }
 661                 }
 662                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 663                                RTE_CACHE_LINE_SIZE);
 664                 if (!u) {
 665                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 666                         return -ENOMEM;
 667                 }
 668                 rte_ether_addr_copy(mac_addr, &u->mac);
 669                 u->vlan = ucast->vlan;
 670                 u->vni = ucast->vni;
 671                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 672                 qdev->num_uc_addr++;
 673         } else {
 674                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 675                         if ((memcmp(mac_addr, &tmp->mac,
 676                                     RTE_ETHER_ADDR_LEN) == 0) &&
 677                             ucast->vlan == tmp->vlan      &&
 678                             ucast->vni == tmp->vni)
 679                         break;
 680                 }
 681                 if (tmp == NULL) {
 682                         DP_INFO(edev, "Unicast MAC is not found\n");
 683                         return -EINVAL;
 684                 }
 685                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 686                 qdev->num_uc_addr--;
 687         }
 688
 689         return 0;
 690 }
 691
 692 static int
 693 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 694                 struct rte_ether_addr *mc_addrs,
 695                 uint32_t mc_addrs_num)
 696 {
 697         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 698         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 699         struct ecore_filter_mcast mcast;
 700         struct qede_mcast_entry *m = NULL;
 701         uint8_t i;
 702         int rc;
 703
 704         for (i = 0; i < mc_addrs_num; i++) {
 705                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 706                                RTE_CACHE_LINE_SIZE);
 707                 if (!m) {
 708                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 709                         return -ENOMEM;
 710                 }
 711                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 712                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 713         }
 714         memset(&mcast, 0, sizeof(mcast));
 715         mcast.num_mc_addrs = mc_addrs_num;
 716         mcast.opcode = ECORE_FILTER_ADD;
 717         for (i = 0; i < mc_addrs_num; i++)
 718                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 719                                                         &mcast.mac[i]);
 720         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 721         if (rc != ECORE_SUCCESS) {
 722                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 723                 return -1;
 724         }
 725
 726         return 0;
 727 }
 728
 729 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 730 {
 731         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 732         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 733         struct qede_mcast_entry *tmp = NULL;
 734         struct ecore_filter_mcast mcast;
 735         int j;
 736         int rc;
 737
 738         memset(&mcast, 0, sizeof(mcast));
 739         mcast.num_mc_addrs = qdev->num_mc_addr;
 740         mcast.opcode = ECORE_FILTER_REMOVE;
 741         j = 0;
 742         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 743                 rte_ether_addr_copy(&tmp->mac,
 744                                 (struct rte_ether_addr *)&mcast.mac[j]);
 745                 j++;
 746         }
 747         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 748         if (rc != ECORE_SUCCESS) {
 749                 DP_ERR(edev, "Failed to delete multicast filter\n");
 750                 return -1;
 751         }
 752         /* Init the list */
 753         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 754                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 755                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 756         }
 757         SLIST_INIT(&qdev->mc_list_head);
 758
 759         return 0;
 760 }
 761
 762 enum _ecore_status_t
 763 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 764                  bool add)
 765 {
 766         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 767         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 768         enum _ecore_status_t rc = ECORE_INVAL;
 769
 770         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 771                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 772                               " Please enable promisc mode\n");
 773                         return ECORE_INVAL;
 774         }
 775
 776         rc = qede_ucast_filter(eth_dev, ucast, add);
 777         if (rc == 0)
 778                 rc = ecore_filter_ucast_cmd(edev, ucast,
 779                                             ECORE_SPQ_MODE_CB, NULL);
 780         /* Indicate error only for add filter operation.
 781          * Delete filter operations are not severe.
 782          */
 783         if ((rc != ECORE_SUCCESS) && add)
 784                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 785                        rc, add);
 786
 787         return rc;
 788 }
 789
 790 static int
 791 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 792                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 793 {
 794         struct ecore_filter_ucast ucast;
 795         int re;
 796
 797         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 798                 return -EINVAL;
 799
 800         qede_set_ucast_cmn_params(&ucast);
 801         ucast.opcode = ECORE_FILTER_ADD;
 802         ucast.type = ECORE_FILTER_MAC;
 803         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 804         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 805         return re;
 806 }
 807
 808 static void
 809 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 810 {
 811         struct qede_dev *qdev = eth_dev->data->dev_private;
 812         struct ecore_dev *edev = &qdev->edev;
 813         struct ecore_filter_ucast ucast;
 814
 815         PMD_INIT_FUNC_TRACE(edev);
 816
 817         if (index >= qdev->dev_info.num_mac_filters) {
 818                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 819                        index, qdev->dev_info.num_mac_filters);
 820                 return;
 821         }
 822
 823         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 824                 return;
 825
 826         qede_set_ucast_cmn_params(&ucast);
 827         ucast.opcode = ECORE_FILTER_REMOVE;
 828         ucast.type = ECORE_FILTER_MAC;
 829
 830         /* Use the index maintained by rte */
 831         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 832                         (struct rte_ether_addr *)&ucast.mac);
 833
 834         qede_mac_int_ops(eth_dev, &ucast, false);
 835 }
 836
 837 static int
 838 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 839 {
 840         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 841         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 842
 843         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 844                                                mac_addr->addr_bytes)) {
 845                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 846                 return -EPERM;
 847         }
 848
 849         qede_mac_addr_remove(eth_dev, 0);
 850
 851         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 852 }
 853
 854 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 855 {
 856         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 857         struct ecore_sp_vport_update_params params;
 858         struct ecore_hwfn *p_hwfn;
 859         uint8_t i;
 860         int rc;
 861
 862         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 863         params.vport_id = 0;
 864         params.update_accept_any_vlan_flg = 1;
 865         params.accept_any_vlan = flg;
 866         for_each_hwfn(edev, i) {
 867                 p_hwfn = &edev->hwfns[i];
 868                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 869                 rc = ecore_sp_vport_update(p_hwfn, &params,
 870                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 871                 if (rc != ECORE_SUCCESS) {
 872                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 873                         return;
 874                 }
 875         }
 876
 877         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 878 }
 879
 880 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 881 {
 882         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 883         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 884         struct ecore_sp_vport_update_params params;
 885         struct ecore_hwfn *p_hwfn;
 886         uint8_t i;
 887         int rc;
 888
 889         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 890         params.vport_id = 0;
 891         params.update_inner_vlan_removal_flg = 1;
 892         params.inner_vlan_removal_flg = flg;
 893         for_each_hwfn(edev, i) {
 894                 p_hwfn = &edev->hwfns[i];
 895                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 896                 rc = ecore_sp_vport_update(p_hwfn, &params,
 897                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 898                 if (rc != ECORE_SUCCESS) {
 899                         DP_ERR(edev, "Failed to update vport\n");
 900                         return -1;
 901                 }
 902         }
 903
 904         qdev->vlan_strip_flg = flg;
 905
 906         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 907         return 0;
 908 }
 909
 910 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 911                                 uint16_t vlan_id, int on)
 912 {
 913         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 914         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 915         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 916         struct qede_vlan_entry *tmp = NULL;
 917         struct qede_vlan_entry *vlan;
 918         struct ecore_filter_ucast ucast;
 919         int rc;
 920
 921         if (on) {
 922                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 923                         DP_ERR(edev, "Reached max VLAN filter limit"
 924                                       " enabling accept_any_vlan\n");
 925                         qede_config_accept_any_vlan(qdev, true);
 926                         return 0;
 927                 }
 928
 929                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 930                         if (tmp->vid == vlan_id) {
 931                                 DP_INFO(edev, "VLAN %u already configured\n",
 932                                         vlan_id);
 933                                 return 0;
 934                         }
 935                 }
 936
 937                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 938                                   RTE_CACHE_LINE_SIZE);
 939
 940                 if (!vlan) {
 941                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 942                         return -ENOMEM;
 943                 }
 944
 945                 qede_set_ucast_cmn_params(&ucast);
 946                 ucast.opcode = ECORE_FILTER_ADD;
 947                 ucast.type = ECORE_FILTER_VLAN;
 948                 ucast.vlan = vlan_id;
 949                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 950                                             NULL);
 951                 if (rc != 0) {
 952                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 953                                rc);
 954                         rte_free(vlan);
 955                 } else {
 956                         vlan->vid = vlan_id;
 957                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 958                         qdev->configured_vlans++;
 959                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 960                                 vlan_id, qdev->configured_vlans);
 961                 }
 962         } else {
 963                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 964                         if (tmp->vid == vlan_id)
 965                                 break;
 966                 }
 967
 968                 if (!tmp) {
 969                         if (qdev->configured_vlans == 0) {
 970                                 DP_INFO(edev,
 971                                         "No VLAN filters configured yet\n");
 972                                 return 0;
 973                         }
 974
 975                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 976                         return -EINVAL;
 977                 }
 978
 979                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 980
 981                 qede_set_ucast_cmn_params(&ucast);
 982                 ucast.opcode = ECORE_FILTER_REMOVE;
 983                 ucast.type = ECORE_FILTER_VLAN;
 984                 ucast.vlan = vlan_id;
 985                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 986                                             NULL);
 987                 if (rc != 0) {
 988                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 989                                vlan_id, rc);
 990                 } else {
 991                         qdev->configured_vlans--;
 992                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 993                                 vlan_id, qdev->configured_vlans);
 994                 }
 995         }
 996
 997         return rc;
 998 }
 999
1000 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1001 {
1002         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1003         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1004         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1005
1006         if (mask & ETH_VLAN_STRIP_MASK) {
1007                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1008                         (void)qede_vlan_stripping(eth_dev, 1);
1009                 else
1010                         (void)qede_vlan_stripping(eth_dev, 0);
1011         }
1012
1013         if (mask & ETH_VLAN_FILTER_MASK) {
1014                 /* VLAN filtering kicks in when a VLAN is added */
1015                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1016                         qede_vlan_filter_set(eth_dev, 0, 1);
1017                 } else {
1018                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1019                                 DP_ERR(edev,
1020                                   " Please remove existing VLAN filters"
1021                                   " before disabling VLAN filtering\n");
1022                                 /* Signal app that VLAN filtering is still
1023                                  * enabled
1024                                  */
1025                                 eth_dev->data->dev_conf.rxmode.offloads |=
1026                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1027                         } else {
1028                                 qede_vlan_filter_set(eth_dev, 0, 0);
1029                         }
1030                 }
1031         }
1032
1033         if (mask & ETH_VLAN_EXTEND_MASK)
1034                 DP_ERR(edev, "Extend VLAN not supported\n");
1035
1036         qdev->vlan_offload_mask = mask;
1037
1038         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1039
1040         return 0;
1041 }
1042
1043 static void qede_prandom_bytes(uint32_t *buff)
1044 {
1045         uint8_t i;
1046
1047         srand((unsigned int)time(NULL));
1048         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1049                 buff[i] = rand();
1050 }
1051
1052 int qede_config_rss(struct rte_eth_dev *eth_dev)
1053 {
1054         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1055         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1056         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1057         struct rte_eth_rss_reta_entry64 reta_conf[2];
1058         struct rte_eth_rss_conf rss_conf;
1059         uint32_t i, id, pos, q;
1060
1061         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1062         if (!rss_conf.rss_key) {
1063                 DP_INFO(edev, "Applying driver default key\n");
1064                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1065                 qede_prandom_bytes(&def_rss_key[0]);
1066                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1067         }
1068
1069         /* Configure RSS hash */
1070         if (qede_rss_hash_update(eth_dev, &rss_conf))
1071                 return -EINVAL;
1072
1073         /* Configure default RETA */
1074         memset(reta_conf, 0, sizeof(reta_conf));
1075         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1076                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1077
1078         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1079                 id = i / RTE_RETA_GROUP_SIZE;
1080                 pos = i % RTE_RETA_GROUP_SIZE;
1081                 q = i % QEDE_RSS_COUNT(eth_dev);
1082                 reta_conf[id].reta[pos] = q;
1083         }
1084         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1085                                  ECORE_RSS_IND_TABLE_SIZE))
1086                 return -EINVAL;
1087
1088         return 0;
1089 }
1090
1091 static void qede_fastpath_start(struct ecore_dev *edev)
1092 {
1093         struct ecore_hwfn *p_hwfn;
1094         int i;
1095
1096         for_each_hwfn(edev, i) {
1097                 p_hwfn = &edev->hwfns[i];
1098                 ecore_hw_start_fastpath(p_hwfn);
1099         }
1100 }
1101
1102 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1103 {
1104         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1105         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1106         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1107
1108         PMD_INIT_FUNC_TRACE(edev);
1109
1110         /* Update MTU only if it has changed */
1111         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1112                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1113                         goto err;
1114                 qdev->mtu = qdev->new_mtu;
1115                 qdev->new_mtu = 0;
1116         }
1117
1118         /* Configure TPA parameters */
1119         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1120                 if (qede_enable_tpa(eth_dev, true))
1121                         return -EINVAL;
1122                 /* Enable scatter mode for LRO */
1123                 if (!eth_dev->data->scattered_rx)
1124                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1125         }
1126
1127         /* Start queues */
1128         if (qede_start_queues(eth_dev))
1129                 goto err;
1130
1131         if (IS_PF(edev))
1132                 qede_reset_queue_stats(qdev, true);
1133
1134         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1135          * enabling RSS. Hence RSS configuration is deferred up to this point.
1136          * Also, we would like to retain similar behavior in PF case, so we
1137          * don't do PF/VF specific check here.
1138          */
1139         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1140                 if (qede_config_rss(eth_dev))
1141                         goto err;
1142
1143         /* Enable vport*/
1144         if (qede_activate_vport(eth_dev, true))
1145                 goto err;
1146
1147         /* Bring-up the link */
1148         qede_dev_set_link_state(eth_dev, true);
1149
1150         /* Update link status */
1151         qede_link_update(eth_dev, 0);
1152
1153         /* Start/resume traffic */
1154         qede_fastpath_start(edev);
1155
1156         /* Assign I/O handlers */
1157         qede_assign_rxtx_handlers(eth_dev, false);
1158
1159         DP_INFO(edev, "Device started\n");
1160
1161         return 0;
1162 err:
1163         DP_ERR(edev, "Device start fails\n");
1164         return -1; /* common error code is < 0 */
1165 }
1166
1167 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1168 {
1169         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1170         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1171
1172         PMD_INIT_FUNC_TRACE(edev);
1173
1174         /* Bring the link down */
1175         qede_dev_set_link_state(eth_dev, false);
1176
1177         /* Update link status */
1178         qede_link_update(eth_dev, 0);
1179
1180         /* Replace I/O functions with dummy ones. It cannot
1181          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1182          */
1183         qede_assign_rxtx_handlers(eth_dev, true);
1184
1185         /* Disable vport */
1186         if (qede_activate_vport(eth_dev, false))
1187                 return;
1188
1189         if (qdev->enable_lro)
1190                 qede_enable_tpa(eth_dev, false);
1191
1192         /* Stop queues */
1193         qede_stop_queues(eth_dev);
1194
1195         /* Disable traffic */
1196         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1197
1198         DP_INFO(edev, "Device is stopped\n");
1199 }
1200
1201 static const char * const valid_args[] = {
1202         QEDE_NPAR_TX_SWITCHING,
1203         QEDE_VF_TX_SWITCHING,
1204         NULL,
1205 };
1206
1207 static int qede_args_check(const char *key, const char *val, void *opaque)
1208 {
1209         unsigned long tmp;
1210         int ret = 0;
1211         struct rte_eth_dev *eth_dev = opaque;
1212         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1213         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1214
1215         errno = 0;
1216         tmp = strtoul(val, NULL, 0);
1217         if (errno) {
1218                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1219                 return errno;
1220         }
1221
1222         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1223             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1224                 qdev->enable_tx_switching = !!tmp;
1225                 DP_INFO(edev, "Disabling %s tx-switching\n",
1226                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1227                         "VF" : "NPAR");
1228         }
1229
1230         return ret;
1231 }
1232
1233 static int qede_args(struct rte_eth_dev *eth_dev)
1234 {
1235         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1236         struct rte_kvargs *kvlist;
1237         struct rte_devargs *devargs;
1238         int ret;
1239         int i;
1240
1241         devargs = pci_dev->device.devargs;
1242         if (!devargs)
1243                 return 0; /* return success */
1244
1245         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1246         if (kvlist == NULL)
1247                 return -EINVAL;
1248
1249          /* Process parameters. */
1250         for (i = 0; (valid_args[i] != NULL); ++i) {
1251                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1252                         ret = rte_kvargs_process(kvlist, valid_args[i],
1253                                                  qede_args_check, eth_dev);
1254                         if (ret != ECORE_SUCCESS) {
1255                                 rte_kvargs_free(kvlist);
1256                                 return ret;
1257                         }
1258                 }
1259         }
1260         rte_kvargs_free(kvlist);
1261
1262         return 0;
1263 }
1264
1265 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1266 {
1267         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1268         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1269         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1270         uint8_t num_rxqs;
1271         uint8_t num_txqs;
1272         int ret;
1273
1274         PMD_INIT_FUNC_TRACE(edev);
1275
1276         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1277                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1278
1279         /* We need to have min 1 RX queue.There is no min check in
1280          * rte_eth_dev_configure(), so we are checking it here.
1281          */
1282         if (eth_dev->data->nb_rx_queues == 0) {
1283                 DP_ERR(edev, "Minimum one RX queue is required\n");
1284                 return -EINVAL;
1285         }
1286
1287         /* Enable Tx switching by default */
1288         qdev->enable_tx_switching = 1;
1289
1290         /* Parse devargs and fix up rxmode */
1291         if (qede_args(eth_dev))
1292                 DP_NOTICE(edev, false,
1293                           "Invalid devargs supplied, requested change will not take effect\n");
1294
1295         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1296               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1297                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1298                 return -ENOTSUP;
1299         }
1300         /* Flow director mode check */
1301         if (qede_check_fdir_support(eth_dev))
1302                 return -ENOTSUP;
1303
1304         /* Allocate/reallocate fastpath resources only for new queue config */
1305         num_txqs = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1306         num_rxqs = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1307         if (qdev->num_tx_queues != num_txqs ||
1308             qdev->num_rx_queues != num_rxqs) {
1309                 qede_dealloc_fp_resc(eth_dev);
1310                 qdev->num_tx_queues = num_txqs;
1311                 qdev->num_rx_queues = num_rxqs;
1312                 if (qede_alloc_fp_resc(qdev))
1313                         return -ENOMEM;
1314         }
1315
1316         /* If jumbo enabled adjust MTU */
1317         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1318                 eth_dev->data->mtu =
1319                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1320                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1321
1322         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1323                 eth_dev->data->scattered_rx = 1;
1324
1325         if (qede_start_vport(qdev, eth_dev->data->mtu))
1326                 return -1;
1327
1328         qdev->mtu = eth_dev->data->mtu;
1329
1330         /* Enable VLAN offloads by default */
1331         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1332                                              ETH_VLAN_FILTER_MASK);
1333         if (ret)
1334                 return ret;
1335
1336         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1337                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1338
1339         if (ECORE_IS_CMT(edev))
1340                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1341                         qdev->num_rx_queues, qdev->num_tx_queues);
1342
1343
1344         return 0;
1345 }
1346
1347 /* Info about HW descriptor ring limitations */
1348 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1349         .nb_max = 0x8000, /* 32K */
1350         .nb_min = 128,
1351         .nb_align = 128 /* lowest common multiple */
1352 };
1353
1354 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1355         .nb_max = 0x8000, /* 32K */
1356         .nb_min = 256,
1357         .nb_align = 256,
1358         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1359         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1360 };
1361
1362 static int
1363 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1364                   struct rte_eth_dev_info *dev_info)
1365 {
1366         struct qede_dev *qdev = eth_dev->data->dev_private;
1367         struct ecore_dev *edev = &qdev->edev;
1368         struct qed_link_output link;
1369         uint32_t speed_cap = 0;
1370
1371         PMD_INIT_FUNC_TRACE(edev);
1372
1373         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1374         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1375         dev_info->rx_desc_lim = qede_rx_desc_lim;
1376         dev_info->tx_desc_lim = qede_tx_desc_lim;
1377
1378         if (IS_PF(edev))
1379                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1380                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1381         else
1382                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1383                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1384         /* Since CMT mode internally doubles the number of queues */
1385         if (ECORE_IS_CMT(edev))
1386                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1387
1388         dev_info->max_tx_queues = dev_info->max_rx_queues;
1389
1390         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1391         dev_info->max_vfs = 0;
1392         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1393         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1394         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1395         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1396                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1397                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1398                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1399                                      DEV_RX_OFFLOAD_TCP_LRO     |
1400                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1401                                      DEV_RX_OFFLOAD_SCATTER     |
1402                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1403                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1404                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1405                                      DEV_RX_OFFLOAD_RSS_HASH);
1406         dev_info->rx_queue_offload_capa = 0;
1407
1408         /* TX offloads are on a per-packet basis, so it is applicable
1409          * to both at port and queue levels.
1410          */
1411         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1412                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1413                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1414                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1415                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1416                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1417                                      DEV_TX_OFFLOAD_TCP_TSO     |
1418                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1419                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1420         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1421
1422         dev_info->default_txconf = (struct rte_eth_txconf) {
1423                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1424         };
1425
1426         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1427                 /* Packets are always dropped if no descriptors are available */
1428                 .rx_drop_en = 1,
1429                 .offloads = 0,
1430         };
1431
1432         memset(&link, 0, sizeof(struct qed_link_output));
1433         qdev->ops->common->get_link(edev, &link);
1434         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1435                 speed_cap |= ETH_LINK_SPEED_1G;
1436         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1437                 speed_cap |= ETH_LINK_SPEED_10G;
1438         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1439                 speed_cap |= ETH_LINK_SPEED_25G;
1440         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1441                 speed_cap |= ETH_LINK_SPEED_40G;
1442         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1443                 speed_cap |= ETH_LINK_SPEED_50G;
1444         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1445                 speed_cap |= ETH_LINK_SPEED_100G;
1446         dev_info->speed_capa = speed_cap;
1447
1448         return 0;
1449 }
1450
1451 /* return 0 means link status changed, -1 means not changed */
1452 int
1453 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1454 {
1455         struct qede_dev *qdev = eth_dev->data->dev_private;
1456         struct ecore_dev *edev = &qdev->edev;
1457         struct qed_link_output q_link;
1458         struct rte_eth_link link;
1459         uint16_t link_duplex;
1460
1461         memset(&q_link, 0, sizeof(q_link));
1462         memset(&link, 0, sizeof(link));
1463
1464         qdev->ops->common->get_link(edev, &q_link);
1465
1466         /* Link Speed */
1467         link.link_speed = q_link.speed;
1468
1469         /* Link Mode */
1470         switch (q_link.duplex) {
1471         case QEDE_DUPLEX_HALF:
1472                 link_duplex = ETH_LINK_HALF_DUPLEX;
1473                 break;
1474         case QEDE_DUPLEX_FULL:
1475                 link_duplex = ETH_LINK_FULL_DUPLEX;
1476                 break;
1477         case QEDE_DUPLEX_UNKNOWN:
1478         default:
1479                 link_duplex = -1;
1480         }
1481         link.link_duplex = link_duplex;
1482
1483         /* Link Status */
1484         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1485
1486         /* AN */
1487         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1488                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1489
1490         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1491                 link.link_speed, link.link_duplex,
1492                 link.link_autoneg, link.link_status);
1493
1494         return rte_eth_linkstatus_set(eth_dev, &link);
1495 }
1496
1497 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1498 {
1499         enum _ecore_status_t ecore_status;
1500         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1501         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1502         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1503
1504         PMD_INIT_FUNC_TRACE(edev);
1505
1506         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1507
1508         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1509 }
1510
1511 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1512 {
1513         struct qede_dev *qdev = eth_dev->data->dev_private;
1514         struct ecore_dev *edev = &qdev->edev;
1515         enum _ecore_status_t ecore_status;
1516
1517         PMD_INIT_FUNC_TRACE(edev);
1518
1519         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1520                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1521                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1522         else
1523                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1524                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1525
1526         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1527 }
1528
1529 static void qede_poll_sp_sb_cb(void *param)
1530 {
1531         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1532         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1533         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1534         int rc;
1535
1536         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1537         qede_interrupt_action(&edev->hwfns[1]);
1538
1539         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1540                                qede_poll_sp_sb_cb,
1541                                (void *)eth_dev);
1542         if (rc != 0) {
1543                 DP_ERR(edev, "Unable to start periodic"
1544                              " timer rc %d\n", rc);
1545         }
1546 }
1547
1548 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1549 {
1550         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1551         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1552         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1553
1554         PMD_INIT_FUNC_TRACE(edev);
1555
1556         /* dev_stop() shall cleanup fp resources in hw but without releasing
1557          * dma memories and sw structures so that dev_start() can be called
1558          * by the app without reconfiguration. However, in dev_close() we
1559          * can release all the resources and device can be brought up newly
1560          */
1561         if (eth_dev->data->dev_started)
1562                 qede_dev_stop(eth_dev);
1563
1564         if (qdev->vport_started)
1565                 qede_stop_vport(edev);
1566         qdev->vport_started = false;
1567         qede_fdir_dealloc_resc(eth_dev);
1568         qede_dealloc_fp_resc(eth_dev);
1569
1570         eth_dev->data->nb_rx_queues = 0;
1571         eth_dev->data->nb_tx_queues = 0;
1572
1573         qdev->ops->common->slowpath_stop(edev);
1574         qdev->ops->common->remove(edev);
1575         rte_intr_disable(&pci_dev->intr_handle);
1576
1577         switch (pci_dev->intr_handle.type) {
1578         case RTE_INTR_HANDLE_UIO_INTX:
1579         case RTE_INTR_HANDLE_VFIO_LEGACY:
1580                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1581                                              qede_interrupt_handler_intx,
1582                                              (void *)eth_dev);
1583                 break;
1584         default:
1585                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1586                                            qede_interrupt_handler,
1587                                            (void *)eth_dev);
1588         }
1589
1590         if (ECORE_IS_CMT(edev))
1591                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1592 }
1593
1594 static int
1595 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1596 {
1597         struct qede_dev *qdev = eth_dev->data->dev_private;
1598         struct ecore_dev *edev = &qdev->edev;
1599         struct ecore_eth_stats stats;
1600         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1601         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1602         struct qede_tx_queue *txq;
1603
1604         ecore_get_vport_stats(edev, &stats);
1605
1606         /* RX Stats */
1607         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1608             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1609
1610         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1611             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1612
1613         eth_stats->ierrors = stats.common.rx_crc_errors +
1614             stats.common.rx_align_errors +
1615             stats.common.rx_carrier_errors +
1616             stats.common.rx_oversize_packets +
1617             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1618
1619         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1620
1621         eth_stats->imissed = stats.common.mftag_filter_discards +
1622             stats.common.mac_filter_discards +
1623             stats.common.no_buff_discards +
1624             stats.common.brb_truncates + stats.common.brb_discards;
1625
1626         /* TX stats */
1627         eth_stats->opackets = stats.common.tx_ucast_pkts +
1628             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1629
1630         eth_stats->obytes = stats.common.tx_ucast_bytes +
1631             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1632
1633         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1634
1635         /* Queue stats */
1636         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1637                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1638         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1639                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1640         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1641             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1642                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1643                        "Not all the queue stats will be displayed. Set"
1644                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1645                        " appropriately and retry.\n");
1646
1647         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1648                 eth_stats->q_ipackets[i] = 0;
1649                 eth_stats->q_errors[i] = 0;
1650
1651                 for_each_hwfn(edev, hw_fn) {
1652                         idx = qid * edev->num_hwfns + hw_fn;
1653
1654                         eth_stats->q_ipackets[i] +=
1655                                 *(uint64_t *)
1656                                         (((char *)(qdev->fp_array[idx].rxq)) +
1657                                          offsetof(struct qede_rx_queue,
1658                                          rcv_pkts));
1659                         eth_stats->q_errors[i] +=
1660                                 *(uint64_t *)
1661                                         (((char *)(qdev->fp_array[idx].rxq)) +
1662                                          offsetof(struct qede_rx_queue,
1663                                          rx_hw_errors)) +
1664                                 *(uint64_t *)
1665                                         (((char *)(qdev->fp_array[idx].rxq)) +
1666                                          offsetof(struct qede_rx_queue,
1667                                          rx_alloc_errors));
1668                 }
1669
1670                 i++;
1671                 if (i == rxq_stat_cntrs)
1672                         break;
1673         }
1674
1675         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1676                 eth_stats->q_opackets[j] = 0;
1677
1678                 for_each_hwfn(edev, hw_fn) {
1679                         idx = qid * edev->num_hwfns + hw_fn;
1680
1681                         txq = qdev->fp_array[idx].txq;
1682                         eth_stats->q_opackets[j] +=
1683                                 *((uint64_t *)(uintptr_t)
1684                                         (((uint64_t)(uintptr_t)(txq)) +
1685                                          offsetof(struct qede_tx_queue,
1686                                                   xmit_pkts)));
1687                 }
1688
1689                 j++;
1690                 if (j == txq_stat_cntrs)
1691                         break;
1692         }
1693
1694         return 0;
1695 }
1696
1697 static unsigned
1698 qede_get_xstats_count(struct qede_dev *qdev) {
1699         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1700
1701         if (ECORE_IS_BB(&qdev->edev))
1702                 return RTE_DIM(qede_xstats_strings) +
1703                        RTE_DIM(qede_bb_xstats_strings) +
1704                        (RTE_DIM(qede_rxq_xstats_strings) *
1705                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1706         else
1707                 return RTE_DIM(qede_xstats_strings) +
1708                        RTE_DIM(qede_ah_xstats_strings) +
1709                        (RTE_DIM(qede_rxq_xstats_strings) *
1710                         QEDE_RSS_COUNT(dev));
1711 }
1712
1713 static int
1714 qede_get_xstats_names(struct rte_eth_dev *dev,
1715                       struct rte_eth_xstat_name *xstats_names,
1716                       __rte_unused unsigned int limit)
1717 {
1718         struct qede_dev *qdev = dev->data->dev_private;
1719         struct ecore_dev *edev = &qdev->edev;
1720         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1721         unsigned int i, qid, hw_fn, stat_idx = 0;
1722
1723         if (xstats_names == NULL)
1724                 return stat_cnt;
1725
1726         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1727                 strlcpy(xstats_names[stat_idx].name,
1728                         qede_xstats_strings[i].name,
1729                         sizeof(xstats_names[stat_idx].name));
1730                 stat_idx++;
1731         }
1732
1733         if (ECORE_IS_BB(edev)) {
1734                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1735                         strlcpy(xstats_names[stat_idx].name,
1736                                 qede_bb_xstats_strings[i].name,
1737                                 sizeof(xstats_names[stat_idx].name));
1738                         stat_idx++;
1739                 }
1740         } else {
1741                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1742                         strlcpy(xstats_names[stat_idx].name,
1743                                 qede_ah_xstats_strings[i].name,
1744                                 sizeof(xstats_names[stat_idx].name));
1745                         stat_idx++;
1746                 }
1747         }
1748
1749         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1750                 for_each_hwfn(edev, hw_fn) {
1751                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1752                                 snprintf(xstats_names[stat_idx].name,
1753                                          RTE_ETH_XSTATS_NAME_SIZE,
1754                                          "%.4s%d.%d%s",
1755                                          qede_rxq_xstats_strings[i].name,
1756                                          hw_fn, qid,
1757                                          qede_rxq_xstats_strings[i].name + 4);
1758                                 stat_idx++;
1759                         }
1760                 }
1761         }
1762
1763         return stat_cnt;
1764 }
1765
1766 static int
1767 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1768                 unsigned int n)
1769 {
1770         struct qede_dev *qdev = dev->data->dev_private;
1771         struct ecore_dev *edev = &qdev->edev;
1772         struct ecore_eth_stats stats;
1773         const unsigned int num = qede_get_xstats_count(qdev);
1774         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1775
1776         if (n < num)
1777                 return num;
1778
1779         ecore_get_vport_stats(edev, &stats);
1780
1781         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1782                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1783                                              qede_xstats_strings[i].offset);
1784                 xstats[stat_idx].id = stat_idx;
1785                 stat_idx++;
1786         }
1787
1788         if (ECORE_IS_BB(edev)) {
1789                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1790                         xstats[stat_idx].value =
1791                                         *(uint64_t *)(((char *)&stats) +
1792                                         qede_bb_xstats_strings[i].offset);
1793                         xstats[stat_idx].id = stat_idx;
1794                         stat_idx++;
1795                 }
1796         } else {
1797                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1798                         xstats[stat_idx].value =
1799                                         *(uint64_t *)(((char *)&stats) +
1800                                         qede_ah_xstats_strings[i].offset);
1801                         xstats[stat_idx].id = stat_idx;
1802                         stat_idx++;
1803                 }
1804         }
1805
1806         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1807                 for_each_hwfn(edev, hw_fn) {
1808                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1809                                 fpidx = qid * edev->num_hwfns + hw_fn;
1810                                 xstats[stat_idx].value = *(uint64_t *)
1811                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1812                                          qede_rxq_xstats_strings[i].offset);
1813                                 xstats[stat_idx].id = stat_idx;
1814                                 stat_idx++;
1815                         }
1816
1817                 }
1818         }
1819
1820         return stat_idx;
1821 }
1822
1823 static int
1824 qede_reset_xstats(struct rte_eth_dev *dev)
1825 {
1826         struct qede_dev *qdev = dev->data->dev_private;
1827         struct ecore_dev *edev = &qdev->edev;
1828
1829         ecore_reset_vport_stats(edev);
1830         qede_reset_queue_stats(qdev, true);
1831
1832         return 0;
1833 }
1834
1835 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1836 {
1837         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1838         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1839         struct qed_link_params link_params;
1840         int rc;
1841
1842         DP_INFO(edev, "setting link state %d\n", link_up);
1843         memset(&link_params, 0, sizeof(link_params));
1844         link_params.link_up = link_up;
1845         rc = qdev->ops->common->set_link(edev, &link_params);
1846         if (rc != ECORE_SUCCESS)
1847                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1848
1849         return rc;
1850 }
1851
1852 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1853 {
1854         return qede_dev_set_link_state(eth_dev, true);
1855 }
1856
1857 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1858 {
1859         return qede_dev_set_link_state(eth_dev, false);
1860 }
1861
1862 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1863 {
1864         struct qede_dev *qdev = eth_dev->data->dev_private;
1865         struct ecore_dev *edev = &qdev->edev;
1866
1867         ecore_reset_vport_stats(edev);
1868         qede_reset_queue_stats(qdev, false);
1869
1870         return 0;
1871 }
1872
1873 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1874 {
1875         enum qed_filter_rx_mode_type type =
1876             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1877         enum _ecore_status_t ecore_status;
1878
1879         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1880
1881         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1882 }
1883
1884 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1885 {
1886         enum _ecore_status_t ecore_status;
1887
1888         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1889                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1890                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1891         else
1892                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1893                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1894
1895         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1896 }
1897
1898 static int
1899 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1900                 struct rte_ether_addr *mc_addrs,
1901                 uint32_t mc_addrs_num)
1902 {
1903         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1904         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1905         uint8_t i;
1906
1907         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1908                 DP_ERR(edev, "Reached max multicast filters limit,"
1909                              "Please enable multicast promisc mode\n");
1910                 return -ENOSPC;
1911         }
1912
1913         for (i = 0; i < mc_addrs_num; i++) {
1914                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1915                         DP_ERR(edev, "Not a valid multicast MAC\n");
1916                         return -EINVAL;
1917                 }
1918         }
1919
1920         /* Flush all existing entries */
1921         if (qede_del_mcast_filters(eth_dev))
1922                 return -1;
1923
1924         /* Set new mcast list */
1925         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1926 }
1927
1928 /* Update MTU via vport-update without doing port restart.
1929  * The vport must be deactivated before calling this API.
1930  */
1931 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1932 {
1933         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1934         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1935         struct ecore_hwfn *p_hwfn;
1936         int rc;
1937         int i;
1938
1939         if (IS_PF(edev)) {
1940                 struct ecore_sp_vport_update_params params;
1941
1942                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1943                 params.vport_id = 0;
1944                 params.mtu = mtu;
1945                 params.vport_id = 0;
1946                 for_each_hwfn(edev, i) {
1947                         p_hwfn = &edev->hwfns[i];
1948                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1949                         rc = ecore_sp_vport_update(p_hwfn, &params,
1950                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1951                         if (rc != ECORE_SUCCESS)
1952                                 goto err;
1953                 }
1954         } else {
1955                 for_each_hwfn(edev, i) {
1956                         p_hwfn = &edev->hwfns[i];
1957                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1958                         if (rc == ECORE_INVAL) {
1959                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1960                                 /* Recreate vport */
1961                                 rc = qede_start_vport(qdev, mtu);
1962                                 if (rc != ECORE_SUCCESS)
1963                                         goto err;
1964
1965                                 /* Restore config lost due to vport stop */
1966                                 if (eth_dev->data->promiscuous)
1967                                         qede_promiscuous_enable(eth_dev);
1968                                 else
1969                                         qede_promiscuous_disable(eth_dev);
1970
1971                                 if (eth_dev->data->all_multicast)
1972                                         qede_allmulticast_enable(eth_dev);
1973                                 else
1974                                         qede_allmulticast_disable(eth_dev);
1975
1976                                 qede_vlan_offload_set(eth_dev,
1977                                                       qdev->vlan_offload_mask);
1978                         } else if (rc != ECORE_SUCCESS) {
1979                                 goto err;
1980                         }
1981                 }
1982         }
1983         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1984
1985         return 0;
1986
1987 err:
1988         DP_ERR(edev, "Failed to update MTU\n");
1989         return -1;
1990 }
1991
1992 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1993                               struct rte_eth_fc_conf *fc_conf)
1994 {
1995         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1996         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1997         struct qed_link_output current_link;
1998         struct qed_link_params params;
1999
2000         memset(&current_link, 0, sizeof(current_link));
2001         qdev->ops->common->get_link(edev, &current_link);
2002
2003         memset(&params, 0, sizeof(params));
2004         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2005         if (fc_conf->autoneg) {
2006                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2007                         DP_ERR(edev, "Autoneg not supported\n");
2008                         return -EINVAL;
2009                 }
2010                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2011         }
2012
2013         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2014         if (fc_conf->mode == RTE_FC_FULL)
2015                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2016                                         QED_LINK_PAUSE_RX_ENABLE);
2017         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2018                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2019         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2020                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2021
2022         params.link_up = true;
2023         (void)qdev->ops->common->set_link(edev, &params);
2024
2025         return 0;
2026 }
2027
2028 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2029                               struct rte_eth_fc_conf *fc_conf)
2030 {
2031         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2032         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2033         struct qed_link_output current_link;
2034
2035         memset(&current_link, 0, sizeof(current_link));
2036         qdev->ops->common->get_link(edev, &current_link);
2037
2038         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2039                 fc_conf->autoneg = true;
2040
2041         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2042                                          QED_LINK_PAUSE_TX_ENABLE))
2043                 fc_conf->mode = RTE_FC_FULL;
2044         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2045                 fc_conf->mode = RTE_FC_RX_PAUSE;
2046         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2047                 fc_conf->mode = RTE_FC_TX_PAUSE;
2048         else
2049                 fc_conf->mode = RTE_FC_NONE;
2050
2051         return 0;
2052 }
2053
2054 static const uint32_t *
2055 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2056 {
2057         static const uint32_t ptypes[] = {
2058                 RTE_PTYPE_L2_ETHER,
2059                 RTE_PTYPE_L2_ETHER_VLAN,
2060                 RTE_PTYPE_L3_IPV4,
2061                 RTE_PTYPE_L3_IPV6,
2062                 RTE_PTYPE_L4_TCP,
2063                 RTE_PTYPE_L4_UDP,
2064                 RTE_PTYPE_TUNNEL_VXLAN,
2065                 RTE_PTYPE_L4_FRAG,
2066                 RTE_PTYPE_TUNNEL_GENEVE,
2067                 RTE_PTYPE_TUNNEL_GRE,
2068                 /* Inner */
2069                 RTE_PTYPE_INNER_L2_ETHER,
2070                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2071                 RTE_PTYPE_INNER_L3_IPV4,
2072                 RTE_PTYPE_INNER_L3_IPV6,
2073                 RTE_PTYPE_INNER_L4_TCP,
2074                 RTE_PTYPE_INNER_L4_UDP,
2075                 RTE_PTYPE_INNER_L4_FRAG,
2076                 RTE_PTYPE_UNKNOWN
2077         };
2078
2079         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
2080             eth_dev->rx_pkt_burst == qede_recv_pkts_regular ||
2081             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
2082                 return ptypes;
2083
2084         return NULL;
2085 }
2086
2087 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2088 {
2089         *rss_caps = 0;
2090         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2091         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2092         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2093         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2094         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2095         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2096         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2097         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2098 }
2099
2100 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2101                          struct rte_eth_rss_conf *rss_conf)
2102 {
2103         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2104         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2105         struct ecore_sp_vport_update_params vport_update_params;
2106         struct ecore_rss_params rss_params;
2107         struct ecore_hwfn *p_hwfn;
2108         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2109         uint64_t hf = rss_conf->rss_hf;
2110         uint8_t len = rss_conf->rss_key_len;
2111         uint8_t idx, i, j, fpidx;
2112         int rc;
2113
2114         memset(&vport_update_params, 0, sizeof(vport_update_params));
2115         memset(&rss_params, 0, sizeof(rss_params));
2116
2117         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2118                 (unsigned long)hf, len, key);
2119
2120         if (hf != 0) {
2121                 /* Enabling RSS */
2122                 DP_INFO(edev, "Enabling rss\n");
2123
2124                 /* RSS caps */
2125                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2126                 rss_params.update_rss_capabilities = 1;
2127
2128                 /* RSS hash key */
2129                 if (key) {
2130                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2131                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2132                                 return -EINVAL;
2133                         }
2134                         DP_INFO(edev, "Applying user supplied hash key\n");
2135                         rss_params.update_rss_key = 1;
2136                         memcpy(&rss_params.rss_key, key, len);
2137                 }
2138                 rss_params.rss_enable = 1;
2139         }
2140
2141         rss_params.update_rss_config = 1;
2142         /* tbl_size has to be set with capabilities */
2143         rss_params.rss_table_size_log = 7;
2144         vport_update_params.vport_id = 0;
2145
2146         for_each_hwfn(edev, i) {
2147                 /* pass the L2 handles instead of qids */
2148                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2149                         idx = j % QEDE_RSS_COUNT(eth_dev);
2150                         fpidx = idx * edev->num_hwfns + i;
2151                         rss_params.rss_ind_table[j] =
2152                                 qdev->fp_array[fpidx].rxq->handle;
2153                 }
2154
2155                 vport_update_params.rss_params = &rss_params;
2156
2157                 p_hwfn = &edev->hwfns[i];
2158                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2159                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2160                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2161                 if (rc) {
2162                         DP_ERR(edev, "vport-update for RSS failed\n");
2163                         return rc;
2164                 }
2165         }
2166         qdev->rss_enable = rss_params.rss_enable;
2167
2168         /* Update local structure for hash query */
2169         qdev->rss_conf.rss_hf = hf;
2170         qdev->rss_conf.rss_key_len = len;
2171         if (qdev->rss_enable) {
2172                 if  (qdev->rss_conf.rss_key == NULL) {
2173                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2174                         if (qdev->rss_conf.rss_key == NULL) {
2175                                 DP_ERR(edev, "No memory to store RSS key\n");
2176                                 return -ENOMEM;
2177                         }
2178                 }
2179                 if (key && len) {
2180                         DP_INFO(edev, "Storing RSS key\n");
2181                         memcpy(qdev->rss_conf.rss_key, key, len);
2182                 }
2183         } else if (!qdev->rss_enable && len == 0) {
2184                 if (qdev->rss_conf.rss_key) {
2185                         free(qdev->rss_conf.rss_key);
2186                         qdev->rss_conf.rss_key = NULL;
2187                         DP_INFO(edev, "Free RSS key\n");
2188                 }
2189         }
2190
2191         return 0;
2192 }
2193
2194 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2195                            struct rte_eth_rss_conf *rss_conf)
2196 {
2197         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2198
2199         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2200         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2201
2202         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2203                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2204                        rss_conf->rss_key_len);
2205         return 0;
2206 }
2207
2208 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2209                          struct rte_eth_rss_reta_entry64 *reta_conf,
2210                          uint16_t reta_size)
2211 {
2212         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2213         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2214         struct ecore_sp_vport_update_params vport_update_params;
2215         struct ecore_rss_params *params;
2216         uint16_t i, j, idx, fid, shift;
2217         struct ecore_hwfn *p_hwfn;
2218         uint8_t entry;
2219         int rc = 0;
2220
2221         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2222                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2223                        reta_size);
2224                 return -EINVAL;
2225         }
2226
2227         memset(&vport_update_params, 0, sizeof(vport_update_params));
2228         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2229         if (params == NULL) {
2230                 DP_ERR(edev, "failed to allocate memory\n");
2231                 return -ENOMEM;
2232         }
2233
2234         params->update_rss_ind_table = 1;
2235         params->rss_table_size_log = 7;
2236         params->update_rss_config = 1;
2237
2238         vport_update_params.vport_id = 0;
2239         /* Use the current value of rss_enable */
2240         params->rss_enable = qdev->rss_enable;
2241         vport_update_params.rss_params = params;
2242
2243         for_each_hwfn(edev, i) {
2244                 for (j = 0; j < reta_size; j++) {
2245                         idx = j / RTE_RETA_GROUP_SIZE;
2246                         shift = j % RTE_RETA_GROUP_SIZE;
2247                         if (reta_conf[idx].mask & (1ULL << shift)) {
2248                                 entry = reta_conf[idx].reta[shift];
2249                                 fid = entry * edev->num_hwfns + i;
2250                                 /* Pass rxq handles to ecore */
2251                                 params->rss_ind_table[j] =
2252                                                 qdev->fp_array[fid].rxq->handle;
2253                                 /* Update the local copy for RETA query cmd */
2254                                 qdev->rss_ind_table[j] = entry;
2255                         }
2256                 }
2257
2258                 p_hwfn = &edev->hwfns[i];
2259                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2260                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2261                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2262                 if (rc) {
2263                         DP_ERR(edev, "vport-update for RSS failed\n");
2264                         goto out;
2265                 }
2266         }
2267
2268 out:
2269         rte_free(params);
2270         return rc;
2271 }
2272
2273 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2274                                struct rte_eth_rss_reta_entry64 *reta_conf,
2275                                uint16_t reta_size)
2276 {
2277         struct qede_dev *qdev = eth_dev->data->dev_private;
2278         struct ecore_dev *edev = &qdev->edev;
2279         uint16_t i, idx, shift;
2280         uint8_t entry;
2281
2282         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2283                 DP_ERR(edev, "reta_size %d is not supported\n",
2284                        reta_size);
2285                 return -EINVAL;
2286         }
2287
2288         for (i = 0; i < reta_size; i++) {
2289                 idx = i / RTE_RETA_GROUP_SIZE;
2290                 shift = i % RTE_RETA_GROUP_SIZE;
2291                 if (reta_conf[idx].mask & (1ULL << shift)) {
2292                         entry = qdev->rss_ind_table[i];
2293                         reta_conf[idx].reta[shift] = entry;
2294                 }
2295         }
2296
2297         return 0;
2298 }
2299
2300
2301
2302 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2303 {
2304         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2305         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2306         struct rte_eth_dev_info dev_info = {0};
2307         struct qede_fastpath *fp;
2308         uint32_t max_rx_pkt_len;
2309         uint32_t frame_size;
2310         uint16_t bufsz;
2311         bool restart = false;
2312         int i, rc;
2313
2314         PMD_INIT_FUNC_TRACE(edev);
2315         rc = qede_dev_info_get(dev, &dev_info);
2316         if (rc != 0) {
2317                 DP_ERR(edev, "Error during getting ethernet device info\n");
2318                 return rc;
2319         }
2320         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2321         frame_size = max_rx_pkt_len;
2322         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2323                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2324                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2325                        QEDE_ETH_OVERHEAD);
2326                 return -EINVAL;
2327         }
2328         if (!dev->data->scattered_rx &&
2329             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2330                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2331                         dev->data->min_rx_buf_size);
2332                 return -EINVAL;
2333         }
2334         if (dev->data->dev_started) {
2335                 dev->data->dev_started = 0;
2336                 qede_dev_stop(dev);
2337                 restart = true;
2338         }
2339         rte_delay_ms(1000);
2340         qdev->new_mtu = mtu;
2341
2342         /* Fix up RX buf size for all queues of the port */
2343         for (i = 0; i < qdev->num_rx_queues; i++) {
2344                 fp = &qdev->fp_array[i];
2345                 if (fp->rxq != NULL) {
2346                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2347                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2348                         /* cache align the mbuf size to simplfy rx_buf_size
2349                          * calculation
2350                          */
2351                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2352                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2353                         if (rc < 0)
2354                                 return rc;
2355
2356                         fp->rxq->rx_buf_size = rc;
2357                 }
2358         }
2359         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2360                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2361         else
2362                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2363
2364         if (!dev->data->dev_started && restart) {
2365                 qede_dev_start(dev);
2366                 dev->data->dev_started = 1;
2367         }
2368
2369         /* update max frame size */
2370         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2371
2372         return 0;
2373 }
2374
2375 static int
2376 qede_dev_reset(struct rte_eth_dev *dev)
2377 {
2378         int ret;
2379
2380         ret = qede_eth_dev_uninit(dev);
2381         if (ret)
2382                 return ret;
2383
2384         return qede_eth_dev_init(dev);
2385 }
2386
2387 static const struct eth_dev_ops qede_eth_dev_ops = {
2388         .dev_configure = qede_dev_configure,
2389         .dev_infos_get = qede_dev_info_get,
2390         .rx_queue_setup = qede_rx_queue_setup,
2391         .rx_queue_release = qede_rx_queue_release,
2392         .rx_descriptor_status = qede_rx_descriptor_status,
2393         .tx_queue_setup = qede_tx_queue_setup,
2394         .tx_queue_release = qede_tx_queue_release,
2395         .dev_start = qede_dev_start,
2396         .dev_reset = qede_dev_reset,
2397         .dev_set_link_up = qede_dev_set_link_up,
2398         .dev_set_link_down = qede_dev_set_link_down,
2399         .link_update = qede_link_update,
2400         .promiscuous_enable = qede_promiscuous_enable,
2401         .promiscuous_disable = qede_promiscuous_disable,
2402         .allmulticast_enable = qede_allmulticast_enable,
2403         .allmulticast_disable = qede_allmulticast_disable,
2404         .set_mc_addr_list = qede_set_mc_addr_list,
2405         .dev_stop = qede_dev_stop,
2406         .dev_close = qede_dev_close,
2407         .stats_get = qede_get_stats,
2408         .stats_reset = qede_reset_stats,
2409         .xstats_get = qede_get_xstats,
2410         .xstats_reset = qede_reset_xstats,
2411         .xstats_get_names = qede_get_xstats_names,
2412         .mac_addr_add = qede_mac_addr_add,
2413         .mac_addr_remove = qede_mac_addr_remove,
2414         .mac_addr_set = qede_mac_addr_set,
2415         .vlan_offload_set = qede_vlan_offload_set,
2416         .vlan_filter_set = qede_vlan_filter_set,
2417         .flow_ctrl_set = qede_flow_ctrl_set,
2418         .flow_ctrl_get = qede_flow_ctrl_get,
2419         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2420         .rss_hash_update = qede_rss_hash_update,
2421         .rss_hash_conf_get = qede_rss_hash_conf_get,
2422         .reta_update  = qede_rss_reta_update,
2423         .reta_query  = qede_rss_reta_query,
2424         .mtu_set = qede_set_mtu,
2425         .filter_ctrl = qede_dev_filter_ctrl,
2426         .udp_tunnel_port_add = qede_udp_dst_port_add,
2427         .udp_tunnel_port_del = qede_udp_dst_port_del,
2428         .fw_version_get = qede_fw_version_get,
2429         .get_reg = qede_get_regs,
2430 };
2431
2432 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2433         .dev_configure = qede_dev_configure,
2434         .dev_infos_get = qede_dev_info_get,
2435         .rx_queue_setup = qede_rx_queue_setup,
2436         .rx_queue_release = qede_rx_queue_release,
2437         .rx_descriptor_status = qede_rx_descriptor_status,
2438         .tx_queue_setup = qede_tx_queue_setup,
2439         .tx_queue_release = qede_tx_queue_release,
2440         .dev_start = qede_dev_start,
2441         .dev_reset = qede_dev_reset,
2442         .dev_set_link_up = qede_dev_set_link_up,
2443         .dev_set_link_down = qede_dev_set_link_down,
2444         .link_update = qede_link_update,
2445         .promiscuous_enable = qede_promiscuous_enable,
2446         .promiscuous_disable = qede_promiscuous_disable,
2447         .allmulticast_enable = qede_allmulticast_enable,
2448         .allmulticast_disable = qede_allmulticast_disable,
2449         .set_mc_addr_list = qede_set_mc_addr_list,
2450         .dev_stop = qede_dev_stop,
2451         .dev_close = qede_dev_close,
2452         .stats_get = qede_get_stats,
2453         .stats_reset = qede_reset_stats,
2454         .xstats_get = qede_get_xstats,
2455         .xstats_reset = qede_reset_xstats,
2456         .xstats_get_names = qede_get_xstats_names,
2457         .vlan_offload_set = qede_vlan_offload_set,
2458         .vlan_filter_set = qede_vlan_filter_set,
2459         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2460         .rss_hash_update = qede_rss_hash_update,
2461         .rss_hash_conf_get = qede_rss_hash_conf_get,
2462         .reta_update  = qede_rss_reta_update,
2463         .reta_query  = qede_rss_reta_query,
2464         .mtu_set = qede_set_mtu,
2465         .udp_tunnel_port_add = qede_udp_dst_port_add,
2466         .udp_tunnel_port_del = qede_udp_dst_port_del,
2467         .mac_addr_add = qede_mac_addr_add,
2468         .mac_addr_remove = qede_mac_addr_remove,
2469         .mac_addr_set = qede_mac_addr_set,
2470         .fw_version_get = qede_fw_version_get,
2471 };
2472
2473 static void qede_update_pf_params(struct ecore_dev *edev)
2474 {
2475         struct ecore_pf_params pf_params;
2476
2477         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2478         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2479         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2480         qed_ops->common->update_pf_params(edev, &pf_params);
2481 }
2482
2483 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2484 {
2485         struct rte_pci_device *pci_dev;
2486         struct rte_pci_addr pci_addr;
2487         struct qede_dev *adapter;
2488         struct ecore_dev *edev;
2489         struct qed_dev_eth_info dev_info;
2490         struct qed_slowpath_params params;
2491         static bool do_once = true;
2492         uint8_t bulletin_change;
2493         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2494         uint8_t is_mac_forced;
2495         bool is_mac_exist;
2496         /* Fix up ecore debug level */
2497         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2498         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2499         uint32_t int_mode;
2500         int rc;
2501
2502         /* Extract key data structures */
2503         adapter = eth_dev->data->dev_private;
2504         adapter->ethdev = eth_dev;
2505         edev = &adapter->edev;
2506         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2507         pci_addr = pci_dev->addr;
2508
2509         PMD_INIT_FUNC_TRACE(edev);
2510
2511         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2512                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2513                  eth_dev->data->port_id);
2514
2515         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2516                 DP_ERR(edev, "Skipping device init from secondary process\n");
2517                 return 0;
2518         }
2519
2520         rte_eth_copy_pci_info(eth_dev, pci_dev);
2521
2522         /* @DPDK */
2523         edev->vendor_id = pci_dev->id.vendor_id;
2524         edev->device_id = pci_dev->id.device_id;
2525
2526         qed_ops = qed_get_eth_ops();
2527         if (!qed_ops) {
2528                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2529                 rc = -EINVAL;
2530                 goto err;
2531         }
2532
2533         DP_INFO(edev, "Starting qede probe\n");
2534         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2535                                     dp_level, is_vf);
2536         if (rc != 0) {
2537                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2538                 rc = -ENODEV;
2539                 goto err;
2540         }
2541         qede_update_pf_params(edev);
2542
2543         switch (pci_dev->intr_handle.type) {
2544         case RTE_INTR_HANDLE_UIO_INTX:
2545         case RTE_INTR_HANDLE_VFIO_LEGACY:
2546                 int_mode = ECORE_INT_MODE_INTA;
2547                 rte_intr_callback_register(&pci_dev->intr_handle,
2548                                            qede_interrupt_handler_intx,
2549                                            (void *)eth_dev);
2550                 break;
2551         default:
2552                 int_mode = ECORE_INT_MODE_MSIX;
2553                 rte_intr_callback_register(&pci_dev->intr_handle,
2554                                            qede_interrupt_handler,
2555                                            (void *)eth_dev);
2556         }
2557
2558         if (rte_intr_enable(&pci_dev->intr_handle)) {
2559                 DP_ERR(edev, "rte_intr_enable() failed\n");
2560                 rc = -ENODEV;
2561                 goto err;
2562         }
2563
2564         /* Start the Slowpath-process */
2565         memset(&params, 0, sizeof(struct qed_slowpath_params));
2566
2567         params.int_mode = int_mode;
2568         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2569         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2570         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2571         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2572         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2573                 QEDE_PMD_DRV_VER_STR_SIZE);
2574
2575         qede_assign_rxtx_handlers(eth_dev, true);
2576         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2577
2578         /* For CMT mode device do periodic polling for slowpath events.
2579          * This is required since uio device uses only one MSI-x
2580          * interrupt vector but we need one for each engine.
2581          */
2582         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2583                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2584                                        qede_poll_sp_sb_cb,
2585                                        (void *)eth_dev);
2586                 if (rc != 0) {
2587                         DP_ERR(edev, "Unable to start periodic"
2588                                      " timer rc %d\n", rc);
2589                         rc = -EINVAL;
2590                         goto err;
2591                 }
2592         }
2593
2594         rc = qed_ops->common->slowpath_start(edev, &params);
2595         if (rc) {
2596                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2597                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2598                                      (void *)eth_dev);
2599                 rc = -ENODEV;
2600                 goto err;
2601         }
2602
2603         rc = qed_ops->fill_dev_info(edev, &dev_info);
2604         if (rc) {
2605                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2606                 qed_ops->common->slowpath_stop(edev);
2607                 qed_ops->common->remove(edev);
2608                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2609                                      (void *)eth_dev);
2610                 rc = -ENODEV;
2611                 goto err;
2612         }
2613
2614         qede_alloc_etherdev(adapter, &dev_info);
2615
2616         if (do_once) {
2617                 qede_print_adapter_info(eth_dev);
2618                 do_once = false;
2619         }
2620
2621         adapter->ops->common->set_name(edev, edev->name);
2622
2623         if (!is_vf)
2624                 adapter->dev_info.num_mac_filters =
2625                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2626                                             ECORE_MAC);
2627         else
2628                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2629                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2630
2631         /* Allocate memory for storing MAC addr */
2632         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2633                                         (RTE_ETHER_ADDR_LEN *
2634                                         adapter->dev_info.num_mac_filters),
2635                                         RTE_CACHE_LINE_SIZE);
2636
2637         if (eth_dev->data->mac_addrs == NULL) {
2638                 DP_ERR(edev, "Failed to allocate MAC address\n");
2639                 qed_ops->common->slowpath_stop(edev);
2640                 qed_ops->common->remove(edev);
2641                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2642                                      (void *)eth_dev);
2643                 return -ENOMEM;
2644         }
2645
2646         if (!is_vf) {
2647                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2648                                 hw_info.hw_mac_addr,
2649                                 &eth_dev->data->mac_addrs[0]);
2650                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2651                                 &adapter->primary_mac);
2652         } else {
2653                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2654                                        &bulletin_change);
2655                 if (bulletin_change) {
2656                         is_mac_exist =
2657                             ecore_vf_bulletin_get_forced_mac(
2658                                                 ECORE_LEADING_HWFN(edev),
2659                                                 vf_mac,
2660                                                 &is_mac_forced);
2661                         if (is_mac_exist) {
2662                                 DP_INFO(edev, "VF macaddr received from PF\n");
2663                                 rte_ether_addr_copy(
2664                                         (struct rte_ether_addr *)&vf_mac,
2665                                         &eth_dev->data->mac_addrs[0]);
2666                                 rte_ether_addr_copy(
2667                                         &eth_dev->data->mac_addrs[0],
2668                                         &adapter->primary_mac);
2669                         } else {
2670                                 DP_ERR(edev, "No VF macaddr assigned\n");
2671                         }
2672                 }
2673         }
2674
2675         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2676
2677         adapter->num_tx_queues = 0;
2678         adapter->num_rx_queues = 0;
2679         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2680         SLIST_INIT(&adapter->vlan_list_head);
2681         SLIST_INIT(&adapter->uc_list_head);
2682         SLIST_INIT(&adapter->mc_list_head);
2683         adapter->mtu = RTE_ETHER_MTU;
2684         adapter->vport_started = false;
2685
2686         /* VF tunnel offloads is enabled by default in PF driver */
2687         adapter->vxlan.num_filters = 0;
2688         adapter->geneve.num_filters = 0;
2689         adapter->ipgre.num_filters = 0;
2690         if (is_vf) {
2691                 adapter->vxlan.enable = true;
2692                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2693                                              ETH_TUNNEL_FILTER_IVLAN;
2694                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2695                 adapter->geneve.enable = true;
2696                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2697                                               ETH_TUNNEL_FILTER_IVLAN;
2698                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2699                 adapter->ipgre.enable = true;
2700                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2701                                              ETH_TUNNEL_FILTER_IVLAN;
2702         } else {
2703                 adapter->vxlan.enable = false;
2704                 adapter->geneve.enable = false;
2705                 adapter->ipgre.enable = false;
2706         }
2707
2708         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2709                 adapter->primary_mac.addr_bytes[0],
2710                 adapter->primary_mac.addr_bytes[1],
2711                 adapter->primary_mac.addr_bytes[2],
2712                 adapter->primary_mac.addr_bytes[3],
2713                 adapter->primary_mac.addr_bytes[4],
2714                 adapter->primary_mac.addr_bytes[5]);
2715
2716         DP_INFO(edev, "Device initialized\n");
2717
2718         return 0;
2719
2720 err:
2721         if (do_once) {
2722                 qede_print_adapter_info(eth_dev);
2723                 do_once = false;
2724         }
2725         return rc;
2726 }
2727
2728 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2729 {
2730         return qede_common_dev_init(eth_dev, 1);
2731 }
2732
2733 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2734 {
2735         return qede_common_dev_init(eth_dev, 0);
2736 }
2737
2738 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2739 {
2740         struct qede_dev *qdev = eth_dev->data->dev_private;
2741         struct ecore_dev *edev = &qdev->edev;
2742
2743         PMD_INIT_FUNC_TRACE(edev);
2744
2745         /* only uninitialize in the primary process */
2746         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2747                 return 0;
2748
2749         /* safe to close dev here */
2750         qede_dev_close(eth_dev);
2751
2752         eth_dev->dev_ops = NULL;
2753         eth_dev->rx_pkt_burst = NULL;
2754         eth_dev->tx_pkt_burst = NULL;
2755
2756         return 0;
2757 }
2758
2759 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2760 {
2761         return qede_dev_common_uninit(eth_dev);
2762 }
2763
2764 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2765 {
2766         return qede_dev_common_uninit(eth_dev);
2767 }
2768
2769 static const struct rte_pci_id pci_id_qedevf_map[] = {
2770 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2771         {
2772                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2773         },
2774         {
2775                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2776         },
2777         {
2778                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2779         },
2780         {.vendor_id = 0,}
2781 };
2782
2783 static const struct rte_pci_id pci_id_qede_map[] = {
2784 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2785         {
2786                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2787         },
2788         {
2789                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2790         },
2791         {
2792                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2793         },
2794         {
2795                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2796         },
2797         {
2798                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2799         },
2800         {
2801                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2802         },
2803         {
2804                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2805         },
2806         {
2807                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2808         },
2809         {
2810                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2811         },
2812         {
2813                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2814         },
2815         {.vendor_id = 0,}
2816 };
2817
2818 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2819         struct rte_pci_device *pci_dev)
2820 {
2821         return rte_eth_dev_pci_generic_probe(pci_dev,
2822                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2823 }
2824
2825 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2826 {
2827         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2828 }
2829
2830 static struct rte_pci_driver rte_qedevf_pmd = {
2831         .id_table = pci_id_qedevf_map,
2832         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2833         .probe = qedevf_eth_dev_pci_probe,
2834         .remove = qedevf_eth_dev_pci_remove,
2835 };
2836
2837 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2838         struct rte_pci_device *pci_dev)
2839 {
2840         return rte_eth_dev_pci_generic_probe(pci_dev,
2841                 sizeof(struct qede_dev), qede_eth_dev_init);
2842 }
2843
2844 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2845 {
2846         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2847 }
2848
2849 static struct rte_pci_driver rte_qede_pmd = {
2850         .id_table = pci_id_qede_map,
2851         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2852         .probe = qede_eth_dev_pci_probe,
2853         .remove = qede_eth_dev_pci_remove,
2854 };
2855
2856 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2857 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2858 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2859 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2860 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2861 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2862 RTE_LOG_REGISTER(qede_logtype_init, pmd.net.qede.init, NOTICE);
2863 RTE_LOG_REGISTER(qede_logtype_driver, pmd.net.qede.driver, NOTICE);