drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler_intx(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347         u64 status;
 348
 349         /* Check if our device actually raised an interrupt */
 350         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 351         if (status & 0x1) {
 352                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 353
 354                 if (rte_intr_enable(eth_dev->intr_handle))
 355                         DP_ERR(edev, "rte_intr_enable failed\n");
 356         }
 357 }
 358
 359 static void
 360 qede_interrupt_handler(void *param)
 361 {
 362         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 363         struct qede_dev *qdev = eth_dev->data->dev_private;
 364         struct ecore_dev *edev = &qdev->edev;
 365
 366         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 367         if (rte_intr_enable(eth_dev->intr_handle))
 368                 DP_ERR(edev, "rte_intr_enable failed\n");
 369 }
 370
 371 static void
 372 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 373 {
 374         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 375         qdev->ops = qed_ops;
 376 }
 377
 378 static void qede_print_adapter_info(struct qede_dev *qdev)
 379 {
 380         struct ecore_dev *edev = &qdev->edev;
 381         struct qed_dev_info *info = &qdev->dev_info.common;
 382         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 383         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 384
 385         DP_INFO(edev, "*********************************\n");
 386         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 387         DP_INFO(edev, " Chip details : %s %c%d\n",
 388                   ECORE_IS_BB(edev) ? "BB" : "AH",
 389                   'A' + edev->chip_rev,
 390                   (int)edev->chip_metal);
 391         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 392                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 393         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 394                  ver_str, QEDE_PMD_VERSION);
 395         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 396         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 397
 398         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 399                  "%d.%d.%d.%d",
 400                 (info->mfw_rev >> 24) & 0xff,
 401                 (info->mfw_rev >> 16) & 0xff,
 402                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 403         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 404         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 405         DP_INFO(edev, "*********************************\n");
 406 }
 407
 408 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 409 {
 410         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 411         unsigned int i = 0, j = 0, qid;
 412         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 413         struct qede_tx_queue *txq;
 414
 415         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 416
 417         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 418                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 419         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 420                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 421
 422         for_each_rss(qid) {
 423                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 424                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 425                             sizeof(uint64_t));
 426                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 427                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 428                             sizeof(uint64_t));
 429                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 430                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 431                             sizeof(uint64_t));
 432
 433                 if (xstats)
 434                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 435                                 OSAL_MEMSET((((char *)
 436                                               (qdev->fp_array[qid].rxq)) +
 437                                              qede_rxq_xstats_strings[j].offset),
 438                                             0,
 439                                             sizeof(uint64_t));
 440
 441                 i++;
 442                 if (i == rxq_stat_cntrs)
 443                         break;
 444         }
 445
 446         i = 0;
 447
 448         for_each_tss(qid) {
 449                 txq = qdev->fp_array[qid].txq;
 450
 451                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 452                                 (((uint64_t)(uintptr_t)(txq)) +
 453                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 454                             sizeof(uint64_t));
 455
 456                 i++;
 457                 if (i == txq_stat_cntrs)
 458                         break;
 459         }
 460 }
 461
 462 static int
 463 qede_stop_vport(struct ecore_dev *edev)
 464 {
 465         struct ecore_hwfn *p_hwfn;
 466         uint8_t vport_id;
 467         int rc;
 468         int i;
 469
 470         vport_id = 0;
 471         for_each_hwfn(edev, i) {
 472                 p_hwfn = &edev->hwfns[i];
 473                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 474                                          vport_id);
 475                 if (rc != ECORE_SUCCESS) {
 476                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 477                         return rc;
 478                 }
 479         }
 480
 481         DP_INFO(edev, "vport stopped\n");
 482
 483         return 0;
 484 }
 485
 486 static int
 487 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 488 {
 489         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 490         struct ecore_sp_vport_start_params params;
 491         struct ecore_hwfn *p_hwfn;
 492         int rc;
 493         int i;
 494
 495         if (qdev->vport_started)
 496                 qede_stop_vport(edev);
 497
 498         memset(&params, 0, sizeof(params));
 499         params.vport_id = 0;
 500         params.mtu = mtu;
 501         /* @DPDK - Disable FW placement */
 502         params.zero_placement_offset = 1;
 503         for_each_hwfn(edev, i) {
 504                 p_hwfn = &edev->hwfns[i];
 505                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 506                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 507                 rc = ecore_sp_vport_start(p_hwfn, &params);
 508                 if (rc != ECORE_SUCCESS) {
 509                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 510                         return rc;
 511                 }
 512         }
 513         ecore_reset_vport_stats(edev);
 514         qdev->vport_started = true;
 515         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 516
 517         return 0;
 518 }
 519
 520 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 521 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 522
 523 /* Activate or deactivate vport via vport-update */
 524 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 525 {
 526         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 527         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 528         struct ecore_sp_vport_update_params params;
 529         struct ecore_hwfn *p_hwfn;
 530         uint8_t i;
 531         int rc = -1;
 532
 533         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 534         params.vport_id = 0;
 535         params.update_vport_active_rx_flg = 1;
 536         params.update_vport_active_tx_flg = 1;
 537         params.vport_active_rx_flg = flg;
 538         params.vport_active_tx_flg = flg;
 539         if (~qdev->enable_tx_switching & flg) {
 540                 params.update_tx_switching_flg = 1;
 541                 params.tx_switching_flg = !flg;
 542         }
 543         for_each_hwfn(edev, i) {
 544                 p_hwfn = &edev->hwfns[i];
 545                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 546                 rc = ecore_sp_vport_update(p_hwfn, &params,
 547                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 548                 if (rc != ECORE_SUCCESS) {
 549                         DP_ERR(edev, "Failed to update vport\n");
 550                         break;
 551                 }
 552         }
 553         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 554
 555         return rc;
 556 }
 557
 558 static void
 559 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 560                            uint16_t mtu, bool enable)
 561 {
 562         /* Enable LRO in split mode */
 563         sge_tpa_params->tpa_ipv4_en_flg = enable;
 564         sge_tpa_params->tpa_ipv6_en_flg = enable;
 565         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 566         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 567         /* set if tpa enable changes */
 568         sge_tpa_params->update_tpa_en_flg = 1;
 569         /* set if tpa parameters should be handled */
 570         sge_tpa_params->update_tpa_param_flg = enable;
 571
 572         sge_tpa_params->max_buffers_per_cqe = 20;
 573         /* Enable TPA in split mode. In this mode each TPA segment
 574          * starts on the new BD, so there is one BD per segment.
 575          */
 576         sge_tpa_params->tpa_pkt_split_flg = 1;
 577         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 578         sge_tpa_params->tpa_gro_consistent_flg = 0;
 579         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 580         sge_tpa_params->tpa_max_size = 0x7FFF;
 581         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 582         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 583 }
 584
 585 /* Enable/disable LRO via vport-update */
 586 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 587 {
 588         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 589         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 590         struct ecore_sp_vport_update_params params;
 591         struct ecore_sge_tpa_params tpa_params;
 592         struct ecore_hwfn *p_hwfn;
 593         int rc;
 594         int i;
 595
 596         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 597         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 598         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 599         params.vport_id = 0;
 600         params.sge_tpa_params = &tpa_params;
 601         for_each_hwfn(edev, i) {
 602                 p_hwfn = &edev->hwfns[i];
 603                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 604                 rc = ecore_sp_vport_update(p_hwfn, &params,
 605                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 606                 if (rc != ECORE_SUCCESS) {
 607                         DP_ERR(edev, "Failed to update LRO\n");
 608                         return -1;
 609                 }
 610         }
 611         qdev->enable_lro = flg;
 612         eth_dev->data->lro = flg;
 613
 614         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 615
 616         return 0;
 617 }
 618
 619 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 620 {
 621         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 622         ucast->is_rx_filter = true;
 623         ucast->is_tx_filter = true;
 624         /* ucast->assert_on_error = true; - For debug */
 625 }
 626
 627 static int
 628 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 629                              enum qed_filter_rx_mode_type type)
 630 {
 631         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 632         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 633         struct ecore_filter_accept_flags flags;
 634
 635         memset(&flags, 0, sizeof(flags));
 636
 637         flags.update_rx_mode_config = 1;
 638         flags.update_tx_mode_config = 1;
 639         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 640                 ECORE_ACCEPT_MCAST_MATCHED |
 641                 ECORE_ACCEPT_BCAST;
 642
 643         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 644                 ECORE_ACCEPT_MCAST_MATCHED |
 645                 ECORE_ACCEPT_BCAST;
 646
 647         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 648                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 649                 if (IS_VF(edev)) {
 650                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 651                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 652                 }
 653         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 654                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 655         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 656                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 657                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 658                         ECORE_ACCEPT_MCAST_UNMATCHED;
 659         }
 660
 661         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 662                         ECORE_SPQ_MODE_CB, NULL);
 663 }
 664
 665 static int
 666 qede_tunnel_update(struct qede_dev *qdev,
 667                    struct ecore_tunnel_info *tunn_info)
 668 {
 669         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 670         enum _ecore_status_t rc = ECORE_INVAL;
 671         struct ecore_hwfn *p_hwfn;
 672         struct ecore_ptt *p_ptt;
 673         int i;
 674
 675         for_each_hwfn(edev, i) {
 676                 p_hwfn = &edev->hwfns[i];
 677                 if (IS_PF(edev)) {
 678                         p_ptt = ecore_ptt_acquire(p_hwfn);
 679                         if (!p_ptt) {
 680                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 681                                 return -EAGAIN;
 682                         }
 683                 } else {
 684                         p_ptt = NULL;
 685                 }
 686
 687                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 688                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 689                 if (IS_PF(edev))
 690                         ecore_ptt_release(p_hwfn, p_ptt);
 691
 692                 if (rc != ECORE_SUCCESS)
 693                         break;
 694         }
 695
 696         return rc;
 697 }
 698
 699 static int
 700 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 701                   bool enable)
 702 {
 703         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 704         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 705         enum _ecore_status_t rc = ECORE_INVAL;
 706         struct ecore_tunnel_info tunn;
 707
 708         if (qdev->vxlan.enable == enable)
 709                 return ECORE_SUCCESS;
 710
 711         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 712         tunn.vxlan.b_update_mode = true;
 713         tunn.vxlan.b_mode_enabled = enable;
 714         tunn.b_update_rx_cls = true;
 715         tunn.b_update_tx_cls = true;
 716         tunn.vxlan.tun_cls = clss;
 717
 718         tunn.vxlan_port.b_update_port = true;
 719         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 720
 721         rc = qede_tunnel_update(qdev, &tunn);
 722         if (rc == ECORE_SUCCESS) {
 723                 qdev->vxlan.enable = enable;
 724                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 725                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 726                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 727         } else {
 728                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 729                        tunn.vxlan.tun_cls);
 730         }
 731
 732         return rc;
 733 }
 734
 735 static int
 736 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 737                   bool enable)
 738 {
 739         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 740         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 741         enum _ecore_status_t rc = ECORE_INVAL;
 742         struct ecore_tunnel_info tunn;
 743
 744         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 745         tunn.l2_geneve.b_update_mode = true;
 746         tunn.l2_geneve.b_mode_enabled = enable;
 747         tunn.ip_geneve.b_update_mode = true;
 748         tunn.ip_geneve.b_mode_enabled = enable;
 749         tunn.l2_geneve.tun_cls = clss;
 750         tunn.ip_geneve.tun_cls = clss;
 751         tunn.b_update_rx_cls = true;
 752         tunn.b_update_tx_cls = true;
 753
 754         tunn.geneve_port.b_update_port = true;
 755         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 756
 757         rc = qede_tunnel_update(qdev, &tunn);
 758         if (rc == ECORE_SUCCESS) {
 759                 qdev->geneve.enable = enable;
 760                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 761                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 762                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 763         } else {
 764                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 765                        clss);
 766         }
 767
 768         return rc;
 769 }
 770
 771 static int
 772 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 773                   bool enable)
 774 {
 775         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 776         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 777         enum _ecore_status_t rc = ECORE_INVAL;
 778         struct ecore_tunnel_info tunn;
 779
 780         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 781         tunn.ip_gre.b_update_mode = true;
 782         tunn.ip_gre.b_mode_enabled = enable;
 783         tunn.ip_gre.tun_cls = clss;
 784         tunn.ip_gre.tun_cls = clss;
 785         tunn.b_update_rx_cls = true;
 786         tunn.b_update_tx_cls = true;
 787
 788         rc = qede_tunnel_update(qdev, &tunn);
 789         if (rc == ECORE_SUCCESS) {
 790                 qdev->ipgre.enable = enable;
 791                 DP_INFO(edev, "IPGRE is %s\n",
 792                         enable ? "enabled" : "disabled");
 793         } else {
 794                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 795                        clss);
 796         }
 797
 798         return rc;
 799 }
 800
 801 static int
 802 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 803                  enum rte_eth_tunnel_type tunn_type, bool enable)
 804 {
 805         int rc = -EINVAL;
 806
 807         switch (tunn_type) {
 808         case RTE_TUNNEL_TYPE_VXLAN:
 809                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 810                 break;
 811         case RTE_TUNNEL_TYPE_GENEVE:
 812                 rc = qede_geneve_enable(eth_dev, clss, enable);
 813                 break;
 814         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 815                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 816                 break;
 817         default:
 818                 rc = -EINVAL;
 819                 break;
 820         }
 821
 822         return rc;
 823 }
 824
 825 static int
 826 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 827                   bool add)
 828 {
 829         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 830         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 831         struct qede_ucast_entry *tmp = NULL;
 832         struct qede_ucast_entry *u;
 833         struct ether_addr *mac_addr;
 834
 835         mac_addr  = (struct ether_addr *)ucast->mac;
 836         if (add) {
 837                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 838                         if ((memcmp(mac_addr, &tmp->mac,
 839                                     ETHER_ADDR_LEN) == 0) &&
 840                              ucast->vni == tmp->vni &&
 841                              ucast->vlan == tmp->vlan) {
 842                                 DP_INFO(edev, "Unicast MAC is already added"
 843                                         " with vlan = %u, vni = %u\n",
 844                                         ucast->vlan,  ucast->vni);
 845                                         return 0;
 846                         }
 847                 }
 848                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 849                                RTE_CACHE_LINE_SIZE);
 850                 if (!u) {
 851                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 852                         return -ENOMEM;
 853                 }
 854                 ether_addr_copy(mac_addr, &u->mac);
 855                 u->vlan = ucast->vlan;
 856                 u->vni = ucast->vni;
 857                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 858                 qdev->num_uc_addr++;
 859         } else {
 860                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 861                         if ((memcmp(mac_addr, &tmp->mac,
 862                                     ETHER_ADDR_LEN) == 0) &&
 863                             ucast->vlan == tmp->vlan      &&
 864                             ucast->vni == tmp->vni)
 865                         break;
 866                 }
 867                 if (tmp == NULL) {
 868                         DP_INFO(edev, "Unicast MAC is not found\n");
 869                         return -EINVAL;
 870                 }
 871                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 872                 qdev->num_uc_addr--;
 873         }
 874
 875         return 0;
 876 }
 877
 878 static int
 879 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 880                        uint32_t mc_addrs_num)
 881 {
 882         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 883         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 884         struct ecore_filter_mcast mcast;
 885         struct qede_mcast_entry *m = NULL;
 886         uint8_t i;
 887         int rc;
 888
 889         for (i = 0; i < mc_addrs_num; i++) {
 890                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 891                                RTE_CACHE_LINE_SIZE);
 892                 if (!m) {
 893                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 894                         return -ENOMEM;
 895                 }
 896                 ether_addr_copy(&mc_addrs[i], &m->mac);
 897                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 898         }
 899         memset(&mcast, 0, sizeof(mcast));
 900         mcast.num_mc_addrs = mc_addrs_num;
 901         mcast.opcode = ECORE_FILTER_ADD;
 902         for (i = 0; i < mc_addrs_num; i++)
 903                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 904                                                         &mcast.mac[i]);
 905         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 906         if (rc != ECORE_SUCCESS) {
 907                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 908                 return -1;
 909         }
 910
 911         return 0;
 912 }
 913
 914 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 915 {
 916         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 917         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 918         struct qede_mcast_entry *tmp = NULL;
 919         struct ecore_filter_mcast mcast;
 920         int j;
 921         int rc;
 922
 923         memset(&mcast, 0, sizeof(mcast));
 924         mcast.num_mc_addrs = qdev->num_mc_addr;
 925         mcast.opcode = ECORE_FILTER_REMOVE;
 926         j = 0;
 927         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 928                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 929                 j++;
 930         }
 931         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 932         if (rc != ECORE_SUCCESS) {
 933                 DP_ERR(edev, "Failed to delete multicast filter\n");
 934                 return -1;
 935         }
 936         /* Init the list */
 937         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 938                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 939                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 940         }
 941         SLIST_INIT(&qdev->mc_list_head);
 942
 943         return 0;
 944 }
 945
 946 static enum _ecore_status_t
 947 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 948                  bool add)
 949 {
 950         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 951         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 952         enum _ecore_status_t rc = ECORE_INVAL;
 953
 954         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 955                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 956                               " Please enable promisc mode\n");
 957                         return ECORE_INVAL;
 958         }
 959
 960         rc = qede_ucast_filter(eth_dev, ucast, add);
 961         if (rc == 0)
 962                 rc = ecore_filter_ucast_cmd(edev, ucast,
 963                                             ECORE_SPQ_MODE_CB, NULL);
 964         if (rc != ECORE_SUCCESS)
 965                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 966                        rc, add);
 967
 968         return rc;
 969 }
 970
 971 static int
 972 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 973                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 974 {
 975         struct ecore_filter_ucast ucast;
 976         int re;
 977
 978         if (!is_valid_assigned_ether_addr(mac_addr))
 979                 return -EINVAL;
 980
 981         qede_set_ucast_cmn_params(&ucast);
 982         ucast.opcode = ECORE_FILTER_ADD;
 983         ucast.type = ECORE_FILTER_MAC;
 984         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 985         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 986         return re;
 987 }
 988
 989 static void
 990 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 991 {
 992         struct qede_dev *qdev = eth_dev->data->dev_private;
 993         struct ecore_dev *edev = &qdev->edev;
 994         struct ecore_filter_ucast ucast;
 995
 996         PMD_INIT_FUNC_TRACE(edev);
 997
 998         if (index >= qdev->dev_info.num_mac_filters) {
 999                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1000                        index, qdev->dev_info.num_mac_filters);
1001                 return;
1002         }
1003
1004         if (!is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
1005                 return;
1006
1007         qede_set_ucast_cmn_params(&ucast);
1008         ucast.opcode = ECORE_FILTER_REMOVE;
1009         ucast.type = ECORE_FILTER_MAC;
1010
1011         /* Use the index maintained by rte */
1012         ether_addr_copy(&eth_dev->data->mac_addrs[index],
1013                         (struct ether_addr *)&ucast.mac);
1014
1015         qede_mac_int_ops(eth_dev, &ucast, false);
1016 }
1017
1018 static int
1019 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1020 {
1021         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1022         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1023
1024         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1025                                                mac_addr->addr_bytes)) {
1026                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1027                 return -EPERM;
1028         }
1029
1030         qede_mac_addr_remove(eth_dev, 0);
1031
1032         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1033 }
1034
1035 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1036 {
1037         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1038         struct ecore_sp_vport_update_params params;
1039         struct ecore_hwfn *p_hwfn;
1040         uint8_t i;
1041         int rc;
1042
1043         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1044         params.vport_id = 0;
1045         params.update_accept_any_vlan_flg = 1;
1046         params.accept_any_vlan = flg;
1047         for_each_hwfn(edev, i) {
1048                 p_hwfn = &edev->hwfns[i];
1049                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1050                 rc = ecore_sp_vport_update(p_hwfn, &params,
1051                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1052                 if (rc != ECORE_SUCCESS) {
1053                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1054                         return;
1055                 }
1056         }
1057
1058         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1059 }
1060
1061 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1062 {
1063         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1064         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1065         struct ecore_sp_vport_update_params params;
1066         struct ecore_hwfn *p_hwfn;
1067         uint8_t i;
1068         int rc;
1069
1070         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1071         params.vport_id = 0;
1072         params.update_inner_vlan_removal_flg = 1;
1073         params.inner_vlan_removal_flg = flg;
1074         for_each_hwfn(edev, i) {
1075                 p_hwfn = &edev->hwfns[i];
1076                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1077                 rc = ecore_sp_vport_update(p_hwfn, &params,
1078                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1079                 if (rc != ECORE_SUCCESS) {
1080                         DP_ERR(edev, "Failed to update vport\n");
1081                         return -1;
1082                 }
1083         }
1084
1085         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1086         return 0;
1087 }
1088
1089 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1090                                 uint16_t vlan_id, int on)
1091 {
1092         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1093         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1094         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1095         struct qede_vlan_entry *tmp = NULL;
1096         struct qede_vlan_entry *vlan;
1097         struct ecore_filter_ucast ucast;
1098         int rc;
1099
1100         if (on) {
1101                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1102                         DP_ERR(edev, "Reached max VLAN filter limit"
1103                                       " enabling accept_any_vlan\n");
1104                         qede_config_accept_any_vlan(qdev, true);
1105                         return 0;
1106                 }
1107
1108                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1109                         if (tmp->vid == vlan_id) {
1110                                 DP_INFO(edev, "VLAN %u already configured\n",
1111                                         vlan_id);
1112                                 return 0;
1113                         }
1114                 }
1115
1116                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1117                                   RTE_CACHE_LINE_SIZE);
1118
1119                 if (!vlan) {
1120                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1121                         return -ENOMEM;
1122                 }
1123
1124                 qede_set_ucast_cmn_params(&ucast);
1125                 ucast.opcode = ECORE_FILTER_ADD;
1126                 ucast.type = ECORE_FILTER_VLAN;
1127                 ucast.vlan = vlan_id;
1128                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1129                                             NULL);
1130                 if (rc != 0) {
1131                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1132                                rc);
1133                         rte_free(vlan);
1134                 } else {
1135                         vlan->vid = vlan_id;
1136                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1137                         qdev->configured_vlans++;
1138                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1139                                 vlan_id, qdev->configured_vlans);
1140                 }
1141         } else {
1142                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1143                         if (tmp->vid == vlan_id)
1144                                 break;
1145                 }
1146
1147                 if (!tmp) {
1148                         if (qdev->configured_vlans == 0) {
1149                                 DP_INFO(edev,
1150                                         "No VLAN filters configured yet\n");
1151                                 return 0;
1152                         }
1153
1154                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1155                         return -EINVAL;
1156                 }
1157
1158                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1159
1160                 qede_set_ucast_cmn_params(&ucast);
1161                 ucast.opcode = ECORE_FILTER_REMOVE;
1162                 ucast.type = ECORE_FILTER_VLAN;
1163                 ucast.vlan = vlan_id;
1164                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1165                                             NULL);
1166                 if (rc != 0) {
1167                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1168                                vlan_id, rc);
1169                 } else {
1170                         qdev->configured_vlans--;
1171                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1172                                 vlan_id, qdev->configured_vlans);
1173                 }
1174         }
1175
1176         return rc;
1177 }
1178
1179 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1180 {
1181         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1182         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1183         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1184
1185         if (mask & ETH_VLAN_STRIP_MASK) {
1186                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1187                         (void)qede_vlan_stripping(eth_dev, 1);
1188                 else
1189                         (void)qede_vlan_stripping(eth_dev, 0);
1190         }
1191
1192         if (mask & ETH_VLAN_FILTER_MASK) {
1193                 /* VLAN filtering kicks in when a VLAN is added */
1194                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1195                         qede_vlan_filter_set(eth_dev, 0, 1);
1196                 } else {
1197                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1198                                 DP_ERR(edev,
1199                                   " Please remove existing VLAN filters"
1200                                   " before disabling VLAN filtering\n");
1201                                 /* Signal app that VLAN filtering is still
1202                                  * enabled
1203                                  */
1204                                 eth_dev->data->dev_conf.rxmode.offloads |=
1205                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1206                         } else {
1207                                 qede_vlan_filter_set(eth_dev, 0, 0);
1208                         }
1209                 }
1210         }
1211
1212         if (mask & ETH_VLAN_EXTEND_MASK)
1213                 DP_ERR(edev, "Extend VLAN not supported\n");
1214
1215         qdev->vlan_offload_mask = mask;
1216
1217         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1218
1219         return 0;
1220 }
1221
1222 static void qede_prandom_bytes(uint32_t *buff)
1223 {
1224         uint8_t i;
1225
1226         srand((unsigned int)time(NULL));
1227         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1228                 buff[i] = rand();
1229 }
1230
1231 int qede_config_rss(struct rte_eth_dev *eth_dev)
1232 {
1233         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1234         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1235         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1236         struct rte_eth_rss_reta_entry64 reta_conf[2];
1237         struct rte_eth_rss_conf rss_conf;
1238         uint32_t i, id, pos, q;
1239
1240         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1241         if (!rss_conf.rss_key) {
1242                 DP_INFO(edev, "Applying driver default key\n");
1243                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1244                 qede_prandom_bytes(&def_rss_key[0]);
1245                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1246         }
1247
1248         /* Configure RSS hash */
1249         if (qede_rss_hash_update(eth_dev, &rss_conf))
1250                 return -EINVAL;
1251
1252         /* Configure default RETA */
1253         memset(reta_conf, 0, sizeof(reta_conf));
1254         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1255                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1256
1257         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1258                 id = i / RTE_RETA_GROUP_SIZE;
1259                 pos = i % RTE_RETA_GROUP_SIZE;
1260                 q = i % QEDE_RSS_COUNT(qdev);
1261                 reta_conf[id].reta[pos] = q;
1262         }
1263         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1264                                  ECORE_RSS_IND_TABLE_SIZE))
1265                 return -EINVAL;
1266
1267         return 0;
1268 }
1269
1270 static void qede_fastpath_start(struct ecore_dev *edev)
1271 {
1272         struct ecore_hwfn *p_hwfn;
1273         int i;
1274
1275         for_each_hwfn(edev, i) {
1276                 p_hwfn = &edev->hwfns[i];
1277                 ecore_hw_start_fastpath(p_hwfn);
1278         }
1279 }
1280
1281 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1282 {
1283         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1284         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1285         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1286
1287         PMD_INIT_FUNC_TRACE(edev);
1288
1289         /* Update MTU only if it has changed */
1290         if (eth_dev->data->mtu != qdev->mtu) {
1291                 if (qede_update_mtu(eth_dev, qdev->mtu))
1292                         goto err;
1293         }
1294
1295         /* Configure TPA parameters */
1296         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1297                 if (qede_enable_tpa(eth_dev, true))
1298                         return -EINVAL;
1299                 /* Enable scatter mode for LRO */
1300                 if (!eth_dev->data->scattered_rx)
1301                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1302         }
1303
1304         /* Start queues */
1305         if (qede_start_queues(eth_dev))
1306                 goto err;
1307
1308         if (IS_PF(edev))
1309                 qede_reset_queue_stats(qdev, true);
1310
1311         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1312          * enabling RSS. Hence RSS configuration is deferred upto this point.
1313          * Also, we would like to retain similar behavior in PF case, so we
1314          * don't do PF/VF specific check here.
1315          */
1316         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1317                 if (qede_config_rss(eth_dev))
1318                         goto err;
1319
1320         /* Enable vport*/
1321         if (qede_activate_vport(eth_dev, true))
1322                 goto err;
1323
1324         /* Update link status */
1325         qede_link_update(eth_dev, 0);
1326
1327         /* Start/resume traffic */
1328         qede_fastpath_start(edev);
1329
1330         DP_INFO(edev, "Device started\n");
1331
1332         return 0;
1333 err:
1334         DP_ERR(edev, "Device start fails\n");
1335         return -1; /* common error code is < 0 */
1336 }
1337
1338 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1339 {
1340         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1341         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1342
1343         PMD_INIT_FUNC_TRACE(edev);
1344
1345         /* Disable vport */
1346         if (qede_activate_vport(eth_dev, false))
1347                 return;
1348
1349         if (qdev->enable_lro)
1350                 qede_enable_tpa(eth_dev, false);
1351
1352         /* Stop queues */
1353         qede_stop_queues(eth_dev);
1354
1355         /* Disable traffic */
1356         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1357
1358         DP_INFO(edev, "Device is stopped\n");
1359 }
1360
1361 const char *valid_args[] = {
1362         QEDE_NPAR_TX_SWITCHING,
1363         QEDE_VF_TX_SWITCHING,
1364         NULL,
1365 };
1366
1367 static int qede_args_check(const char *key, const char *val, void *opaque)
1368 {
1369         unsigned long tmp;
1370         int ret = 0;
1371         struct rte_eth_dev *eth_dev = opaque;
1372         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1373         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1374
1375         errno = 0;
1376         tmp = strtoul(val, NULL, 0);
1377         if (errno) {
1378                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1379                 return errno;
1380         }
1381
1382         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1383             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1384                 qdev->enable_tx_switching = !!tmp;
1385                 DP_INFO(edev, "Disabling %s tx-switching\n",
1386                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1387                         "VF" : "NPAR");
1388         }
1389
1390         return ret;
1391 }
1392
1393 static int qede_args(struct rte_eth_dev *eth_dev)
1394 {
1395         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1396         struct rte_kvargs *kvlist;
1397         struct rte_devargs *devargs;
1398         int ret;
1399         int i;
1400
1401         devargs = pci_dev->device.devargs;
1402         if (!devargs)
1403                 return 0; /* return success */
1404
1405         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1406         if (kvlist == NULL)
1407                 return -EINVAL;
1408
1409          /* Process parameters. */
1410         for (i = 0; (valid_args[i] != NULL); ++i) {
1411                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1412                         ret = rte_kvargs_process(kvlist, valid_args[i],
1413                                                  qede_args_check, eth_dev);
1414                         if (ret != ECORE_SUCCESS) {
1415                                 rte_kvargs_free(kvlist);
1416                                 return ret;
1417                         }
1418                 }
1419         }
1420         rte_kvargs_free(kvlist);
1421
1422         return 0;
1423 }
1424
1425 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1426 {
1427         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1428         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1429         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1430         int ret;
1431
1432         PMD_INIT_FUNC_TRACE(edev);
1433
1434         /* Check requirements for 100G mode */
1435         if (ECORE_IS_CMT(edev)) {
1436                 if (eth_dev->data->nb_rx_queues < 2 ||
1437                     eth_dev->data->nb_tx_queues < 2) {
1438                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1439                         return -EINVAL;
1440                 }
1441
1442                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1443                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1444                         DP_ERR(edev,
1445                                "100G mode needs even no. of RX/TX queues\n");
1446                         return -EINVAL;
1447                 }
1448         }
1449
1450         /* We need to have min 1 RX queue.There is no min check in
1451          * rte_eth_dev_configure(), so we are checking it here.
1452          */
1453         if (eth_dev->data->nb_rx_queues == 0) {
1454                 DP_ERR(edev, "Minimum one RX queue is required\n");
1455                 return -EINVAL;
1456         }
1457
1458         /* Enable Tx switching by default */
1459         qdev->enable_tx_switching = 1;
1460
1461         /* Parse devargs and fix up rxmode */
1462         if (qede_args(eth_dev))
1463                 DP_NOTICE(edev, false,
1464                           "Invalid devargs supplied, requested change will not take effect\n");
1465
1466         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1467               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1468                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1469                 return -ENOTSUP;
1470         }
1471         /* Flow director mode check */
1472         if (qede_check_fdir_support(eth_dev))
1473                 return -ENOTSUP;
1474
1475         qede_dealloc_fp_resc(eth_dev);
1476         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1477         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1478         if (qede_alloc_fp_resc(qdev))
1479                 return -ENOMEM;
1480
1481         /* If jumbo enabled adjust MTU */
1482         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1483                 eth_dev->data->mtu =
1484                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1485                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1486
1487         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1488                 eth_dev->data->scattered_rx = 1;
1489
1490         if (qede_start_vport(qdev, eth_dev->data->mtu))
1491                 return -1;
1492
1493         qdev->mtu = eth_dev->data->mtu;
1494
1495         /* Enable VLAN offloads by default */
1496         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1497                                              ETH_VLAN_FILTER_MASK);
1498         if (ret)
1499                 return ret;
1500
1501         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1502                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1503
1504         return 0;
1505 }
1506
1507 /* Info about HW descriptor ring limitations */
1508 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1509         .nb_max = 0x8000, /* 32K */
1510         .nb_min = 128,
1511         .nb_align = 128 /* lowest common multiple */
1512 };
1513
1514 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1515         .nb_max = 0x8000, /* 32K */
1516         .nb_min = 256,
1517         .nb_align = 256,
1518         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1519         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1520 };
1521
1522 static void
1523 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1524                   struct rte_eth_dev_info *dev_info)
1525 {
1526         struct qede_dev *qdev = eth_dev->data->dev_private;
1527         struct ecore_dev *edev = &qdev->edev;
1528         struct qed_link_output link;
1529         uint32_t speed_cap = 0;
1530
1531         PMD_INIT_FUNC_TRACE(edev);
1532
1533         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1534         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1535         dev_info->rx_desc_lim = qede_rx_desc_lim;
1536         dev_info->tx_desc_lim = qede_tx_desc_lim;
1537
1538         if (IS_PF(edev))
1539                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1540                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1541         else
1542                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1543                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1544         dev_info->max_tx_queues = dev_info->max_rx_queues;
1545
1546         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1547         dev_info->max_vfs = 0;
1548         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1549         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1550         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1551         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1552                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1553                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1554                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1555                                      DEV_RX_OFFLOAD_TCP_LRO     |
1556                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1557                                      DEV_RX_OFFLOAD_SCATTER     |
1558                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1559                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1560                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1561         dev_info->rx_queue_offload_capa = 0;
1562
1563         /* TX offloads are on a per-packet basis, so it is applicable
1564          * to both at port and queue levels.
1565          */
1566         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1567                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1568                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1569                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1570                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1571                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1572                                      DEV_TX_OFFLOAD_TCP_TSO     |
1573                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1574                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1575         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1576
1577         dev_info->default_txconf = (struct rte_eth_txconf) {
1578                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1579         };
1580
1581         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1582                 /* Packets are always dropped if no descriptors are available */
1583                 .rx_drop_en = 1,
1584                 .offloads = 0,
1585         };
1586
1587         memset(&link, 0, sizeof(struct qed_link_output));
1588         qdev->ops->common->get_link(edev, &link);
1589         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1590                 speed_cap |= ETH_LINK_SPEED_1G;
1591         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1592                 speed_cap |= ETH_LINK_SPEED_10G;
1593         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1594                 speed_cap |= ETH_LINK_SPEED_25G;
1595         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1596                 speed_cap |= ETH_LINK_SPEED_40G;
1597         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1598                 speed_cap |= ETH_LINK_SPEED_50G;
1599         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1600                 speed_cap |= ETH_LINK_SPEED_100G;
1601         dev_info->speed_capa = speed_cap;
1602 }
1603
1604 /* return 0 means link status changed, -1 means not changed */
1605 int
1606 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1607 {
1608         struct qede_dev *qdev = eth_dev->data->dev_private;
1609         struct ecore_dev *edev = &qdev->edev;
1610         struct qed_link_output q_link;
1611         struct rte_eth_link link;
1612         uint16_t link_duplex;
1613
1614         memset(&q_link, 0, sizeof(q_link));
1615         memset(&link, 0, sizeof(link));
1616
1617         qdev->ops->common->get_link(edev, &q_link);
1618
1619         /* Link Speed */
1620         link.link_speed = q_link.speed;
1621
1622         /* Link Mode */
1623         switch (q_link.duplex) {
1624         case QEDE_DUPLEX_HALF:
1625                 link_duplex = ETH_LINK_HALF_DUPLEX;
1626                 break;
1627         case QEDE_DUPLEX_FULL:
1628                 link_duplex = ETH_LINK_FULL_DUPLEX;
1629                 break;
1630         case QEDE_DUPLEX_UNKNOWN:
1631         default:
1632                 link_duplex = -1;
1633         }
1634         link.link_duplex = link_duplex;
1635
1636         /* Link Status */
1637         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1638
1639         /* AN */
1640         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1641                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1642
1643         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1644                 link.link_speed, link.link_duplex,
1645                 link.link_autoneg, link.link_status);
1646
1647         return rte_eth_linkstatus_set(eth_dev, &link);
1648 }
1649
1650 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1651 {
1652 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1653         struct qede_dev *qdev = eth_dev->data->dev_private;
1654         struct ecore_dev *edev = &qdev->edev;
1655
1656         PMD_INIT_FUNC_TRACE(edev);
1657 #endif
1658
1659         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1660
1661         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1662                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1663
1664         qed_configure_filter_rx_mode(eth_dev, type);
1665 }
1666
1667 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1668 {
1669 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1670         struct qede_dev *qdev = eth_dev->data->dev_private;
1671         struct ecore_dev *edev = &qdev->edev;
1672
1673         PMD_INIT_FUNC_TRACE(edev);
1674 #endif
1675
1676         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1677                 qed_configure_filter_rx_mode(eth_dev,
1678                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1679         else
1680                 qed_configure_filter_rx_mode(eth_dev,
1681                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1682 }
1683
1684 static void qede_poll_sp_sb_cb(void *param)
1685 {
1686         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1687         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1688         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1689         int rc;
1690
1691         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1692         qede_interrupt_action(&edev->hwfns[1]);
1693
1694         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1695                                qede_poll_sp_sb_cb,
1696                                (void *)eth_dev);
1697         if (rc != 0) {
1698                 DP_ERR(edev, "Unable to start periodic"
1699                              " timer rc %d\n", rc);
1700                 assert(false && "Unable to start periodic timer");
1701         }
1702 }
1703
1704 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1705 {
1706         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1707         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1708         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1709
1710         PMD_INIT_FUNC_TRACE(edev);
1711
1712         /* dev_stop() shall cleanup fp resources in hw but without releasing
1713          * dma memories and sw structures so that dev_start() can be called
1714          * by the app without reconfiguration. However, in dev_close() we
1715          * can release all the resources and device can be brought up newly
1716          */
1717         if (eth_dev->data->dev_started)
1718                 qede_dev_stop(eth_dev);
1719
1720         qede_stop_vport(edev);
1721         qdev->vport_started = false;
1722         qede_fdir_dealloc_resc(eth_dev);
1723         qede_dealloc_fp_resc(eth_dev);
1724
1725         eth_dev->data->nb_rx_queues = 0;
1726         eth_dev->data->nb_tx_queues = 0;
1727
1728         /* Bring the link down */
1729         qede_dev_set_link_state(eth_dev, false);
1730         qdev->ops->common->slowpath_stop(edev);
1731         qdev->ops->common->remove(edev);
1732         rte_intr_disable(&pci_dev->intr_handle);
1733         rte_intr_callback_unregister(&pci_dev->intr_handle,
1734                                      qede_interrupt_handler, (void *)eth_dev);
1735         if (ECORE_IS_CMT(edev))
1736                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1737 }
1738
1739 static int
1740 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1741 {
1742         struct qede_dev *qdev = eth_dev->data->dev_private;
1743         struct ecore_dev *edev = &qdev->edev;
1744         struct ecore_eth_stats stats;
1745         unsigned int i = 0, j = 0, qid;
1746         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1747         struct qede_tx_queue *txq;
1748
1749         ecore_get_vport_stats(edev, &stats);
1750
1751         /* RX Stats */
1752         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1753             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1754
1755         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1756             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1757
1758         eth_stats->ierrors = stats.common.rx_crc_errors +
1759             stats.common.rx_align_errors +
1760             stats.common.rx_carrier_errors +
1761             stats.common.rx_oversize_packets +
1762             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1763
1764         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1765
1766         eth_stats->imissed = stats.common.mftag_filter_discards +
1767             stats.common.mac_filter_discards +
1768             stats.common.no_buff_discards +
1769             stats.common.brb_truncates + stats.common.brb_discards;
1770
1771         /* TX stats */
1772         eth_stats->opackets = stats.common.tx_ucast_pkts +
1773             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1774
1775         eth_stats->obytes = stats.common.tx_ucast_bytes +
1776             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1777
1778         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1779
1780         /* Queue stats */
1781         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1782                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1783         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1784                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1785         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1786             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1787                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1788                        "Not all the queue stats will be displayed. Set"
1789                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1790                        " appropriately and retry.\n");
1791
1792         for_each_rss(qid) {
1793                 eth_stats->q_ipackets[i] =
1794                         *(uint64_t *)(
1795                                 ((char *)(qdev->fp_array[qid].rxq)) +
1796                                 offsetof(struct qede_rx_queue,
1797                                 rcv_pkts));
1798                 eth_stats->q_errors[i] =
1799                         *(uint64_t *)(
1800                                 ((char *)(qdev->fp_array[qid].rxq)) +
1801                                 offsetof(struct qede_rx_queue,
1802                                 rx_hw_errors)) +
1803                         *(uint64_t *)(
1804                                 ((char *)(qdev->fp_array[qid].rxq)) +
1805                                 offsetof(struct qede_rx_queue,
1806                                 rx_alloc_errors));
1807                 i++;
1808                 if (i == rxq_stat_cntrs)
1809                         break;
1810         }
1811
1812         for_each_tss(qid) {
1813                 txq = qdev->fp_array[qid].txq;
1814                 eth_stats->q_opackets[j] =
1815                         *((uint64_t *)(uintptr_t)
1816                                 (((uint64_t)(uintptr_t)(txq)) +
1817                                  offsetof(struct qede_tx_queue,
1818                                           xmit_pkts)));
1819                 j++;
1820                 if (j == txq_stat_cntrs)
1821                         break;
1822         }
1823
1824         return 0;
1825 }
1826
1827 static unsigned
1828 qede_get_xstats_count(struct qede_dev *qdev) {
1829         if (ECORE_IS_BB(&qdev->edev))
1830                 return RTE_DIM(qede_xstats_strings) +
1831                        RTE_DIM(qede_bb_xstats_strings) +
1832                        (RTE_DIM(qede_rxq_xstats_strings) *
1833                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1834                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1835         else
1836                 return RTE_DIM(qede_xstats_strings) +
1837                        RTE_DIM(qede_ah_xstats_strings) +
1838                        (RTE_DIM(qede_rxq_xstats_strings) *
1839                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1840                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1841 }
1842
1843 static int
1844 qede_get_xstats_names(struct rte_eth_dev *dev,
1845                       struct rte_eth_xstat_name *xstats_names,
1846                       __rte_unused unsigned int limit)
1847 {
1848         struct qede_dev *qdev = dev->data->dev_private;
1849         struct ecore_dev *edev = &qdev->edev;
1850         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1851         unsigned int i, qid, stat_idx = 0;
1852         unsigned int rxq_stat_cntrs;
1853
1854         if (xstats_names != NULL) {
1855                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1856                         snprintf(xstats_names[stat_idx].name,
1857                                 sizeof(xstats_names[stat_idx].name),
1858                                 "%s",
1859                                 qede_xstats_strings[i].name);
1860                         stat_idx++;
1861                 }
1862
1863                 if (ECORE_IS_BB(edev)) {
1864                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1865                                 snprintf(xstats_names[stat_idx].name,
1866                                         sizeof(xstats_names[stat_idx].name),
1867                                         "%s",
1868                                         qede_bb_xstats_strings[i].name);
1869                                 stat_idx++;
1870                         }
1871                 } else {
1872                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1873                                 snprintf(xstats_names[stat_idx].name,
1874                                         sizeof(xstats_names[stat_idx].name),
1875                                         "%s",
1876                                         qede_ah_xstats_strings[i].name);
1877                                 stat_idx++;
1878                         }
1879                 }
1880
1881                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1882                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1883                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1884                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1885                                 snprintf(xstats_names[stat_idx].name,
1886                                         sizeof(xstats_names[stat_idx].name),
1887                                         "%.4s%d%s",
1888                                         qede_rxq_xstats_strings[i].name, qid,
1889                                         qede_rxq_xstats_strings[i].name + 4);
1890                                 stat_idx++;
1891                         }
1892                 }
1893         }
1894
1895         return stat_cnt;
1896 }
1897
1898 static int
1899 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1900                 unsigned int n)
1901 {
1902         struct qede_dev *qdev = dev->data->dev_private;
1903         struct ecore_dev *edev = &qdev->edev;
1904         struct ecore_eth_stats stats;
1905         const unsigned int num = qede_get_xstats_count(qdev);
1906         unsigned int i, qid, stat_idx = 0;
1907         unsigned int rxq_stat_cntrs;
1908
1909         if (n < num)
1910                 return num;
1911
1912         ecore_get_vport_stats(edev, &stats);
1913
1914         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1915                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1916                                              qede_xstats_strings[i].offset);
1917                 xstats[stat_idx].id = stat_idx;
1918                 stat_idx++;
1919         }
1920
1921         if (ECORE_IS_BB(edev)) {
1922                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1923                         xstats[stat_idx].value =
1924                                         *(uint64_t *)(((char *)&stats) +
1925                                         qede_bb_xstats_strings[i].offset);
1926                         xstats[stat_idx].id = stat_idx;
1927                         stat_idx++;
1928                 }
1929         } else {
1930                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1931                         xstats[stat_idx].value =
1932                                         *(uint64_t *)(((char *)&stats) +
1933                                         qede_ah_xstats_strings[i].offset);
1934                         xstats[stat_idx].id = stat_idx;
1935                         stat_idx++;
1936                 }
1937         }
1938
1939         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1940                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1941         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1942                 for_each_rss(qid) {
1943                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1944                                 xstats[stat_idx].value = *(uint64_t *)(
1945                                         ((char *)(qdev->fp_array[qid].rxq)) +
1946                                          qede_rxq_xstats_strings[i].offset);
1947                                 xstats[stat_idx].id = stat_idx;
1948                                 stat_idx++;
1949                         }
1950                 }
1951         }
1952
1953         return stat_idx;
1954 }
1955
1956 static void
1957 qede_reset_xstats(struct rte_eth_dev *dev)
1958 {
1959         struct qede_dev *qdev = dev->data->dev_private;
1960         struct ecore_dev *edev = &qdev->edev;
1961
1962         ecore_reset_vport_stats(edev);
1963         qede_reset_queue_stats(qdev, true);
1964 }
1965
1966 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1967 {
1968         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1969         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1970         struct qed_link_params link_params;
1971         int rc;
1972
1973         DP_INFO(edev, "setting link state %d\n", link_up);
1974         memset(&link_params, 0, sizeof(link_params));
1975         link_params.link_up = link_up;
1976         rc = qdev->ops->common->set_link(edev, &link_params);
1977         if (rc != ECORE_SUCCESS)
1978                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1979
1980         return rc;
1981 }
1982
1983 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1984 {
1985         return qede_dev_set_link_state(eth_dev, true);
1986 }
1987
1988 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1989 {
1990         return qede_dev_set_link_state(eth_dev, false);
1991 }
1992
1993 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1994 {
1995         struct qede_dev *qdev = eth_dev->data->dev_private;
1996         struct ecore_dev *edev = &qdev->edev;
1997
1998         ecore_reset_vport_stats(edev);
1999         qede_reset_queue_stats(qdev, false);
2000 }
2001
2002 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2003 {
2004         enum qed_filter_rx_mode_type type =
2005             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2006
2007         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2008                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2009
2010         qed_configure_filter_rx_mode(eth_dev, type);
2011 }
2012
2013 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2014 {
2015         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2016                 qed_configure_filter_rx_mode(eth_dev,
2017                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2018         else
2019                 qed_configure_filter_rx_mode(eth_dev,
2020                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2021 }
2022
2023 static int
2024 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2025                       uint32_t mc_addrs_num)
2026 {
2027         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2028         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2029         uint8_t i;
2030
2031         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2032                 DP_ERR(edev, "Reached max multicast filters limit,"
2033                              "Please enable multicast promisc mode\n");
2034                 return -ENOSPC;
2035         }
2036
2037         for (i = 0; i < mc_addrs_num; i++) {
2038                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2039                         DP_ERR(edev, "Not a valid multicast MAC\n");
2040                         return -EINVAL;
2041                 }
2042         }
2043
2044         /* Flush all existing entries */
2045         if (qede_del_mcast_filters(eth_dev))
2046                 return -1;
2047
2048         /* Set new mcast list */
2049         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2050 }
2051
2052 /* Update MTU via vport-update without doing port restart.
2053  * The vport must be deactivated before calling this API.
2054  */
2055 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
2056 {
2057         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2058         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2059         struct ecore_hwfn *p_hwfn;
2060         int rc;
2061         int i;
2062
2063         if (IS_PF(edev)) {
2064                 struct ecore_sp_vport_update_params params;
2065
2066                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
2067                 params.vport_id = 0;
2068                 params.mtu = mtu;
2069                 params.vport_id = 0;
2070                 for_each_hwfn(edev, i) {
2071                         p_hwfn = &edev->hwfns[i];
2072                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2073                         rc = ecore_sp_vport_update(p_hwfn, &params,
2074                                         ECORE_SPQ_MODE_EBLOCK, NULL);
2075                         if (rc != ECORE_SUCCESS)
2076                                 goto err;
2077                 }
2078         } else {
2079                 for_each_hwfn(edev, i) {
2080                         p_hwfn = &edev->hwfns[i];
2081                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
2082                         if (rc == ECORE_INVAL) {
2083                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
2084                                 /* Recreate vport */
2085                                 rc = qede_start_vport(qdev, mtu);
2086                                 if (rc != ECORE_SUCCESS)
2087                                         goto err;
2088
2089                                 /* Restore config lost due to vport stop */
2090                                 if (eth_dev->data->promiscuous)
2091                                         qede_promiscuous_enable(eth_dev);
2092                                 else
2093                                         qede_promiscuous_disable(eth_dev);
2094
2095                                 if (eth_dev->data->all_multicast)
2096                                         qede_allmulticast_enable(eth_dev);
2097                                 else
2098                                         qede_allmulticast_disable(eth_dev);
2099
2100                                 qede_vlan_offload_set(eth_dev,
2101                                                       qdev->vlan_offload_mask);
2102                         } else if (rc != ECORE_SUCCESS) {
2103                                 goto err;
2104                         }
2105                 }
2106         }
2107         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
2108
2109         return 0;
2110
2111 err:
2112         DP_ERR(edev, "Failed to update MTU\n");
2113         return -1;
2114 }
2115
2116 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2117                               struct rte_eth_fc_conf *fc_conf)
2118 {
2119         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2120         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2121         struct qed_link_output current_link;
2122         struct qed_link_params params;
2123
2124         memset(&current_link, 0, sizeof(current_link));
2125         qdev->ops->common->get_link(edev, &current_link);
2126
2127         memset(&params, 0, sizeof(params));
2128         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2129         if (fc_conf->autoneg) {
2130                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2131                         DP_ERR(edev, "Autoneg not supported\n");
2132                         return -EINVAL;
2133                 }
2134                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2135         }
2136
2137         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2138         if (fc_conf->mode == RTE_FC_FULL)
2139                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2140                                         QED_LINK_PAUSE_RX_ENABLE);
2141         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2142                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2143         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2144                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2145
2146         params.link_up = true;
2147         (void)qdev->ops->common->set_link(edev, &params);
2148
2149         return 0;
2150 }
2151
2152 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2153                               struct rte_eth_fc_conf *fc_conf)
2154 {
2155         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2156         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2157         struct qed_link_output current_link;
2158
2159         memset(&current_link, 0, sizeof(current_link));
2160         qdev->ops->common->get_link(edev, &current_link);
2161
2162         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2163                 fc_conf->autoneg = true;
2164
2165         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2166                                          QED_LINK_PAUSE_TX_ENABLE))
2167                 fc_conf->mode = RTE_FC_FULL;
2168         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2169                 fc_conf->mode = RTE_FC_RX_PAUSE;
2170         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2171                 fc_conf->mode = RTE_FC_TX_PAUSE;
2172         else
2173                 fc_conf->mode = RTE_FC_NONE;
2174
2175         return 0;
2176 }
2177
2178 static const uint32_t *
2179 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2180 {
2181         static const uint32_t ptypes[] = {
2182                 RTE_PTYPE_L2_ETHER,
2183                 RTE_PTYPE_L2_ETHER_VLAN,
2184                 RTE_PTYPE_L3_IPV4,
2185                 RTE_PTYPE_L3_IPV6,
2186                 RTE_PTYPE_L4_TCP,
2187                 RTE_PTYPE_L4_UDP,
2188                 RTE_PTYPE_TUNNEL_VXLAN,
2189                 RTE_PTYPE_L4_FRAG,
2190                 RTE_PTYPE_TUNNEL_GENEVE,
2191                 RTE_PTYPE_TUNNEL_GRE,
2192                 /* Inner */
2193                 RTE_PTYPE_INNER_L2_ETHER,
2194                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2195                 RTE_PTYPE_INNER_L3_IPV4,
2196                 RTE_PTYPE_INNER_L3_IPV6,
2197                 RTE_PTYPE_INNER_L4_TCP,
2198                 RTE_PTYPE_INNER_L4_UDP,
2199                 RTE_PTYPE_INNER_L4_FRAG,
2200                 RTE_PTYPE_UNKNOWN
2201         };
2202
2203         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2204                 return ptypes;
2205
2206         return NULL;
2207 }
2208
2209 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2210 {
2211         *rss_caps = 0;
2212         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2213         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2214         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2215         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2216         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2217         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2218         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2219         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2220 }
2221
2222 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2223                          struct rte_eth_rss_conf *rss_conf)
2224 {
2225         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2226         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2227         struct ecore_sp_vport_update_params vport_update_params;
2228         struct ecore_rss_params rss_params;
2229         struct ecore_hwfn *p_hwfn;
2230         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2231         uint64_t hf = rss_conf->rss_hf;
2232         uint8_t len = rss_conf->rss_key_len;
2233         uint8_t idx;
2234         uint8_t i;
2235         int rc;
2236
2237         memset(&vport_update_params, 0, sizeof(vport_update_params));
2238         memset(&rss_params, 0, sizeof(rss_params));
2239
2240         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2241                 (unsigned long)hf, len, key);
2242
2243         if (hf != 0) {
2244                 /* Enabling RSS */
2245                 DP_INFO(edev, "Enabling rss\n");
2246
2247                 /* RSS caps */
2248                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2249                 rss_params.update_rss_capabilities = 1;
2250
2251                 /* RSS hash key */
2252                 if (key) {
2253                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2254                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2255                                 return -EINVAL;
2256                         }
2257                         DP_INFO(edev, "Applying user supplied hash key\n");
2258                         rss_params.update_rss_key = 1;
2259                         memcpy(&rss_params.rss_key, key, len);
2260                 }
2261                 rss_params.rss_enable = 1;
2262         }
2263
2264         rss_params.update_rss_config = 1;
2265         /* tbl_size has to be set with capabilities */
2266         rss_params.rss_table_size_log = 7;
2267         vport_update_params.vport_id = 0;
2268         /* pass the L2 handles instead of qids */
2269         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2270                 idx = i % QEDE_RSS_COUNT(qdev);
2271                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2272         }
2273         vport_update_params.rss_params = &rss_params;
2274
2275         for_each_hwfn(edev, i) {
2276                 p_hwfn = &edev->hwfns[i];
2277                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2278                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2279                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2280                 if (rc) {
2281                         DP_ERR(edev, "vport-update for RSS failed\n");
2282                         return rc;
2283                 }
2284         }
2285         qdev->rss_enable = rss_params.rss_enable;
2286
2287         /* Update local structure for hash query */
2288         qdev->rss_conf.rss_hf = hf;
2289         qdev->rss_conf.rss_key_len = len;
2290         if (qdev->rss_enable) {
2291                 if  (qdev->rss_conf.rss_key == NULL) {
2292                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2293                         if (qdev->rss_conf.rss_key == NULL) {
2294                                 DP_ERR(edev, "No memory to store RSS key\n");
2295                                 return -ENOMEM;
2296                         }
2297                 }
2298                 if (key && len) {
2299                         DP_INFO(edev, "Storing RSS key\n");
2300                         memcpy(qdev->rss_conf.rss_key, key, len);
2301                 }
2302         } else if (!qdev->rss_enable && len == 0) {
2303                 if (qdev->rss_conf.rss_key) {
2304                         free(qdev->rss_conf.rss_key);
2305                         qdev->rss_conf.rss_key = NULL;
2306                         DP_INFO(edev, "Free RSS key\n");
2307                 }
2308         }
2309
2310         return 0;
2311 }
2312
2313 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2314                            struct rte_eth_rss_conf *rss_conf)
2315 {
2316         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2317
2318         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2319         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2320
2321         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2322                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2323                        rss_conf->rss_key_len);
2324         return 0;
2325 }
2326
2327 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2328                                     struct ecore_rss_params *rss)
2329 {
2330         int i, fn;
2331         bool rss_mode = 1; /* enable */
2332         struct ecore_queue_cid *cid;
2333         struct ecore_rss_params *t_rss;
2334
2335         /* In regular scenario, we'd simply need to take input handlers.
2336          * But in CMT, we'd have to split the handlers according to the
2337          * engine they were configured on. We'd then have to understand
2338          * whether RSS is really required, since 2-queues on CMT doesn't
2339          * require RSS.
2340          */
2341
2342         /* CMT should be round-robin */
2343         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2344                 cid = rss->rss_ind_table[i];
2345
2346                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2347                         t_rss = &rss[0];
2348                 else
2349                         t_rss = &rss[1];
2350
2351                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2352         }
2353
2354         t_rss = &rss[1];
2355         t_rss->update_rss_ind_table = 1;
2356         t_rss->rss_table_size_log = 7;
2357         t_rss->update_rss_config = 1;
2358
2359         /* Make sure RSS is actually required */
2360         for_each_hwfn(edev, fn) {
2361                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2362                      i++) {
2363                         if (rss[fn].rss_ind_table[i] !=
2364                             rss[fn].rss_ind_table[0])
2365                                 break;
2366                 }
2367
2368                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2369                         DP_INFO(edev,
2370                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2371                         rss_mode = 0;
2372                         goto out;
2373                 }
2374         }
2375
2376 out:
2377         t_rss->rss_enable = rss_mode;
2378
2379         return rss_mode;
2380 }
2381
2382 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2383                          struct rte_eth_rss_reta_entry64 *reta_conf,
2384                          uint16_t reta_size)
2385 {
2386         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2387         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2388         struct ecore_sp_vport_update_params vport_update_params;
2389         struct ecore_rss_params *params;
2390         struct ecore_hwfn *p_hwfn;
2391         uint16_t i, idx, shift;
2392         uint8_t entry;
2393         int rc = 0;
2394
2395         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2396                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2397                        reta_size);
2398                 return -EINVAL;
2399         }
2400
2401         memset(&vport_update_params, 0, sizeof(vport_update_params));
2402         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2403                              RTE_CACHE_LINE_SIZE);
2404         if (params == NULL) {
2405                 DP_ERR(edev, "failed to allocate memory\n");
2406                 return -ENOMEM;
2407         }
2408
2409         for (i = 0; i < reta_size; i++) {
2410                 idx = i / RTE_RETA_GROUP_SIZE;
2411                 shift = i % RTE_RETA_GROUP_SIZE;
2412                 if (reta_conf[idx].mask & (1ULL << shift)) {
2413                         entry = reta_conf[idx].reta[shift];
2414                         /* Pass rxq handles to ecore */
2415                         params->rss_ind_table[i] =
2416                                         qdev->fp_array[entry].rxq->handle;
2417                         /* Update the local copy for RETA query command */
2418                         qdev->rss_ind_table[i] = entry;
2419                 }
2420         }
2421
2422         params->update_rss_ind_table = 1;
2423         params->rss_table_size_log = 7;
2424         params->update_rss_config = 1;
2425
2426         /* Fix up RETA for CMT mode device */
2427         if (ECORE_IS_CMT(edev))
2428                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2429                                                             params);
2430         vport_update_params.vport_id = 0;
2431         /* Use the current value of rss_enable */
2432         params->rss_enable = qdev->rss_enable;
2433         vport_update_params.rss_params = params;
2434
2435         for_each_hwfn(edev, i) {
2436                 p_hwfn = &edev->hwfns[i];
2437                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2438                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2439                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2440                 if (rc) {
2441                         DP_ERR(edev, "vport-update for RSS failed\n");
2442                         goto out;
2443                 }
2444         }
2445
2446 out:
2447         rte_free(params);
2448         return rc;
2449 }
2450
2451 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2452                                struct rte_eth_rss_reta_entry64 *reta_conf,
2453                                uint16_t reta_size)
2454 {
2455         struct qede_dev *qdev = eth_dev->data->dev_private;
2456         struct ecore_dev *edev = &qdev->edev;
2457         uint16_t i, idx, shift;
2458         uint8_t entry;
2459
2460         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2461                 DP_ERR(edev, "reta_size %d is not supported\n",
2462                        reta_size);
2463                 return -EINVAL;
2464         }
2465
2466         for (i = 0; i < reta_size; i++) {
2467                 idx = i / RTE_RETA_GROUP_SIZE;
2468                 shift = i % RTE_RETA_GROUP_SIZE;
2469                 if (reta_conf[idx].mask & (1ULL << shift)) {
2470                         entry = qdev->rss_ind_table[i];
2471                         reta_conf[idx].reta[shift] = entry;
2472                 }
2473         }
2474
2475         return 0;
2476 }
2477
2478
2479
2480 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2481 {
2482         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2483         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2484         struct rte_eth_dev_info dev_info = {0};
2485         struct qede_fastpath *fp;
2486         uint32_t max_rx_pkt_len;
2487         uint32_t frame_size;
2488         uint16_t rx_buf_size;
2489         uint16_t bufsz;
2490         bool restart = false;
2491         int i;
2492
2493         PMD_INIT_FUNC_TRACE(edev);
2494         qede_dev_info_get(dev, &dev_info);
2495         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2496         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2497         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2498                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2499                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2500                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2501                 return -EINVAL;
2502         }
2503         if (!dev->data->scattered_rx &&
2504             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2505                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2506                         dev->data->min_rx_buf_size);
2507                 return -EINVAL;
2508         }
2509         /* Temporarily replace I/O functions with dummy ones. It cannot
2510          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2511          */
2512         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2513         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2514         if (dev->data->dev_started) {
2515                 dev->data->dev_started = 0;
2516                 qede_dev_stop(dev);
2517                 restart = true;
2518         }
2519         rte_delay_ms(1000);
2520         qdev->mtu = mtu;
2521
2522         /* Fix up RX buf size for all queues of the port */
2523         for_each_rss(i) {
2524                 fp = &qdev->fp_array[i];
2525                 if (fp->rxq != NULL) {
2526                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2527                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2528                         if (dev->data->scattered_rx)
2529                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2530                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2531                         else
2532                                 rx_buf_size = frame_size;
2533                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2534                         fp->rxq->rx_buf_size = rx_buf_size;
2535                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2536                 }
2537         }
2538         if (max_rx_pkt_len > ETHER_MAX_LEN)
2539                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2540         else
2541                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2542
2543         if (!dev->data->dev_started && restart) {
2544                 qede_dev_start(dev);
2545                 dev->data->dev_started = 1;
2546         }
2547
2548         /* update max frame size */
2549         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2550         /* Reassign back */
2551         dev->rx_pkt_burst = qede_recv_pkts;
2552         dev->tx_pkt_burst = qede_xmit_pkts;
2553
2554         return 0;
2555 }
2556
2557 static int
2558 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2559                       struct rte_eth_udp_tunnel *tunnel_udp)
2560 {
2561         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2562         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2563         struct ecore_tunnel_info tunn; /* @DPDK */
2564         uint16_t udp_port;
2565         int rc;
2566
2567         PMD_INIT_FUNC_TRACE(edev);
2568
2569         memset(&tunn, 0, sizeof(tunn));
2570
2571         switch (tunnel_udp->prot_type) {
2572         case RTE_TUNNEL_TYPE_VXLAN:
2573                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2574                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2575                                 tunnel_udp->udp_port);
2576                         return ECORE_INVAL;
2577                 }
2578                 udp_port = 0;
2579
2580                 tunn.vxlan_port.b_update_port = true;
2581                 tunn.vxlan_port.port = udp_port;
2582
2583                 rc = qede_tunnel_update(qdev, &tunn);
2584                 if (rc != ECORE_SUCCESS) {
2585                         DP_ERR(edev, "Unable to config UDP port %u\n",
2586                                tunn.vxlan_port.port);
2587                         return rc;
2588                 }
2589
2590                 qdev->vxlan.udp_port = udp_port;
2591                 /* If the request is to delete UDP port and if the number of
2592                  * VXLAN filters have reached 0 then VxLAN offload can be be
2593                  * disabled.
2594                  */
2595                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2596                         return qede_vxlan_enable(eth_dev,
2597                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2598
2599                 break;
2600         case RTE_TUNNEL_TYPE_GENEVE:
2601                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2602                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2603                                 tunnel_udp->udp_port);
2604                         return ECORE_INVAL;
2605                 }
2606
2607                 udp_port = 0;
2608
2609                 tunn.geneve_port.b_update_port = true;
2610                 tunn.geneve_port.port = udp_port;
2611
2612                 rc = qede_tunnel_update(qdev, &tunn);
2613                 if (rc != ECORE_SUCCESS) {
2614                         DP_ERR(edev, "Unable to config UDP port %u\n",
2615                                tunn.vxlan_port.port);
2616                         return rc;
2617                 }
2618
2619                 qdev->vxlan.udp_port = udp_port;
2620                 /* If the request is to delete UDP port and if the number of
2621                  * GENEVE filters have reached 0 then GENEVE offload can be be
2622                  * disabled.
2623                  */
2624                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2625                         return qede_geneve_enable(eth_dev,
2626                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2627
2628                 break;
2629
2630         default:
2631                 return ECORE_INVAL;
2632         }
2633
2634         return 0;
2635
2636 }
2637 static int
2638 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2639                       struct rte_eth_udp_tunnel *tunnel_udp)
2640 {
2641         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2642         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2643         struct ecore_tunnel_info tunn; /* @DPDK */
2644         uint16_t udp_port;
2645         int rc;
2646
2647         PMD_INIT_FUNC_TRACE(edev);
2648
2649         memset(&tunn, 0, sizeof(tunn));
2650
2651         switch (tunnel_udp->prot_type) {
2652         case RTE_TUNNEL_TYPE_VXLAN:
2653                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2654                         DP_INFO(edev,
2655                                 "UDP port %u for VXLAN was already configured\n",
2656                                 tunnel_udp->udp_port);
2657                         return ECORE_SUCCESS;
2658                 }
2659
2660                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2661                  * it was not enabled while adding VXLAN filter before UDP port
2662                  * update.
2663                  */
2664                 if (!qdev->vxlan.enable) {
2665                         rc = qede_vxlan_enable(eth_dev,
2666                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2667                         if (rc != ECORE_SUCCESS) {
2668                                 DP_ERR(edev, "Failed to enable VXLAN "
2669                                         "prior to updating UDP port\n");
2670                                 return rc;
2671                         }
2672                 }
2673                 udp_port = tunnel_udp->udp_port;
2674
2675                 tunn.vxlan_port.b_update_port = true;
2676                 tunn.vxlan_port.port = udp_port;
2677
2678                 rc = qede_tunnel_update(qdev, &tunn);
2679                 if (rc != ECORE_SUCCESS) {
2680                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2681                                udp_port);
2682                         return rc;
2683                 }
2684
2685                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2686
2687                 qdev->vxlan.udp_port = udp_port;
2688                 break;
2689         case RTE_TUNNEL_TYPE_GENEVE:
2690                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2691                         DP_INFO(edev,
2692                                 "UDP port %u for GENEVE was already configured\n",
2693                                 tunnel_udp->udp_port);
2694                         return ECORE_SUCCESS;
2695                 }
2696
2697                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2698                  * it was not enabled while adding GENEVE filter before UDP port
2699                  * update.
2700                  */
2701                 if (!qdev->geneve.enable) {
2702                         rc = qede_geneve_enable(eth_dev,
2703                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2704                         if (rc != ECORE_SUCCESS) {
2705                                 DP_ERR(edev, "Failed to enable GENEVE "
2706                                         "prior to updating UDP port\n");
2707                                 return rc;
2708                         }
2709                 }
2710                 udp_port = tunnel_udp->udp_port;
2711
2712                 tunn.geneve_port.b_update_port = true;
2713                 tunn.geneve_port.port = udp_port;
2714
2715                 rc = qede_tunnel_update(qdev, &tunn);
2716                 if (rc != ECORE_SUCCESS) {
2717                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2718                                udp_port);
2719                         return rc;
2720                 }
2721
2722                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2723
2724                 qdev->geneve.udp_port = udp_port;
2725                 break;
2726         default:
2727                 return ECORE_INVAL;
2728         }
2729
2730         return 0;
2731 }
2732
2733 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2734                                        uint32_t *clss, char *str)
2735 {
2736         uint16_t j;
2737         *clss = MAX_ECORE_TUNN_CLSS;
2738
2739         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2740                 if (filter == qede_tunn_types[j].rte_filter_type) {
2741                         *type = qede_tunn_types[j].qede_type;
2742                         *clss = qede_tunn_types[j].qede_tunn_clss;
2743                         strcpy(str, qede_tunn_types[j].string);
2744                         return;
2745                 }
2746         }
2747 }
2748
2749 static int
2750 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2751                               const struct rte_eth_tunnel_filter_conf *conf,
2752                               uint32_t type)
2753 {
2754         /* Init commmon ucast params first */
2755         qede_set_ucast_cmn_params(ucast);
2756
2757         /* Copy out the required fields based on classification type */
2758         ucast->type = type;
2759
2760         switch (type) {
2761         case ECORE_FILTER_VNI:
2762                 ucast->vni = conf->tenant_id;
2763         break;
2764         case ECORE_FILTER_INNER_VLAN:
2765                 ucast->vlan = conf->inner_vlan;
2766         break;
2767         case ECORE_FILTER_MAC:
2768                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2769                        ETHER_ADDR_LEN);
2770         break;
2771         case ECORE_FILTER_INNER_MAC:
2772                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2773                        ETHER_ADDR_LEN);
2774         break;
2775         case ECORE_FILTER_MAC_VNI_PAIR:
2776                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2777                         ETHER_ADDR_LEN);
2778                 ucast->vni = conf->tenant_id;
2779         break;
2780         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2781                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2782                         ETHER_ADDR_LEN);
2783                 ucast->vni = conf->tenant_id;
2784         break;
2785         case ECORE_FILTER_INNER_PAIR:
2786                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2787                         ETHER_ADDR_LEN);
2788                 ucast->vlan = conf->inner_vlan;
2789         break;
2790         default:
2791                 return -EINVAL;
2792         }
2793
2794         return ECORE_SUCCESS;
2795 }
2796
2797 static int
2798 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2799                          const struct rte_eth_tunnel_filter_conf *conf,
2800                          __attribute__((unused)) enum rte_filter_op filter_op,
2801                          enum ecore_tunn_clss *clss,
2802                          bool add)
2803 {
2804         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2805         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2806         struct ecore_filter_ucast ucast = {0};
2807         enum ecore_filter_ucast_type type;
2808         uint16_t filter_type = 0;
2809         char str[80];
2810         int rc;
2811
2812         filter_type = conf->filter_type;
2813         /* Determine if the given filter classification is supported */
2814         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2815         if (*clss == MAX_ECORE_TUNN_CLSS) {
2816                 DP_ERR(edev, "Unsupported filter type\n");
2817                 return -EINVAL;
2818         }
2819         /* Init tunnel ucast params */
2820         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2821         if (rc != ECORE_SUCCESS) {
2822                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2823                 conf->filter_type);
2824                 return rc;
2825         }
2826         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2827                 str, filter_op, ucast.type);
2828
2829         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2830
2831         /* Skip MAC/VLAN if filter is based on VNI */
2832         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2833                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2834                 if ((rc == 0) && add) {
2835                         /* Enable accept anyvlan */
2836                         qede_config_accept_any_vlan(qdev, true);
2837                 }
2838         } else {
2839                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2840                 if (rc == 0)
2841                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2842                                             ECORE_SPQ_MODE_CB, NULL);
2843         }
2844
2845         return rc;
2846 }
2847
2848 static int
2849 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2850                         enum rte_filter_op filter_op,
2851                         const struct rte_eth_tunnel_filter_conf *conf)
2852 {
2853         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2854         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2855         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2856         bool add;
2857         int rc;
2858
2859         PMD_INIT_FUNC_TRACE(edev);
2860
2861         switch (filter_op) {
2862         case RTE_ETH_FILTER_ADD:
2863                 add = true;
2864                 break;
2865         case RTE_ETH_FILTER_DELETE:
2866                 add = false;
2867                 break;
2868         default:
2869                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2870                 return -EINVAL;
2871         }
2872
2873         if (IS_VF(edev))
2874                 return qede_tunn_enable(eth_dev,
2875                                         ECORE_TUNN_CLSS_MAC_VLAN,
2876                                         conf->tunnel_type, add);
2877
2878         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2879         if (rc != ECORE_SUCCESS)
2880                 return rc;
2881
2882         if (add) {
2883                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2884                         qdev->vxlan.num_filters++;
2885                         qdev->vxlan.filter_type = conf->filter_type;
2886                 } else { /* GENEVE */
2887                         qdev->geneve.num_filters++;
2888                         qdev->geneve.filter_type = conf->filter_type;
2889                 }
2890
2891                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2892                     !qdev->ipgre.enable)
2893                         return qede_tunn_enable(eth_dev, clss,
2894                                                 conf->tunnel_type,
2895                                                 true);
2896         } else {
2897                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2898                         qdev->vxlan.num_filters--;
2899                 else /*GENEVE*/
2900                         qdev->geneve.num_filters--;
2901
2902                 /* Disable VXLAN if VXLAN filters become 0 */
2903                 if ((qdev->vxlan.num_filters == 0) ||
2904                     (qdev->geneve.num_filters == 0))
2905                         return qede_tunn_enable(eth_dev, clss,
2906                                                 conf->tunnel_type,
2907                                                 false);
2908         }
2909
2910         return 0;
2911 }
2912
2913 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2914                          enum rte_filter_type filter_type,
2915                          enum rte_filter_op filter_op,
2916                          void *arg)
2917 {
2918         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2919         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2920         struct rte_eth_tunnel_filter_conf *filter_conf =
2921                         (struct rte_eth_tunnel_filter_conf *)arg;
2922
2923         switch (filter_type) {
2924         case RTE_ETH_FILTER_TUNNEL:
2925                 switch (filter_conf->tunnel_type) {
2926                 case RTE_TUNNEL_TYPE_VXLAN:
2927                 case RTE_TUNNEL_TYPE_GENEVE:
2928                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2929                         DP_INFO(edev,
2930                                 "Packet steering to the specified Rx queue"
2931                                 " is not supported with UDP tunneling");
2932                         return(qede_tunn_filter_config(eth_dev, filter_op,
2933                                                       filter_conf));
2934                 case RTE_TUNNEL_TYPE_TEREDO:
2935                 case RTE_TUNNEL_TYPE_NVGRE:
2936                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2937                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2938                                 filter_conf->tunnel_type);
2939                         return -EINVAL;
2940                 case RTE_TUNNEL_TYPE_NONE:
2941                 default:
2942                         return 0;
2943                 }
2944                 break;
2945         case RTE_ETH_FILTER_FDIR:
2946                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2947         case RTE_ETH_FILTER_NTUPLE:
2948                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2949         case RTE_ETH_FILTER_MACVLAN:
2950         case RTE_ETH_FILTER_ETHERTYPE:
2951         case RTE_ETH_FILTER_FLEXIBLE:
2952         case RTE_ETH_FILTER_SYN:
2953         case RTE_ETH_FILTER_HASH:
2954         case RTE_ETH_FILTER_L2_TUNNEL:
2955         case RTE_ETH_FILTER_MAX:
2956         default:
2957                 DP_ERR(edev, "Unsupported filter type %d\n",
2958                         filter_type);
2959                 return -EINVAL;
2960         }
2961
2962         return 0;
2963 }
2964
2965 static const struct eth_dev_ops qede_eth_dev_ops = {
2966         .dev_configure = qede_dev_configure,
2967         .dev_infos_get = qede_dev_info_get,
2968         .rx_queue_setup = qede_rx_queue_setup,
2969         .rx_queue_release = qede_rx_queue_release,
2970         .tx_queue_setup = qede_tx_queue_setup,
2971         .tx_queue_release = qede_tx_queue_release,
2972         .dev_start = qede_dev_start,
2973         .dev_set_link_up = qede_dev_set_link_up,
2974         .dev_set_link_down = qede_dev_set_link_down,
2975         .link_update = qede_link_update,
2976         .promiscuous_enable = qede_promiscuous_enable,
2977         .promiscuous_disable = qede_promiscuous_disable,
2978         .allmulticast_enable = qede_allmulticast_enable,
2979         .allmulticast_disable = qede_allmulticast_disable,
2980         .set_mc_addr_list = qede_set_mc_addr_list,
2981         .dev_stop = qede_dev_stop,
2982         .dev_close = qede_dev_close,
2983         .stats_get = qede_get_stats,
2984         .stats_reset = qede_reset_stats,
2985         .xstats_get = qede_get_xstats,
2986         .xstats_reset = qede_reset_xstats,
2987         .xstats_get_names = qede_get_xstats_names,
2988         .mac_addr_add = qede_mac_addr_add,
2989         .mac_addr_remove = qede_mac_addr_remove,
2990         .mac_addr_set = qede_mac_addr_set,
2991         .vlan_offload_set = qede_vlan_offload_set,
2992         .vlan_filter_set = qede_vlan_filter_set,
2993         .flow_ctrl_set = qede_flow_ctrl_set,
2994         .flow_ctrl_get = qede_flow_ctrl_get,
2995         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2996         .rss_hash_update = qede_rss_hash_update,
2997         .rss_hash_conf_get = qede_rss_hash_conf_get,
2998         .reta_update  = qede_rss_reta_update,
2999         .reta_query  = qede_rss_reta_query,
3000         .mtu_set = qede_set_mtu,
3001         .filter_ctrl = qede_dev_filter_ctrl,
3002         .udp_tunnel_port_add = qede_udp_dst_port_add,
3003         .udp_tunnel_port_del = qede_udp_dst_port_del,
3004 };
3005
3006 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
3007         .dev_configure = qede_dev_configure,
3008         .dev_infos_get = qede_dev_info_get,
3009         .rx_queue_setup = qede_rx_queue_setup,
3010         .rx_queue_release = qede_rx_queue_release,
3011         .tx_queue_setup = qede_tx_queue_setup,
3012         .tx_queue_release = qede_tx_queue_release,
3013         .dev_start = qede_dev_start,
3014         .dev_set_link_up = qede_dev_set_link_up,
3015         .dev_set_link_down = qede_dev_set_link_down,
3016         .link_update = qede_link_update,
3017         .promiscuous_enable = qede_promiscuous_enable,
3018         .promiscuous_disable = qede_promiscuous_disable,
3019         .allmulticast_enable = qede_allmulticast_enable,
3020         .allmulticast_disable = qede_allmulticast_disable,
3021         .set_mc_addr_list = qede_set_mc_addr_list,
3022         .dev_stop = qede_dev_stop,
3023         .dev_close = qede_dev_close,
3024         .stats_get = qede_get_stats,
3025         .stats_reset = qede_reset_stats,
3026         .xstats_get = qede_get_xstats,
3027         .xstats_reset = qede_reset_xstats,
3028         .xstats_get_names = qede_get_xstats_names,
3029         .vlan_offload_set = qede_vlan_offload_set,
3030         .vlan_filter_set = qede_vlan_filter_set,
3031         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3032         .rss_hash_update = qede_rss_hash_update,
3033         .rss_hash_conf_get = qede_rss_hash_conf_get,
3034         .reta_update  = qede_rss_reta_update,
3035         .reta_query  = qede_rss_reta_query,
3036         .mtu_set = qede_set_mtu,
3037         .udp_tunnel_port_add = qede_udp_dst_port_add,
3038         .udp_tunnel_port_del = qede_udp_dst_port_del,
3039         .mac_addr_add = qede_mac_addr_add,
3040         .mac_addr_remove = qede_mac_addr_remove,
3041         .mac_addr_set = qede_mac_addr_set,
3042 };
3043
3044 static void qede_update_pf_params(struct ecore_dev *edev)
3045 {
3046         struct ecore_pf_params pf_params;
3047
3048         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3049         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3050         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3051         qed_ops->common->update_pf_params(edev, &pf_params);
3052 }
3053
3054 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3055 {
3056         struct rte_pci_device *pci_dev;
3057         struct rte_pci_addr pci_addr;
3058         struct qede_dev *adapter;
3059         struct ecore_dev *edev;
3060         struct qed_dev_eth_info dev_info;
3061         struct qed_slowpath_params params;
3062         static bool do_once = true;
3063         uint8_t bulletin_change;
3064         uint8_t vf_mac[ETHER_ADDR_LEN];
3065         uint8_t is_mac_forced;
3066         bool is_mac_exist;
3067         /* Fix up ecore debug level */
3068         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3069         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3070         uint32_t int_mode;
3071         int rc;
3072
3073         /* Extract key data structures */
3074         adapter = eth_dev->data->dev_private;
3075         adapter->ethdev = eth_dev;
3076         edev = &adapter->edev;
3077         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3078         pci_addr = pci_dev->addr;
3079
3080         PMD_INIT_FUNC_TRACE(edev);
3081
3082         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3083                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3084                  eth_dev->data->port_id);
3085
3086         eth_dev->rx_pkt_burst = qede_recv_pkts;
3087         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3088         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3089
3090         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3091                 DP_ERR(edev, "Skipping device init from secondary process\n");
3092                 return 0;
3093         }
3094
3095         rte_eth_copy_pci_info(eth_dev, pci_dev);
3096
3097         /* @DPDK */
3098         edev->vendor_id = pci_dev->id.vendor_id;
3099         edev->device_id = pci_dev->id.device_id;
3100
3101         qed_ops = qed_get_eth_ops();
3102         if (!qed_ops) {
3103                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3104                 return -EINVAL;
3105         }
3106
3107         DP_INFO(edev, "Starting qede probe\n");
3108         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3109                                     dp_level, is_vf);
3110         if (rc != 0) {
3111                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3112                 return -ENODEV;
3113         }
3114         qede_update_pf_params(edev);
3115
3116         switch (pci_dev->intr_handle.type) {
3117         case RTE_INTR_HANDLE_UIO_INTX:
3118         case RTE_INTR_HANDLE_VFIO_LEGACY:
3119                 int_mode = ECORE_INT_MODE_INTA;
3120                 rte_intr_callback_register(&pci_dev->intr_handle,
3121                                            qede_interrupt_handler_intx,
3122                                            (void *)eth_dev);
3123                 break;
3124         default:
3125                 int_mode = ECORE_INT_MODE_MSIX;
3126                 rte_intr_callback_register(&pci_dev->intr_handle,
3127                                            qede_interrupt_handler,
3128                                            (void *)eth_dev);
3129         }
3130
3131         if (rte_intr_enable(&pci_dev->intr_handle)) {
3132                 DP_ERR(edev, "rte_intr_enable() failed\n");
3133                 return -ENODEV;
3134         }
3135
3136         /* Start the Slowpath-process */
3137         memset(&params, 0, sizeof(struct qed_slowpath_params));
3138
3139         params.int_mode = int_mode;
3140         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3141         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3142         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3143         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3144         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3145                 QEDE_PMD_DRV_VER_STR_SIZE);
3146
3147         /* For CMT mode device do periodic polling for slowpath events.
3148          * This is required since uio device uses only one MSI-x
3149          * interrupt vector but we need one for each engine.
3150          */
3151         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3152                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3153                                        qede_poll_sp_sb_cb,
3154                                        (void *)eth_dev);
3155                 if (rc != 0) {
3156                         DP_ERR(edev, "Unable to start periodic"
3157                                      " timer rc %d\n", rc);
3158                         return -EINVAL;
3159                 }
3160         }
3161
3162         rc = qed_ops->common->slowpath_start(edev, &params);
3163         if (rc) {
3164                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3165                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3166                                      (void *)eth_dev);
3167                 return -ENODEV;
3168         }
3169
3170         rc = qed_ops->fill_dev_info(edev, &dev_info);
3171         if (rc) {
3172                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3173                 qed_ops->common->slowpath_stop(edev);
3174                 qed_ops->common->remove(edev);
3175                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3176                                      (void *)eth_dev);
3177                 return -ENODEV;
3178         }
3179
3180         qede_alloc_etherdev(adapter, &dev_info);
3181
3182         adapter->ops->common->set_name(edev, edev->name);
3183
3184         if (!is_vf)
3185                 adapter->dev_info.num_mac_filters =
3186                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3187                                             ECORE_MAC);
3188         else
3189                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3190                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3191
3192         /* Allocate memory for storing MAC addr */
3193         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3194                                         (ETHER_ADDR_LEN *
3195                                         adapter->dev_info.num_mac_filters),
3196                                         RTE_CACHE_LINE_SIZE);
3197
3198         if (eth_dev->data->mac_addrs == NULL) {
3199                 DP_ERR(edev, "Failed to allocate MAC address\n");
3200                 qed_ops->common->slowpath_stop(edev);
3201                 qed_ops->common->remove(edev);
3202                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3203                                      (void *)eth_dev);
3204                 return -ENOMEM;
3205         }
3206
3207         if (!is_vf) {
3208                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3209                                 hw_info.hw_mac_addr,
3210                                 &eth_dev->data->mac_addrs[0]);
3211                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3212                                 &adapter->primary_mac);
3213         } else {
3214                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3215                                        &bulletin_change);
3216                 if (bulletin_change) {
3217                         is_mac_exist =
3218                             ecore_vf_bulletin_get_forced_mac(
3219                                                 ECORE_LEADING_HWFN(edev),
3220                                                 vf_mac,
3221                                                 &is_mac_forced);
3222                         if (is_mac_exist) {
3223                                 DP_INFO(edev, "VF macaddr received from PF\n");
3224                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3225                                                 &eth_dev->data->mac_addrs[0]);
3226                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3227                                                 &adapter->primary_mac);
3228                         } else {
3229                                 DP_ERR(edev, "No VF macaddr assigned\n");
3230                         }
3231                 }
3232         }
3233
3234         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3235
3236         if (do_once) {
3237                 qede_print_adapter_info(adapter);
3238                 do_once = false;
3239         }
3240
3241         /* Bring-up the link */
3242         qede_dev_set_link_state(eth_dev, true);
3243
3244         adapter->num_tx_queues = 0;
3245         adapter->num_rx_queues = 0;
3246         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3247         SLIST_INIT(&adapter->vlan_list_head);
3248         SLIST_INIT(&adapter->uc_list_head);
3249         SLIST_INIT(&adapter->mc_list_head);
3250         adapter->mtu = ETHER_MTU;
3251         adapter->vport_started = false;
3252
3253         /* VF tunnel offloads is enabled by default in PF driver */
3254         adapter->vxlan.num_filters = 0;
3255         adapter->geneve.num_filters = 0;
3256         adapter->ipgre.num_filters = 0;
3257         if (is_vf) {
3258                 adapter->vxlan.enable = true;
3259                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3260                                              ETH_TUNNEL_FILTER_IVLAN;
3261                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3262                 adapter->geneve.enable = true;
3263                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3264                                               ETH_TUNNEL_FILTER_IVLAN;
3265                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3266                 adapter->ipgre.enable = true;
3267                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3268                                              ETH_TUNNEL_FILTER_IVLAN;
3269         } else {
3270                 adapter->vxlan.enable = false;
3271                 adapter->geneve.enable = false;
3272                 adapter->ipgre.enable = false;
3273         }
3274
3275         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3276                 adapter->primary_mac.addr_bytes[0],
3277                 adapter->primary_mac.addr_bytes[1],
3278                 adapter->primary_mac.addr_bytes[2],
3279                 adapter->primary_mac.addr_bytes[3],
3280                 adapter->primary_mac.addr_bytes[4],
3281                 adapter->primary_mac.addr_bytes[5]);
3282
3283         DP_INFO(edev, "Device initialized\n");
3284
3285         return 0;
3286 }
3287
3288 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3289 {
3290         return qede_common_dev_init(eth_dev, 1);
3291 }
3292
3293 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3294 {
3295         return qede_common_dev_init(eth_dev, 0);
3296 }
3297
3298 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3299 {
3300 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3301         struct qede_dev *qdev = eth_dev->data->dev_private;
3302         struct ecore_dev *edev = &qdev->edev;
3303
3304         PMD_INIT_FUNC_TRACE(edev);
3305 #endif
3306
3307         /* only uninitialize in the primary process */
3308         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3309                 return 0;
3310
3311         /* safe to close dev here */
3312         qede_dev_close(eth_dev);
3313
3314         eth_dev->dev_ops = NULL;
3315         eth_dev->rx_pkt_burst = NULL;
3316         eth_dev->tx_pkt_burst = NULL;
3317
3318         if (eth_dev->data->mac_addrs)
3319                 rte_free(eth_dev->data->mac_addrs);
3320
3321         eth_dev->data->mac_addrs = NULL;
3322
3323         return 0;
3324 }
3325
3326 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3327 {
3328         return qede_dev_common_uninit(eth_dev);
3329 }
3330
3331 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3332 {
3333         return qede_dev_common_uninit(eth_dev);
3334 }
3335
3336 static const struct rte_pci_id pci_id_qedevf_map[] = {
3337 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3338         {
3339                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3340         },
3341         {
3342                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3343         },
3344         {
3345                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3346         },
3347         {.vendor_id = 0,}
3348 };
3349
3350 static const struct rte_pci_id pci_id_qede_map[] = {
3351 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3352         {
3353                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3354         },
3355         {
3356                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3357         },
3358         {
3359                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3360         },
3361         {
3362                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3363         },
3364         {
3365                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3366         },
3367         {
3368                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3369         },
3370         {
3371                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3372         },
3373         {
3374                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3375         },
3376         {
3377                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3378         },
3379         {
3380                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3381         },
3382         {.vendor_id = 0,}
3383 };
3384
3385 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3386         struct rte_pci_device *pci_dev)
3387 {
3388         return rte_eth_dev_pci_generic_probe(pci_dev,
3389                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3390 }
3391
3392 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3393 {
3394         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3395 }
3396
3397 static struct rte_pci_driver rte_qedevf_pmd = {
3398         .id_table = pci_id_qedevf_map,
3399         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3400         .probe = qedevf_eth_dev_pci_probe,
3401         .remove = qedevf_eth_dev_pci_remove,
3402 };
3403
3404 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3405         struct rte_pci_device *pci_dev)
3406 {
3407         return rte_eth_dev_pci_generic_probe(pci_dev,
3408                 sizeof(struct qede_dev), qede_eth_dev_init);
3409 }
3410
3411 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3412 {
3413         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3414 }
3415
3416 static struct rte_pci_driver rte_qede_pmd = {
3417         .id_table = pci_id_qede_map,
3418         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3419         .probe = qede_eth_dev_pci_probe,
3420         .remove = qede_eth_dev_pci_remove,
3421 };
3422
3423 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3424 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3425 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3426 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3427 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3428 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3429
3430 RTE_INIT(qede_init_log);
3431 static void
3432 qede_init_log(void)
3433 {
3434         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3435         if (qede_logtype_init >= 0)
3436                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3437         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3438         if (qede_logtype_driver >= 0)
3439                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3440 }