drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329
 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 331 {
 332         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 333         ucast->is_rx_filter = true;
 334         ucast->is_tx_filter = true;
 335         /* ucast->assert_on_error = true; - For debug */
 336 }
 337
 338 static void qede_set_cmn_tunn_param(struct ecore_tunn_update_params *params,
 339                                      uint8_t clss, uint64_t mode, uint64_t mask)
 340 {
 341         memset(params, 0, sizeof(struct ecore_tunn_update_params));
 342         params->tunn_mode = mode;
 343         params->tunn_mode_update_mask = mask;
 344         params->update_tx_pf_clss = 1;
 345         params->update_rx_pf_clss = 1;
 346         params->tunn_clss_vxlan = clss;
 347 }
 348
 349 static int
 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 351                   bool add)
 352 {
 353         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 354         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 355         struct qede_ucast_entry *tmp = NULL;
 356         struct qede_ucast_entry *u;
 357         struct ether_addr *mac_addr;
 358
 359         mac_addr  = (struct ether_addr *)ucast->mac;
 360         if (add) {
 361                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 362                         if ((memcmp(mac_addr, &tmp->mac,
 363                                     ETHER_ADDR_LEN) == 0) &&
 364                              ucast->vlan == tmp->vlan) {
 365                                 DP_ERR(edev, "Unicast MAC is already added"
 366                                        " with vlan = %u, vni = %u\n",
 367                                        ucast->vlan,  ucast->vni);
 368                                         return -EEXIST;
 369                         }
 370                 }
 371                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 372                                RTE_CACHE_LINE_SIZE);
 373                 if (!u) {
 374                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 375                         return -ENOMEM;
 376                 }
 377                 ether_addr_copy(mac_addr, &u->mac);
 378                 u->vlan = ucast->vlan;
 379                 u->vni = ucast->vni;
 380                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 381                 qdev->num_uc_addr++;
 382         } else {
 383                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 384                         if ((memcmp(mac_addr, &tmp->mac,
 385                                     ETHER_ADDR_LEN) == 0) &&
 386                             ucast->vlan == tmp->vlan      &&
 387                             ucast->vni == tmp->vni)
 388                         break;
 389                 }
 390                 if (tmp == NULL) {
 391                         DP_INFO(edev, "Unicast MAC is not found\n");
 392                         return -EINVAL;
 393                 }
 394                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 395                 qdev->num_uc_addr--;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int
 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 403                   bool add)
 404 {
 405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 407         struct ether_addr *mac_addr;
 408         struct qede_mcast_entry *tmp = NULL;
 409         struct qede_mcast_entry *m;
 410
 411         mac_addr  = (struct ether_addr *)mcast->mac;
 412         if (add) {
 413                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 414                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 415                                 DP_ERR(edev,
 416                                         "Multicast MAC is already added\n");
 417                                 return -EEXIST;
 418                         }
 419                 }
 420                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 421                         RTE_CACHE_LINE_SIZE);
 422                 if (!m) {
 423                         DP_ERR(edev,
 424                                 "Did not allocate memory for mcast\n");
 425                         return -ENOMEM;
 426                 }
 427                 ether_addr_copy(mac_addr, &m->mac);
 428                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 429                 qdev->num_mc_addr++;
 430         } else {
 431                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 432                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 433                                 break;
 434                 }
 435                 if (tmp == NULL) {
 436                         DP_INFO(edev, "Multicast mac is not found\n");
 437                         return -EINVAL;
 438                 }
 439                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 440                              qede_mcast_entry, list);
 441                 qdev->num_mc_addr--;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static enum _ecore_status_t
 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 449                  bool add)
 450 {
 451         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 452         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 453         enum _ecore_status_t rc;
 454         struct ecore_filter_mcast mcast;
 455         struct qede_mcast_entry *tmp;
 456         uint16_t j = 0;
 457
 458         /* Multicast */
 459         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 460                 if (add) {
 461                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 462                                 DP_ERR(edev,
 463                                        "Mcast filter table limit exceeded, "
 464                                        "Please enable mcast promisc mode\n");
 465                                 return -ECORE_INVAL;
 466                         }
 467                 }
 468                 rc = qede_mcast_filter(eth_dev, ucast, add);
 469                 if (rc == 0) {
 470                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 471                         memset(&mcast, 0, sizeof(mcast));
 472                         mcast.num_mc_addrs = qdev->num_mc_addr;
 473                         mcast.opcode = ECORE_FILTER_ADD;
 474                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 475                                 ether_addr_copy(&tmp->mac,
 476                                         (struct ether_addr *)&mcast.mac[j]);
 477                                 j++;
 478                         }
 479                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 480                                                     ECORE_SPQ_MODE_CB, NULL);
 481                 }
 482                 if (rc != ECORE_SUCCESS) {
 483                         DP_ERR(edev, "Failed to add multicast filter"
 484                                " rc = %d, op = %d\n", rc, add);
 485                 }
 486         } else { /* Unicast */
 487                 if (add) {
 488                         if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
 489                                 DP_ERR(edev,
 490                                        "Ucast filter table limit exceeded,"
 491                                        " Please enable promisc mode\n");
 492                                 return -ECORE_INVAL;
 493                         }
 494                 }
 495                 rc = qede_ucast_filter(eth_dev, ucast, add);
 496                 if (rc == 0)
 497                         rc = ecore_filter_ucast_cmd(edev, ucast,
 498                                                     ECORE_SPQ_MODE_CB, NULL);
 499                 if (rc != ECORE_SUCCESS) {
 500                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 501                                rc, add);
 502                 }
 503         }
 504
 505         return rc;
 506 }
 507
 508 static void
 509 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 510                   uint32_t index, __rte_unused uint32_t pool)
 511 {
 512         struct ecore_filter_ucast ucast;
 513
 514         qede_set_ucast_cmn_params(&ucast);
 515         ucast.type = ECORE_FILTER_MAC;
 516         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 517         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 518 }
 519
 520 static void
 521 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 522 {
 523         struct qede_dev *qdev = eth_dev->data->dev_private;
 524         struct ecore_dev *edev = &qdev->edev;
 525         struct ether_addr mac_addr;
 526         struct ecore_filter_ucast ucast;
 527         int rc;
 528
 529         PMD_INIT_FUNC_TRACE(edev);
 530
 531         if (index >= qdev->dev_info.num_mac_addrs) {
 532                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 533                        index, qdev->dev_info.num_mac_addrs);
 534                 return;
 535         }
 536
 537         qede_set_ucast_cmn_params(&ucast);
 538         ucast.opcode = ECORE_FILTER_REMOVE;
 539         ucast.type = ECORE_FILTER_MAC;
 540
 541         /* Use the index maintained by rte */
 542         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 543                         (struct ether_addr *)&ucast.mac);
 544
 545         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 546 }
 547
 548 static void
 549 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 550 {
 551         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 552         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 553         struct ecore_filter_ucast ucast;
 554         int rc;
 555
 556         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 557                                                mac_addr->addr_bytes)) {
 558                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 559                 ether_addr_copy(&qdev->primary_mac,
 560                                 &eth_dev->data->mac_addrs[0]);
 561                 return;
 562         }
 563
 564         /* First remove the primary mac */
 565         qede_set_ucast_cmn_params(&ucast);
 566         ucast.opcode = ECORE_FILTER_REMOVE;
 567         ucast.type = ECORE_FILTER_MAC;
 568         ether_addr_copy(&qdev->primary_mac,
 569                         (struct ether_addr *)&ucast.mac);
 570         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 571         if (rc != 0) {
 572                 DP_ERR(edev, "Unable to remove current macaddr"
 573                              " Reverting to previous default mac\n");
 574                 ether_addr_copy(&qdev->primary_mac,
 575                                 &eth_dev->data->mac_addrs[0]);
 576                 return;
 577         }
 578
 579         /* Add new MAC */
 580         ucast.opcode = ECORE_FILTER_ADD;
 581         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 582         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 583         if (rc != 0)
 584                 DP_ERR(edev, "Unable to add new default mac\n");
 585         else
 586                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 587 }
 588
 589 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 590 {
 591         struct ecore_dev *edev = &qdev->edev;
 592         struct qed_update_vport_params params = {
 593                 .vport_id = 0,
 594                 .accept_any_vlan = action,
 595                 .update_accept_any_vlan_flg = 1,
 596         };
 597         int rc;
 598
 599         /* Proceed only if action actually needs to be performed */
 600         if (qdev->accept_any_vlan == action)
 601                 return;
 602
 603         rc = qdev->ops->vport_update(edev, &params);
 604         if (rc) {
 605                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 606                        action ? "enable" : "disable");
 607         } else {
 608                 DP_INFO(edev, "%s accept-any-vlan\n",
 609                         action ? "enabled" : "disabled");
 610                 qdev->accept_any_vlan = action;
 611         }
 612 }
 613
 614 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 615 {
 616         struct qed_update_vport_params vport_update_params;
 617         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 618         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 619         int rc;
 620
 621         memset(&vport_update_params, 0, sizeof(vport_update_params));
 622         vport_update_params.vport_id = 0;
 623         vport_update_params.update_inner_vlan_removal_flg = 1;
 624         vport_update_params.inner_vlan_removal_flg = set_stripping;
 625         rc = qdev->ops->vport_update(edev, &vport_update_params);
 626         if (rc) {
 627                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 628                 return rc;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 635 {
 636         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 637         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 638         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 639
 640         if (mask & ETH_VLAN_STRIP_MASK) {
 641                 if (rxmode->hw_vlan_strip)
 642                         (void)qede_vlan_stripping(eth_dev, 1);
 643                 else
 644                         (void)qede_vlan_stripping(eth_dev, 0);
 645         }
 646
 647         if (mask & ETH_VLAN_FILTER_MASK) {
 648                 /* VLAN filtering kicks in when a VLAN is added */
 649                 if (rxmode->hw_vlan_filter) {
 650                         qede_vlan_filter_set(eth_dev, 0, 1);
 651                 } else {
 652                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 653                                 DP_NOTICE(edev, false,
 654                                   " Please remove existing VLAN filters"
 655                                   " before disabling VLAN filtering\n");
 656                                 /* Signal app that VLAN filtering is still
 657                                  * enabled
 658                                  */
 659                                 rxmode->hw_vlan_filter = true;
 660                         } else {
 661                                 qede_vlan_filter_set(eth_dev, 0, 0);
 662                         }
 663                 }
 664         }
 665
 666         if (mask & ETH_VLAN_EXTEND_MASK)
 667                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 668                         " and classification is based on outer tag only\n");
 669
 670         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 671                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 672 }
 673
 674 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 675                                 uint16_t vlan_id, int on)
 676 {
 677         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 678         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 679         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 680         struct qede_vlan_entry *tmp = NULL;
 681         struct qede_vlan_entry *vlan;
 682         struct ecore_filter_ucast ucast;
 683         int rc;
 684
 685         if (on) {
 686                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 687                         DP_INFO(edev, "Reached max VLAN filter limit"
 688                                       " enabling accept_any_vlan\n");
 689                         qede_config_accept_any_vlan(qdev, true);
 690                         return 0;
 691                 }
 692
 693                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 694                         if (tmp->vid == vlan_id) {
 695                                 DP_ERR(edev, "VLAN %u already configured\n",
 696                                        vlan_id);
 697                                 return -EEXIST;
 698                         }
 699                 }
 700
 701                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 702                                   RTE_CACHE_LINE_SIZE);
 703
 704                 if (!vlan) {
 705                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 706                         return -ENOMEM;
 707                 }
 708
 709                 qede_set_ucast_cmn_params(&ucast);
 710                 ucast.opcode = ECORE_FILTER_ADD;
 711                 ucast.type = ECORE_FILTER_VLAN;
 712                 ucast.vlan = vlan_id;
 713                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 714                                             NULL);
 715                 if (rc != 0) {
 716                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 717                                rc);
 718                         rte_free(vlan);
 719                 } else {
 720                         vlan->vid = vlan_id;
 721                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 722                         qdev->configured_vlans++;
 723                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 724                                 vlan_id, qdev->configured_vlans);
 725                 }
 726         } else {
 727                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 728                         if (tmp->vid == vlan_id)
 729                                 break;
 730                 }
 731
 732                 if (!tmp) {
 733                         if (qdev->configured_vlans == 0) {
 734                                 DP_INFO(edev,
 735                                         "No VLAN filters configured yet\n");
 736                                 return 0;
 737                         }
 738
 739                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 740                         return -EINVAL;
 741                 }
 742
 743                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 744
 745                 qede_set_ucast_cmn_params(&ucast);
 746                 ucast.opcode = ECORE_FILTER_REMOVE;
 747                 ucast.type = ECORE_FILTER_VLAN;
 748                 ucast.vlan = vlan_id;
 749                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 750                                             NULL);
 751                 if (rc != 0) {
 752                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 753                                vlan_id, rc);
 754                 } else {
 755                         qdev->configured_vlans--;
 756                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 757                                 vlan_id, qdev->configured_vlans);
 758                 }
 759         }
 760
 761         return rc;
 762 }
 763
 764 static int qede_init_vport(struct qede_dev *qdev)
 765 {
 766         struct ecore_dev *edev = &qdev->edev;
 767         struct qed_start_vport_params start = {0};
 768         int rc;
 769
 770         start.remove_inner_vlan = 1;
 771         start.gro_enable = 0;
 772         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 773         start.vport_id = 0;
 774         start.drop_ttl0 = false;
 775         start.clear_stats = 1;
 776         start.handle_ptp_pkts = 0;
 777
 778         rc = qdev->ops->vport_start(edev, &start);
 779         if (rc) {
 780                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 781                 return rc;
 782         }
 783
 784         DP_INFO(edev,
 785                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 786                 start.vport_id, ETHER_MTU);
 787
 788         return 0;
 789 }
 790
 791 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 792 {
 793         struct qede_dev *qdev = eth_dev->data->dev_private;
 794         struct ecore_dev *edev = &qdev->edev;
 795         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 796         int rc, i, j;
 797
 798         PMD_INIT_FUNC_TRACE(edev);
 799
 800         /* Check requirements for 100G mode */
 801         if (edev->num_hwfns > 1) {
 802                 if (eth_dev->data->nb_rx_queues < 2 ||
 803                     eth_dev->data->nb_tx_queues < 2) {
 804                         DP_NOTICE(edev, false,
 805                                   "100G mode needs min. 2 RX/TX queues\n");
 806                         return -EINVAL;
 807                 }
 808
 809                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 810                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 811                         DP_NOTICE(edev, false,
 812                                   "100G mode needs even no. of RX/TX queues\n");
 813                         return -EINVAL;
 814                 }
 815         }
 816
 817         /* Sanity checks and throw warnings */
 818         if (rxmode->enable_scatter == 1)
 819                 eth_dev->data->scattered_rx = 1;
 820
 821         if (rxmode->enable_lro == 1) {
 822                 DP_INFO(edev, "LRO is not supported\n");
 823                 return -EINVAL;
 824         }
 825
 826         if (!rxmode->hw_strip_crc)
 827                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 828
 829         if (!rxmode->hw_ip_checksum)
 830                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 831                               "in hw\n");
 832
 833         /* Check for the port restart case */
 834         if (qdev->state != QEDE_DEV_INIT) {
 835                 rc = qdev->ops->vport_stop(edev, 0);
 836                 if (rc != 0)
 837                         return rc;
 838                 qede_dealloc_fp_resc(eth_dev);
 839         }
 840
 841         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 842         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 843         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 844
 845         /* Fastpath status block should be initialized before sending
 846          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 847          */
 848         rc = qede_alloc_fp_resc(qdev);
 849         if (rc != 0)
 850                 return rc;
 851
 852         /* Issue VPORT-START with default config values to allow
 853          * other port configurations early on.
 854          */
 855         rc = qede_init_vport(qdev);
 856         if (rc != 0)
 857                 return rc;
 858
 859         SLIST_INIT(&qdev->vlan_list_head);
 860
 861         /* Add primary mac for PF */
 862         if (IS_PF(edev))
 863                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 864
 865         /* Enable VLAN offloads by default */
 866         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 867                                        ETH_VLAN_FILTER_MASK |
 868                                        ETH_VLAN_EXTEND_MASK);
 869
 870         qdev->state = QEDE_DEV_CONFIG;
 871
 872         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 873                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 874                 qdev->num_tc);
 875
 876         return 0;
 877 }
 878
 879 /* Info about HW descriptor ring limitations */
 880 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 881         .nb_max = NUM_RX_BDS_MAX,
 882         .nb_min = 128,
 883         .nb_align = 128 /* lowest common multiple */
 884 };
 885
 886 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 887         .nb_max = NUM_TX_BDS_MAX,
 888         .nb_min = 256,
 889         .nb_align = 256
 890 };
 891
 892 static void
 893 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 894                   struct rte_eth_dev_info *dev_info)
 895 {
 896         struct qede_dev *qdev = eth_dev->data->dev_private;
 897         struct ecore_dev *edev = &qdev->edev;
 898         struct qed_link_output link;
 899         uint32_t speed_cap = 0;
 900
 901         PMD_INIT_FUNC_TRACE(edev);
 902
 903         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 904         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 905                                               QEDE_ETH_OVERHEAD);
 906         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 907         dev_info->rx_desc_lim = qede_rx_desc_lim;
 908         dev_info->tx_desc_lim = qede_tx_desc_lim;
 909         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 910         dev_info->max_tx_queues = dev_info->max_rx_queues;
 911         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 912         if (IS_VF(edev))
 913                 dev_info->max_vfs = 0;
 914         else
 915                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 916         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 917         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 918
 919         dev_info->default_txconf = (struct rte_eth_txconf) {
 920                 .txq_flags = QEDE_TXQ_FLAGS,
 921         };
 922
 923         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 924                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 925                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 926                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 927                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM);
 928         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 929                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 930                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
 931                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
 932                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM);
 933
 934         memset(&link, 0, sizeof(struct qed_link_output));
 935         qdev->ops->common->get_link(edev, &link);
 936         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 937                 speed_cap |= ETH_LINK_SPEED_1G;
 938         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 939                 speed_cap |= ETH_LINK_SPEED_10G;
 940         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 941                 speed_cap |= ETH_LINK_SPEED_25G;
 942         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 943                 speed_cap |= ETH_LINK_SPEED_40G;
 944         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 945                 speed_cap |= ETH_LINK_SPEED_50G;
 946         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 947                 speed_cap |= ETH_LINK_SPEED_100G;
 948         dev_info->speed_capa = speed_cap;
 949 }
 950
 951 /* return 0 means link status changed, -1 means not changed */
 952 static int
 953 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 954 {
 955         struct qede_dev *qdev = eth_dev->data->dev_private;
 956         struct ecore_dev *edev = &qdev->edev;
 957         uint16_t link_duplex;
 958         struct qed_link_output link;
 959         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 960
 961         memset(&link, 0, sizeof(struct qed_link_output));
 962         qdev->ops->common->get_link(edev, &link);
 963
 964         /* Link Speed */
 965         curr->link_speed = link.speed;
 966
 967         /* Link Mode */
 968         switch (link.duplex) {
 969         case QEDE_DUPLEX_HALF:
 970                 link_duplex = ETH_LINK_HALF_DUPLEX;
 971                 break;
 972         case QEDE_DUPLEX_FULL:
 973                 link_duplex = ETH_LINK_FULL_DUPLEX;
 974                 break;
 975         case QEDE_DUPLEX_UNKNOWN:
 976         default:
 977                 link_duplex = -1;
 978         }
 979         curr->link_duplex = link_duplex;
 980
 981         /* Link Status */
 982         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 983
 984         /* AN */
 985         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 986                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 987
 988         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 989                 curr->link_speed, curr->link_duplex,
 990                 curr->link_autoneg, curr->link_status);
 991
 992         /* return 0 means link status changed, -1 means not changed */
 993         return ((curr->link_status == link.link_up) ? -1 : 0);
 994 }
 995
 996 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 997 {
 998         struct qede_dev *qdev = eth_dev->data->dev_private;
 999         struct ecore_dev *edev = &qdev->edev;
1000
1001         PMD_INIT_FUNC_TRACE(edev);
1002
1003         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1004
1005         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1006                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1007
1008         qed_configure_filter_rx_mode(eth_dev, type);
1009 }
1010
1011 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1012 {
1013         struct qede_dev *qdev = eth_dev->data->dev_private;
1014         struct ecore_dev *edev = &qdev->edev;
1015
1016         PMD_INIT_FUNC_TRACE(edev);
1017
1018         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1019                 qed_configure_filter_rx_mode(eth_dev,
1020                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1021         else
1022                 qed_configure_filter_rx_mode(eth_dev,
1023                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1024 }
1025
1026 static void qede_poll_sp_sb_cb(void *param)
1027 {
1028         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1029         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1030         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1031         int rc;
1032
1033         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1034         qede_interrupt_action(&edev->hwfns[1]);
1035
1036         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1037                                qede_poll_sp_sb_cb,
1038                                (void *)eth_dev);
1039         if (rc != 0) {
1040                 DP_ERR(edev, "Unable to start periodic"
1041                              " timer rc %d\n", rc);
1042                 assert(false && "Unable to start periodic timer");
1043         }
1044 }
1045
1046 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1047 {
1048         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1049         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1050         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1051         int rc;
1052
1053         PMD_INIT_FUNC_TRACE(edev);
1054
1055         /* dev_stop() shall cleanup fp resources in hw but without releasing
1056          * dma memories and sw structures so that dev_start() can be called
1057          * by the app without reconfiguration. However, in dev_close() we
1058          * can release all the resources and device can be brought up newly
1059          */
1060         if (qdev->state != QEDE_DEV_STOP)
1061                 qede_dev_stop(eth_dev);
1062         else
1063                 DP_INFO(edev, "Device is already stopped\n");
1064
1065         rc = qdev->ops->vport_stop(edev, 0);
1066         if (rc != 0)
1067                 DP_ERR(edev, "Failed to stop VPORT\n");
1068
1069         qede_dealloc_fp_resc(eth_dev);
1070
1071         qdev->ops->common->slowpath_stop(edev);
1072
1073         qdev->ops->common->remove(edev);
1074
1075         rte_intr_disable(&pci_dev->intr_handle);
1076
1077         rte_intr_callback_unregister(&pci_dev->intr_handle,
1078                                      qede_interrupt_handler, (void *)eth_dev);
1079
1080         if (edev->num_hwfns > 1)
1081                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1082
1083         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1084 }
1085
1086 static void
1087 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1088 {
1089         struct qede_dev *qdev = eth_dev->data->dev_private;
1090         struct ecore_dev *edev = &qdev->edev;
1091         struct ecore_eth_stats stats;
1092         unsigned int i = 0, j = 0, qid;
1093         struct qede_tx_queue *txq;
1094
1095         qdev->ops->get_vport_stats(edev, &stats);
1096
1097         /* RX Stats */
1098         eth_stats->ipackets = stats.rx_ucast_pkts +
1099             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1100
1101         eth_stats->ibytes = stats.rx_ucast_bytes +
1102             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1103
1104         eth_stats->ierrors = stats.rx_crc_errors +
1105             stats.rx_align_errors +
1106             stats.rx_carrier_errors +
1107             stats.rx_oversize_packets +
1108             stats.rx_jabbers + stats.rx_undersize_packets;
1109
1110         eth_stats->rx_nombuf = stats.no_buff_discards;
1111
1112         eth_stats->imissed = stats.mftag_filter_discards +
1113             stats.mac_filter_discards +
1114             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1115
1116         /* TX stats */
1117         eth_stats->opackets = stats.tx_ucast_pkts +
1118             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1119
1120         eth_stats->obytes = stats.tx_ucast_bytes +
1121             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1122
1123         eth_stats->oerrors = stats.tx_err_drop_pkts;
1124
1125         /* Queue stats */
1126         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1127                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1128                         eth_stats->q_ipackets[i] =
1129                                 *(uint64_t *)(
1130                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1131                                         offsetof(struct qede_rx_queue,
1132                                         rcv_pkts));
1133                         eth_stats->q_errors[i] =
1134                                 *(uint64_t *)(
1135                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1136                                         offsetof(struct qede_rx_queue,
1137                                         rx_hw_errors)) +
1138                                 *(uint64_t *)(
1139                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1140                                         offsetof(struct qede_rx_queue,
1141                                         rx_alloc_errors));
1142                         i++;
1143                 }
1144
1145                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1146                         txq = qdev->fp_array[(qid)].txqs[0];
1147                         eth_stats->q_opackets[j] =
1148                                 *((uint64_t *)(uintptr_t)
1149                                         (((uint64_t)(uintptr_t)(txq)) +
1150                                          offsetof(struct qede_tx_queue,
1151                                                   xmit_pkts)));
1152                         j++;
1153                 }
1154         }
1155 }
1156
1157 static unsigned
1158 qede_get_xstats_count(struct qede_dev *qdev) {
1159         return RTE_DIM(qede_xstats_strings) +
1160                 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev));
1161 }
1162
1163 static int
1164 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1165                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1166 {
1167         struct qede_dev *qdev = dev->data->dev_private;
1168         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1169         unsigned int i, qid, stat_idx = 0;
1170
1171         if (xstats_names != NULL) {
1172                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1173                         snprintf(xstats_names[stat_idx].name,
1174                                 sizeof(xstats_names[stat_idx].name),
1175                                 "%s",
1176                                 qede_xstats_strings[i].name);
1177                         stat_idx++;
1178                 }
1179
1180                 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) {
1181                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1182                                 snprintf(xstats_names[stat_idx].name,
1183                                         sizeof(xstats_names[stat_idx].name),
1184                                         "%.4s%d%s",
1185                                         qede_rxq_xstats_strings[i].name, qid,
1186                                         qede_rxq_xstats_strings[i].name + 4);
1187                                 stat_idx++;
1188                         }
1189                 }
1190         }
1191
1192         return stat_cnt;
1193 }
1194
1195 static int
1196 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1197                 unsigned int n)
1198 {
1199         struct qede_dev *qdev = dev->data->dev_private;
1200         struct ecore_dev *edev = &qdev->edev;
1201         struct ecore_eth_stats stats;
1202         const unsigned int num = qede_get_xstats_count(qdev);
1203         unsigned int i, qid, stat_idx = 0;
1204
1205         if (n < num)
1206                 return num;
1207
1208         qdev->ops->get_vport_stats(edev, &stats);
1209
1210         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1211                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1212                                              qede_xstats_strings[i].offset);
1213                 xstats[stat_idx].id = stat_idx;
1214                 stat_idx++;
1215         }
1216
1217         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1218                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1219                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1220                                 xstats[stat_idx].value = *(uint64_t *)(
1221                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1222                                          qede_rxq_xstats_strings[i].offset);
1223                                 xstats[stat_idx].id = stat_idx;
1224                                 stat_idx++;
1225                         }
1226                 }
1227         }
1228
1229         return stat_idx;
1230 }
1231
1232 static void
1233 qede_reset_xstats(struct rte_eth_dev *dev)
1234 {
1235         struct qede_dev *qdev = dev->data->dev_private;
1236         struct ecore_dev *edev = &qdev->edev;
1237
1238         ecore_reset_vport_stats(edev);
1239 }
1240
1241 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1242 {
1243         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1244         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1245         struct qed_link_params link_params;
1246         int rc;
1247
1248         DP_INFO(edev, "setting link state %d\n", link_up);
1249         memset(&link_params, 0, sizeof(link_params));
1250         link_params.link_up = link_up;
1251         rc = qdev->ops->common->set_link(edev, &link_params);
1252         if (rc != ECORE_SUCCESS)
1253                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1254
1255         return rc;
1256 }
1257
1258 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1259 {
1260         return qede_dev_set_link_state(eth_dev, true);
1261 }
1262
1263 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1264 {
1265         return qede_dev_set_link_state(eth_dev, false);
1266 }
1267
1268 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1269 {
1270         struct qede_dev *qdev = eth_dev->data->dev_private;
1271         struct ecore_dev *edev = &qdev->edev;
1272
1273         ecore_reset_vport_stats(edev);
1274 }
1275
1276 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1277 {
1278         enum qed_filter_rx_mode_type type =
1279             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1280
1281         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1282                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1283
1284         qed_configure_filter_rx_mode(eth_dev, type);
1285 }
1286
1287 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1288 {
1289         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1290                 qed_configure_filter_rx_mode(eth_dev,
1291                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1292         else
1293                 qed_configure_filter_rx_mode(eth_dev,
1294                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1295 }
1296
1297 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1298                               struct rte_eth_fc_conf *fc_conf)
1299 {
1300         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1301         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1302         struct qed_link_output current_link;
1303         struct qed_link_params params;
1304
1305         memset(&current_link, 0, sizeof(current_link));
1306         qdev->ops->common->get_link(edev, &current_link);
1307
1308         memset(&params, 0, sizeof(params));
1309         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1310         if (fc_conf->autoneg) {
1311                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1312                         DP_ERR(edev, "Autoneg not supported\n");
1313                         return -EINVAL;
1314                 }
1315                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1316         }
1317
1318         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1319         if (fc_conf->mode == RTE_FC_FULL)
1320                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1321                                         QED_LINK_PAUSE_RX_ENABLE);
1322         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1323                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1324         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1325                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1326
1327         params.link_up = true;
1328         (void)qdev->ops->common->set_link(edev, &params);
1329
1330         return 0;
1331 }
1332
1333 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1334                               struct rte_eth_fc_conf *fc_conf)
1335 {
1336         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1337         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1338         struct qed_link_output current_link;
1339
1340         memset(&current_link, 0, sizeof(current_link));
1341         qdev->ops->common->get_link(edev, &current_link);
1342
1343         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1344                 fc_conf->autoneg = true;
1345
1346         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1347                                          QED_LINK_PAUSE_TX_ENABLE))
1348                 fc_conf->mode = RTE_FC_FULL;
1349         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1350                 fc_conf->mode = RTE_FC_RX_PAUSE;
1351         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1352                 fc_conf->mode = RTE_FC_TX_PAUSE;
1353         else
1354                 fc_conf->mode = RTE_FC_NONE;
1355
1356         return 0;
1357 }
1358
1359 static const uint32_t *
1360 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1361 {
1362         static const uint32_t ptypes[] = {
1363                 RTE_PTYPE_L3_IPV4,
1364                 RTE_PTYPE_L3_IPV6,
1365                 RTE_PTYPE_UNKNOWN
1366         };
1367
1368         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1369                 return ptypes;
1370
1371         return NULL;
1372 }
1373
1374 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1375 {
1376         *rss_caps = 0;
1377         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1378         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1379         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1380         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1381         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1382         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1383 }
1384
1385 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1386                                 struct rte_eth_rss_conf *rss_conf)
1387 {
1388         struct qed_update_vport_params vport_update_params;
1389         struct qede_dev *qdev = eth_dev->data->dev_private;
1390         struct ecore_dev *edev = &qdev->edev;
1391         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1392         uint64_t hf = rss_conf->rss_hf;
1393         int i;
1394
1395         memset(&vport_update_params, 0, sizeof(vport_update_params));
1396
1397         if (hf != 0) {
1398                 /* Enable RSS */
1399                 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1400                 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1401                        sizeof(vport_update_params.rss_params));
1402                 if (key)
1403                         memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1404                                rss_conf->rss_key_len);
1405                 vport_update_params.update_rss_flg = 1;
1406                 qdev->rss_enabled = 1;
1407         } else {
1408                 /* Disable RSS */
1409                 qdev->rss_enabled = 0;
1410         }
1411
1412         /* If the mapping doesn't fit any supported, return */
1413         if (qdev->rss_params.rss_caps == 0 && hf != 0)
1414                 return -EINVAL;
1415
1416         DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1417                                 "Enabling RSS" : "Disabling RSS");
1418
1419         vport_update_params.vport_id = 0;
1420
1421         return qdev->ops->vport_update(edev, &vport_update_params);
1422 }
1423
1424 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1425                            struct rte_eth_rss_conf *rss_conf)
1426 {
1427         struct qede_dev *qdev = eth_dev->data->dev_private;
1428         uint64_t hf;
1429
1430         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1431                 return -EINVAL;
1432
1433         if (rss_conf->rss_key)
1434                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1435                        sizeof(qdev->rss_params.rss_key));
1436
1437         hf = 0;
1438         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1439                         ETH_RSS_IPV4 : 0;
1440         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1441                         ETH_RSS_IPV6 : 0;
1442         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1443                         ETH_RSS_IPV6_EX : 0;
1444         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1445                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1446         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1447                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1448         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1449                         ETH_RSS_IPV6_TCP_EX : 0;
1450
1451         rss_conf->rss_hf = hf;
1452
1453         return 0;
1454 }
1455
1456 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1457                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1458                                 uint16_t reta_size)
1459 {
1460         struct qed_update_vport_params vport_update_params;
1461         struct qede_dev *qdev = eth_dev->data->dev_private;
1462         struct ecore_dev *edev = &qdev->edev;
1463         uint16_t i, idx, shift;
1464
1465         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1466                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1467                        reta_size);
1468                 return -EINVAL;
1469         }
1470
1471         memset(&vport_update_params, 0, sizeof(vport_update_params));
1472         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1473                sizeof(vport_update_params.rss_params));
1474
1475         for (i = 0; i < reta_size; i++) {
1476                 idx = i / RTE_RETA_GROUP_SIZE;
1477                 shift = i % RTE_RETA_GROUP_SIZE;
1478                 if (reta_conf[idx].mask & (1ULL << shift)) {
1479                         uint8_t entry = reta_conf[idx].reta[shift];
1480                         qdev->rss_params.rss_ind_table[i] = entry;
1481                 }
1482         }
1483
1484         vport_update_params.update_rss_flg = 1;
1485         vport_update_params.vport_id = 0;
1486
1487         return qdev->ops->vport_update(edev, &vport_update_params);
1488 }
1489
1490 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1491                         struct rte_eth_rss_reta_entry64 *reta_conf,
1492                         uint16_t reta_size)
1493 {
1494         struct qede_dev *qdev = eth_dev->data->dev_private;
1495         uint16_t i, idx, shift;
1496
1497         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1498                 struct ecore_dev *edev = &qdev->edev;
1499                 DP_ERR(edev, "reta_size %d is not supported\n",
1500                        reta_size);
1501         }
1502
1503         for (i = 0; i < reta_size; i++) {
1504                 idx = i / RTE_RETA_GROUP_SIZE;
1505                 shift = i % RTE_RETA_GROUP_SIZE;
1506                 if (reta_conf[idx].mask & (1ULL << shift)) {
1507                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1508                         reta_conf[idx].reta[shift] = entry;
1509                 }
1510         }
1511
1512         return 0;
1513 }
1514
1515 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1516 {
1517         uint32_t frame_size;
1518         struct qede_dev *qdev = dev->data->dev_private;
1519         struct rte_eth_dev_info dev_info = {0};
1520
1521         qede_dev_info_get(dev, &dev_info);
1522
1523         /* VLAN_TAG = 4 */
1524         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1525
1526         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1527                 return -EINVAL;
1528
1529         if (!dev->data->scattered_rx &&
1530             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1531                 return -EINVAL;
1532
1533         if (frame_size > ETHER_MAX_LEN)
1534                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1535         else
1536                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1537
1538         /* update max frame size */
1539         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1540         qdev->mtu = mtu;
1541         qede_dev_stop(dev);
1542         qede_dev_start(dev);
1543
1544         return 0;
1545 }
1546
1547 static int
1548 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1549                        struct rte_eth_udp_tunnel *tunnel_udp,
1550                        bool add)
1551 {
1552         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1553         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1554         struct ecore_tunn_update_params params;
1555         struct ecore_hwfn *p_hwfn;
1556         int rc, i;
1557
1558         PMD_INIT_FUNC_TRACE(edev);
1559
1560         memset(&params, 0, sizeof(params));
1561         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1562                 params.update_vxlan_udp_port = 1;
1563                 params.vxlan_udp_port = (add) ? tunnel_udp->udp_port :
1564                                         QEDE_VXLAN_DEF_PORT;
1565                 for_each_hwfn(edev, i) {
1566                         p_hwfn = &edev->hwfns[i];
1567                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &params,
1568                                                 ECORE_SPQ_MODE_CB, NULL);
1569                         if (rc != ECORE_SUCCESS) {
1570                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1571                                         params.vxlan_udp_port);
1572                                 return rc;
1573                         }
1574                 }
1575         }
1576
1577         return 0;
1578 }
1579
1580 int
1581 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1582                       struct rte_eth_udp_tunnel *tunnel_udp)
1583 {
1584         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1585 }
1586
1587 int
1588 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1589                       struct rte_eth_udp_tunnel *tunnel_udp)
1590 {
1591         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1592 }
1593
1594 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1595                                        uint32_t *clss, char *str)
1596 {
1597         uint16_t j;
1598         *clss = MAX_ECORE_TUNN_CLSS;
1599
1600         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1601                 if (filter == qede_tunn_types[j].rte_filter_type) {
1602                         *type = qede_tunn_types[j].qede_type;
1603                         *clss = qede_tunn_types[j].qede_tunn_clss;
1604                         strcpy(str, qede_tunn_types[j].string);
1605                         return;
1606                 }
1607         }
1608 }
1609
1610 static int
1611 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1612                               const struct rte_eth_tunnel_filter_conf *conf,
1613                               uint32_t type)
1614 {
1615         /* Init commmon ucast params first */
1616         qede_set_ucast_cmn_params(ucast);
1617
1618         /* Copy out the required fields based on classification type */
1619         ucast->type = type;
1620
1621         switch (type) {
1622         case ECORE_FILTER_VNI:
1623                 ucast->vni = conf->tenant_id;
1624         break;
1625         case ECORE_FILTER_INNER_VLAN:
1626                 ucast->vlan = conf->inner_vlan;
1627         break;
1628         case ECORE_FILTER_MAC:
1629                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1630                        ETHER_ADDR_LEN);
1631         break;
1632         case ECORE_FILTER_INNER_MAC:
1633                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1634                        ETHER_ADDR_LEN);
1635         break;
1636         case ECORE_FILTER_MAC_VNI_PAIR:
1637                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1638                         ETHER_ADDR_LEN);
1639                 ucast->vni = conf->tenant_id;
1640         break;
1641         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1642                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1643                         ETHER_ADDR_LEN);
1644                 ucast->vni = conf->tenant_id;
1645         break;
1646         case ECORE_FILTER_INNER_PAIR:
1647                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1648                         ETHER_ADDR_LEN);
1649                 ucast->vlan = conf->inner_vlan;
1650         break;
1651         default:
1652                 return -EINVAL;
1653         }
1654
1655         return ECORE_SUCCESS;
1656 }
1657
1658 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1659                                   enum rte_filter_op filter_op,
1660                                   const struct rte_eth_tunnel_filter_conf *conf)
1661 {
1662         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1663         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1664         struct ecore_tunn_update_params params;
1665         struct ecore_hwfn *p_hwfn;
1666         enum ecore_filter_ucast_type type;
1667         enum ecore_tunn_clss clss;
1668         struct ecore_filter_ucast ucast;
1669         char str[80];
1670         uint16_t filter_type;
1671         int rc, i;
1672
1673         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1674         /* First determine if the given filter classification is supported */
1675         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1676         if (clss == MAX_ECORE_TUNN_CLSS) {
1677                 DP_ERR(edev, "Wrong filter type\n");
1678                 return -EINVAL;
1679         }
1680         /* Init tunnel ucast params */
1681         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1682         if (rc != ECORE_SUCCESS) {
1683                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1684                                 conf->filter_type);
1685                 return rc;
1686         }
1687         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1688                 str, filter_op, ucast.type);
1689         switch (filter_op) {
1690         case RTE_ETH_FILTER_ADD:
1691                 ucast.opcode = ECORE_FILTER_ADD;
1692
1693                 /* Skip MAC/VLAN if filter is based on VNI */
1694                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1695                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1696                         if (rc == 0) {
1697                                 /* Enable accept anyvlan */
1698                                 qede_config_accept_any_vlan(qdev, true);
1699                         }
1700                 } else {
1701                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1702                         if (rc == 0)
1703                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1704                                                     ECORE_SPQ_MODE_CB, NULL);
1705                 }
1706
1707                 if (rc != ECORE_SUCCESS)
1708                         return rc;
1709
1710                 qdev->vxlan_filter_type = filter_type;
1711
1712                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1713                 qede_set_cmn_tunn_param(&params, clss,
1714                                         (1 << ECORE_MODE_VXLAN_TUNN),
1715                                         (1 << ECORE_MODE_VXLAN_TUNN));
1716                 for_each_hwfn(edev, i) {
1717                         p_hwfn = &edev->hwfns[i];
1718                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1719                                 &params, ECORE_SPQ_MODE_CB, NULL);
1720                         if (rc != ECORE_SUCCESS) {
1721                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1722                                         params.tunn_clss_vxlan);
1723                         }
1724                 }
1725                 qdev->num_tunn_filters++; /* Filter added successfully */
1726         break;
1727         case RTE_ETH_FILTER_DELETE:
1728                 ucast.opcode = ECORE_FILTER_REMOVE;
1729
1730                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1731                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1732                 } else {
1733                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1734                         if (rc == 0)
1735                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1736                                                     ECORE_SPQ_MODE_CB, NULL);
1737                 }
1738                 if (rc != ECORE_SUCCESS)
1739                         return rc;
1740
1741                 qdev->vxlan_filter_type = filter_type;
1742                 qdev->num_tunn_filters--;
1743
1744                 /* Disable VXLAN if VXLAN filters become 0 */
1745                 if (qdev->num_tunn_filters == 0) {
1746                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1747
1748                         /* Use 0 as tunnel mode */
1749                         qede_set_cmn_tunn_param(&params, clss, 0,
1750                                                 (1 << ECORE_MODE_VXLAN_TUNN));
1751                         for_each_hwfn(edev, i) {
1752                                 p_hwfn = &edev->hwfns[i];
1753                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1754                                         &params, ECORE_SPQ_MODE_CB, NULL);
1755                                 if (rc != ECORE_SUCCESS) {
1756                                         DP_ERR(edev,
1757                                                 "Failed to update tunn_clss %u\n",
1758                                                 params.tunn_clss_vxlan);
1759                                         break;
1760                                 }
1761                         }
1762                 }
1763         break;
1764         default:
1765                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1766                 return -EINVAL;
1767         }
1768         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1769
1770         return 0;
1771 }
1772
1773 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1774                          enum rte_filter_type filter_type,
1775                          enum rte_filter_op filter_op,
1776                          void *arg)
1777 {
1778         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1779         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1780         struct rte_eth_tunnel_filter_conf *filter_conf =
1781                         (struct rte_eth_tunnel_filter_conf *)arg;
1782
1783         switch (filter_type) {
1784         case RTE_ETH_FILTER_TUNNEL:
1785                 switch (filter_conf->tunnel_type) {
1786                 case RTE_TUNNEL_TYPE_VXLAN:
1787                         DP_INFO(edev,
1788                                 "Packet steering to the specified Rx queue"
1789                                 " is not supported with VXLAN tunneling");
1790                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1791                                                       filter_conf));
1792                 /* Place holders for future tunneling support */
1793                 case RTE_TUNNEL_TYPE_GENEVE:
1794                 case RTE_TUNNEL_TYPE_TEREDO:
1795                 case RTE_TUNNEL_TYPE_NVGRE:
1796                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1797                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1798                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1799                                 filter_conf->tunnel_type);
1800                         return -EINVAL;
1801                 case RTE_TUNNEL_TYPE_NONE:
1802                 default:
1803                         return 0;
1804                 }
1805                 break;
1806         case RTE_ETH_FILTER_FDIR:
1807         case RTE_ETH_FILTER_MACVLAN:
1808         case RTE_ETH_FILTER_ETHERTYPE:
1809         case RTE_ETH_FILTER_FLEXIBLE:
1810         case RTE_ETH_FILTER_SYN:
1811         case RTE_ETH_FILTER_NTUPLE:
1812         case RTE_ETH_FILTER_HASH:
1813         case RTE_ETH_FILTER_L2_TUNNEL:
1814         case RTE_ETH_FILTER_MAX:
1815         default:
1816                 DP_ERR(edev, "Unsupported filter type %d\n",
1817                         filter_type);
1818                 return -EINVAL;
1819         }
1820
1821         return 0;
1822 }
1823
1824 static const struct eth_dev_ops qede_eth_dev_ops = {
1825         .dev_configure = qede_dev_configure,
1826         .dev_infos_get = qede_dev_info_get,
1827         .rx_queue_setup = qede_rx_queue_setup,
1828         .rx_queue_release = qede_rx_queue_release,
1829         .tx_queue_setup = qede_tx_queue_setup,
1830         .tx_queue_release = qede_tx_queue_release,
1831         .dev_start = qede_dev_start,
1832         .dev_set_link_up = qede_dev_set_link_up,
1833         .dev_set_link_down = qede_dev_set_link_down,
1834         .link_update = qede_link_update,
1835         .promiscuous_enable = qede_promiscuous_enable,
1836         .promiscuous_disable = qede_promiscuous_disable,
1837         .allmulticast_enable = qede_allmulticast_enable,
1838         .allmulticast_disable = qede_allmulticast_disable,
1839         .dev_stop = qede_dev_stop,
1840         .dev_close = qede_dev_close,
1841         .stats_get = qede_get_stats,
1842         .stats_reset = qede_reset_stats,
1843         .xstats_get = qede_get_xstats,
1844         .xstats_reset = qede_reset_xstats,
1845         .xstats_get_names = qede_get_xstats_names,
1846         .mac_addr_add = qede_mac_addr_add,
1847         .mac_addr_remove = qede_mac_addr_remove,
1848         .mac_addr_set = qede_mac_addr_set,
1849         .vlan_offload_set = qede_vlan_offload_set,
1850         .vlan_filter_set = qede_vlan_filter_set,
1851         .flow_ctrl_set = qede_flow_ctrl_set,
1852         .flow_ctrl_get = qede_flow_ctrl_get,
1853         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1854         .rss_hash_update = qede_rss_hash_update,
1855         .rss_hash_conf_get = qede_rss_hash_conf_get,
1856         .reta_update  = qede_rss_reta_update,
1857         .reta_query  = qede_rss_reta_query,
1858         .mtu_set = qede_set_mtu,
1859         .filter_ctrl = qede_dev_filter_ctrl,
1860         .udp_tunnel_port_add = qede_udp_dst_port_add,
1861         .udp_tunnel_port_del = qede_udp_dst_port_del,
1862 };
1863
1864 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1865         .dev_configure = qede_dev_configure,
1866         .dev_infos_get = qede_dev_info_get,
1867         .rx_queue_setup = qede_rx_queue_setup,
1868         .rx_queue_release = qede_rx_queue_release,
1869         .tx_queue_setup = qede_tx_queue_setup,
1870         .tx_queue_release = qede_tx_queue_release,
1871         .dev_start = qede_dev_start,
1872         .dev_set_link_up = qede_dev_set_link_up,
1873         .dev_set_link_down = qede_dev_set_link_down,
1874         .link_update = qede_link_update,
1875         .promiscuous_enable = qede_promiscuous_enable,
1876         .promiscuous_disable = qede_promiscuous_disable,
1877         .allmulticast_enable = qede_allmulticast_enable,
1878         .allmulticast_disable = qede_allmulticast_disable,
1879         .dev_stop = qede_dev_stop,
1880         .dev_close = qede_dev_close,
1881         .stats_get = qede_get_stats,
1882         .stats_reset = qede_reset_stats,
1883         .xstats_get = qede_get_xstats,
1884         .xstats_reset = qede_reset_xstats,
1885         .xstats_get_names = qede_get_xstats_names,
1886         .vlan_offload_set = qede_vlan_offload_set,
1887         .vlan_filter_set = qede_vlan_filter_set,
1888         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1889         .rss_hash_update = qede_rss_hash_update,
1890         .rss_hash_conf_get = qede_rss_hash_conf_get,
1891         .reta_update  = qede_rss_reta_update,
1892         .reta_query  = qede_rss_reta_query,
1893         .mtu_set = qede_set_mtu,
1894 };
1895
1896 static void qede_update_pf_params(struct ecore_dev *edev)
1897 {
1898         struct ecore_pf_params pf_params;
1899         /* 32 rx + 32 tx */
1900         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1901         pf_params.eth_pf_params.num_cons = 64;
1902         qed_ops->common->update_pf_params(edev, &pf_params);
1903 }
1904
1905 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1906 {
1907         struct rte_pci_device *pci_dev;
1908         struct rte_pci_addr pci_addr;
1909         struct qede_dev *adapter;
1910         struct ecore_dev *edev;
1911         struct qed_dev_eth_info dev_info;
1912         struct qed_slowpath_params params;
1913         static bool do_once = true;
1914         uint8_t bulletin_change;
1915         uint8_t vf_mac[ETHER_ADDR_LEN];
1916         uint8_t is_mac_forced;
1917         bool is_mac_exist;
1918         /* Fix up ecore debug level */
1919         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1920         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1921         uint32_t max_mac_addrs;
1922         int rc;
1923
1924         /* Extract key data structures */
1925         adapter = eth_dev->data->dev_private;
1926         edev = &adapter->edev;
1927         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1928         pci_addr = pci_dev->addr;
1929
1930         PMD_INIT_FUNC_TRACE(edev);
1931
1932         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1933                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1934                  eth_dev->data->port_id);
1935
1936         eth_dev->rx_pkt_burst = qede_recv_pkts;
1937         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1938
1939         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1940                 DP_NOTICE(edev, false,
1941                           "Skipping device init from secondary process\n");
1942                 return 0;
1943         }
1944
1945         rte_eth_copy_pci_info(eth_dev, pci_dev);
1946
1947         qed_ops = qed_get_eth_ops();
1948         if (!qed_ops) {
1949                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1950                 return -EINVAL;
1951         }
1952
1953         DP_INFO(edev, "Starting qede probe\n");
1954
1955         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1956                                     dp_module, dp_level, is_vf);
1957
1958         if (rc != 0) {
1959                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1960                 return -ENODEV;
1961         }
1962
1963         qede_update_pf_params(edev);
1964
1965         rte_intr_callback_register(&pci_dev->intr_handle,
1966                                    qede_interrupt_handler, (void *)eth_dev);
1967
1968         if (rte_intr_enable(&pci_dev->intr_handle)) {
1969                 DP_ERR(edev, "rte_intr_enable() failed\n");
1970                 return -ENODEV;
1971         }
1972
1973         /* Start the Slowpath-process */
1974         memset(&params, 0, sizeof(struct qed_slowpath_params));
1975         params.int_mode = ECORE_INT_MODE_MSIX;
1976         params.drv_major = QEDE_PMD_VERSION_MAJOR;
1977         params.drv_minor = QEDE_PMD_VERSION_MINOR;
1978         params.drv_rev = QEDE_PMD_VERSION_REVISION;
1979         params.drv_eng = QEDE_PMD_VERSION_PATCH;
1980         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1981                 QEDE_PMD_DRV_VER_STR_SIZE);
1982
1983         /* For CMT mode device do periodic polling for slowpath events.
1984          * This is required since uio device uses only one MSI-x
1985          * interrupt vector but we need one for each engine.
1986          */
1987         if (edev->num_hwfns > 1 && IS_PF(edev)) {
1988                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1989                                        qede_poll_sp_sb_cb,
1990                                        (void *)eth_dev);
1991                 if (rc != 0) {
1992                         DP_ERR(edev, "Unable to start periodic"
1993                                      " timer rc %d\n", rc);
1994                         return -EINVAL;
1995                 }
1996         }
1997
1998         rc = qed_ops->common->slowpath_start(edev, &params);
1999         if (rc) {
2000                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2001                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2002                                      (void *)eth_dev);
2003                 return -ENODEV;
2004         }
2005
2006         rc = qed_ops->fill_dev_info(edev, &dev_info);
2007         if (rc) {
2008                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2009                 qed_ops->common->slowpath_stop(edev);
2010                 qed_ops->common->remove(edev);
2011                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2012                                      (void *)eth_dev);
2013                 return -ENODEV;
2014         }
2015
2016         qede_alloc_etherdev(adapter, &dev_info);
2017
2018         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
2019
2020         if (!is_vf)
2021                 adapter->dev_info.num_mac_addrs =
2022                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2023                                             ECORE_MAC);
2024         else
2025                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2026                                              &adapter->dev_info.num_mac_addrs);
2027
2028         /* Allocate memory for storing MAC addr */
2029         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2030                                         (ETHER_ADDR_LEN *
2031                                         adapter->dev_info.num_mac_addrs),
2032                                         RTE_CACHE_LINE_SIZE);
2033
2034         if (eth_dev->data->mac_addrs == NULL) {
2035                 DP_ERR(edev, "Failed to allocate MAC address\n");
2036                 qed_ops->common->slowpath_stop(edev);
2037                 qed_ops->common->remove(edev);
2038                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2039                                      (void *)eth_dev);
2040                 return -ENOMEM;
2041         }
2042
2043         if (!is_vf) {
2044                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2045                                 hw_info.hw_mac_addr,
2046                                 &eth_dev->data->mac_addrs[0]);
2047                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2048                                 &adapter->primary_mac);
2049         } else {
2050                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2051                                        &bulletin_change);
2052                 if (bulletin_change) {
2053                         is_mac_exist =
2054                             ecore_vf_bulletin_get_forced_mac(
2055                                                 ECORE_LEADING_HWFN(edev),
2056                                                 vf_mac,
2057                                                 &is_mac_forced);
2058                         if (is_mac_exist && is_mac_forced) {
2059                                 DP_INFO(edev, "VF macaddr received from PF\n");
2060                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2061                                                 &eth_dev->data->mac_addrs[0]);
2062                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2063                                                 &adapter->primary_mac);
2064                         } else {
2065                                 DP_NOTICE(edev, false,
2066                                           "No VF macaddr assigned\n");
2067                         }
2068                 }
2069         }
2070
2071         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2072
2073         if (do_once) {
2074                 qede_print_adapter_info(adapter);
2075                 do_once = false;
2076         }
2077
2078         adapter->state = QEDE_DEV_INIT;
2079
2080         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2081                   adapter->primary_mac.addr_bytes[0],
2082                   adapter->primary_mac.addr_bytes[1],
2083                   adapter->primary_mac.addr_bytes[2],
2084                   adapter->primary_mac.addr_bytes[3],
2085                   adapter->primary_mac.addr_bytes[4],
2086                   adapter->primary_mac.addr_bytes[5]);
2087
2088         return rc;
2089 }
2090
2091 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2092 {
2093         return qede_common_dev_init(eth_dev, 1);
2094 }
2095
2096 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2097 {
2098         return qede_common_dev_init(eth_dev, 0);
2099 }
2100
2101 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2102 {
2103         /* only uninitialize in the primary process */
2104         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2105                 return 0;
2106
2107         /* safe to close dev here */
2108         qede_dev_close(eth_dev);
2109
2110         eth_dev->dev_ops = NULL;
2111         eth_dev->rx_pkt_burst = NULL;
2112         eth_dev->tx_pkt_burst = NULL;
2113
2114         if (eth_dev->data->mac_addrs)
2115                 rte_free(eth_dev->data->mac_addrs);
2116
2117         eth_dev->data->mac_addrs = NULL;
2118
2119         return 0;
2120 }
2121
2122 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2123 {
2124         return qede_dev_common_uninit(eth_dev);
2125 }
2126
2127 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2128 {
2129         return qede_dev_common_uninit(eth_dev);
2130 }
2131
2132 static struct rte_pci_id pci_id_qedevf_map[] = {
2133 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2134         {
2135                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
2136         },
2137         {
2138                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
2139         },
2140         {.vendor_id = 0,}
2141 };
2142
2143 static struct rte_pci_id pci_id_qede_map[] = {
2144 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2145         {
2146                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
2147         },
2148         {
2149                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
2150         },
2151         {
2152                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
2153         },
2154         {
2155                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
2156         },
2157         {
2158                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
2159         },
2160         {.vendor_id = 0,}
2161 };
2162
2163 static struct eth_driver rte_qedevf_pmd = {
2164         .pci_drv = {
2165                     .id_table = pci_id_qedevf_map,
2166                     .drv_flags =
2167                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2168                     .probe = rte_eth_dev_pci_probe,
2169                     .remove = rte_eth_dev_pci_remove,
2170                    },
2171         .eth_dev_init = qedevf_eth_dev_init,
2172         .eth_dev_uninit = qedevf_eth_dev_uninit,
2173         .dev_private_size = sizeof(struct qede_dev),
2174 };
2175
2176 static struct eth_driver rte_qede_pmd = {
2177         .pci_drv = {
2178                     .id_table = pci_id_qede_map,
2179                     .drv_flags =
2180                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2181                     .probe = rte_eth_dev_pci_probe,
2182                     .remove = rte_eth_dev_pci_remove,
2183                    },
2184         .eth_dev_init = qede_eth_dev_init,
2185         .eth_dev_uninit = qede_eth_dev_uninit,
2186         .dev_private_size = sizeof(struct qede_dev),
2187 };
2188
2189 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
2190 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2191 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2192 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
2193 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2194 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");