drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(eth_dev->intr_handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329
 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 331 {
 332         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 333         ucast->is_rx_filter = true;
 334         ucast->is_tx_filter = true;
 335         /* ucast->assert_on_error = true; - For debug */
 336 }
 337
 338 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 339                                     uint8_t clss, bool mode, bool mask)
 340 {
 341         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 342         p_tunn->vxlan.b_update_mode = mode;
 343         p_tunn->vxlan.b_mode_enabled = mask;
 344         p_tunn->b_update_rx_cls = true;
 345         p_tunn->b_update_tx_cls = true;
 346         p_tunn->vxlan.tun_cls = clss;
 347 }
 348
 349 static int
 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 351                   bool add)
 352 {
 353         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 354         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 355         struct qede_ucast_entry *tmp = NULL;
 356         struct qede_ucast_entry *u;
 357         struct ether_addr *mac_addr;
 358
 359         mac_addr  = (struct ether_addr *)ucast->mac;
 360         if (add) {
 361                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 362                         if ((memcmp(mac_addr, &tmp->mac,
 363                                     ETHER_ADDR_LEN) == 0) &&
 364                              ucast->vlan == tmp->vlan) {
 365                                 DP_ERR(edev, "Unicast MAC is already added"
 366                                        " with vlan = %u, vni = %u\n",
 367                                        ucast->vlan,  ucast->vni);
 368                                         return -EEXIST;
 369                         }
 370                 }
 371                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 372                                RTE_CACHE_LINE_SIZE);
 373                 if (!u) {
 374                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 375                         return -ENOMEM;
 376                 }
 377                 ether_addr_copy(mac_addr, &u->mac);
 378                 u->vlan = ucast->vlan;
 379                 u->vni = ucast->vni;
 380                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 381                 qdev->num_uc_addr++;
 382         } else {
 383                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 384                         if ((memcmp(mac_addr, &tmp->mac,
 385                                     ETHER_ADDR_LEN) == 0) &&
 386                             ucast->vlan == tmp->vlan      &&
 387                             ucast->vni == tmp->vni)
 388                         break;
 389                 }
 390                 if (tmp == NULL) {
 391                         DP_INFO(edev, "Unicast MAC is not found\n");
 392                         return -EINVAL;
 393                 }
 394                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 395                 qdev->num_uc_addr--;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int
 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 403                   bool add)
 404 {
 405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 407         struct ether_addr *mac_addr;
 408         struct qede_mcast_entry *tmp = NULL;
 409         struct qede_mcast_entry *m;
 410
 411         mac_addr  = (struct ether_addr *)mcast->mac;
 412         if (add) {
 413                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 414                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 415                                 DP_ERR(edev,
 416                                         "Multicast MAC is already added\n");
 417                                 return -EEXIST;
 418                         }
 419                 }
 420                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 421                         RTE_CACHE_LINE_SIZE);
 422                 if (!m) {
 423                         DP_ERR(edev,
 424                                 "Did not allocate memory for mcast\n");
 425                         return -ENOMEM;
 426                 }
 427                 ether_addr_copy(mac_addr, &m->mac);
 428                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 429                 qdev->num_mc_addr++;
 430         } else {
 431                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 432                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 433                                 break;
 434                 }
 435                 if (tmp == NULL) {
 436                         DP_INFO(edev, "Multicast mac is not found\n");
 437                         return -EINVAL;
 438                 }
 439                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 440                              qede_mcast_entry, list);
 441                 qdev->num_mc_addr--;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static enum _ecore_status_t
 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 449                  bool add)
 450 {
 451         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 452         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 453         enum _ecore_status_t rc;
 454         struct ecore_filter_mcast mcast;
 455         struct qede_mcast_entry *tmp;
 456         uint16_t j = 0;
 457
 458         /* Multicast */
 459         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 460                 if (add) {
 461                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 462                                 DP_ERR(edev,
 463                                        "Mcast filter table limit exceeded, "
 464                                        "Please enable mcast promisc mode\n");
 465                                 return -ECORE_INVAL;
 466                         }
 467                 }
 468                 rc = qede_mcast_filter(eth_dev, ucast, add);
 469                 if (rc == 0) {
 470                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 471                         memset(&mcast, 0, sizeof(mcast));
 472                         mcast.num_mc_addrs = qdev->num_mc_addr;
 473                         mcast.opcode = ECORE_FILTER_ADD;
 474                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 475                                 ether_addr_copy(&tmp->mac,
 476                                         (struct ether_addr *)&mcast.mac[j]);
 477                                 j++;
 478                         }
 479                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 480                                                     ECORE_SPQ_MODE_CB, NULL);
 481                 }
 482                 if (rc != ECORE_SUCCESS) {
 483                         DP_ERR(edev, "Failed to add multicast filter"
 484                                " rc = %d, op = %d\n", rc, add);
 485                 }
 486         } else { /* Unicast */
 487                 if (add) {
 488                         if (qdev->num_uc_addr >=
 489                             qdev->dev_info.num_mac_filters) {
 490                                 DP_ERR(edev,
 491                                        "Ucast filter table limit exceeded,"
 492                                        " Please enable promisc mode\n");
 493                                 return -ECORE_INVAL;
 494                         }
 495                 }
 496                 rc = qede_ucast_filter(eth_dev, ucast, add);
 497                 if (rc == 0)
 498                         rc = ecore_filter_ucast_cmd(edev, ucast,
 499                                                     ECORE_SPQ_MODE_CB, NULL);
 500                 if (rc != ECORE_SUCCESS) {
 501                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 502                                rc, add);
 503                 }
 504         }
 505
 506         return rc;
 507 }
 508
 509 static void
 510 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 511                   uint32_t index, __rte_unused uint32_t pool)
 512 {
 513         struct ecore_filter_ucast ucast;
 514
 515         qede_set_ucast_cmn_params(&ucast);
 516         ucast.type = ECORE_FILTER_MAC;
 517         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 518         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 519 }
 520
 521 static void
 522 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 523 {
 524         struct qede_dev *qdev = eth_dev->data->dev_private;
 525         struct ecore_dev *edev = &qdev->edev;
 526         struct ether_addr mac_addr;
 527         struct ecore_filter_ucast ucast;
 528         int rc;
 529
 530         PMD_INIT_FUNC_TRACE(edev);
 531
 532         if (index >= qdev->dev_info.num_mac_filters) {
 533                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 534                        index, qdev->dev_info.num_mac_filters);
 535                 return;
 536         }
 537
 538         qede_set_ucast_cmn_params(&ucast);
 539         ucast.opcode = ECORE_FILTER_REMOVE;
 540         ucast.type = ECORE_FILTER_MAC;
 541
 542         /* Use the index maintained by rte */
 543         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 544                         (struct ether_addr *)&ucast.mac);
 545
 546         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 547 }
 548
 549 static void
 550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 551 {
 552         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 553         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 554
 555         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 556                                                mac_addr->addr_bytes)) {
 557                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 558                 ether_addr_copy(&qdev->primary_mac,
 559                                 &eth_dev->data->mac_addrs[0]);
 560                 return;
 561         }
 562
 563         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 564 }
 565
 566 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 567 {
 568         struct ecore_dev *edev = &qdev->edev;
 569         struct qed_update_vport_params params = {
 570                 .vport_id = 0,
 571                 .accept_any_vlan = action,
 572                 .update_accept_any_vlan_flg = 1,
 573         };
 574         int rc;
 575
 576         /* Proceed only if action actually needs to be performed */
 577         if (qdev->accept_any_vlan == action)
 578                 return;
 579
 580         rc = qdev->ops->vport_update(edev, &params);
 581         if (rc) {
 582                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 583                        action ? "enable" : "disable");
 584         } else {
 585                 DP_INFO(edev, "%s accept-any-vlan\n",
 586                         action ? "enabled" : "disabled");
 587                 qdev->accept_any_vlan = action;
 588         }
 589 }
 590
 591 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 592 {
 593         struct qed_update_vport_params vport_update_params;
 594         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 595         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 596         int rc;
 597
 598         memset(&vport_update_params, 0, sizeof(vport_update_params));
 599         vport_update_params.vport_id = 0;
 600         vport_update_params.update_inner_vlan_removal_flg = 1;
 601         vport_update_params.inner_vlan_removal_flg = set_stripping;
 602         rc = qdev->ops->vport_update(edev, &vport_update_params);
 603         if (rc) {
 604                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 605                 return rc;
 606         }
 607
 608         return 0;
 609 }
 610
 611 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 612 {
 613         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 614         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 615         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 616
 617         if (mask & ETH_VLAN_STRIP_MASK) {
 618                 if (rxmode->hw_vlan_strip)
 619                         (void)qede_vlan_stripping(eth_dev, 1);
 620                 else
 621                         (void)qede_vlan_stripping(eth_dev, 0);
 622         }
 623
 624         if (mask & ETH_VLAN_FILTER_MASK) {
 625                 /* VLAN filtering kicks in when a VLAN is added */
 626                 if (rxmode->hw_vlan_filter) {
 627                         qede_vlan_filter_set(eth_dev, 0, 1);
 628                 } else {
 629                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 630                                 DP_ERR(edev,
 631                                   " Please remove existing VLAN filters"
 632                                   " before disabling VLAN filtering\n");
 633                                 /* Signal app that VLAN filtering is still
 634                                  * enabled
 635                                  */
 636                                 rxmode->hw_vlan_filter = true;
 637                         } else {
 638                                 qede_vlan_filter_set(eth_dev, 0, 0);
 639                         }
 640                 }
 641         }
 642
 643         if (mask & ETH_VLAN_EXTEND_MASK)
 644                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 645                         " and classification is based on outer tag only\n");
 646
 647         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 648                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 649 }
 650
 651 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 652                                 uint16_t vlan_id, int on)
 653 {
 654         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 655         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 656         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 657         struct qede_vlan_entry *tmp = NULL;
 658         struct qede_vlan_entry *vlan;
 659         struct ecore_filter_ucast ucast;
 660         int rc;
 661
 662         if (on) {
 663                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 664                         DP_ERR(edev, "Reached max VLAN filter limit"
 665                                       " enabling accept_any_vlan\n");
 666                         qede_config_accept_any_vlan(qdev, true);
 667                         return 0;
 668                 }
 669
 670                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 671                         if (tmp->vid == vlan_id) {
 672                                 DP_ERR(edev, "VLAN %u already configured\n",
 673                                        vlan_id);
 674                                 return -EEXIST;
 675                         }
 676                 }
 677
 678                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 679                                   RTE_CACHE_LINE_SIZE);
 680
 681                 if (!vlan) {
 682                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 683                         return -ENOMEM;
 684                 }
 685
 686                 qede_set_ucast_cmn_params(&ucast);
 687                 ucast.opcode = ECORE_FILTER_ADD;
 688                 ucast.type = ECORE_FILTER_VLAN;
 689                 ucast.vlan = vlan_id;
 690                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 691                                             NULL);
 692                 if (rc != 0) {
 693                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 694                                rc);
 695                         rte_free(vlan);
 696                 } else {
 697                         vlan->vid = vlan_id;
 698                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 699                         qdev->configured_vlans++;
 700                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 701                                 vlan_id, qdev->configured_vlans);
 702                 }
 703         } else {
 704                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 705                         if (tmp->vid == vlan_id)
 706                                 break;
 707                 }
 708
 709                 if (!tmp) {
 710                         if (qdev->configured_vlans == 0) {
 711                                 DP_INFO(edev,
 712                                         "No VLAN filters configured yet\n");
 713                                 return 0;
 714                         }
 715
 716                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 717                         return -EINVAL;
 718                 }
 719
 720                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 721
 722                 qede_set_ucast_cmn_params(&ucast);
 723                 ucast.opcode = ECORE_FILTER_REMOVE;
 724                 ucast.type = ECORE_FILTER_VLAN;
 725                 ucast.vlan = vlan_id;
 726                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 727                                             NULL);
 728                 if (rc != 0) {
 729                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 730                                vlan_id, rc);
 731                 } else {
 732                         qdev->configured_vlans--;
 733                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 734                                 vlan_id, qdev->configured_vlans);
 735                 }
 736         }
 737
 738         return rc;
 739 }
 740
 741 static int qede_init_vport(struct qede_dev *qdev)
 742 {
 743         struct ecore_dev *edev = &qdev->edev;
 744         struct qed_start_vport_params start = {0};
 745         int rc;
 746
 747         start.remove_inner_vlan = 1;
 748         start.enable_lro = qdev->enable_lro;
 749         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 750         start.vport_id = 0;
 751         start.drop_ttl0 = false;
 752         start.clear_stats = 1;
 753         start.handle_ptp_pkts = 0;
 754
 755         rc = qdev->ops->vport_start(edev, &start);
 756         if (rc) {
 757                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 758                 return rc;
 759         }
 760
 761         DP_INFO(edev,
 762                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 763                 start.vport_id, ETHER_MTU);
 764
 765         return 0;
 766 }
 767
 768 static void qede_prandom_bytes(uint32_t *buff)
 769 {
 770         uint8_t i;
 771
 772         srand((unsigned int)time(NULL));
 773         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 774                 buff[i] = rand();
 775 }
 776
 777 int qede_config_rss(struct rte_eth_dev *eth_dev)
 778 {
 779         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 780         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 781         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 782         struct rte_eth_rss_reta_entry64 reta_conf[2];
 783         struct rte_eth_rss_conf rss_conf;
 784         uint32_t i, id, pos, q;
 785
 786         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 787         if (!rss_conf.rss_key) {
 788                 DP_INFO(edev, "Applying driver default key\n");
 789                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 790                 qede_prandom_bytes(&def_rss_key[0]);
 791                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 792         }
 793
 794         /* Configure RSS hash */
 795         if (qede_rss_hash_update(eth_dev, &rss_conf))
 796                 return -EINVAL;
 797
 798         /* Configure default RETA */
 799         memset(reta_conf, 0, sizeof(reta_conf));
 800         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 801                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 802
 803         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 804                 id = i / RTE_RETA_GROUP_SIZE;
 805                 pos = i % RTE_RETA_GROUP_SIZE;
 806                 q = i % QEDE_RSS_COUNT(qdev);
 807                 reta_conf[id].reta[pos] = q;
 808         }
 809         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 810                                  ECORE_RSS_IND_TABLE_SIZE))
 811                 return -EINVAL;
 812
 813         return 0;
 814 }
 815
 816 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 817 {
 818         struct qede_dev *qdev = eth_dev->data->dev_private;
 819         struct ecore_dev *edev = &qdev->edev;
 820         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 821         int rc, i, j;
 822
 823         PMD_INIT_FUNC_TRACE(edev);
 824
 825         /* Check requirements for 100G mode */
 826         if (edev->num_hwfns > 1) {
 827                 if (eth_dev->data->nb_rx_queues < 2 ||
 828                     eth_dev->data->nb_tx_queues < 2) {
 829                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
 830                         return -EINVAL;
 831                 }
 832
 833                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 834                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 835                         DP_ERR(edev,
 836                                   "100G mode needs even no. of RX/TX queues\n");
 837                         return -EINVAL;
 838                 }
 839         }
 840
 841         /* Sanity checks and throw warnings */
 842         if (rxmode->enable_scatter == 1)
 843                 eth_dev->data->scattered_rx = 1;
 844
 845         if (!rxmode->hw_strip_crc)
 846                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 847
 848         if (!rxmode->hw_ip_checksum)
 849                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 850                               "in hw\n");
 851
 852         if (rxmode->enable_lro) {
 853                 qdev->enable_lro = true;
 854                 /* Enable scatter mode for LRO */
 855                 if (!rxmode->enable_scatter)
 856                         eth_dev->data->scattered_rx = 1;
 857         }
 858
 859         /* Check for the port restart case */
 860         if (qdev->state != QEDE_DEV_INIT) {
 861                 rc = qdev->ops->vport_stop(edev, 0);
 862                 if (rc != 0)
 863                         return rc;
 864                 qede_dealloc_fp_resc(eth_dev);
 865         }
 866
 867         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 868         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 869         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 870
 871         /* Fastpath status block should be initialized before sending
 872          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 873          */
 874         rc = qede_alloc_fp_resc(qdev);
 875         if (rc != 0)
 876                 return rc;
 877
 878         /* Issue VPORT-START with default config values to allow
 879          * other port configurations early on.
 880          */
 881         rc = qede_init_vport(qdev);
 882         if (rc != 0)
 883                 return rc;
 884
 885         if (!(rxmode->mq_mode == ETH_MQ_RX_RSS ||
 886             rxmode->mq_mode == ETH_MQ_RX_NONE)) {
 887                 DP_ERR(edev, "Unsupported RSS mode\n");
 888                 qdev->ops->vport_stop(edev, 0);
 889                 qede_dealloc_fp_resc(eth_dev);
 890                 return -EINVAL;
 891         }
 892
 893         /* Flow director mode check */
 894         rc = qede_check_fdir_support(eth_dev);
 895         if (rc) {
 896                 qdev->ops->vport_stop(edev, 0);
 897                 qede_dealloc_fp_resc(eth_dev);
 898                 return -EINVAL;
 899         }
 900         SLIST_INIT(&qdev->fdir_info.fdir_list_head);
 901
 902         SLIST_INIT(&qdev->vlan_list_head);
 903
 904         /* Enable VLAN offloads by default */
 905         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 906                                        ETH_VLAN_FILTER_MASK |
 907                                        ETH_VLAN_EXTEND_MASK);
 908
 909         qdev->state = QEDE_DEV_CONFIG;
 910
 911         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 912                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 913                 qdev->num_tc);
 914
 915         return 0;
 916 }
 917
 918 /* Info about HW descriptor ring limitations */
 919 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 920         .nb_max = NUM_RX_BDS_MAX,
 921         .nb_min = 128,
 922         .nb_align = 128 /* lowest common multiple */
 923 };
 924
 925 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 926         .nb_max = NUM_TX_BDS_MAX,
 927         .nb_min = 256,
 928         .nb_align = 256,
 929         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
 930         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
 931 };
 932
 933 static void
 934 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 935                   struct rte_eth_dev_info *dev_info)
 936 {
 937         struct qede_dev *qdev = eth_dev->data->dev_private;
 938         struct ecore_dev *edev = &qdev->edev;
 939         struct qed_link_output link;
 940         uint32_t speed_cap = 0;
 941
 942         PMD_INIT_FUNC_TRACE(edev);
 943
 944         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 945         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
 946         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 947         dev_info->rx_desc_lim = qede_rx_desc_lim;
 948         dev_info->tx_desc_lim = qede_tx_desc_lim;
 949
 950         if (IS_PF(edev))
 951                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 952                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
 953         else
 954                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 955                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
 956         dev_info->max_tx_queues = dev_info->max_rx_queues;
 957
 958         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
 959         dev_info->max_vfs = 0;
 960         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 961         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 962         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 963
 964         dev_info->default_txconf = (struct rte_eth_txconf) {
 965                 .txq_flags = QEDE_TXQ_FLAGS,
 966         };
 967
 968         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 969                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 970                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 971                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 972                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 973                                      DEV_RX_OFFLOAD_TCP_LRO);
 974
 975         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 976                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 977                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
 978                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
 979                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 980                                      DEV_TX_OFFLOAD_TCP_TSO |
 981                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
 982
 983         memset(&link, 0, sizeof(struct qed_link_output));
 984         qdev->ops->common->get_link(edev, &link);
 985         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 986                 speed_cap |= ETH_LINK_SPEED_1G;
 987         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 988                 speed_cap |= ETH_LINK_SPEED_10G;
 989         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 990                 speed_cap |= ETH_LINK_SPEED_25G;
 991         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 992                 speed_cap |= ETH_LINK_SPEED_40G;
 993         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 994                 speed_cap |= ETH_LINK_SPEED_50G;
 995         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 996                 speed_cap |= ETH_LINK_SPEED_100G;
 997         dev_info->speed_capa = speed_cap;
 998 }
 999
1000 /* return 0 means link status changed, -1 means not changed */
1001 static int
1002 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1003 {
1004         struct qede_dev *qdev = eth_dev->data->dev_private;
1005         struct ecore_dev *edev = &qdev->edev;
1006         uint16_t link_duplex;
1007         struct qed_link_output link;
1008         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1009
1010         memset(&link, 0, sizeof(struct qed_link_output));
1011         qdev->ops->common->get_link(edev, &link);
1012
1013         /* Link Speed */
1014         curr->link_speed = link.speed;
1015
1016         /* Link Mode */
1017         switch (link.duplex) {
1018         case QEDE_DUPLEX_HALF:
1019                 link_duplex = ETH_LINK_HALF_DUPLEX;
1020                 break;
1021         case QEDE_DUPLEX_FULL:
1022                 link_duplex = ETH_LINK_FULL_DUPLEX;
1023                 break;
1024         case QEDE_DUPLEX_UNKNOWN:
1025         default:
1026                 link_duplex = -1;
1027         }
1028         curr->link_duplex = link_duplex;
1029
1030         /* Link Status */
1031         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1032
1033         /* AN */
1034         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1035                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1036
1037         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1038                 curr->link_speed, curr->link_duplex,
1039                 curr->link_autoneg, curr->link_status);
1040
1041         /* return 0 means link status changed, -1 means not changed */
1042         return ((curr->link_status == link.link_up) ? -1 : 0);
1043 }
1044
1045 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1046 {
1047         struct qede_dev *qdev = eth_dev->data->dev_private;
1048         struct ecore_dev *edev = &qdev->edev;
1049
1050         PMD_INIT_FUNC_TRACE(edev);
1051
1052         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1053
1054         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1055                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1056
1057         qed_configure_filter_rx_mode(eth_dev, type);
1058 }
1059
1060 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1061 {
1062         struct qede_dev *qdev = eth_dev->data->dev_private;
1063         struct ecore_dev *edev = &qdev->edev;
1064
1065         PMD_INIT_FUNC_TRACE(edev);
1066
1067         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1068                 qed_configure_filter_rx_mode(eth_dev,
1069                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1070         else
1071                 qed_configure_filter_rx_mode(eth_dev,
1072                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1073 }
1074
1075 static void qede_poll_sp_sb_cb(void *param)
1076 {
1077         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1078         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1079         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1080         int rc;
1081
1082         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1083         qede_interrupt_action(&edev->hwfns[1]);
1084
1085         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1086                                qede_poll_sp_sb_cb,
1087                                (void *)eth_dev);
1088         if (rc != 0) {
1089                 DP_ERR(edev, "Unable to start periodic"
1090                              " timer rc %d\n", rc);
1091                 assert(false && "Unable to start periodic timer");
1092         }
1093 }
1094
1095 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1096 {
1097         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1098         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1099         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1100         int rc;
1101
1102         PMD_INIT_FUNC_TRACE(edev);
1103
1104         qede_fdir_dealloc_resc(eth_dev);
1105
1106         /* dev_stop() shall cleanup fp resources in hw but without releasing
1107          * dma memories and sw structures so that dev_start() can be called
1108          * by the app without reconfiguration. However, in dev_close() we
1109          * can release all the resources and device can be brought up newly
1110          */
1111         if (qdev->state != QEDE_DEV_STOP)
1112                 qede_dev_stop(eth_dev);
1113         else
1114                 DP_INFO(edev, "Device is already stopped\n");
1115
1116         rc = qdev->ops->vport_stop(edev, 0);
1117         if (rc != 0)
1118                 DP_ERR(edev, "Failed to stop VPORT\n");
1119
1120         qede_dealloc_fp_resc(eth_dev);
1121
1122         qdev->ops->common->slowpath_stop(edev);
1123
1124         qdev->ops->common->remove(edev);
1125
1126         rte_intr_disable(&pci_dev->intr_handle);
1127
1128         rte_intr_callback_unregister(&pci_dev->intr_handle,
1129                                      qede_interrupt_handler, (void *)eth_dev);
1130
1131         if (edev->num_hwfns > 1)
1132                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1133
1134         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1135 }
1136
1137 static void
1138 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1139 {
1140         struct qede_dev *qdev = eth_dev->data->dev_private;
1141         struct ecore_dev *edev = &qdev->edev;
1142         struct ecore_eth_stats stats;
1143         unsigned int i = 0, j = 0, qid;
1144         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1145         struct qede_tx_queue *txq;
1146
1147         qdev->ops->get_vport_stats(edev, &stats);
1148
1149         /* RX Stats */
1150         eth_stats->ipackets = stats.rx_ucast_pkts +
1151             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1152
1153         eth_stats->ibytes = stats.rx_ucast_bytes +
1154             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1155
1156         eth_stats->ierrors = stats.rx_crc_errors +
1157             stats.rx_align_errors +
1158             stats.rx_carrier_errors +
1159             stats.rx_oversize_packets +
1160             stats.rx_jabbers + stats.rx_undersize_packets;
1161
1162         eth_stats->rx_nombuf = stats.no_buff_discards;
1163
1164         eth_stats->imissed = stats.mftag_filter_discards +
1165             stats.mac_filter_discards +
1166             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1167
1168         /* TX stats */
1169         eth_stats->opackets = stats.tx_ucast_pkts +
1170             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1171
1172         eth_stats->obytes = stats.tx_ucast_bytes +
1173             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1174
1175         eth_stats->oerrors = stats.tx_err_drop_pkts;
1176
1177         /* Queue stats */
1178         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1179                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1180         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1181                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1182         if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
1183             (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
1184                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1185                        "Not all the queue stats will be displayed. Set"
1186                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1187                        " appropriately and retry.\n");
1188
1189         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1190                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1191                         eth_stats->q_ipackets[i] =
1192                                 *(uint64_t *)(
1193                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1194                                         offsetof(struct qede_rx_queue,
1195                                         rcv_pkts));
1196                         eth_stats->q_errors[i] =
1197                                 *(uint64_t *)(
1198                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1199                                         offsetof(struct qede_rx_queue,
1200                                         rx_hw_errors)) +
1201                                 *(uint64_t *)(
1202                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1203                                         offsetof(struct qede_rx_queue,
1204                                         rx_alloc_errors));
1205                         i++;
1206                 }
1207                 if (i == rxq_stat_cntrs)
1208                         break;
1209         }
1210
1211         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1212                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1213                         txq = qdev->fp_array[(qid)].txqs[0];
1214                         eth_stats->q_opackets[j] =
1215                                 *((uint64_t *)(uintptr_t)
1216                                         (((uint64_t)(uintptr_t)(txq)) +
1217                                          offsetof(struct qede_tx_queue,
1218                                                   xmit_pkts)));
1219                         j++;
1220                 }
1221                 if (j == txq_stat_cntrs)
1222                         break;
1223         }
1224 }
1225
1226 static unsigned
1227 qede_get_xstats_count(struct qede_dev *qdev) {
1228         return RTE_DIM(qede_xstats_strings) +
1229                 (RTE_DIM(qede_rxq_xstats_strings) *
1230                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1231                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1232 }
1233
1234 static int
1235 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1236                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1237 {
1238         struct qede_dev *qdev = dev->data->dev_private;
1239         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1240         unsigned int i, qid, stat_idx = 0;
1241         unsigned int rxq_stat_cntrs;
1242
1243         if (xstats_names != NULL) {
1244                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1245                         snprintf(xstats_names[stat_idx].name,
1246                                 sizeof(xstats_names[stat_idx].name),
1247                                 "%s",
1248                                 qede_xstats_strings[i].name);
1249                         stat_idx++;
1250                 }
1251
1252                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1253                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1254                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1255                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1256                                 snprintf(xstats_names[stat_idx].name,
1257                                         sizeof(xstats_names[stat_idx].name),
1258                                         "%.4s%d%s",
1259                                         qede_rxq_xstats_strings[i].name, qid,
1260                                         qede_rxq_xstats_strings[i].name + 4);
1261                                 stat_idx++;
1262                         }
1263                 }
1264         }
1265
1266         return stat_cnt;
1267 }
1268
1269 static int
1270 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1271                 unsigned int n)
1272 {
1273         struct qede_dev *qdev = dev->data->dev_private;
1274         struct ecore_dev *edev = &qdev->edev;
1275         struct ecore_eth_stats stats;
1276         const unsigned int num = qede_get_xstats_count(qdev);
1277         unsigned int i, qid, stat_idx = 0;
1278         unsigned int rxq_stat_cntrs;
1279
1280         if (n < num)
1281                 return num;
1282
1283         qdev->ops->get_vport_stats(edev, &stats);
1284
1285         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1286                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1287                                              qede_xstats_strings[i].offset);
1288                 xstats[stat_idx].id = stat_idx;
1289                 stat_idx++;
1290         }
1291
1292         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1293                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1294         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1295                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1296                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1297                                 xstats[stat_idx].value = *(uint64_t *)(
1298                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1299                                          qede_rxq_xstats_strings[i].offset);
1300                                 xstats[stat_idx].id = stat_idx;
1301                                 stat_idx++;
1302                         }
1303                 }
1304         }
1305
1306         return stat_idx;
1307 }
1308
1309 static void
1310 qede_reset_xstats(struct rte_eth_dev *dev)
1311 {
1312         struct qede_dev *qdev = dev->data->dev_private;
1313         struct ecore_dev *edev = &qdev->edev;
1314
1315         ecore_reset_vport_stats(edev);
1316 }
1317
1318 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1319 {
1320         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1321         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1322         struct qed_link_params link_params;
1323         int rc;
1324
1325         DP_INFO(edev, "setting link state %d\n", link_up);
1326         memset(&link_params, 0, sizeof(link_params));
1327         link_params.link_up = link_up;
1328         rc = qdev->ops->common->set_link(edev, &link_params);
1329         if (rc != ECORE_SUCCESS)
1330                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1331
1332         return rc;
1333 }
1334
1335 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1336 {
1337         return qede_dev_set_link_state(eth_dev, true);
1338 }
1339
1340 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1341 {
1342         return qede_dev_set_link_state(eth_dev, false);
1343 }
1344
1345 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1346 {
1347         struct qede_dev *qdev = eth_dev->data->dev_private;
1348         struct ecore_dev *edev = &qdev->edev;
1349
1350         ecore_reset_vport_stats(edev);
1351 }
1352
1353 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1354 {
1355         enum qed_filter_rx_mode_type type =
1356             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1357
1358         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1359                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1360
1361         qed_configure_filter_rx_mode(eth_dev, type);
1362 }
1363
1364 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1365 {
1366         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1367                 qed_configure_filter_rx_mode(eth_dev,
1368                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1369         else
1370                 qed_configure_filter_rx_mode(eth_dev,
1371                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1372 }
1373
1374 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1375                               struct rte_eth_fc_conf *fc_conf)
1376 {
1377         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1378         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1379         struct qed_link_output current_link;
1380         struct qed_link_params params;
1381
1382         memset(&current_link, 0, sizeof(current_link));
1383         qdev->ops->common->get_link(edev, &current_link);
1384
1385         memset(&params, 0, sizeof(params));
1386         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1387         if (fc_conf->autoneg) {
1388                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1389                         DP_ERR(edev, "Autoneg not supported\n");
1390                         return -EINVAL;
1391                 }
1392                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1393         }
1394
1395         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1396         if (fc_conf->mode == RTE_FC_FULL)
1397                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1398                                         QED_LINK_PAUSE_RX_ENABLE);
1399         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1400                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1401         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1402                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1403
1404         params.link_up = true;
1405         (void)qdev->ops->common->set_link(edev, &params);
1406
1407         return 0;
1408 }
1409
1410 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1411                               struct rte_eth_fc_conf *fc_conf)
1412 {
1413         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1414         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1415         struct qed_link_output current_link;
1416
1417         memset(&current_link, 0, sizeof(current_link));
1418         qdev->ops->common->get_link(edev, &current_link);
1419
1420         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1421                 fc_conf->autoneg = true;
1422
1423         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1424                                          QED_LINK_PAUSE_TX_ENABLE))
1425                 fc_conf->mode = RTE_FC_FULL;
1426         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1427                 fc_conf->mode = RTE_FC_RX_PAUSE;
1428         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1429                 fc_conf->mode = RTE_FC_TX_PAUSE;
1430         else
1431                 fc_conf->mode = RTE_FC_NONE;
1432
1433         return 0;
1434 }
1435
1436 static const uint32_t *
1437 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1438 {
1439         static const uint32_t ptypes[] = {
1440                 RTE_PTYPE_L3_IPV4,
1441                 RTE_PTYPE_L3_IPV6,
1442                 RTE_PTYPE_UNKNOWN
1443         };
1444
1445         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1446                 return ptypes;
1447
1448         return NULL;
1449 }
1450
1451 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1452 {
1453         *rss_caps = 0;
1454         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1455         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1456         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1457         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1458         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1459         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1460         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1461         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1462 }
1463
1464 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1465                                 struct rte_eth_rss_conf *rss_conf)
1466 {
1467         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1468         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1469         struct ecore_sp_vport_update_params vport_update_params;
1470         struct ecore_rss_params rss_params;
1471         struct ecore_hwfn *p_hwfn;
1472         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1473         uint64_t hf = rss_conf->rss_hf;
1474         uint8_t len = rss_conf->rss_key_len;
1475         uint8_t idx;
1476         uint8_t i;
1477         int rc;
1478
1479         memset(&vport_update_params, 0, sizeof(vport_update_params));
1480         memset(&rss_params, 0, sizeof(rss_params));
1481
1482         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1483                 (unsigned long)hf, len, key);
1484
1485         if (hf != 0) {
1486                 /* Enabling RSS */
1487                 DP_INFO(edev, "Enabling rss\n");
1488
1489                 /* RSS caps */
1490                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1491                 rss_params.update_rss_capabilities = 1;
1492
1493                 /* RSS hash key */
1494                 if (key) {
1495                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1496                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1497                                 return -EINVAL;
1498                         }
1499                         DP_INFO(edev, "Applying user supplied hash key\n");
1500                         rss_params.update_rss_key = 1;
1501                         memcpy(&rss_params.rss_key, key, len);
1502                 }
1503                 rss_params.rss_enable = 1;
1504         }
1505
1506         rss_params.update_rss_config = 1;
1507         /* tbl_size has to be set with capabilities */
1508         rss_params.rss_table_size_log = 7;
1509         vport_update_params.vport_id = 0;
1510         /* pass the L2 handles instead of qids */
1511         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1512                 idx = qdev->rss_ind_table[i];
1513                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1514         }
1515         vport_update_params.rss_params = &rss_params;
1516
1517         for_each_hwfn(edev, i) {
1518                 p_hwfn = &edev->hwfns[i];
1519                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1520                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1521                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1522                 if (rc) {
1523                         DP_ERR(edev, "vport-update for RSS failed\n");
1524                         return rc;
1525                 }
1526         }
1527         qdev->rss_enable = rss_params.rss_enable;
1528
1529         /* Update local structure for hash query */
1530         qdev->rss_conf.rss_hf = hf;
1531         qdev->rss_conf.rss_key_len = len;
1532         if (qdev->rss_enable) {
1533                 if  (qdev->rss_conf.rss_key == NULL) {
1534                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1535                         if (qdev->rss_conf.rss_key == NULL) {
1536                                 DP_ERR(edev, "No memory to store RSS key\n");
1537                                 return -ENOMEM;
1538                         }
1539                 }
1540                 if (key && len) {
1541                         DP_INFO(edev, "Storing RSS key\n");
1542                         memcpy(qdev->rss_conf.rss_key, key, len);
1543                 }
1544         } else if (!qdev->rss_enable && len == 0) {
1545                 if (qdev->rss_conf.rss_key) {
1546                         free(qdev->rss_conf.rss_key);
1547                         qdev->rss_conf.rss_key = NULL;
1548                         DP_INFO(edev, "Free RSS key\n");
1549                 }
1550         }
1551
1552         return 0;
1553 }
1554
1555 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1556                            struct rte_eth_rss_conf *rss_conf)
1557 {
1558         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1559
1560         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1561         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1562
1563         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1564                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1565                        rss_conf->rss_key_len);
1566         return 0;
1567 }
1568
1569 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1570                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1571                                 uint16_t reta_size)
1572 {
1573         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1574         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1575         struct ecore_sp_vport_update_params vport_update_params;
1576         struct ecore_rss_params params;
1577         struct ecore_hwfn *p_hwfn;
1578         uint16_t i, idx, shift;
1579         uint8_t entry;
1580         int rc;
1581
1582         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1583                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1584                        reta_size);
1585                 return -EINVAL;
1586         }
1587
1588         memset(&vport_update_params, 0, sizeof(vport_update_params));
1589         memset(&params, 0, sizeof(params));
1590
1591         for (i = 0; i < reta_size; i++) {
1592                 idx = i / RTE_RETA_GROUP_SIZE;
1593                 shift = i % RTE_RETA_GROUP_SIZE;
1594                 if (reta_conf[idx].mask & (1ULL << shift)) {
1595                         entry = reta_conf[idx].reta[shift];
1596                         /* Pass rxq handles to ecore */
1597                         params.rss_ind_table[i] =
1598                                         qdev->fp_array[entry].rxq->handle;
1599                         /* Update the local copy for RETA query command */
1600                         qdev->rss_ind_table[i] = entry;
1601                 }
1602         }
1603
1604         /* Fix up RETA for CMT mode device */
1605         if (edev->num_hwfns > 1)
1606                 qdev->rss_enable = qed_update_rss_parm_cmt(edev,
1607                                         params.rss_ind_table[0]);
1608         params.update_rss_ind_table = 1;
1609         params.rss_table_size_log = 7;
1610         params.update_rss_config = 1;
1611         vport_update_params.vport_id = 0;
1612         /* Use the current value of rss_enable */
1613         params.rss_enable = qdev->rss_enable;
1614         vport_update_params.rss_params = &params;
1615
1616         for_each_hwfn(edev, i) {
1617                 p_hwfn = &edev->hwfns[i];
1618                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1619                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1620                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1621                 if (rc) {
1622                         DP_ERR(edev, "vport-update for RSS failed\n");
1623                         return rc;
1624                 }
1625         }
1626
1627         return 0;
1628 }
1629
1630 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1631                                struct rte_eth_rss_reta_entry64 *reta_conf,
1632                                uint16_t reta_size)
1633 {
1634         struct qede_dev *qdev = eth_dev->data->dev_private;
1635         struct ecore_dev *edev = &qdev->edev;
1636         uint16_t i, idx, shift;
1637         uint8_t entry;
1638
1639         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1640                 DP_ERR(edev, "reta_size %d is not supported\n",
1641                        reta_size);
1642                 return -EINVAL;
1643         }
1644
1645         for (i = 0; i < reta_size; i++) {
1646                 idx = i / RTE_RETA_GROUP_SIZE;
1647                 shift = i % RTE_RETA_GROUP_SIZE;
1648                 if (reta_conf[idx].mask & (1ULL << shift)) {
1649                         entry = qdev->rss_ind_table[i];
1650                         reta_conf[idx].reta[shift] = entry;
1651                 }
1652         }
1653
1654         return 0;
1655 }
1656
1657 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1658 {
1659         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1660         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1661         struct rte_eth_dev_info dev_info = {0};
1662         struct qede_fastpath *fp;
1663         uint32_t frame_size;
1664         uint16_t rx_buf_size;
1665         uint16_t bufsz;
1666         int i;
1667
1668         PMD_INIT_FUNC_TRACE(edev);
1669         qede_dev_info_get(dev, &dev_info);
1670         frame_size = mtu + QEDE_ETH_OVERHEAD;
1671         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1672                 DP_ERR(edev, "MTU %u out of range\n", mtu);
1673                 return -EINVAL;
1674         }
1675         if (!dev->data->scattered_rx &&
1676             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1677                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1678                         dev->data->min_rx_buf_size);
1679                 return -EINVAL;
1680         }
1681         /* Temporarily replace I/O functions with dummy ones. It cannot
1682          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1683          */
1684         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1685         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1686         qede_dev_stop(dev);
1687         rte_delay_ms(1000);
1688         qdev->mtu = mtu;
1689         /* Fix up RX buf size for all queues of the port */
1690         for_each_queue(i) {
1691                 fp = &qdev->fp_array[i];
1692                 if (fp->type & QEDE_FASTPATH_RX) {
1693                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1694                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1695                         if (dev->data->scattered_rx)
1696                                 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
1697                         else
1698                                 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
1699                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1700                         fp->rxq->rx_buf_size = rx_buf_size;
1701                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1702                 }
1703         }
1704         qede_dev_start(dev);
1705         if (frame_size > ETHER_MAX_LEN)
1706                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1707         else
1708                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1709         /* update max frame size */
1710         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1711         /* Reassign back */
1712         dev->rx_pkt_burst = qede_recv_pkts;
1713         dev->tx_pkt_burst = qede_xmit_pkts;
1714
1715         return 0;
1716 }
1717
1718 static int
1719 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1720                        struct rte_eth_udp_tunnel *tunnel_udp,
1721                        bool add)
1722 {
1723         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1724         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1725         struct ecore_tunnel_info tunn; /* @DPDK */
1726         struct ecore_hwfn *p_hwfn;
1727         int rc, i;
1728
1729         PMD_INIT_FUNC_TRACE(edev);
1730
1731         memset(&tunn, 0, sizeof(tunn));
1732         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1733                 tunn.vxlan_port.b_update_port = true;
1734                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
1735                                                   QEDE_VXLAN_DEF_PORT;
1736                 for_each_hwfn(edev, i) {
1737                         p_hwfn = &edev->hwfns[i];
1738                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1739                                                 ECORE_SPQ_MODE_CB, NULL);
1740                         if (rc != ECORE_SUCCESS) {
1741                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1742                                        tunn.vxlan_port.port);
1743                                 return rc;
1744                         }
1745                 }
1746         }
1747
1748         return 0;
1749 }
1750
1751 int
1752 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1753                       struct rte_eth_udp_tunnel *tunnel_udp)
1754 {
1755         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1756 }
1757
1758 int
1759 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1760                       struct rte_eth_udp_tunnel *tunnel_udp)
1761 {
1762         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1763 }
1764
1765 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1766                                        uint32_t *clss, char *str)
1767 {
1768         uint16_t j;
1769         *clss = MAX_ECORE_TUNN_CLSS;
1770
1771         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1772                 if (filter == qede_tunn_types[j].rte_filter_type) {
1773                         *type = qede_tunn_types[j].qede_type;
1774                         *clss = qede_tunn_types[j].qede_tunn_clss;
1775                         strcpy(str, qede_tunn_types[j].string);
1776                         return;
1777                 }
1778         }
1779 }
1780
1781 static int
1782 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1783                               const struct rte_eth_tunnel_filter_conf *conf,
1784                               uint32_t type)
1785 {
1786         /* Init commmon ucast params first */
1787         qede_set_ucast_cmn_params(ucast);
1788
1789         /* Copy out the required fields based on classification type */
1790         ucast->type = type;
1791
1792         switch (type) {
1793         case ECORE_FILTER_VNI:
1794                 ucast->vni = conf->tenant_id;
1795         break;
1796         case ECORE_FILTER_INNER_VLAN:
1797                 ucast->vlan = conf->inner_vlan;
1798         break;
1799         case ECORE_FILTER_MAC:
1800                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1801                        ETHER_ADDR_LEN);
1802         break;
1803         case ECORE_FILTER_INNER_MAC:
1804                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1805                        ETHER_ADDR_LEN);
1806         break;
1807         case ECORE_FILTER_MAC_VNI_PAIR:
1808                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1809                         ETHER_ADDR_LEN);
1810                 ucast->vni = conf->tenant_id;
1811         break;
1812         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1813                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1814                         ETHER_ADDR_LEN);
1815                 ucast->vni = conf->tenant_id;
1816         break;
1817         case ECORE_FILTER_INNER_PAIR:
1818                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1819                         ETHER_ADDR_LEN);
1820                 ucast->vlan = conf->inner_vlan;
1821         break;
1822         default:
1823                 return -EINVAL;
1824         }
1825
1826         return ECORE_SUCCESS;
1827 }
1828
1829 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1830                                   enum rte_filter_op filter_op,
1831                                   const struct rte_eth_tunnel_filter_conf *conf)
1832 {
1833         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1834         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1835         struct ecore_tunnel_info tunn;
1836         struct ecore_hwfn *p_hwfn;
1837         enum ecore_filter_ucast_type type;
1838         enum ecore_tunn_clss clss;
1839         struct ecore_filter_ucast ucast;
1840         char str[80];
1841         uint16_t filter_type;
1842         int rc, i;
1843
1844         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1845         /* First determine if the given filter classification is supported */
1846         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1847         if (clss == MAX_ECORE_TUNN_CLSS) {
1848                 DP_ERR(edev, "Wrong filter type\n");
1849                 return -EINVAL;
1850         }
1851         /* Init tunnel ucast params */
1852         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1853         if (rc != ECORE_SUCCESS) {
1854                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1855                                 conf->filter_type);
1856                 return rc;
1857         }
1858         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1859                 str, filter_op, ucast.type);
1860         switch (filter_op) {
1861         case RTE_ETH_FILTER_ADD:
1862                 ucast.opcode = ECORE_FILTER_ADD;
1863
1864                 /* Skip MAC/VLAN if filter is based on VNI */
1865                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1866                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1867                         if (rc == 0) {
1868                                 /* Enable accept anyvlan */
1869                                 qede_config_accept_any_vlan(qdev, true);
1870                         }
1871                 } else {
1872                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1873                         if (rc == 0)
1874                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1875                                                     ECORE_SPQ_MODE_CB, NULL);
1876                 }
1877
1878                 if (rc != ECORE_SUCCESS)
1879                         return rc;
1880
1881                 qdev->vxlan_filter_type = filter_type;
1882
1883                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1884                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
1885                 for_each_hwfn(edev, i) {
1886                         p_hwfn = &edev->hwfns[i];
1887                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1888                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
1889                         if (rc != ECORE_SUCCESS) {
1890                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1891                                        tunn.vxlan.tun_cls);
1892                         }
1893                 }
1894                 qdev->num_tunn_filters++; /* Filter added successfully */
1895         break;
1896         case RTE_ETH_FILTER_DELETE:
1897                 ucast.opcode = ECORE_FILTER_REMOVE;
1898
1899                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1900                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1901                 } else {
1902                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1903                         if (rc == 0)
1904                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1905                                                     ECORE_SPQ_MODE_CB, NULL);
1906                 }
1907                 if (rc != ECORE_SUCCESS)
1908                         return rc;
1909
1910                 qdev->vxlan_filter_type = filter_type;
1911                 qdev->num_tunn_filters--;
1912
1913                 /* Disable VXLAN if VXLAN filters become 0 */
1914                 if (qdev->num_tunn_filters == 0) {
1915                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1916
1917                         /* Use 0 as tunnel mode */
1918                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
1919                         for_each_hwfn(edev, i) {
1920                                 p_hwfn = &edev->hwfns[i];
1921                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1922                                         ECORE_SPQ_MODE_CB, NULL);
1923                                 if (rc != ECORE_SUCCESS) {
1924                                         DP_ERR(edev,
1925                                                 "Failed to update tunn_clss %u\n",
1926                                                 tunn.vxlan.tun_cls);
1927                                         break;
1928                                 }
1929                         }
1930                 }
1931         break;
1932         default:
1933                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1934                 return -EINVAL;
1935         }
1936         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1937
1938         return 0;
1939 }
1940
1941 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1942                          enum rte_filter_type filter_type,
1943                          enum rte_filter_op filter_op,
1944                          void *arg)
1945 {
1946         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1947         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1948         struct rte_eth_tunnel_filter_conf *filter_conf =
1949                         (struct rte_eth_tunnel_filter_conf *)arg;
1950
1951         switch (filter_type) {
1952         case RTE_ETH_FILTER_TUNNEL:
1953                 switch (filter_conf->tunnel_type) {
1954                 case RTE_TUNNEL_TYPE_VXLAN:
1955                         DP_INFO(edev,
1956                                 "Packet steering to the specified Rx queue"
1957                                 " is not supported with VXLAN tunneling");
1958                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1959                                                       filter_conf));
1960                 /* Place holders for future tunneling support */
1961                 case RTE_TUNNEL_TYPE_GENEVE:
1962                 case RTE_TUNNEL_TYPE_TEREDO:
1963                 case RTE_TUNNEL_TYPE_NVGRE:
1964                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1965                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1966                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1967                                 filter_conf->tunnel_type);
1968                         return -EINVAL;
1969                 case RTE_TUNNEL_TYPE_NONE:
1970                 default:
1971                         return 0;
1972                 }
1973                 break;
1974         case RTE_ETH_FILTER_FDIR:
1975                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
1976         case RTE_ETH_FILTER_NTUPLE:
1977                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
1978         case RTE_ETH_FILTER_MACVLAN:
1979         case RTE_ETH_FILTER_ETHERTYPE:
1980         case RTE_ETH_FILTER_FLEXIBLE:
1981         case RTE_ETH_FILTER_SYN:
1982         case RTE_ETH_FILTER_HASH:
1983         case RTE_ETH_FILTER_L2_TUNNEL:
1984         case RTE_ETH_FILTER_MAX:
1985         default:
1986                 DP_ERR(edev, "Unsupported filter type %d\n",
1987                         filter_type);
1988                 return -EINVAL;
1989         }
1990
1991         return 0;
1992 }
1993
1994 static const struct eth_dev_ops qede_eth_dev_ops = {
1995         .dev_configure = qede_dev_configure,
1996         .dev_infos_get = qede_dev_info_get,
1997         .rx_queue_setup = qede_rx_queue_setup,
1998         .rx_queue_release = qede_rx_queue_release,
1999         .tx_queue_setup = qede_tx_queue_setup,
2000         .tx_queue_release = qede_tx_queue_release,
2001         .dev_start = qede_dev_start,
2002         .dev_set_link_up = qede_dev_set_link_up,
2003         .dev_set_link_down = qede_dev_set_link_down,
2004         .link_update = qede_link_update,
2005         .promiscuous_enable = qede_promiscuous_enable,
2006         .promiscuous_disable = qede_promiscuous_disable,
2007         .allmulticast_enable = qede_allmulticast_enable,
2008         .allmulticast_disable = qede_allmulticast_disable,
2009         .dev_stop = qede_dev_stop,
2010         .dev_close = qede_dev_close,
2011         .stats_get = qede_get_stats,
2012         .stats_reset = qede_reset_stats,
2013         .xstats_get = qede_get_xstats,
2014         .xstats_reset = qede_reset_xstats,
2015         .xstats_get_names = qede_get_xstats_names,
2016         .mac_addr_add = qede_mac_addr_add,
2017         .mac_addr_remove = qede_mac_addr_remove,
2018         .mac_addr_set = qede_mac_addr_set,
2019         .vlan_offload_set = qede_vlan_offload_set,
2020         .vlan_filter_set = qede_vlan_filter_set,
2021         .flow_ctrl_set = qede_flow_ctrl_set,
2022         .flow_ctrl_get = qede_flow_ctrl_get,
2023         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2024         .rss_hash_update = qede_rss_hash_update,
2025         .rss_hash_conf_get = qede_rss_hash_conf_get,
2026         .reta_update  = qede_rss_reta_update,
2027         .reta_query  = qede_rss_reta_query,
2028         .mtu_set = qede_set_mtu,
2029         .filter_ctrl = qede_dev_filter_ctrl,
2030         .udp_tunnel_port_add = qede_udp_dst_port_add,
2031         .udp_tunnel_port_del = qede_udp_dst_port_del,
2032 };
2033
2034 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2035         .dev_configure = qede_dev_configure,
2036         .dev_infos_get = qede_dev_info_get,
2037         .rx_queue_setup = qede_rx_queue_setup,
2038         .rx_queue_release = qede_rx_queue_release,
2039         .tx_queue_setup = qede_tx_queue_setup,
2040         .tx_queue_release = qede_tx_queue_release,
2041         .dev_start = qede_dev_start,
2042         .dev_set_link_up = qede_dev_set_link_up,
2043         .dev_set_link_down = qede_dev_set_link_down,
2044         .link_update = qede_link_update,
2045         .promiscuous_enable = qede_promiscuous_enable,
2046         .promiscuous_disable = qede_promiscuous_disable,
2047         .allmulticast_enable = qede_allmulticast_enable,
2048         .allmulticast_disable = qede_allmulticast_disable,
2049         .dev_stop = qede_dev_stop,
2050         .dev_close = qede_dev_close,
2051         .stats_get = qede_get_stats,
2052         .stats_reset = qede_reset_stats,
2053         .xstats_get = qede_get_xstats,
2054         .xstats_reset = qede_reset_xstats,
2055         .xstats_get_names = qede_get_xstats_names,
2056         .vlan_offload_set = qede_vlan_offload_set,
2057         .vlan_filter_set = qede_vlan_filter_set,
2058         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2059         .rss_hash_update = qede_rss_hash_update,
2060         .rss_hash_conf_get = qede_rss_hash_conf_get,
2061         .reta_update  = qede_rss_reta_update,
2062         .reta_query  = qede_rss_reta_query,
2063         .mtu_set = qede_set_mtu,
2064 };
2065
2066 static void qede_update_pf_params(struct ecore_dev *edev)
2067 {
2068         struct ecore_pf_params pf_params;
2069
2070         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2071         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2072         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2073         qed_ops->common->update_pf_params(edev, &pf_params);
2074 }
2075
2076 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2077 {
2078         struct rte_pci_device *pci_dev;
2079         struct rte_pci_addr pci_addr;
2080         struct qede_dev *adapter;
2081         struct ecore_dev *edev;
2082         struct qed_dev_eth_info dev_info;
2083         struct qed_slowpath_params params;
2084         static bool do_once = true;
2085         uint8_t bulletin_change;
2086         uint8_t vf_mac[ETHER_ADDR_LEN];
2087         uint8_t is_mac_forced;
2088         bool is_mac_exist;
2089         /* Fix up ecore debug level */
2090         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2091         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2092         uint32_t max_mac_addrs;
2093         int rc;
2094
2095         /* Extract key data structures */
2096         adapter = eth_dev->data->dev_private;
2097         edev = &adapter->edev;
2098         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2099         pci_addr = pci_dev->addr;
2100
2101         PMD_INIT_FUNC_TRACE(edev);
2102
2103         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2104                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2105                  eth_dev->data->port_id);
2106
2107         eth_dev->rx_pkt_burst = qede_recv_pkts;
2108         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2109         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2110
2111         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2112                 DP_NOTICE(edev, false,
2113                           "Skipping device init from secondary process\n");
2114                 return 0;
2115         }
2116
2117         rte_eth_copy_pci_info(eth_dev, pci_dev);
2118
2119         /* @DPDK */
2120         edev->vendor_id = pci_dev->id.vendor_id;
2121         edev->device_id = pci_dev->id.device_id;
2122
2123         qed_ops = qed_get_eth_ops();
2124         if (!qed_ops) {
2125                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2126                 return -EINVAL;
2127         }
2128
2129         DP_INFO(edev, "Starting qede probe\n");
2130
2131         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2132                                     dp_module, dp_level, is_vf);
2133
2134         if (rc != 0) {
2135                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2136                 return -ENODEV;
2137         }
2138
2139         qede_update_pf_params(edev);
2140
2141         rte_intr_callback_register(&pci_dev->intr_handle,
2142                                    qede_interrupt_handler, (void *)eth_dev);
2143
2144         if (rte_intr_enable(&pci_dev->intr_handle)) {
2145                 DP_ERR(edev, "rte_intr_enable() failed\n");
2146                 return -ENODEV;
2147         }
2148
2149         /* Start the Slowpath-process */
2150         memset(&params, 0, sizeof(struct qed_slowpath_params));
2151         params.int_mode = ECORE_INT_MODE_MSIX;
2152         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2153         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2154         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2155         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2156         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2157                 QEDE_PMD_DRV_VER_STR_SIZE);
2158
2159         /* For CMT mode device do periodic polling for slowpath events.
2160          * This is required since uio device uses only one MSI-x
2161          * interrupt vector but we need one for each engine.
2162          */
2163         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2164                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2165                                        qede_poll_sp_sb_cb,
2166                                        (void *)eth_dev);
2167                 if (rc != 0) {
2168                         DP_ERR(edev, "Unable to start periodic"
2169                                      " timer rc %d\n", rc);
2170                         return -EINVAL;
2171                 }
2172         }
2173
2174         rc = qed_ops->common->slowpath_start(edev, &params);
2175         if (rc) {
2176                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2177                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2178                                      (void *)eth_dev);
2179                 return -ENODEV;
2180         }
2181
2182         rc = qed_ops->fill_dev_info(edev, &dev_info);
2183         if (rc) {
2184                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2185                 qed_ops->common->slowpath_stop(edev);
2186                 qed_ops->common->remove(edev);
2187                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2188                                      (void *)eth_dev);
2189                 return -ENODEV;
2190         }
2191
2192         qede_alloc_etherdev(adapter, &dev_info);
2193
2194         adapter->ops->common->set_name(edev, edev->name);
2195
2196         if (!is_vf)
2197                 adapter->dev_info.num_mac_filters =
2198                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2199                                             ECORE_MAC);
2200         else
2201                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2202                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2203
2204         /* Allocate memory for storing MAC addr */
2205         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2206                                         (ETHER_ADDR_LEN *
2207                                         adapter->dev_info.num_mac_filters),
2208                                         RTE_CACHE_LINE_SIZE);
2209
2210         if (eth_dev->data->mac_addrs == NULL) {
2211                 DP_ERR(edev, "Failed to allocate MAC address\n");
2212                 qed_ops->common->slowpath_stop(edev);
2213                 qed_ops->common->remove(edev);
2214                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2215                                      (void *)eth_dev);
2216                 return -ENOMEM;
2217         }
2218
2219         if (!is_vf) {
2220                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2221                                 hw_info.hw_mac_addr,
2222                                 &eth_dev->data->mac_addrs[0]);
2223                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2224                                 &adapter->primary_mac);
2225         } else {
2226                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2227                                        &bulletin_change);
2228                 if (bulletin_change) {
2229                         is_mac_exist =
2230                             ecore_vf_bulletin_get_forced_mac(
2231                                                 ECORE_LEADING_HWFN(edev),
2232                                                 vf_mac,
2233                                                 &is_mac_forced);
2234                         if (is_mac_exist && is_mac_forced) {
2235                                 DP_INFO(edev, "VF macaddr received from PF\n");
2236                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2237                                                 &eth_dev->data->mac_addrs[0]);
2238                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2239                                                 &adapter->primary_mac);
2240                         } else {
2241                                 DP_NOTICE(edev, false,
2242                                           "No VF macaddr assigned\n");
2243                         }
2244                 }
2245         }
2246
2247         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2248
2249         if (do_once) {
2250                 qede_print_adapter_info(adapter);
2251                 do_once = false;
2252         }
2253
2254         adapter->state = QEDE_DEV_INIT;
2255
2256         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2257                   adapter->primary_mac.addr_bytes[0],
2258                   adapter->primary_mac.addr_bytes[1],
2259                   adapter->primary_mac.addr_bytes[2],
2260                   adapter->primary_mac.addr_bytes[3],
2261                   adapter->primary_mac.addr_bytes[4],
2262                   adapter->primary_mac.addr_bytes[5]);
2263
2264         return rc;
2265 }
2266
2267 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2268 {
2269         return qede_common_dev_init(eth_dev, 1);
2270 }
2271
2272 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2273 {
2274         return qede_common_dev_init(eth_dev, 0);
2275 }
2276
2277 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2278 {
2279         /* only uninitialize in the primary process */
2280         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2281                 return 0;
2282
2283         /* safe to close dev here */
2284         qede_dev_close(eth_dev);
2285
2286         eth_dev->dev_ops = NULL;
2287         eth_dev->rx_pkt_burst = NULL;
2288         eth_dev->tx_pkt_burst = NULL;
2289
2290         if (eth_dev->data->mac_addrs)
2291                 rte_free(eth_dev->data->mac_addrs);
2292
2293         eth_dev->data->mac_addrs = NULL;
2294
2295         return 0;
2296 }
2297
2298 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2299 {
2300         return qede_dev_common_uninit(eth_dev);
2301 }
2302
2303 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2304 {
2305         return qede_dev_common_uninit(eth_dev);
2306 }
2307
2308 static const struct rte_pci_id pci_id_qedevf_map[] = {
2309 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2310         {
2311                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2312         },
2313         {
2314                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2315         },
2316         {
2317                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2318         },
2319         {.vendor_id = 0,}
2320 };
2321
2322 static const struct rte_pci_id pci_id_qede_map[] = {
2323 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2324         {
2325                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2326         },
2327         {
2328                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2329         },
2330         {
2331                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2332         },
2333         {
2334                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2335         },
2336         {
2337                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2338         },
2339         {
2340                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2341         },
2342         {
2343                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2344         },
2345         {
2346                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2347         },
2348         {
2349                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2350         },
2351         {
2352                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2353         },
2354         {.vendor_id = 0,}
2355 };
2356
2357 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2358         struct rte_pci_device *pci_dev)
2359 {
2360         return rte_eth_dev_pci_generic_probe(pci_dev,
2361                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2362 }
2363
2364 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2365 {
2366         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2367 }
2368
2369 static struct rte_pci_driver rte_qedevf_pmd = {
2370         .id_table = pci_id_qedevf_map,
2371         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2372         .probe = qedevf_eth_dev_pci_probe,
2373         .remove = qedevf_eth_dev_pci_remove,
2374 };
2375
2376 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2377         struct rte_pci_device *pci_dev)
2378 {
2379         return rte_eth_dev_pci_generic_probe(pci_dev,
2380                 sizeof(struct qede_dev), qede_eth_dev_init);
2381 }
2382
2383 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2384 {
2385         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2386 }
2387
2388 static struct rte_pci_driver rte_qede_pmd = {
2389         .id_table = pci_id_qede_map,
2390         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2391         .probe = qede_eth_dev_pci_probe,
2392         .remove = qede_eth_dev_pci_remove,
2393 };
2394
2395 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2396 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2397 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2398 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2399 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2400 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");