drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static const char *drivername = "qede pmd";
  16 static int64_t timer_period = 1;
  17
  18 struct rte_qede_xstats_name_off {
  19         char name[RTE_ETH_XSTATS_NAME_SIZE];
  20         uint64_t offset;
  21 };
  22
  23 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  24         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
  25         {"rx_multicast_bytes",
  26                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
  27         {"rx_broadcast_bytes",
  28                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
  29         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
  30         {"rx_multicast_packets",
  31                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
  32         {"rx_broadcast_packets",
  33                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
  34
  35         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
  36         {"tx_multicast_bytes",
  37                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
  38         {"tx_broadcast_bytes",
  39                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
  40         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
  41         {"tx_multicast_packets",
  42                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
  43         {"tx_broadcast_packets",
  44                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
  45
  46         {"rx_64_byte_packets",
  47                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
  48         {"rx_65_to_127_byte_packets",
  49                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
  50         {"rx_128_to_255_byte_packets",
  51                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
  52         {"rx_256_to_511_byte_packets",
  53                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
  54         {"rx_512_to_1023_byte_packets",
  55                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
  56         {"rx_1024_to_1518_byte_packets",
  57                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
  58         {"rx_1519_to_1522_byte_packets",
  59                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
  60         {"rx_1519_to_2047_byte_packets",
  61                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
  62         {"rx_2048_to_4095_byte_packets",
  63                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
  64         {"rx_4096_to_9216_byte_packets",
  65                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
  66         {"rx_9217_to_16383_byte_packets",
  67                 offsetof(struct ecore_eth_stats,
  68                          rx_9217_to_16383_byte_packets)},
  69         {"tx_64_byte_packets",
  70                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
  71         {"tx_65_to_127_byte_packets",
  72                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
  73         {"tx_128_to_255_byte_packets",
  74                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
  75         {"tx_256_to_511_byte_packets",
  76                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
  77         {"tx_512_to_1023_byte_packets",
  78                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
  79         {"tx_1024_to_1518_byte_packets",
  80                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
  81         {"trx_1519_to_1522_byte_packets",
  82                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
  83         {"tx_2048_to_4095_byte_packets",
  84                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
  85         {"tx_4096_to_9216_byte_packets",
  86                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
  87         {"tx_9217_to_16383_byte_packets",
  88                 offsetof(struct ecore_eth_stats,
  89                          tx_9217_to_16383_byte_packets)},
  90
  91         {"rx_mac_crtl_frames",
  92                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
  93         {"tx_mac_control_frames",
  94                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
  95         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
  96         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
  97         {"rx_priority_flow_control_frames",
  98                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
  99         {"tx_priority_flow_control_frames",
 100                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 101
 102         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 103         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 104         {"rx_carrier_errors",
 105                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 106         {"rx_oversize_packet_errors",
 107                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 108         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 109         {"rx_undersize_packet_errors",
 110                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 111         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 112         {"rx_host_buffer_not_available",
 113                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 114         /* Number of packets discarded because they are bigger than MTU */
 115         {"rx_packet_too_big_discards",
 116                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 117         {"rx_ttl_zero_discards",
 118                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 119         {"rx_multi_function_tag_filter_discards",
 120                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 121         {"rx_mac_filter_discards",
 122                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 123         {"rx_hw_buffer_truncates",
 124                 offsetof(struct ecore_eth_stats, brb_truncates)},
 125         {"rx_hw_buffer_discards",
 126                 offsetof(struct ecore_eth_stats, brb_discards)},
 127         {"tx_lpi_entry_count",
 128                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 129         {"tx_total_collisions",
 130                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 131         {"tx_error_drop_packets",
 132                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 133
 134         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 135         {"rx_mac_unicast_packets",
 136                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 137         {"rx_mac_multicast_packets",
 138                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 139         {"rx_mac_broadcast_packets",
 140                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 141         {"rx_mac_frames_ok",
 142                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 143         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 144         {"tx_mac_unicast_packets",
 145                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 146         {"tx_mac_multicast_packets",
 147                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 148         {"tx_mac_broadcast_packets",
 149                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 150
 151         {"lro_coalesced_packets",
 152                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 153         {"lro_coalesced_events",
 154                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 155         {"lro_aborts_num",
 156                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 157         {"lro_not_coalesced_packets",
 158                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 159         {"lro_coalesced_bytes",
 160                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 161 };
 162
 163 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 164         {"rx_q_segments",
 165                 offsetof(struct qede_rx_queue, rx_segs)},
 166         {"rx_q_hw_errors",
 167                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 168         {"rx_q_allocation_errors",
 169                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 170 };
 171
 172 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 173 {
 174         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 175 }
 176
 177 static void
 178 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
 179 {
 180         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 181         struct qede_dev *qdev = eth_dev->data->dev_private;
 182         struct ecore_dev *edev = &qdev->edev;
 183
 184         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 185         if (rte_intr_enable(handle))
 186                 DP_ERR(edev, "rte_intr_enable failed\n");
 187 }
 188
 189 static void
 190 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 191 {
 192         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 193         qdev->num_tc = qdev->dev_info.num_tc;
 194         qdev->ops = qed_ops;
 195 }
 196
 197 static void qede_print_adapter_info(struct qede_dev *qdev)
 198 {
 199         struct ecore_dev *edev = &qdev->edev;
 200         struct qed_dev_info *info = &qdev->dev_info.common;
 201         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 202         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 203
 204         DP_INFO(edev, "*********************************\n");
 205         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 206         DP_INFO(edev, " Chip details : %s%d\n",
 207                   ECORE_IS_BB(edev) ? "BB" : "AH",
 208                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 209         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 210                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 211         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 212                  ver_str, QEDE_PMD_VERSION);
 213         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 214         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 215
 216         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 217                  "%d.%d.%d.%d",
 218                 (info->mfw_rev >> 24) & 0xff,
 219                 (info->mfw_rev >> 16) & 0xff,
 220                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 221         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 222         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 223         DP_INFO(edev, "*********************************\n");
 224 }
 225
 226 static int
 227 qede_set_ucast_rx_mac(struct qede_dev *qdev,
 228                       enum qed_filter_xcast_params_type opcode,
 229                       uint8_t mac[ETHER_ADDR_LEN])
 230 {
 231         struct ecore_dev *edev = &qdev->edev;
 232         struct qed_filter_params filter_cmd;
 233
 234         memset(&filter_cmd, 0, sizeof(filter_cmd));
 235         filter_cmd.type = QED_FILTER_TYPE_UCAST;
 236         filter_cmd.filter.ucast.type = opcode;
 237         filter_cmd.filter.ucast.mac_valid = 1;
 238         rte_memcpy(&filter_cmd.filter.ucast.mac[0], &mac[0], ETHER_ADDR_LEN);
 239         return qdev->ops->filter_config(edev, &filter_cmd);
 240 }
 241
 242 static void
 243 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 244                   uint32_t index, __rte_unused uint32_t pool)
 245 {
 246         struct qede_dev *qdev = eth_dev->data->dev_private;
 247         struct ecore_dev *edev = &qdev->edev;
 248         int rc;
 249
 250         PMD_INIT_FUNC_TRACE(edev);
 251
 252         if (index >= qdev->dev_info.num_mac_addrs) {
 253                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 254                        index, qdev->dev_info.num_mac_addrs);
 255                 return;
 256         }
 257
 258         /* Adding macaddr even though promiscuous mode is set */
 259         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
 260                 DP_INFO(edev, "Port is in promisc mode, yet adding it\n");
 261
 262         /* Add MAC filters according to the unicast secondary macs */
 263         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD,
 264                                    mac_addr->addr_bytes);
 265         if (rc)
 266                 DP_ERR(edev, "Unable to add macaddr rc=%d\n", rc);
 267 }
 268
 269 static void
 270 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 271 {
 272         struct qede_dev *qdev = eth_dev->data->dev_private;
 273         struct ecore_dev *edev = &qdev->edev;
 274         struct ether_addr mac_addr;
 275         int rc;
 276
 277         PMD_INIT_FUNC_TRACE(edev);
 278
 279         if (index >= qdev->dev_info.num_mac_addrs) {
 280                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 281                        index, qdev->dev_info.num_mac_addrs);
 282                 return;
 283         }
 284
 285         /* Use the index maintained by rte */
 286         ether_addr_copy(&eth_dev->data->mac_addrs[index], &mac_addr);
 287         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL,
 288                                    mac_addr.addr_bytes);
 289         if (rc)
 290                 DP_ERR(edev, "Unable to remove macaddr rc=%d\n", rc);
 291 }
 292
 293 static void
 294 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 295 {
 296         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 297         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 298         int rc;
 299
 300         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 301                                                mac_addr->addr_bytes)) {
 302                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 303                 ether_addr_copy(&qdev->primary_mac,
 304                                 &eth_dev->data->mac_addrs[0]);
 305                 return;
 306         }
 307
 308         /* First remove the primary mac */
 309         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL,
 310                                    qdev->primary_mac.addr_bytes);
 311
 312         if (rc) {
 313                 DP_ERR(edev, "Unable to remove current macaddr"
 314                              " Reverting to previous default mac\n");
 315                 ether_addr_copy(&qdev->primary_mac,
 316                                 &eth_dev->data->mac_addrs[0]);
 317                 return;
 318         }
 319
 320         /* Add new MAC */
 321         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD,
 322                                    mac_addr->addr_bytes);
 323
 324         if (rc)
 325                 DP_ERR(edev, "Unable to add new default mac\n");
 326         else
 327                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 328 }
 329
 330
 331
 332
 333 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 334 {
 335         struct ecore_dev *edev = &qdev->edev;
 336         struct qed_update_vport_params params = {
 337                 .vport_id = 0,
 338                 .accept_any_vlan = action,
 339                 .update_accept_any_vlan_flg = 1,
 340         };
 341         int rc;
 342
 343         /* Proceed only if action actually needs to be performed */
 344         if (qdev->accept_any_vlan == action)
 345                 return;
 346
 347         rc = qdev->ops->vport_update(edev, &params);
 348         if (rc) {
 349                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 350                        action ? "enable" : "disable");
 351         } else {
 352                 DP_INFO(edev, "%s accept-any-vlan\n",
 353                         action ? "enabled" : "disabled");
 354                 qdev->accept_any_vlan = action;
 355         }
 356 }
 357
 358 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 359 {
 360         struct qed_update_vport_params vport_update_params;
 361         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 362         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 363         int rc;
 364
 365         memset(&vport_update_params, 0, sizeof(vport_update_params));
 366         vport_update_params.vport_id = 0;
 367         vport_update_params.update_inner_vlan_removal_flg = 1;
 368         vport_update_params.inner_vlan_removal_flg = set_stripping;
 369         rc = qdev->ops->vport_update(edev, &vport_update_params);
 370         if (rc) {
 371                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 372                 return rc;
 373         }
 374
 375         return 0;
 376 }
 377
 378 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 379 {
 380         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 381         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 382         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 383
 384         if (mask & ETH_VLAN_STRIP_MASK) {
 385                 if (rxmode->hw_vlan_strip)
 386                         (void)qede_vlan_stripping(eth_dev, 1);
 387                 else
 388                         (void)qede_vlan_stripping(eth_dev, 0);
 389         }
 390
 391         if (mask & ETH_VLAN_FILTER_MASK) {
 392                 /* VLAN filtering kicks in when a VLAN is added */
 393                 if (rxmode->hw_vlan_filter) {
 394                         qede_vlan_filter_set(eth_dev, 0, 1);
 395                 } else {
 396                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 397                                 DP_NOTICE(edev, false,
 398                                   " Please remove existing VLAN filters"
 399                                   " before disabling VLAN filtering\n");
 400                                 /* Signal app that VLAN filtering is still
 401                                  * enabled
 402                                  */
 403                                 rxmode->hw_vlan_filter = true;
 404                         } else {
 405                                 qede_vlan_filter_set(eth_dev, 0, 0);
 406                         }
 407                 }
 408         }
 409
 410         if (mask & ETH_VLAN_EXTEND_MASK)
 411                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 412                         " and classification is based on outer tag only\n");
 413
 414         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 415                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 416 }
 417
 418 static int qede_set_ucast_rx_vlan(struct qede_dev *qdev,
 419                                   enum qed_filter_xcast_params_type opcode,
 420                                   uint16_t vid)
 421 {
 422         struct qed_filter_params filter_cmd;
 423         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 424
 425         memset(&filter_cmd, 0, sizeof(filter_cmd));
 426         filter_cmd.type = QED_FILTER_TYPE_UCAST;
 427         filter_cmd.filter.ucast.type = opcode;
 428         filter_cmd.filter.ucast.vlan_valid = 1;
 429         filter_cmd.filter.ucast.vlan = vid;
 430
 431         return qdev->ops->filter_config(edev, &filter_cmd);
 432 }
 433
 434 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 435                                 uint16_t vlan_id, int on)
 436 {
 437         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 438         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 439         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 440         struct qede_vlan_entry *tmp = NULL;
 441         struct qede_vlan_entry *vlan;
 442         int rc;
 443
 444         if (on) {
 445                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 446                         DP_INFO(edev, "Reached max VLAN filter limit"
 447                                       " enabling accept_any_vlan\n");
 448                         qede_config_accept_any_vlan(qdev, true);
 449                         return 0;
 450                 }
 451
 452                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 453                         if (tmp->vid == vlan_id) {
 454                                 DP_ERR(edev, "VLAN %u already configured\n",
 455                                        vlan_id);
 456                                 return -EEXIST;
 457                         }
 458                 }
 459
 460                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 461                                   RTE_CACHE_LINE_SIZE);
 462
 463                 if (!vlan) {
 464                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 465                         return -ENOMEM;
 466                 }
 467
 468                 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_ADD,
 469                                             vlan_id);
 470                 if (rc) {
 471                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 472                                rc);
 473                         rte_free(vlan);
 474                 } else {
 475                         vlan->vid = vlan_id;
 476                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 477                         qdev->configured_vlans++;
 478                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 479                                 vlan_id, qdev->configured_vlans);
 480                 }
 481         } else {
 482                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 483                         if (tmp->vid == vlan_id)
 484                                 break;
 485                 }
 486
 487                 if (!tmp) {
 488                         if (qdev->configured_vlans == 0) {
 489                                 DP_INFO(edev,
 490                                         "No VLAN filters configured yet\n");
 491                                 return 0;
 492                         }
 493
 494                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 495                         return -EINVAL;
 496                 }
 497
 498                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 499
 500                 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_DEL,
 501                                             vlan_id);
 502                 if (rc) {
 503                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 504                                vlan_id, rc);
 505                 } else {
 506                         qdev->configured_vlans--;
 507                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 508                                 vlan_id, qdev->configured_vlans);
 509                 }
 510         }
 511
 512         return rc;
 513 }
 514
 515 static int qede_init_vport(struct qede_dev *qdev)
 516 {
 517         struct ecore_dev *edev = &qdev->edev;
 518         struct qed_start_vport_params start = {0};
 519         int rc;
 520
 521         start.remove_inner_vlan = 1;
 522         start.gro_enable = 0;
 523         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 524         start.vport_id = 0;
 525         start.drop_ttl0 = false;
 526         start.clear_stats = 1;
 527         start.handle_ptp_pkts = 0;
 528
 529         rc = qdev->ops->vport_start(edev, &start);
 530         if (rc) {
 531                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 532                 return rc;
 533         }
 534
 535         DP_INFO(edev,
 536                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 537                 start.vport_id, ETHER_MTU);
 538
 539         return 0;
 540 }
 541
 542 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 543 {
 544         struct qede_dev *qdev = eth_dev->data->dev_private;
 545         struct ecore_dev *edev = &qdev->edev;
 546         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 547         int rc, i, j;
 548
 549         PMD_INIT_FUNC_TRACE(edev);
 550
 551         /* Check requirements for 100G mode */
 552         if (edev->num_hwfns > 1) {
 553                 if (eth_dev->data->nb_rx_queues < 2 ||
 554                     eth_dev->data->nb_tx_queues < 2) {
 555                         DP_NOTICE(edev, false,
 556                                   "100G mode needs min. 2 RX/TX queues\n");
 557                         return -EINVAL;
 558                 }
 559
 560                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 561                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 562                         DP_NOTICE(edev, false,
 563                                   "100G mode needs even no. of RX/TX queues\n");
 564                         return -EINVAL;
 565                 }
 566         }
 567
 568         /* Sanity checks and throw warnings */
 569         if (rxmode->enable_scatter == 1)
 570                 eth_dev->data->scattered_rx = 1;
 571
 572         if (rxmode->enable_lro == 1) {
 573                 DP_INFO(edev, "LRO is not supported\n");
 574                 return -EINVAL;
 575         }
 576
 577         if (!rxmode->hw_strip_crc)
 578                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 579
 580         if (!rxmode->hw_ip_checksum)
 581                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 582                               "in hw\n");
 583
 584         /* Check for the port restart case */
 585         if (qdev->state != QEDE_DEV_INIT) {
 586                 rc = qdev->ops->vport_stop(edev, 0);
 587                 if (rc != 0)
 588                         return rc;
 589                 qede_dealloc_fp_resc(eth_dev);
 590         }
 591
 592         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 593         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 594         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 595
 596         /* Fastpath status block should be initialized before sending
 597          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 598          */
 599         rc = qede_alloc_fp_resc(qdev);
 600         if (rc != 0)
 601                 return rc;
 602
 603         /* Issue VPORT-START with default config values to allow
 604          * other port configurations early on.
 605          */
 606         rc = qede_init_vport(qdev);
 607         if (rc != 0)
 608                 return rc;
 609
 610         SLIST_INIT(&qdev->vlan_list_head);
 611
 612         /* Add primary mac for PF */
 613         if (IS_PF(edev))
 614                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 615
 616         /* Enable VLAN offloads by default */
 617         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 618                                        ETH_VLAN_FILTER_MASK |
 619                                        ETH_VLAN_EXTEND_MASK);
 620
 621         qdev->state = QEDE_DEV_CONFIG;
 622
 623         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 624                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 625                 qdev->num_tc);
 626
 627         return 0;
 628 }
 629
 630 /* Info about HW descriptor ring limitations */
 631 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 632         .nb_max = NUM_RX_BDS_MAX,
 633         .nb_min = 128,
 634         .nb_align = 128 /* lowest common multiple */
 635 };
 636
 637 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 638         .nb_max = NUM_TX_BDS_MAX,
 639         .nb_min = 256,
 640         .nb_align = 256
 641 };
 642
 643 static void
 644 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 645                   struct rte_eth_dev_info *dev_info)
 646 {
 647         struct qede_dev *qdev = eth_dev->data->dev_private;
 648         struct ecore_dev *edev = &qdev->edev;
 649         struct qed_link_output link;
 650         uint32_t speed_cap = 0;
 651
 652         PMD_INIT_FUNC_TRACE(edev);
 653
 654         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 655         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 656                                               QEDE_ETH_OVERHEAD);
 657         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 658         dev_info->rx_desc_lim = qede_rx_desc_lim;
 659         dev_info->tx_desc_lim = qede_tx_desc_lim;
 660         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 661         dev_info->max_tx_queues = dev_info->max_rx_queues;
 662         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 663         if (IS_VF(edev))
 664                 dev_info->max_vfs = 0;
 665         else
 666                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 667         dev_info->driver_name = qdev->drv_ver;
 668         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 669         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 670
 671         dev_info->default_txconf = (struct rte_eth_txconf) {
 672                 .txq_flags = QEDE_TXQ_FLAGS,
 673         };
 674
 675         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
 676                                      DEV_RX_OFFLOAD_IPV4_CKSUM |
 677                                      DEV_RX_OFFLOAD_UDP_CKSUM |
 678                                      DEV_RX_OFFLOAD_TCP_CKSUM);
 679         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 680                                      DEV_TX_OFFLOAD_IPV4_CKSUM |
 681                                      DEV_TX_OFFLOAD_UDP_CKSUM |
 682                                      DEV_TX_OFFLOAD_TCP_CKSUM);
 683
 684         memset(&link, 0, sizeof(struct qed_link_output));
 685         qdev->ops->common->get_link(edev, &link);
 686         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 687                 speed_cap |= ETH_LINK_SPEED_1G;
 688         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 689                 speed_cap |= ETH_LINK_SPEED_10G;
 690         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 691                 speed_cap |= ETH_LINK_SPEED_25G;
 692         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 693                 speed_cap |= ETH_LINK_SPEED_40G;
 694         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 695                 speed_cap |= ETH_LINK_SPEED_50G;
 696         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 697                 speed_cap |= ETH_LINK_SPEED_100G;
 698         dev_info->speed_capa = speed_cap;
 699 }
 700
 701 /* return 0 means link status changed, -1 means not changed */
 702 static int
 703 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 704 {
 705         struct qede_dev *qdev = eth_dev->data->dev_private;
 706         struct ecore_dev *edev = &qdev->edev;
 707         uint16_t link_duplex;
 708         struct qed_link_output link;
 709         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 710
 711         memset(&link, 0, sizeof(struct qed_link_output));
 712         qdev->ops->common->get_link(edev, &link);
 713
 714         /* Link Speed */
 715         curr->link_speed = link.speed;
 716
 717         /* Link Mode */
 718         switch (link.duplex) {
 719         case QEDE_DUPLEX_HALF:
 720                 link_duplex = ETH_LINK_HALF_DUPLEX;
 721                 break;
 722         case QEDE_DUPLEX_FULL:
 723                 link_duplex = ETH_LINK_FULL_DUPLEX;
 724                 break;
 725         case QEDE_DUPLEX_UNKNOWN:
 726         default:
 727                 link_duplex = -1;
 728         }
 729         curr->link_duplex = link_duplex;
 730
 731         /* Link Status */
 732         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 733
 734         /* AN */
 735         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 736                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 737
 738         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 739                 curr->link_speed, curr->link_duplex,
 740                 curr->link_autoneg, curr->link_status);
 741
 742         /* return 0 means link status changed, -1 means not changed */
 743         return ((curr->link_status == link.link_up) ? -1 : 0);
 744 }
 745
 746 static void
 747 qede_rx_mode_setting(struct rte_eth_dev *eth_dev,
 748                      enum qed_filter_rx_mode_type accept_flags)
 749 {
 750         struct qede_dev *qdev = eth_dev->data->dev_private;
 751         struct ecore_dev *edev = &qdev->edev;
 752         struct qed_filter_params rx_mode;
 753
 754         DP_INFO(edev, "%s mode %u\n", __func__, accept_flags);
 755
 756         memset(&rx_mode, 0, sizeof(struct qed_filter_params));
 757         rx_mode.type = QED_FILTER_TYPE_RX_MODE;
 758         rx_mode.filter.accept_flags = accept_flags;
 759         qdev->ops->filter_config(edev, &rx_mode);
 760 }
 761
 762 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 763 {
 764         struct qede_dev *qdev = eth_dev->data->dev_private;
 765         struct ecore_dev *edev = &qdev->edev;
 766
 767         PMD_INIT_FUNC_TRACE(edev);
 768
 769         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
 770
 771         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 772                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
 773
 774         qede_rx_mode_setting(eth_dev, type);
 775 }
 776
 777 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
 778 {
 779         struct qede_dev *qdev = eth_dev->data->dev_private;
 780         struct ecore_dev *edev = &qdev->edev;
 781
 782         PMD_INIT_FUNC_TRACE(edev);
 783
 784         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 785                 qede_rx_mode_setting(eth_dev,
 786                                      QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
 787         else
 788                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR);
 789 }
 790
 791 static void qede_poll_sp_sb_cb(void *param)
 792 {
 793         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 794         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 795         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 796         int rc;
 797
 798         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 799         qede_interrupt_action(&edev->hwfns[1]);
 800
 801         rc = rte_eal_alarm_set(timer_period * US_PER_S,
 802                                qede_poll_sp_sb_cb,
 803                                (void *)eth_dev);
 804         if (rc != 0) {
 805                 DP_ERR(edev, "Unable to start periodic"
 806                              " timer rc %d\n", rc);
 807                 assert(false && "Unable to start periodic timer");
 808         }
 809 }
 810
 811 static void qede_dev_close(struct rte_eth_dev *eth_dev)
 812 {
 813         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 814         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 815         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 816         int rc;
 817
 818         PMD_INIT_FUNC_TRACE(edev);
 819
 820         /* dev_stop() shall cleanup fp resources in hw but without releasing
 821          * dma memories and sw structures so that dev_start() can be called
 822          * by the app without reconfiguration. However, in dev_close() we
 823          * can release all the resources and device can be brought up newly
 824          */
 825         if (qdev->state != QEDE_DEV_STOP)
 826                 qede_dev_stop(eth_dev);
 827         else
 828                 DP_INFO(edev, "Device is already stopped\n");
 829
 830         rc = qdev->ops->vport_stop(edev, 0);
 831         if (rc != 0)
 832                 DP_ERR(edev, "Failed to stop VPORT\n");
 833
 834         qede_dealloc_fp_resc(eth_dev);
 835
 836         qdev->ops->common->slowpath_stop(edev);
 837
 838         qdev->ops->common->remove(edev);
 839
 840         rte_intr_disable(&pci_dev->intr_handle);
 841
 842         rte_intr_callback_unregister(&pci_dev->intr_handle,
 843                                      qede_interrupt_handler, (void *)eth_dev);
 844
 845         if (edev->num_hwfns > 1)
 846                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
 847
 848         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
 849 }
 850
 851 static void
 852 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
 853 {
 854         struct qede_dev *qdev = eth_dev->data->dev_private;
 855         struct ecore_dev *edev = &qdev->edev;
 856         struct ecore_eth_stats stats;
 857         unsigned int i = 0, j = 0, qid;
 858         struct qede_tx_queue *txq;
 859
 860         qdev->ops->get_vport_stats(edev, &stats);
 861
 862         /* RX Stats */
 863         eth_stats->ipackets = stats.rx_ucast_pkts +
 864             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
 865
 866         eth_stats->ibytes = stats.rx_ucast_bytes +
 867             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
 868
 869         eth_stats->ierrors = stats.rx_crc_errors +
 870             stats.rx_align_errors +
 871             stats.rx_carrier_errors +
 872             stats.rx_oversize_packets +
 873             stats.rx_jabbers + stats.rx_undersize_packets;
 874
 875         eth_stats->rx_nombuf = stats.no_buff_discards;
 876
 877         eth_stats->imissed = stats.mftag_filter_discards +
 878             stats.mac_filter_discards +
 879             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
 880
 881         /* TX stats */
 882         eth_stats->opackets = stats.tx_ucast_pkts +
 883             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
 884
 885         eth_stats->obytes = stats.tx_ucast_bytes +
 886             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
 887
 888         eth_stats->oerrors = stats.tx_err_drop_pkts;
 889
 890         /* Queue stats */
 891         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
 892                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
 893                         eth_stats->q_ipackets[i] =
 894                                 *(uint64_t *)(
 895                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
 896                                         offsetof(struct qede_rx_queue,
 897                                         rcv_pkts));
 898                         eth_stats->q_errors[i] =
 899                                 *(uint64_t *)(
 900                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
 901                                         offsetof(struct qede_rx_queue,
 902                                         rx_hw_errors)) +
 903                                 *(uint64_t *)(
 904                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
 905                                         offsetof(struct qede_rx_queue,
 906                                         rx_alloc_errors));
 907                         i++;
 908                 }
 909
 910                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
 911                         txq = qdev->fp_array[(qid)].txqs[0];
 912                         eth_stats->q_opackets[j] =
 913                                 *((uint64_t *)(uintptr_t)
 914                                         (((uint64_t)(uintptr_t)(txq)) +
 915                                          offsetof(struct qede_tx_queue,
 916                                                   xmit_pkts)));
 917                         j++;
 918                 }
 919         }
 920 }
 921
 922 static unsigned
 923 qede_get_xstats_count(struct qede_dev *qdev) {
 924         return RTE_DIM(qede_xstats_strings) +
 925                 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev));
 926 }
 927
 928 static int
 929 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
 930                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
 931 {
 932         struct qede_dev *qdev = dev->data->dev_private;
 933         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
 934         unsigned int i, qid, stat_idx = 0;
 935
 936         if (xstats_names != NULL) {
 937                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
 938                         snprintf(xstats_names[stat_idx].name,
 939                                 sizeof(xstats_names[stat_idx].name),
 940                                 "%s",
 941                                 qede_xstats_strings[i].name);
 942                         stat_idx++;
 943                 }
 944
 945                 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) {
 946                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
 947                                 snprintf(xstats_names[stat_idx].name,
 948                                         sizeof(xstats_names[stat_idx].name),
 949                                         "%.4s%d%s",
 950                                         qede_rxq_xstats_strings[i].name, qid,
 951                                         qede_rxq_xstats_strings[i].name + 4);
 952                                 stat_idx++;
 953                         }
 954                 }
 955         }
 956
 957         return stat_cnt;
 958 }
 959
 960 static int
 961 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 962                 unsigned int n)
 963 {
 964         struct qede_dev *qdev = dev->data->dev_private;
 965         struct ecore_dev *edev = &qdev->edev;
 966         struct ecore_eth_stats stats;
 967         const unsigned int num = qede_get_xstats_count(qdev);
 968         unsigned int i, qid, stat_idx = 0;
 969
 970         if (n < num)
 971                 return num;
 972
 973         qdev->ops->get_vport_stats(edev, &stats);
 974
 975         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
 976                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
 977                                              qede_xstats_strings[i].offset);
 978                 xstats[stat_idx].id = stat_idx;
 979                 stat_idx++;
 980         }
 981
 982         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
 983                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
 984                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
 985                                 xstats[stat_idx].value = *(uint64_t *)(
 986                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
 987                                          qede_rxq_xstats_strings[i].offset);
 988                                 xstats[stat_idx].id = stat_idx;
 989                                 stat_idx++;
 990                         }
 991                 }
 992         }
 993
 994         return stat_idx;
 995 }
 996
 997 static void
 998 qede_reset_xstats(struct rte_eth_dev *dev)
 999 {
1000         struct qede_dev *qdev = dev->data->dev_private;
1001         struct ecore_dev *edev = &qdev->edev;
1002
1003         ecore_reset_vport_stats(edev);
1004 }
1005
1006 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1007 {
1008         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1009         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1010         struct qed_link_params link_params;
1011         int rc;
1012
1013         DP_INFO(edev, "setting link state %d\n", link_up);
1014         memset(&link_params, 0, sizeof(link_params));
1015         link_params.link_up = link_up;
1016         rc = qdev->ops->common->set_link(edev, &link_params);
1017         if (rc != ECORE_SUCCESS)
1018                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1019
1020         return rc;
1021 }
1022
1023 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1024 {
1025         return qede_dev_set_link_state(eth_dev, true);
1026 }
1027
1028 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1029 {
1030         return qede_dev_set_link_state(eth_dev, false);
1031 }
1032
1033 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1034 {
1035         struct qede_dev *qdev = eth_dev->data->dev_private;
1036         struct ecore_dev *edev = &qdev->edev;
1037
1038         ecore_reset_vport_stats(edev);
1039 }
1040
1041 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1042 {
1043         enum qed_filter_rx_mode_type type =
1044             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1045
1046         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1047                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1048
1049         qede_rx_mode_setting(eth_dev, type);
1050 }
1051
1052 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1053 {
1054         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1055                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_PROMISC);
1056         else
1057                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR);
1058 }
1059
1060 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1061                               struct rte_eth_fc_conf *fc_conf)
1062 {
1063         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1064         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1065         struct qed_link_output current_link;
1066         struct qed_link_params params;
1067
1068         memset(&current_link, 0, sizeof(current_link));
1069         qdev->ops->common->get_link(edev, &current_link);
1070
1071         memset(&params, 0, sizeof(params));
1072         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1073         if (fc_conf->autoneg) {
1074                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1075                         DP_ERR(edev, "Autoneg not supported\n");
1076                         return -EINVAL;
1077                 }
1078                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1079         }
1080
1081         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1082         if (fc_conf->mode == RTE_FC_FULL)
1083                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1084                                         QED_LINK_PAUSE_RX_ENABLE);
1085         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1086                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1087         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1088                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1089
1090         params.link_up = true;
1091         (void)qdev->ops->common->set_link(edev, &params);
1092
1093         return 0;
1094 }
1095
1096 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1097                               struct rte_eth_fc_conf *fc_conf)
1098 {
1099         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1100         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1101         struct qed_link_output current_link;
1102
1103         memset(&current_link, 0, sizeof(current_link));
1104         qdev->ops->common->get_link(edev, &current_link);
1105
1106         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1107                 fc_conf->autoneg = true;
1108
1109         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1110                                          QED_LINK_PAUSE_TX_ENABLE))
1111                 fc_conf->mode = RTE_FC_FULL;
1112         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1113                 fc_conf->mode = RTE_FC_RX_PAUSE;
1114         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1115                 fc_conf->mode = RTE_FC_TX_PAUSE;
1116         else
1117                 fc_conf->mode = RTE_FC_NONE;
1118
1119         return 0;
1120 }
1121
1122 static const uint32_t *
1123 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1124 {
1125         static const uint32_t ptypes[] = {
1126                 RTE_PTYPE_L3_IPV4,
1127                 RTE_PTYPE_L3_IPV6,
1128                 RTE_PTYPE_UNKNOWN
1129         };
1130
1131         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1132                 return ptypes;
1133
1134         return NULL;
1135 }
1136
1137 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1138 {
1139         *rss_caps = 0;
1140         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1141         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1142         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1143         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1144         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1145         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1146 }
1147
1148 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1149                                 struct rte_eth_rss_conf *rss_conf)
1150 {
1151         struct qed_update_vport_params vport_update_params;
1152         struct qede_dev *qdev = eth_dev->data->dev_private;
1153         struct ecore_dev *edev = &qdev->edev;
1154         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1155         uint64_t hf = rss_conf->rss_hf;
1156         int i;
1157
1158         memset(&vport_update_params, 0, sizeof(vport_update_params));
1159
1160         if (hf != 0) {
1161                 /* Enable RSS */
1162                 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1163                 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1164                        sizeof(vport_update_params.rss_params));
1165                 if (key)
1166                         memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1167                                rss_conf->rss_key_len);
1168                 vport_update_params.update_rss_flg = 1;
1169                 qdev->rss_enabled = 1;
1170         } else {
1171                 /* Disable RSS */
1172                 qdev->rss_enabled = 0;
1173         }
1174
1175         /* If the mapping doesn't fit any supported, return */
1176         if (qdev->rss_params.rss_caps == 0 && hf != 0)
1177                 return -EINVAL;
1178
1179         DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1180                                 "Enabling RSS" : "Disabling RSS");
1181
1182         vport_update_params.vport_id = 0;
1183
1184         return qdev->ops->vport_update(edev, &vport_update_params);
1185 }
1186
1187 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1188                            struct rte_eth_rss_conf *rss_conf)
1189 {
1190         struct qede_dev *qdev = eth_dev->data->dev_private;
1191         uint64_t hf;
1192
1193         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1194                 return -EINVAL;
1195
1196         if (rss_conf->rss_key)
1197                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1198                        sizeof(qdev->rss_params.rss_key));
1199
1200         hf = 0;
1201         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1202                         ETH_RSS_IPV4 : 0;
1203         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1204                         ETH_RSS_IPV6 : 0;
1205         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1206                         ETH_RSS_IPV6_EX : 0;
1207         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1208                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1209         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1210                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1211         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1212                         ETH_RSS_IPV6_TCP_EX : 0;
1213
1214         rss_conf->rss_hf = hf;
1215
1216         return 0;
1217 }
1218
1219 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1220                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1221                                 uint16_t reta_size)
1222 {
1223         struct qed_update_vport_params vport_update_params;
1224         struct qede_dev *qdev = eth_dev->data->dev_private;
1225         struct ecore_dev *edev = &qdev->edev;
1226         uint16_t i, idx, shift;
1227
1228         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1229                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1230                        reta_size);
1231                 return -EINVAL;
1232         }
1233
1234         memset(&vport_update_params, 0, sizeof(vport_update_params));
1235         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1236                sizeof(vport_update_params.rss_params));
1237
1238         for (i = 0; i < reta_size; i++) {
1239                 idx = i / RTE_RETA_GROUP_SIZE;
1240                 shift = i % RTE_RETA_GROUP_SIZE;
1241                 if (reta_conf[idx].mask & (1ULL << shift)) {
1242                         uint8_t entry = reta_conf[idx].reta[shift];
1243                         qdev->rss_params.rss_ind_table[i] = entry;
1244                 }
1245         }
1246
1247         vport_update_params.update_rss_flg = 1;
1248         vport_update_params.vport_id = 0;
1249
1250         return qdev->ops->vport_update(edev, &vport_update_params);
1251 }
1252
1253 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1254                         struct rte_eth_rss_reta_entry64 *reta_conf,
1255                         uint16_t reta_size)
1256 {
1257         struct qede_dev *qdev = eth_dev->data->dev_private;
1258         uint16_t i, idx, shift;
1259
1260         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1261                 struct ecore_dev *edev = &qdev->edev;
1262                 DP_ERR(edev, "reta_size %d is not supported\n",
1263                        reta_size);
1264         }
1265
1266         for (i = 0; i < reta_size; i++) {
1267                 idx = i / RTE_RETA_GROUP_SIZE;
1268                 shift = i % RTE_RETA_GROUP_SIZE;
1269                 if (reta_conf[idx].mask & (1ULL << shift)) {
1270                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1271                         reta_conf[idx].reta[shift] = entry;
1272                 }
1273         }
1274
1275         return 0;
1276 }
1277
1278 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1279 {
1280         uint32_t frame_size;
1281         struct qede_dev *qdev = dev->data->dev_private;
1282         struct rte_eth_dev_info dev_info = {0};
1283
1284         qede_dev_info_get(dev, &dev_info);
1285
1286         /* VLAN_TAG = 4 */
1287         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1288
1289         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1290                 return -EINVAL;
1291
1292         if (!dev->data->scattered_rx &&
1293             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1294                 return -EINVAL;
1295
1296         if (frame_size > ETHER_MAX_LEN)
1297                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1298         else
1299                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1300
1301         /* update max frame size */
1302         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1303         qdev->mtu = mtu;
1304         qede_dev_stop(dev);
1305         qede_dev_start(dev);
1306
1307         return 0;
1308 }
1309
1310 static const struct eth_dev_ops qede_eth_dev_ops = {
1311         .dev_configure = qede_dev_configure,
1312         .dev_infos_get = qede_dev_info_get,
1313         .rx_queue_setup = qede_rx_queue_setup,
1314         .rx_queue_release = qede_rx_queue_release,
1315         .tx_queue_setup = qede_tx_queue_setup,
1316         .tx_queue_release = qede_tx_queue_release,
1317         .dev_start = qede_dev_start,
1318         .dev_set_link_up = qede_dev_set_link_up,
1319         .dev_set_link_down = qede_dev_set_link_down,
1320         .link_update = qede_link_update,
1321         .promiscuous_enable = qede_promiscuous_enable,
1322         .promiscuous_disable = qede_promiscuous_disable,
1323         .allmulticast_enable = qede_allmulticast_enable,
1324         .allmulticast_disable = qede_allmulticast_disable,
1325         .dev_stop = qede_dev_stop,
1326         .dev_close = qede_dev_close,
1327         .stats_get = qede_get_stats,
1328         .stats_reset = qede_reset_stats,
1329         .xstats_get = qede_get_xstats,
1330         .xstats_reset = qede_reset_xstats,
1331         .xstats_get_names = qede_get_xstats_names,
1332         .mac_addr_add = qede_mac_addr_add,
1333         .mac_addr_remove = qede_mac_addr_remove,
1334         .mac_addr_set = qede_mac_addr_set,
1335         .vlan_offload_set = qede_vlan_offload_set,
1336         .vlan_filter_set = qede_vlan_filter_set,
1337         .flow_ctrl_set = qede_flow_ctrl_set,
1338         .flow_ctrl_get = qede_flow_ctrl_get,
1339         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1340         .rss_hash_update = qede_rss_hash_update,
1341         .rss_hash_conf_get = qede_rss_hash_conf_get,
1342         .reta_update  = qede_rss_reta_update,
1343         .reta_query  = qede_rss_reta_query,
1344         .mtu_set = qede_set_mtu,
1345 };
1346
1347 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1348         .dev_configure = qede_dev_configure,
1349         .dev_infos_get = qede_dev_info_get,
1350         .rx_queue_setup = qede_rx_queue_setup,
1351         .rx_queue_release = qede_rx_queue_release,
1352         .tx_queue_setup = qede_tx_queue_setup,
1353         .tx_queue_release = qede_tx_queue_release,
1354         .dev_start = qede_dev_start,
1355         .dev_set_link_up = qede_dev_set_link_up,
1356         .dev_set_link_down = qede_dev_set_link_down,
1357         .link_update = qede_link_update,
1358         .promiscuous_enable = qede_promiscuous_enable,
1359         .promiscuous_disable = qede_promiscuous_disable,
1360         .allmulticast_enable = qede_allmulticast_enable,
1361         .allmulticast_disable = qede_allmulticast_disable,
1362         .dev_stop = qede_dev_stop,
1363         .dev_close = qede_dev_close,
1364         .stats_get = qede_get_stats,
1365         .stats_reset = qede_reset_stats,
1366         .xstats_get = qede_get_xstats,
1367         .xstats_reset = qede_reset_xstats,
1368         .xstats_get_names = qede_get_xstats_names,
1369         .vlan_offload_set = qede_vlan_offload_set,
1370         .vlan_filter_set = qede_vlan_filter_set,
1371         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1372         .rss_hash_update = qede_rss_hash_update,
1373         .rss_hash_conf_get = qede_rss_hash_conf_get,
1374         .reta_update  = qede_rss_reta_update,
1375         .reta_query  = qede_rss_reta_query,
1376         .mtu_set = qede_set_mtu,
1377 };
1378
1379 static void qede_update_pf_params(struct ecore_dev *edev)
1380 {
1381         struct ecore_pf_params pf_params;
1382         /* 32 rx + 32 tx */
1383         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1384         pf_params.eth_pf_params.num_cons = 64;
1385         qed_ops->common->update_pf_params(edev, &pf_params);
1386 }
1387
1388 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1389 {
1390         struct rte_pci_device *pci_dev;
1391         struct rte_pci_addr pci_addr;
1392         struct qede_dev *adapter;
1393         struct ecore_dev *edev;
1394         struct qed_dev_eth_info dev_info;
1395         struct qed_slowpath_params params;
1396         static bool do_once = true;
1397         uint8_t bulletin_change;
1398         uint8_t vf_mac[ETHER_ADDR_LEN];
1399         uint8_t is_mac_forced;
1400         bool is_mac_exist;
1401         /* Fix up ecore debug level */
1402         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1403         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1404         uint32_t max_mac_addrs;
1405         int rc;
1406
1407         /* Extract key data structures */
1408         adapter = eth_dev->data->dev_private;
1409         edev = &adapter->edev;
1410         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1411         pci_addr = pci_dev->addr;
1412
1413         PMD_INIT_FUNC_TRACE(edev);
1414
1415         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1416                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1417                  eth_dev->data->port_id);
1418
1419         eth_dev->rx_pkt_burst = qede_recv_pkts;
1420         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1421
1422         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1423                 DP_NOTICE(edev, false,
1424                           "Skipping device init from secondary process\n");
1425                 return 0;
1426         }
1427
1428         rte_eth_copy_pci_info(eth_dev, pci_dev);
1429
1430         qed_ops = qed_get_eth_ops();
1431         if (!qed_ops) {
1432                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1433                 return -EINVAL;
1434         }
1435
1436         DP_INFO(edev, "Starting qede probe\n");
1437
1438         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1439                                     dp_module, dp_level, is_vf);
1440
1441         if (rc != 0) {
1442                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1443                 return -ENODEV;
1444         }
1445
1446         qede_update_pf_params(edev);
1447
1448         rte_intr_callback_register(&pci_dev->intr_handle,
1449                                    qede_interrupt_handler, (void *)eth_dev);
1450
1451         if (rte_intr_enable(&pci_dev->intr_handle)) {
1452                 DP_ERR(edev, "rte_intr_enable() failed\n");
1453                 return -ENODEV;
1454         }
1455
1456         /* Start the Slowpath-process */
1457         memset(&params, 0, sizeof(struct qed_slowpath_params));
1458         params.int_mode = ECORE_INT_MODE_MSIX;
1459         params.drv_major = QEDE_PMD_VERSION_MAJOR;
1460         params.drv_minor = QEDE_PMD_VERSION_MINOR;
1461         params.drv_rev = QEDE_PMD_VERSION_REVISION;
1462         params.drv_eng = QEDE_PMD_VERSION_PATCH;
1463         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1464                 QEDE_PMD_DRV_VER_STR_SIZE);
1465
1466         /* For CMT mode device do periodic polling for slowpath events.
1467          * This is required since uio device uses only one MSI-x
1468          * interrupt vector but we need one for each engine.
1469          */
1470         if (edev->num_hwfns > 1 && IS_PF(edev)) {
1471                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1472                                        qede_poll_sp_sb_cb,
1473                                        (void *)eth_dev);
1474                 if (rc != 0) {
1475                         DP_ERR(edev, "Unable to start periodic"
1476                                      " timer rc %d\n", rc);
1477                         return -EINVAL;
1478                 }
1479         }
1480
1481         rc = qed_ops->common->slowpath_start(edev, &params);
1482         if (rc) {
1483                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1484                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1485                                      (void *)eth_dev);
1486                 return -ENODEV;
1487         }
1488
1489         rc = qed_ops->fill_dev_info(edev, &dev_info);
1490         if (rc) {
1491                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1492                 qed_ops->common->slowpath_stop(edev);
1493                 qed_ops->common->remove(edev);
1494                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1495                                      (void *)eth_dev);
1496                 return -ENODEV;
1497         }
1498
1499         qede_alloc_etherdev(adapter, &dev_info);
1500
1501         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
1502
1503         if (!is_vf)
1504                 adapter->dev_info.num_mac_addrs =
1505                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1506                                             ECORE_MAC);
1507         else
1508                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1509                                              &adapter->dev_info.num_mac_addrs);
1510
1511         /* Allocate memory for storing MAC addr */
1512         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1513                                         (ETHER_ADDR_LEN *
1514                                         adapter->dev_info.num_mac_addrs),
1515                                         RTE_CACHE_LINE_SIZE);
1516
1517         if (eth_dev->data->mac_addrs == NULL) {
1518                 DP_ERR(edev, "Failed to allocate MAC address\n");
1519                 qed_ops->common->slowpath_stop(edev);
1520                 qed_ops->common->remove(edev);
1521                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1522                                      (void *)eth_dev);
1523                 return -ENOMEM;
1524         }
1525
1526         if (!is_vf) {
1527                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1528                                 hw_info.hw_mac_addr,
1529                                 &eth_dev->data->mac_addrs[0]);
1530                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1531                                 &adapter->primary_mac);
1532         } else {
1533                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1534                                        &bulletin_change);
1535                 if (bulletin_change) {
1536                         is_mac_exist =
1537                             ecore_vf_bulletin_get_forced_mac(
1538                                                 ECORE_LEADING_HWFN(edev),
1539                                                 vf_mac,
1540                                                 &is_mac_forced);
1541                         if (is_mac_exist && is_mac_forced) {
1542                                 DP_INFO(edev, "VF macaddr received from PF\n");
1543                                 ether_addr_copy((struct ether_addr *)&vf_mac,
1544                                                 &eth_dev->data->mac_addrs[0]);
1545                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1546                                                 &adapter->primary_mac);
1547                         } else {
1548                                 DP_NOTICE(edev, false,
1549                                           "No VF macaddr assigned\n");
1550                         }
1551                 }
1552         }
1553
1554         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1555
1556         if (do_once) {
1557                 qede_print_adapter_info(adapter);
1558                 do_once = false;
1559         }
1560
1561         adapter->state = QEDE_DEV_INIT;
1562
1563         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1564                   adapter->primary_mac.addr_bytes[0],
1565                   adapter->primary_mac.addr_bytes[1],
1566                   adapter->primary_mac.addr_bytes[2],
1567                   adapter->primary_mac.addr_bytes[3],
1568                   adapter->primary_mac.addr_bytes[4],
1569                   adapter->primary_mac.addr_bytes[5]);
1570
1571         return rc;
1572 }
1573
1574 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1575 {
1576         return qede_common_dev_init(eth_dev, 1);
1577 }
1578
1579 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1580 {
1581         return qede_common_dev_init(eth_dev, 0);
1582 }
1583
1584 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1585 {
1586         /* only uninitialize in the primary process */
1587         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1588                 return 0;
1589
1590         /* safe to close dev here */
1591         qede_dev_close(eth_dev);
1592
1593         eth_dev->dev_ops = NULL;
1594         eth_dev->rx_pkt_burst = NULL;
1595         eth_dev->tx_pkt_burst = NULL;
1596
1597         if (eth_dev->data->mac_addrs)
1598                 rte_free(eth_dev->data->mac_addrs);
1599
1600         eth_dev->data->mac_addrs = NULL;
1601
1602         return 0;
1603 }
1604
1605 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1606 {
1607         return qede_dev_common_uninit(eth_dev);
1608 }
1609
1610 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1611 {
1612         return qede_dev_common_uninit(eth_dev);
1613 }
1614
1615 static struct rte_pci_id pci_id_qedevf_map[] = {
1616 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1617         {
1618                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1619         },
1620         {
1621                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1622         },
1623         {.vendor_id = 0,}
1624 };
1625
1626 static struct rte_pci_id pci_id_qede_map[] = {
1627 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1628         {
1629                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1630         },
1631         {
1632                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1633         },
1634         {
1635                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1636         },
1637         {
1638                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1639         },
1640         {
1641                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1642         },
1643         {.vendor_id = 0,}
1644 };
1645
1646 static struct eth_driver rte_qedevf_pmd = {
1647         .pci_drv = {
1648                     .id_table = pci_id_qedevf_map,
1649                     .drv_flags =
1650                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1651                     .probe = rte_eth_dev_pci_probe,
1652                     .remove = rte_eth_dev_pci_remove,
1653                    },
1654         .eth_dev_init = qedevf_eth_dev_init,
1655         .eth_dev_uninit = qedevf_eth_dev_uninit,
1656         .dev_private_size = sizeof(struct qede_dev),
1657 };
1658
1659 static struct eth_driver rte_qede_pmd = {
1660         .pci_drv = {
1661                     .id_table = pci_id_qede_map,
1662                     .drv_flags =
1663                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1664                     .probe = rte_eth_dev_pci_probe,
1665                     .remove = rte_eth_dev_pci_remove,
1666                    },
1667         .eth_dev_init = qede_eth_dev_init,
1668         .eth_dev_uninit = qede_eth_dev_uninit,
1669         .dev_private_size = sizeof(struct qede_dev),
1670 };
1671
1672 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1673 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1674 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
1675 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1676 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
1677 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");