drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329
 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 331 {
 332         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 333         ucast->is_rx_filter = true;
 334         ucast->is_tx_filter = true;
 335         /* ucast->assert_on_error = true; - For debug */
 336 }
 337
 338 static void qede_set_cmn_tunn_param(struct ecore_tunn_update_params *params,
 339                                      uint8_t clss, uint64_t mode, uint64_t mask)
 340 {
 341         memset(params, 0, sizeof(struct ecore_tunn_update_params));
 342         params->tunn_mode = mode;
 343         params->tunn_mode_update_mask = mask;
 344         params->update_tx_pf_clss = 1;
 345         params->update_rx_pf_clss = 1;
 346         params->tunn_clss_vxlan = clss;
 347 }
 348
 349 static int
 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 351                   bool add)
 352 {
 353         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 354         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 355         struct qede_ucast_entry *tmp = NULL;
 356         struct qede_ucast_entry *u;
 357         struct ether_addr *mac_addr;
 358
 359         mac_addr  = (struct ether_addr *)ucast->mac;
 360         if (add) {
 361                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 362                         if ((memcmp(mac_addr, &tmp->mac,
 363                                     ETHER_ADDR_LEN) == 0) &&
 364                              ucast->vlan == tmp->vlan) {
 365                                 DP_ERR(edev, "Unicast MAC is already added"
 366                                        " with vlan = %u, vni = %u\n",
 367                                        ucast->vlan,  ucast->vni);
 368                                         return -EEXIST;
 369                         }
 370                 }
 371                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 372                                RTE_CACHE_LINE_SIZE);
 373                 if (!u) {
 374                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 375                         return -ENOMEM;
 376                 }
 377                 ether_addr_copy(mac_addr, &u->mac);
 378                 u->vlan = ucast->vlan;
 379                 u->vni = ucast->vni;
 380                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 381                 qdev->num_uc_addr++;
 382         } else {
 383                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 384                         if ((memcmp(mac_addr, &tmp->mac,
 385                                     ETHER_ADDR_LEN) == 0) &&
 386                             ucast->vlan == tmp->vlan      &&
 387                             ucast->vni == tmp->vni)
 388                         break;
 389                 }
 390                 if (tmp == NULL) {
 391                         DP_INFO(edev, "Unicast MAC is not found\n");
 392                         return -EINVAL;
 393                 }
 394                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 395                 qdev->num_uc_addr--;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int
 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 403                   bool add)
 404 {
 405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 407         struct ether_addr *mac_addr;
 408         struct qede_mcast_entry *tmp = NULL;
 409         struct qede_mcast_entry *m;
 410
 411         mac_addr  = (struct ether_addr *)mcast->mac;
 412         if (add) {
 413                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 414                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 415                                 DP_ERR(edev,
 416                                         "Multicast MAC is already added\n");
 417                                 return -EEXIST;
 418                         }
 419                 }
 420                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 421                         RTE_CACHE_LINE_SIZE);
 422                 if (!m) {
 423                         DP_ERR(edev,
 424                                 "Did not allocate memory for mcast\n");
 425                         return -ENOMEM;
 426                 }
 427                 ether_addr_copy(mac_addr, &m->mac);
 428                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 429                 qdev->num_mc_addr++;
 430         } else {
 431                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 432                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 433                                 break;
 434                 }
 435                 if (tmp == NULL) {
 436                         DP_INFO(edev, "Multicast mac is not found\n");
 437                         return -EINVAL;
 438                 }
 439                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 440                              qede_mcast_entry, list);
 441                 qdev->num_mc_addr--;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static enum _ecore_status_t
 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 449                  bool add)
 450 {
 451         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 452         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 453         enum _ecore_status_t rc;
 454         struct ecore_filter_mcast mcast;
 455         struct qede_mcast_entry *tmp;
 456         uint16_t j = 0;
 457
 458         /* Multicast */
 459         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 460                 if (add) {
 461                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 462                                 DP_ERR(edev,
 463                                        "Mcast filter table limit exceeded, "
 464                                        "Please enable mcast promisc mode\n");
 465                                 return -ECORE_INVAL;
 466                         }
 467                 }
 468                 rc = qede_mcast_filter(eth_dev, ucast, add);
 469                 if (rc == 0) {
 470                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 471                         memset(&mcast, 0, sizeof(mcast));
 472                         mcast.num_mc_addrs = qdev->num_mc_addr;
 473                         mcast.opcode = ECORE_FILTER_ADD;
 474                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 475                                 ether_addr_copy(&tmp->mac,
 476                                         (struct ether_addr *)&mcast.mac[j]);
 477                                 j++;
 478                         }
 479                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 480                                                     ECORE_SPQ_MODE_CB, NULL);
 481                 }
 482                 if (rc != ECORE_SUCCESS) {
 483                         DP_ERR(edev, "Failed to add multicast filter"
 484                                " rc = %d, op = %d\n", rc, add);
 485                 }
 486         } else { /* Unicast */
 487                 if (add) {
 488                         if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
 489                                 DP_ERR(edev,
 490                                        "Ucast filter table limit exceeded,"
 491                                        " Please enable promisc mode\n");
 492                                 return -ECORE_INVAL;
 493                         }
 494                 }
 495                 rc = qede_ucast_filter(eth_dev, ucast, add);
 496                 if (rc == 0)
 497                         rc = ecore_filter_ucast_cmd(edev, ucast,
 498                                                     ECORE_SPQ_MODE_CB, NULL);
 499                 if (rc != ECORE_SUCCESS) {
 500                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 501                                rc, add);
 502                 }
 503         }
 504
 505         return rc;
 506 }
 507
 508 static void
 509 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 510                   uint32_t index, __rte_unused uint32_t pool)
 511 {
 512         struct ecore_filter_ucast ucast;
 513
 514         qede_set_ucast_cmn_params(&ucast);
 515         ucast.type = ECORE_FILTER_MAC;
 516         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 517         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 518 }
 519
 520 static void
 521 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 522 {
 523         struct qede_dev *qdev = eth_dev->data->dev_private;
 524         struct ecore_dev *edev = &qdev->edev;
 525         struct ether_addr mac_addr;
 526         struct ecore_filter_ucast ucast;
 527         int rc;
 528
 529         PMD_INIT_FUNC_TRACE(edev);
 530
 531         if (index >= qdev->dev_info.num_mac_addrs) {
 532                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 533                        index, qdev->dev_info.num_mac_addrs);
 534                 return;
 535         }
 536
 537         qede_set_ucast_cmn_params(&ucast);
 538         ucast.opcode = ECORE_FILTER_REMOVE;
 539         ucast.type = ECORE_FILTER_MAC;
 540
 541         /* Use the index maintained by rte */
 542         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 543                         (struct ether_addr *)&ucast.mac);
 544
 545         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 546 }
 547
 548 static void
 549 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 550 {
 551         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 552         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 553         struct ecore_filter_ucast ucast;
 554         int rc;
 555
 556         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 557                                                mac_addr->addr_bytes)) {
 558                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 559                 ether_addr_copy(&qdev->primary_mac,
 560                                 &eth_dev->data->mac_addrs[0]);
 561                 return;
 562         }
 563
 564         /* First remove the primary mac */
 565         qede_set_ucast_cmn_params(&ucast);
 566         ucast.opcode = ECORE_FILTER_REMOVE;
 567         ucast.type = ECORE_FILTER_MAC;
 568         ether_addr_copy(&qdev->primary_mac,
 569                         (struct ether_addr *)&ucast.mac);
 570         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 571         if (rc != 0) {
 572                 DP_ERR(edev, "Unable to remove current macaddr"
 573                              " Reverting to previous default mac\n");
 574                 ether_addr_copy(&qdev->primary_mac,
 575                                 &eth_dev->data->mac_addrs[0]);
 576                 return;
 577         }
 578
 579         /* Add new MAC */
 580         ucast.opcode = ECORE_FILTER_ADD;
 581         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 582         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 583         if (rc != 0)
 584                 DP_ERR(edev, "Unable to add new default mac\n");
 585         else
 586                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 587 }
 588
 589 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 590 {
 591         struct ecore_dev *edev = &qdev->edev;
 592         struct qed_update_vport_params params = {
 593                 .vport_id = 0,
 594                 .accept_any_vlan = action,
 595                 .update_accept_any_vlan_flg = 1,
 596         };
 597         int rc;
 598
 599         /* Proceed only if action actually needs to be performed */
 600         if (qdev->accept_any_vlan == action)
 601                 return;
 602
 603         rc = qdev->ops->vport_update(edev, &params);
 604         if (rc) {
 605                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 606                        action ? "enable" : "disable");
 607         } else {
 608                 DP_INFO(edev, "%s accept-any-vlan\n",
 609                         action ? "enabled" : "disabled");
 610                 qdev->accept_any_vlan = action;
 611         }
 612 }
 613
 614 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 615 {
 616         struct qed_update_vport_params vport_update_params;
 617         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 618         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 619         int rc;
 620
 621         memset(&vport_update_params, 0, sizeof(vport_update_params));
 622         vport_update_params.vport_id = 0;
 623         vport_update_params.update_inner_vlan_removal_flg = 1;
 624         vport_update_params.inner_vlan_removal_flg = set_stripping;
 625         rc = qdev->ops->vport_update(edev, &vport_update_params);
 626         if (rc) {
 627                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 628                 return rc;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 635 {
 636         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 637         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 638         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 639
 640         if (mask & ETH_VLAN_STRIP_MASK) {
 641                 if (rxmode->hw_vlan_strip)
 642                         (void)qede_vlan_stripping(eth_dev, 1);
 643                 else
 644                         (void)qede_vlan_stripping(eth_dev, 0);
 645         }
 646
 647         if (mask & ETH_VLAN_FILTER_MASK) {
 648                 /* VLAN filtering kicks in when a VLAN is added */
 649                 if (rxmode->hw_vlan_filter) {
 650                         qede_vlan_filter_set(eth_dev, 0, 1);
 651                 } else {
 652                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 653                                 DP_NOTICE(edev, false,
 654                                   " Please remove existing VLAN filters"
 655                                   " before disabling VLAN filtering\n");
 656                                 /* Signal app that VLAN filtering is still
 657                                  * enabled
 658                                  */
 659                                 rxmode->hw_vlan_filter = true;
 660                         } else {
 661                                 qede_vlan_filter_set(eth_dev, 0, 0);
 662                         }
 663                 }
 664         }
 665
 666         if (mask & ETH_VLAN_EXTEND_MASK)
 667                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 668                         " and classification is based on outer tag only\n");
 669
 670         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 671                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 672 }
 673
 674 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 675                                 uint16_t vlan_id, int on)
 676 {
 677         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 678         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 679         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 680         struct qede_vlan_entry *tmp = NULL;
 681         struct qede_vlan_entry *vlan;
 682         struct ecore_filter_ucast ucast;
 683         int rc;
 684
 685         if (on) {
 686                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 687                         DP_INFO(edev, "Reached max VLAN filter limit"
 688                                       " enabling accept_any_vlan\n");
 689                         qede_config_accept_any_vlan(qdev, true);
 690                         return 0;
 691                 }
 692
 693                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 694                         if (tmp->vid == vlan_id) {
 695                                 DP_ERR(edev, "VLAN %u already configured\n",
 696                                        vlan_id);
 697                                 return -EEXIST;
 698                         }
 699                 }
 700
 701                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 702                                   RTE_CACHE_LINE_SIZE);
 703
 704                 if (!vlan) {
 705                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 706                         return -ENOMEM;
 707                 }
 708
 709                 qede_set_ucast_cmn_params(&ucast);
 710                 ucast.opcode = ECORE_FILTER_ADD;
 711                 ucast.type = ECORE_FILTER_VLAN;
 712                 ucast.vlan = vlan_id;
 713                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 714                                             NULL);
 715                 if (rc != 0) {
 716                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 717                                rc);
 718                         rte_free(vlan);
 719                 } else {
 720                         vlan->vid = vlan_id;
 721                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 722                         qdev->configured_vlans++;
 723                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 724                                 vlan_id, qdev->configured_vlans);
 725                 }
 726         } else {
 727                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 728                         if (tmp->vid == vlan_id)
 729                                 break;
 730                 }
 731
 732                 if (!tmp) {
 733                         if (qdev->configured_vlans == 0) {
 734                                 DP_INFO(edev,
 735                                         "No VLAN filters configured yet\n");
 736                                 return 0;
 737                         }
 738
 739                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 740                         return -EINVAL;
 741                 }
 742
 743                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 744
 745                 qede_set_ucast_cmn_params(&ucast);
 746                 ucast.opcode = ECORE_FILTER_REMOVE;
 747                 ucast.type = ECORE_FILTER_VLAN;
 748                 ucast.vlan = vlan_id;
 749                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 750                                             NULL);
 751                 if (rc != 0) {
 752                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 753                                vlan_id, rc);
 754                 } else {
 755                         qdev->configured_vlans--;
 756                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 757                                 vlan_id, qdev->configured_vlans);
 758                 }
 759         }
 760
 761         return rc;
 762 }
 763
 764 static int qede_init_vport(struct qede_dev *qdev)
 765 {
 766         struct ecore_dev *edev = &qdev->edev;
 767         struct qed_start_vport_params start = {0};
 768         int rc;
 769
 770         start.remove_inner_vlan = 1;
 771         start.gro_enable = 0;
 772         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 773         start.vport_id = 0;
 774         start.drop_ttl0 = false;
 775         start.clear_stats = 1;
 776         start.handle_ptp_pkts = 0;
 777
 778         rc = qdev->ops->vport_start(edev, &start);
 779         if (rc) {
 780                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 781                 return rc;
 782         }
 783
 784         DP_INFO(edev,
 785                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 786                 start.vport_id, ETHER_MTU);
 787
 788         return 0;
 789 }
 790
 791 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 792 {
 793         struct qede_dev *qdev = eth_dev->data->dev_private;
 794         struct ecore_dev *edev = &qdev->edev;
 795         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 796         int rc, i, j;
 797
 798         PMD_INIT_FUNC_TRACE(edev);
 799
 800         /* Check requirements for 100G mode */
 801         if (edev->num_hwfns > 1) {
 802                 if (eth_dev->data->nb_rx_queues < 2 ||
 803                     eth_dev->data->nb_tx_queues < 2) {
 804                         DP_NOTICE(edev, false,
 805                                   "100G mode needs min. 2 RX/TX queues\n");
 806                         return -EINVAL;
 807                 }
 808
 809                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 810                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 811                         DP_NOTICE(edev, false,
 812                                   "100G mode needs even no. of RX/TX queues\n");
 813                         return -EINVAL;
 814                 }
 815         }
 816
 817         /* Sanity checks and throw warnings */
 818         if (rxmode->enable_scatter == 1)
 819                 eth_dev->data->scattered_rx = 1;
 820
 821         if (rxmode->enable_lro == 1) {
 822                 DP_INFO(edev, "LRO is not supported\n");
 823                 return -EINVAL;
 824         }
 825
 826         if (!rxmode->hw_strip_crc)
 827                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 828
 829         if (!rxmode->hw_ip_checksum)
 830                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 831                               "in hw\n");
 832
 833         /* Check for the port restart case */
 834         if (qdev->state != QEDE_DEV_INIT) {
 835                 rc = qdev->ops->vport_stop(edev, 0);
 836                 if (rc != 0)
 837                         return rc;
 838                 qede_dealloc_fp_resc(eth_dev);
 839         }
 840
 841         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 842         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 843         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 844
 845         /* Fastpath status block should be initialized before sending
 846          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 847          */
 848         rc = qede_alloc_fp_resc(qdev);
 849         if (rc != 0)
 850                 return rc;
 851
 852         /* Issue VPORT-START with default config values to allow
 853          * other port configurations early on.
 854          */
 855         rc = qede_init_vport(qdev);
 856         if (rc != 0)
 857                 return rc;
 858
 859         SLIST_INIT(&qdev->vlan_list_head);
 860
 861         /* Add primary mac for PF */
 862         if (IS_PF(edev))
 863                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 864
 865         /* Enable VLAN offloads by default */
 866         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 867                                        ETH_VLAN_FILTER_MASK |
 868                                        ETH_VLAN_EXTEND_MASK);
 869
 870         qdev->state = QEDE_DEV_CONFIG;
 871
 872         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 873                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 874                 qdev->num_tc);
 875
 876         return 0;
 877 }
 878
 879 /* Info about HW descriptor ring limitations */
 880 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 881         .nb_max = NUM_RX_BDS_MAX,
 882         .nb_min = 128,
 883         .nb_align = 128 /* lowest common multiple */
 884 };
 885
 886 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 887         .nb_max = NUM_TX_BDS_MAX,
 888         .nb_min = 256,
 889         .nb_align = 256
 890 };
 891
 892 static void
 893 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 894                   struct rte_eth_dev_info *dev_info)
 895 {
 896         struct qede_dev *qdev = eth_dev->data->dev_private;
 897         struct ecore_dev *edev = &qdev->edev;
 898         struct qed_link_output link;
 899         uint32_t speed_cap = 0;
 900
 901         PMD_INIT_FUNC_TRACE(edev);
 902
 903         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 904         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 905                                               QEDE_ETH_OVERHEAD);
 906         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 907         dev_info->rx_desc_lim = qede_rx_desc_lim;
 908         dev_info->tx_desc_lim = qede_tx_desc_lim;
 909         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 910         dev_info->max_tx_queues = dev_info->max_rx_queues;
 911         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 912         if (IS_VF(edev))
 913                 dev_info->max_vfs = 0;
 914         else
 915                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 916         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 917         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 918
 919         dev_info->default_txconf = (struct rte_eth_txconf) {
 920                 .txq_flags = QEDE_TXQ_FLAGS,
 921         };
 922
 923         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
 924                                      DEV_RX_OFFLOAD_IPV4_CKSUM |
 925                                      DEV_RX_OFFLOAD_UDP_CKSUM |
 926                                      DEV_RX_OFFLOAD_TCP_CKSUM);
 927         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 928                                      DEV_TX_OFFLOAD_IPV4_CKSUM |
 929                                      DEV_TX_OFFLOAD_UDP_CKSUM |
 930                                      DEV_TX_OFFLOAD_TCP_CKSUM);
 931
 932         memset(&link, 0, sizeof(struct qed_link_output));
 933         qdev->ops->common->get_link(edev, &link);
 934         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 935                 speed_cap |= ETH_LINK_SPEED_1G;
 936         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 937                 speed_cap |= ETH_LINK_SPEED_10G;
 938         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 939                 speed_cap |= ETH_LINK_SPEED_25G;
 940         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 941                 speed_cap |= ETH_LINK_SPEED_40G;
 942         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 943                 speed_cap |= ETH_LINK_SPEED_50G;
 944         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 945                 speed_cap |= ETH_LINK_SPEED_100G;
 946         dev_info->speed_capa = speed_cap;
 947 }
 948
 949 /* return 0 means link status changed, -1 means not changed */
 950 static int
 951 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 952 {
 953         struct qede_dev *qdev = eth_dev->data->dev_private;
 954         struct ecore_dev *edev = &qdev->edev;
 955         uint16_t link_duplex;
 956         struct qed_link_output link;
 957         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 958
 959         memset(&link, 0, sizeof(struct qed_link_output));
 960         qdev->ops->common->get_link(edev, &link);
 961
 962         /* Link Speed */
 963         curr->link_speed = link.speed;
 964
 965         /* Link Mode */
 966         switch (link.duplex) {
 967         case QEDE_DUPLEX_HALF:
 968                 link_duplex = ETH_LINK_HALF_DUPLEX;
 969                 break;
 970         case QEDE_DUPLEX_FULL:
 971                 link_duplex = ETH_LINK_FULL_DUPLEX;
 972                 break;
 973         case QEDE_DUPLEX_UNKNOWN:
 974         default:
 975                 link_duplex = -1;
 976         }
 977         curr->link_duplex = link_duplex;
 978
 979         /* Link Status */
 980         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 981
 982         /* AN */
 983         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 984                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 985
 986         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 987                 curr->link_speed, curr->link_duplex,
 988                 curr->link_autoneg, curr->link_status);
 989
 990         /* return 0 means link status changed, -1 means not changed */
 991         return ((curr->link_status == link.link_up) ? -1 : 0);
 992 }
 993
 994 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 995 {
 996         struct qede_dev *qdev = eth_dev->data->dev_private;
 997         struct ecore_dev *edev = &qdev->edev;
 998
 999         PMD_INIT_FUNC_TRACE(edev);
1000
1001         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1002
1003         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1004                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1005
1006         qed_configure_filter_rx_mode(eth_dev, type);
1007 }
1008
1009 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1010 {
1011         struct qede_dev *qdev = eth_dev->data->dev_private;
1012         struct ecore_dev *edev = &qdev->edev;
1013
1014         PMD_INIT_FUNC_TRACE(edev);
1015
1016         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1017                 qed_configure_filter_rx_mode(eth_dev,
1018                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1019         else
1020                 qed_configure_filter_rx_mode(eth_dev,
1021                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1022 }
1023
1024 static void qede_poll_sp_sb_cb(void *param)
1025 {
1026         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1027         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1028         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1029         int rc;
1030
1031         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1032         qede_interrupt_action(&edev->hwfns[1]);
1033
1034         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1035                                qede_poll_sp_sb_cb,
1036                                (void *)eth_dev);
1037         if (rc != 0) {
1038                 DP_ERR(edev, "Unable to start periodic"
1039                              " timer rc %d\n", rc);
1040                 assert(false && "Unable to start periodic timer");
1041         }
1042 }
1043
1044 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1045 {
1046         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1047         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1048         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1049         int rc;
1050
1051         PMD_INIT_FUNC_TRACE(edev);
1052
1053         /* dev_stop() shall cleanup fp resources in hw but without releasing
1054          * dma memories and sw structures so that dev_start() can be called
1055          * by the app without reconfiguration. However, in dev_close() we
1056          * can release all the resources and device can be brought up newly
1057          */
1058         if (qdev->state != QEDE_DEV_STOP)
1059                 qede_dev_stop(eth_dev);
1060         else
1061                 DP_INFO(edev, "Device is already stopped\n");
1062
1063         rc = qdev->ops->vport_stop(edev, 0);
1064         if (rc != 0)
1065                 DP_ERR(edev, "Failed to stop VPORT\n");
1066
1067         qede_dealloc_fp_resc(eth_dev);
1068
1069         qdev->ops->common->slowpath_stop(edev);
1070
1071         qdev->ops->common->remove(edev);
1072
1073         rte_intr_disable(&pci_dev->intr_handle);
1074
1075         rte_intr_callback_unregister(&pci_dev->intr_handle,
1076                                      qede_interrupt_handler, (void *)eth_dev);
1077
1078         if (edev->num_hwfns > 1)
1079                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1080
1081         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1082 }
1083
1084 static void
1085 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1086 {
1087         struct qede_dev *qdev = eth_dev->data->dev_private;
1088         struct ecore_dev *edev = &qdev->edev;
1089         struct ecore_eth_stats stats;
1090         unsigned int i = 0, j = 0, qid;
1091         struct qede_tx_queue *txq;
1092
1093         qdev->ops->get_vport_stats(edev, &stats);
1094
1095         /* RX Stats */
1096         eth_stats->ipackets = stats.rx_ucast_pkts +
1097             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1098
1099         eth_stats->ibytes = stats.rx_ucast_bytes +
1100             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1101
1102         eth_stats->ierrors = stats.rx_crc_errors +
1103             stats.rx_align_errors +
1104             stats.rx_carrier_errors +
1105             stats.rx_oversize_packets +
1106             stats.rx_jabbers + stats.rx_undersize_packets;
1107
1108         eth_stats->rx_nombuf = stats.no_buff_discards;
1109
1110         eth_stats->imissed = stats.mftag_filter_discards +
1111             stats.mac_filter_discards +
1112             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1113
1114         /* TX stats */
1115         eth_stats->opackets = stats.tx_ucast_pkts +
1116             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1117
1118         eth_stats->obytes = stats.tx_ucast_bytes +
1119             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1120
1121         eth_stats->oerrors = stats.tx_err_drop_pkts;
1122
1123         /* Queue stats */
1124         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1125                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1126                         eth_stats->q_ipackets[i] =
1127                                 *(uint64_t *)(
1128                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1129                                         offsetof(struct qede_rx_queue,
1130                                         rcv_pkts));
1131                         eth_stats->q_errors[i] =
1132                                 *(uint64_t *)(
1133                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1134                                         offsetof(struct qede_rx_queue,
1135                                         rx_hw_errors)) +
1136                                 *(uint64_t *)(
1137                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1138                                         offsetof(struct qede_rx_queue,
1139                                         rx_alloc_errors));
1140                         i++;
1141                 }
1142
1143                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1144                         txq = qdev->fp_array[(qid)].txqs[0];
1145                         eth_stats->q_opackets[j] =
1146                                 *((uint64_t *)(uintptr_t)
1147                                         (((uint64_t)(uintptr_t)(txq)) +
1148                                          offsetof(struct qede_tx_queue,
1149                                                   xmit_pkts)));
1150                         j++;
1151                 }
1152         }
1153 }
1154
1155 static unsigned
1156 qede_get_xstats_count(struct qede_dev *qdev) {
1157         return RTE_DIM(qede_xstats_strings) +
1158                 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev));
1159 }
1160
1161 static int
1162 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1163                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1164 {
1165         struct qede_dev *qdev = dev->data->dev_private;
1166         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1167         unsigned int i, qid, stat_idx = 0;
1168
1169         if (xstats_names != NULL) {
1170                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1171                         snprintf(xstats_names[stat_idx].name,
1172                                 sizeof(xstats_names[stat_idx].name),
1173                                 "%s",
1174                                 qede_xstats_strings[i].name);
1175                         stat_idx++;
1176                 }
1177
1178                 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) {
1179                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1180                                 snprintf(xstats_names[stat_idx].name,
1181                                         sizeof(xstats_names[stat_idx].name),
1182                                         "%.4s%d%s",
1183                                         qede_rxq_xstats_strings[i].name, qid,
1184                                         qede_rxq_xstats_strings[i].name + 4);
1185                                 stat_idx++;
1186                         }
1187                 }
1188         }
1189
1190         return stat_cnt;
1191 }
1192
1193 static int
1194 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1195                 unsigned int n)
1196 {
1197         struct qede_dev *qdev = dev->data->dev_private;
1198         struct ecore_dev *edev = &qdev->edev;
1199         struct ecore_eth_stats stats;
1200         const unsigned int num = qede_get_xstats_count(qdev);
1201         unsigned int i, qid, stat_idx = 0;
1202
1203         if (n < num)
1204                 return num;
1205
1206         qdev->ops->get_vport_stats(edev, &stats);
1207
1208         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1209                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1210                                              qede_xstats_strings[i].offset);
1211                 xstats[stat_idx].id = stat_idx;
1212                 stat_idx++;
1213         }
1214
1215         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1216                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1217                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1218                                 xstats[stat_idx].value = *(uint64_t *)(
1219                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1220                                          qede_rxq_xstats_strings[i].offset);
1221                                 xstats[stat_idx].id = stat_idx;
1222                                 stat_idx++;
1223                         }
1224                 }
1225         }
1226
1227         return stat_idx;
1228 }
1229
1230 static void
1231 qede_reset_xstats(struct rte_eth_dev *dev)
1232 {
1233         struct qede_dev *qdev = dev->data->dev_private;
1234         struct ecore_dev *edev = &qdev->edev;
1235
1236         ecore_reset_vport_stats(edev);
1237 }
1238
1239 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1240 {
1241         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1242         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1243         struct qed_link_params link_params;
1244         int rc;
1245
1246         DP_INFO(edev, "setting link state %d\n", link_up);
1247         memset(&link_params, 0, sizeof(link_params));
1248         link_params.link_up = link_up;
1249         rc = qdev->ops->common->set_link(edev, &link_params);
1250         if (rc != ECORE_SUCCESS)
1251                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1252
1253         return rc;
1254 }
1255
1256 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1257 {
1258         return qede_dev_set_link_state(eth_dev, true);
1259 }
1260
1261 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1262 {
1263         return qede_dev_set_link_state(eth_dev, false);
1264 }
1265
1266 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1267 {
1268         struct qede_dev *qdev = eth_dev->data->dev_private;
1269         struct ecore_dev *edev = &qdev->edev;
1270
1271         ecore_reset_vport_stats(edev);
1272 }
1273
1274 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1275 {
1276         enum qed_filter_rx_mode_type type =
1277             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1278
1279         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1280                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1281
1282         qed_configure_filter_rx_mode(eth_dev, type);
1283 }
1284
1285 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1286 {
1287         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1288                 qed_configure_filter_rx_mode(eth_dev,
1289                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1290         else
1291                 qed_configure_filter_rx_mode(eth_dev,
1292                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1293 }
1294
1295 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1296                               struct rte_eth_fc_conf *fc_conf)
1297 {
1298         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1299         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1300         struct qed_link_output current_link;
1301         struct qed_link_params params;
1302
1303         memset(&current_link, 0, sizeof(current_link));
1304         qdev->ops->common->get_link(edev, &current_link);
1305
1306         memset(&params, 0, sizeof(params));
1307         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1308         if (fc_conf->autoneg) {
1309                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1310                         DP_ERR(edev, "Autoneg not supported\n");
1311                         return -EINVAL;
1312                 }
1313                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1314         }
1315
1316         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1317         if (fc_conf->mode == RTE_FC_FULL)
1318                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1319                                         QED_LINK_PAUSE_RX_ENABLE);
1320         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1321                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1322         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1323                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1324
1325         params.link_up = true;
1326         (void)qdev->ops->common->set_link(edev, &params);
1327
1328         return 0;
1329 }
1330
1331 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1332                               struct rte_eth_fc_conf *fc_conf)
1333 {
1334         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1335         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1336         struct qed_link_output current_link;
1337
1338         memset(&current_link, 0, sizeof(current_link));
1339         qdev->ops->common->get_link(edev, &current_link);
1340
1341         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1342                 fc_conf->autoneg = true;
1343
1344         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1345                                          QED_LINK_PAUSE_TX_ENABLE))
1346                 fc_conf->mode = RTE_FC_FULL;
1347         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1348                 fc_conf->mode = RTE_FC_RX_PAUSE;
1349         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1350                 fc_conf->mode = RTE_FC_TX_PAUSE;
1351         else
1352                 fc_conf->mode = RTE_FC_NONE;
1353
1354         return 0;
1355 }
1356
1357 static const uint32_t *
1358 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1359 {
1360         static const uint32_t ptypes[] = {
1361                 RTE_PTYPE_L3_IPV4,
1362                 RTE_PTYPE_L3_IPV6,
1363                 RTE_PTYPE_UNKNOWN
1364         };
1365
1366         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1367                 return ptypes;
1368
1369         return NULL;
1370 }
1371
1372 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1373 {
1374         *rss_caps = 0;
1375         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1376         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1377         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1378         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1379         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1380         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1381 }
1382
1383 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1384                                 struct rte_eth_rss_conf *rss_conf)
1385 {
1386         struct qed_update_vport_params vport_update_params;
1387         struct qede_dev *qdev = eth_dev->data->dev_private;
1388         struct ecore_dev *edev = &qdev->edev;
1389         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1390         uint64_t hf = rss_conf->rss_hf;
1391         int i;
1392
1393         memset(&vport_update_params, 0, sizeof(vport_update_params));
1394
1395         if (hf != 0) {
1396                 /* Enable RSS */
1397                 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1398                 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1399                        sizeof(vport_update_params.rss_params));
1400                 if (key)
1401                         memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1402                                rss_conf->rss_key_len);
1403                 vport_update_params.update_rss_flg = 1;
1404                 qdev->rss_enabled = 1;
1405         } else {
1406                 /* Disable RSS */
1407                 qdev->rss_enabled = 0;
1408         }
1409
1410         /* If the mapping doesn't fit any supported, return */
1411         if (qdev->rss_params.rss_caps == 0 && hf != 0)
1412                 return -EINVAL;
1413
1414         DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1415                                 "Enabling RSS" : "Disabling RSS");
1416
1417         vport_update_params.vport_id = 0;
1418
1419         return qdev->ops->vport_update(edev, &vport_update_params);
1420 }
1421
1422 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1423                            struct rte_eth_rss_conf *rss_conf)
1424 {
1425         struct qede_dev *qdev = eth_dev->data->dev_private;
1426         uint64_t hf;
1427
1428         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1429                 return -EINVAL;
1430
1431         if (rss_conf->rss_key)
1432                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1433                        sizeof(qdev->rss_params.rss_key));
1434
1435         hf = 0;
1436         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1437                         ETH_RSS_IPV4 : 0;
1438         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1439                         ETH_RSS_IPV6 : 0;
1440         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1441                         ETH_RSS_IPV6_EX : 0;
1442         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1443                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1444         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1445                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1446         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1447                         ETH_RSS_IPV6_TCP_EX : 0;
1448
1449         rss_conf->rss_hf = hf;
1450
1451         return 0;
1452 }
1453
1454 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1455                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1456                                 uint16_t reta_size)
1457 {
1458         struct qed_update_vport_params vport_update_params;
1459         struct qede_dev *qdev = eth_dev->data->dev_private;
1460         struct ecore_dev *edev = &qdev->edev;
1461         uint16_t i, idx, shift;
1462
1463         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1464                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1465                        reta_size);
1466                 return -EINVAL;
1467         }
1468
1469         memset(&vport_update_params, 0, sizeof(vport_update_params));
1470         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1471                sizeof(vport_update_params.rss_params));
1472
1473         for (i = 0; i < reta_size; i++) {
1474                 idx = i / RTE_RETA_GROUP_SIZE;
1475                 shift = i % RTE_RETA_GROUP_SIZE;
1476                 if (reta_conf[idx].mask & (1ULL << shift)) {
1477                         uint8_t entry = reta_conf[idx].reta[shift];
1478                         qdev->rss_params.rss_ind_table[i] = entry;
1479                 }
1480         }
1481
1482         vport_update_params.update_rss_flg = 1;
1483         vport_update_params.vport_id = 0;
1484
1485         return qdev->ops->vport_update(edev, &vport_update_params);
1486 }
1487
1488 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1489                         struct rte_eth_rss_reta_entry64 *reta_conf,
1490                         uint16_t reta_size)
1491 {
1492         struct qede_dev *qdev = eth_dev->data->dev_private;
1493         uint16_t i, idx, shift;
1494
1495         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1496                 struct ecore_dev *edev = &qdev->edev;
1497                 DP_ERR(edev, "reta_size %d is not supported\n",
1498                        reta_size);
1499         }
1500
1501         for (i = 0; i < reta_size; i++) {
1502                 idx = i / RTE_RETA_GROUP_SIZE;
1503                 shift = i % RTE_RETA_GROUP_SIZE;
1504                 if (reta_conf[idx].mask & (1ULL << shift)) {
1505                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1506                         reta_conf[idx].reta[shift] = entry;
1507                 }
1508         }
1509
1510         return 0;
1511 }
1512
1513 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1514 {
1515         uint32_t frame_size;
1516         struct qede_dev *qdev = dev->data->dev_private;
1517         struct rte_eth_dev_info dev_info = {0};
1518
1519         qede_dev_info_get(dev, &dev_info);
1520
1521         /* VLAN_TAG = 4 */
1522         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1523
1524         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1525                 return -EINVAL;
1526
1527         if (!dev->data->scattered_rx &&
1528             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1529                 return -EINVAL;
1530
1531         if (frame_size > ETHER_MAX_LEN)
1532                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1533         else
1534                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1535
1536         /* update max frame size */
1537         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1538         qdev->mtu = mtu;
1539         qede_dev_stop(dev);
1540         qede_dev_start(dev);
1541
1542         return 0;
1543 }
1544
1545 static int
1546 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1547                        struct rte_eth_udp_tunnel *tunnel_udp,
1548                        bool add)
1549 {
1550         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1551         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1552         struct ecore_tunn_update_params params;
1553         struct ecore_hwfn *p_hwfn;
1554         int rc, i;
1555
1556         PMD_INIT_FUNC_TRACE(edev);
1557
1558         memset(&params, 0, sizeof(params));
1559         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1560                 params.update_vxlan_udp_port = 1;
1561                 params.vxlan_udp_port = (add) ? tunnel_udp->udp_port :
1562                                         QEDE_VXLAN_DEF_PORT;
1563                 for_each_hwfn(edev, i) {
1564                         p_hwfn = &edev->hwfns[i];
1565                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &params,
1566                                                 ECORE_SPQ_MODE_CB, NULL);
1567                         if (rc != ECORE_SUCCESS) {
1568                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1569                                         params.vxlan_udp_port);
1570                                 return rc;
1571                         }
1572                 }
1573         }
1574
1575         return 0;
1576 }
1577
1578 int
1579 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1580                       struct rte_eth_udp_tunnel *tunnel_udp)
1581 {
1582         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1583 }
1584
1585 int
1586 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1587                       struct rte_eth_udp_tunnel *tunnel_udp)
1588 {
1589         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1590 }
1591
1592 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1593                                        uint32_t *clss, char *str)
1594 {
1595         uint16_t j;
1596         *clss = MAX_ECORE_TUNN_CLSS;
1597
1598         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1599                 if (filter == qede_tunn_types[j].rte_filter_type) {
1600                         *type = qede_tunn_types[j].qede_type;
1601                         *clss = qede_tunn_types[j].qede_tunn_clss;
1602                         strcpy(str, qede_tunn_types[j].string);
1603                         return;
1604                 }
1605         }
1606 }
1607
1608 static int
1609 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1610                               const struct rte_eth_tunnel_filter_conf *conf,
1611                               uint32_t type)
1612 {
1613         /* Init commmon ucast params first */
1614         qede_set_ucast_cmn_params(ucast);
1615
1616         /* Copy out the required fields based on classification type */
1617         ucast->type = type;
1618
1619         switch (type) {
1620         case ECORE_FILTER_VNI:
1621                 ucast->vni = conf->tenant_id;
1622         break;
1623         case ECORE_FILTER_INNER_VLAN:
1624                 ucast->vlan = conf->inner_vlan;
1625         break;
1626         case ECORE_FILTER_MAC:
1627                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1628                        ETHER_ADDR_LEN);
1629         break;
1630         case ECORE_FILTER_INNER_MAC:
1631                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1632                        ETHER_ADDR_LEN);
1633         break;
1634         case ECORE_FILTER_MAC_VNI_PAIR:
1635                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1636                         ETHER_ADDR_LEN);
1637                 ucast->vni = conf->tenant_id;
1638         break;
1639         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1640                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1641                         ETHER_ADDR_LEN);
1642                 ucast->vni = conf->tenant_id;
1643         break;
1644         case ECORE_FILTER_INNER_PAIR:
1645                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1646                         ETHER_ADDR_LEN);
1647                 ucast->vlan = conf->inner_vlan;
1648         break;
1649         default:
1650                 return -EINVAL;
1651         }
1652
1653         return ECORE_SUCCESS;
1654 }
1655
1656 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1657                                   enum rte_filter_op filter_op,
1658                                   const struct rte_eth_tunnel_filter_conf *conf)
1659 {
1660         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1661         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1662         struct ecore_tunn_update_params params;
1663         struct ecore_hwfn *p_hwfn;
1664         enum ecore_filter_ucast_type type;
1665         enum ecore_tunn_clss clss;
1666         struct ecore_filter_ucast ucast;
1667         char str[80];
1668         uint16_t filter_type;
1669         int rc, i;
1670
1671         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1672         /* First determine if the given filter classification is supported */
1673         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1674         if (clss == MAX_ECORE_TUNN_CLSS) {
1675                 DP_ERR(edev, "Wrong filter type\n");
1676                 return -EINVAL;
1677         }
1678         /* Init tunnel ucast params */
1679         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1680         if (rc != ECORE_SUCCESS) {
1681                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1682                                 conf->filter_type);
1683                 return rc;
1684         }
1685         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1686                 str, filter_op, ucast.type);
1687         switch (filter_op) {
1688         case RTE_ETH_FILTER_ADD:
1689                 ucast.opcode = ECORE_FILTER_ADD;
1690
1691                 /* Skip MAC/VLAN if filter is based on VNI */
1692                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1693                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1694                         if (rc == 0) {
1695                                 /* Enable accept anyvlan */
1696                                 qede_config_accept_any_vlan(qdev, true);
1697                         }
1698                 } else {
1699                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1700                         if (rc == 0)
1701                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1702                                                     ECORE_SPQ_MODE_CB, NULL);
1703                 }
1704
1705                 if (rc != ECORE_SUCCESS)
1706                         return rc;
1707
1708                 qdev->vxlan_filter_type = filter_type;
1709
1710                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1711                 qede_set_cmn_tunn_param(&params, clss,
1712                                         (1 << ECORE_MODE_VXLAN_TUNN),
1713                                         (1 << ECORE_MODE_VXLAN_TUNN));
1714                 for_each_hwfn(edev, i) {
1715                         p_hwfn = &edev->hwfns[i];
1716                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1717                                 &params, ECORE_SPQ_MODE_CB, NULL);
1718                         if (rc != ECORE_SUCCESS) {
1719                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1720                                         params.tunn_clss_vxlan);
1721                         }
1722                 }
1723                 qdev->num_tunn_filters++; /* Filter added successfully */
1724         break;
1725         case RTE_ETH_FILTER_DELETE:
1726                 ucast.opcode = ECORE_FILTER_REMOVE;
1727
1728                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1729                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1730                 } else {
1731                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1732                         if (rc == 0)
1733                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1734                                                     ECORE_SPQ_MODE_CB, NULL);
1735                 }
1736                 if (rc != ECORE_SUCCESS)
1737                         return rc;
1738
1739                 qdev->vxlan_filter_type = filter_type;
1740                 qdev->num_tunn_filters--;
1741
1742                 /* Disable VXLAN if VXLAN filters become 0 */
1743                 if (qdev->num_tunn_filters == 0) {
1744                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1745
1746                         /* Use 0 as tunnel mode */
1747                         qede_set_cmn_tunn_param(&params, clss, 0,
1748                                                 (1 << ECORE_MODE_VXLAN_TUNN));
1749                         for_each_hwfn(edev, i) {
1750                                 p_hwfn = &edev->hwfns[i];
1751                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1752                                         &params, ECORE_SPQ_MODE_CB, NULL);
1753                                 if (rc != ECORE_SUCCESS) {
1754                                         DP_ERR(edev,
1755                                                 "Failed to update tunn_clss %u\n",
1756                                                 params.tunn_clss_vxlan);
1757                                         break;
1758                                 }
1759                         }
1760                 }
1761         break;
1762         default:
1763                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1764                 return -EINVAL;
1765         }
1766         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1767
1768         return 0;
1769 }
1770
1771 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1772                          enum rte_filter_type filter_type,
1773                          enum rte_filter_op filter_op,
1774                          void *arg)
1775 {
1776         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1777         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1778         struct rte_eth_tunnel_filter_conf *filter_conf =
1779                         (struct rte_eth_tunnel_filter_conf *)arg;
1780
1781         switch (filter_type) {
1782         case RTE_ETH_FILTER_TUNNEL:
1783                 switch (filter_conf->tunnel_type) {
1784                 case RTE_TUNNEL_TYPE_VXLAN:
1785                         DP_INFO(edev,
1786                                 "Packet steering to the specified Rx queue"
1787                                 " is not supported with VXLAN tunneling");
1788                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1789                                                       filter_conf));
1790                 /* Place holders for future tunneling support */
1791                 case RTE_TUNNEL_TYPE_GENEVE:
1792                 case RTE_TUNNEL_TYPE_TEREDO:
1793                 case RTE_TUNNEL_TYPE_NVGRE:
1794                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1795                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1796                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1797                                 filter_conf->tunnel_type);
1798                         return -EINVAL;
1799                 case RTE_TUNNEL_TYPE_NONE:
1800                 default:
1801                         return 0;
1802                 }
1803                 break;
1804         case RTE_ETH_FILTER_FDIR:
1805         case RTE_ETH_FILTER_MACVLAN:
1806         case RTE_ETH_FILTER_ETHERTYPE:
1807         case RTE_ETH_FILTER_FLEXIBLE:
1808         case RTE_ETH_FILTER_SYN:
1809         case RTE_ETH_FILTER_NTUPLE:
1810         case RTE_ETH_FILTER_HASH:
1811         case RTE_ETH_FILTER_L2_TUNNEL:
1812         case RTE_ETH_FILTER_MAX:
1813         default:
1814                 DP_ERR(edev, "Unsupported filter type %d\n",
1815                         filter_type);
1816                 return -EINVAL;
1817         }
1818
1819         return 0;
1820 }
1821
1822 static const struct eth_dev_ops qede_eth_dev_ops = {
1823         .dev_configure = qede_dev_configure,
1824         .dev_infos_get = qede_dev_info_get,
1825         .rx_queue_setup = qede_rx_queue_setup,
1826         .rx_queue_release = qede_rx_queue_release,
1827         .tx_queue_setup = qede_tx_queue_setup,
1828         .tx_queue_release = qede_tx_queue_release,
1829         .dev_start = qede_dev_start,
1830         .dev_set_link_up = qede_dev_set_link_up,
1831         .dev_set_link_down = qede_dev_set_link_down,
1832         .link_update = qede_link_update,
1833         .promiscuous_enable = qede_promiscuous_enable,
1834         .promiscuous_disable = qede_promiscuous_disable,
1835         .allmulticast_enable = qede_allmulticast_enable,
1836         .allmulticast_disable = qede_allmulticast_disable,
1837         .dev_stop = qede_dev_stop,
1838         .dev_close = qede_dev_close,
1839         .stats_get = qede_get_stats,
1840         .stats_reset = qede_reset_stats,
1841         .xstats_get = qede_get_xstats,
1842         .xstats_reset = qede_reset_xstats,
1843         .xstats_get_names = qede_get_xstats_names,
1844         .mac_addr_add = qede_mac_addr_add,
1845         .mac_addr_remove = qede_mac_addr_remove,
1846         .mac_addr_set = qede_mac_addr_set,
1847         .vlan_offload_set = qede_vlan_offload_set,
1848         .vlan_filter_set = qede_vlan_filter_set,
1849         .flow_ctrl_set = qede_flow_ctrl_set,
1850         .flow_ctrl_get = qede_flow_ctrl_get,
1851         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1852         .rss_hash_update = qede_rss_hash_update,
1853         .rss_hash_conf_get = qede_rss_hash_conf_get,
1854         .reta_update  = qede_rss_reta_update,
1855         .reta_query  = qede_rss_reta_query,
1856         .mtu_set = qede_set_mtu,
1857         .filter_ctrl = qede_dev_filter_ctrl,
1858         .udp_tunnel_port_add = qede_udp_dst_port_add,
1859         .udp_tunnel_port_del = qede_udp_dst_port_del,
1860 };
1861
1862 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1863         .dev_configure = qede_dev_configure,
1864         .dev_infos_get = qede_dev_info_get,
1865         .rx_queue_setup = qede_rx_queue_setup,
1866         .rx_queue_release = qede_rx_queue_release,
1867         .tx_queue_setup = qede_tx_queue_setup,
1868         .tx_queue_release = qede_tx_queue_release,
1869         .dev_start = qede_dev_start,
1870         .dev_set_link_up = qede_dev_set_link_up,
1871         .dev_set_link_down = qede_dev_set_link_down,
1872         .link_update = qede_link_update,
1873         .promiscuous_enable = qede_promiscuous_enable,
1874         .promiscuous_disable = qede_promiscuous_disable,
1875         .allmulticast_enable = qede_allmulticast_enable,
1876         .allmulticast_disable = qede_allmulticast_disable,
1877         .dev_stop = qede_dev_stop,
1878         .dev_close = qede_dev_close,
1879         .stats_get = qede_get_stats,
1880         .stats_reset = qede_reset_stats,
1881         .xstats_get = qede_get_xstats,
1882         .xstats_reset = qede_reset_xstats,
1883         .xstats_get_names = qede_get_xstats_names,
1884         .vlan_offload_set = qede_vlan_offload_set,
1885         .vlan_filter_set = qede_vlan_filter_set,
1886         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1887         .rss_hash_update = qede_rss_hash_update,
1888         .rss_hash_conf_get = qede_rss_hash_conf_get,
1889         .reta_update  = qede_rss_reta_update,
1890         .reta_query  = qede_rss_reta_query,
1891         .mtu_set = qede_set_mtu,
1892 };
1893
1894 static void qede_update_pf_params(struct ecore_dev *edev)
1895 {
1896         struct ecore_pf_params pf_params;
1897         /* 32 rx + 32 tx */
1898         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1899         pf_params.eth_pf_params.num_cons = 64;
1900         qed_ops->common->update_pf_params(edev, &pf_params);
1901 }
1902
1903 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1904 {
1905         struct rte_pci_device *pci_dev;
1906         struct rte_pci_addr pci_addr;
1907         struct qede_dev *adapter;
1908         struct ecore_dev *edev;
1909         struct qed_dev_eth_info dev_info;
1910         struct qed_slowpath_params params;
1911         static bool do_once = true;
1912         uint8_t bulletin_change;
1913         uint8_t vf_mac[ETHER_ADDR_LEN];
1914         uint8_t is_mac_forced;
1915         bool is_mac_exist;
1916         /* Fix up ecore debug level */
1917         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1918         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1919         uint32_t max_mac_addrs;
1920         int rc;
1921
1922         /* Extract key data structures */
1923         adapter = eth_dev->data->dev_private;
1924         edev = &adapter->edev;
1925         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1926         pci_addr = pci_dev->addr;
1927
1928         PMD_INIT_FUNC_TRACE(edev);
1929
1930         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1931                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1932                  eth_dev->data->port_id);
1933
1934         eth_dev->rx_pkt_burst = qede_recv_pkts;
1935         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1936
1937         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1938                 DP_NOTICE(edev, false,
1939                           "Skipping device init from secondary process\n");
1940                 return 0;
1941         }
1942
1943         rte_eth_copy_pci_info(eth_dev, pci_dev);
1944
1945         qed_ops = qed_get_eth_ops();
1946         if (!qed_ops) {
1947                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1948                 return -EINVAL;
1949         }
1950
1951         DP_INFO(edev, "Starting qede probe\n");
1952
1953         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1954                                     dp_module, dp_level, is_vf);
1955
1956         if (rc != 0) {
1957                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1958                 return -ENODEV;
1959         }
1960
1961         qede_update_pf_params(edev);
1962
1963         rte_intr_callback_register(&pci_dev->intr_handle,
1964                                    qede_interrupt_handler, (void *)eth_dev);
1965
1966         if (rte_intr_enable(&pci_dev->intr_handle)) {
1967                 DP_ERR(edev, "rte_intr_enable() failed\n");
1968                 return -ENODEV;
1969         }
1970
1971         /* Start the Slowpath-process */
1972         memset(&params, 0, sizeof(struct qed_slowpath_params));
1973         params.int_mode = ECORE_INT_MODE_MSIX;
1974         params.drv_major = QEDE_PMD_VERSION_MAJOR;
1975         params.drv_minor = QEDE_PMD_VERSION_MINOR;
1976         params.drv_rev = QEDE_PMD_VERSION_REVISION;
1977         params.drv_eng = QEDE_PMD_VERSION_PATCH;
1978         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1979                 QEDE_PMD_DRV_VER_STR_SIZE);
1980
1981         /* For CMT mode device do periodic polling for slowpath events.
1982          * This is required since uio device uses only one MSI-x
1983          * interrupt vector but we need one for each engine.
1984          */
1985         if (edev->num_hwfns > 1 && IS_PF(edev)) {
1986                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1987                                        qede_poll_sp_sb_cb,
1988                                        (void *)eth_dev);
1989                 if (rc != 0) {
1990                         DP_ERR(edev, "Unable to start periodic"
1991                                      " timer rc %d\n", rc);
1992                         return -EINVAL;
1993                 }
1994         }
1995
1996         rc = qed_ops->common->slowpath_start(edev, &params);
1997         if (rc) {
1998                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1999                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2000                                      (void *)eth_dev);
2001                 return -ENODEV;
2002         }
2003
2004         rc = qed_ops->fill_dev_info(edev, &dev_info);
2005         if (rc) {
2006                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2007                 qed_ops->common->slowpath_stop(edev);
2008                 qed_ops->common->remove(edev);
2009                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2010                                      (void *)eth_dev);
2011                 return -ENODEV;
2012         }
2013
2014         qede_alloc_etherdev(adapter, &dev_info);
2015
2016         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
2017
2018         if (!is_vf)
2019                 adapter->dev_info.num_mac_addrs =
2020                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2021                                             ECORE_MAC);
2022         else
2023                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2024                                              &adapter->dev_info.num_mac_addrs);
2025
2026         /* Allocate memory for storing MAC addr */
2027         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2028                                         (ETHER_ADDR_LEN *
2029                                         adapter->dev_info.num_mac_addrs),
2030                                         RTE_CACHE_LINE_SIZE);
2031
2032         if (eth_dev->data->mac_addrs == NULL) {
2033                 DP_ERR(edev, "Failed to allocate MAC address\n");
2034                 qed_ops->common->slowpath_stop(edev);
2035                 qed_ops->common->remove(edev);
2036                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2037                                      (void *)eth_dev);
2038                 return -ENOMEM;
2039         }
2040
2041         if (!is_vf) {
2042                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2043                                 hw_info.hw_mac_addr,
2044                                 &eth_dev->data->mac_addrs[0]);
2045                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2046                                 &adapter->primary_mac);
2047         } else {
2048                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2049                                        &bulletin_change);
2050                 if (bulletin_change) {
2051                         is_mac_exist =
2052                             ecore_vf_bulletin_get_forced_mac(
2053                                                 ECORE_LEADING_HWFN(edev),
2054                                                 vf_mac,
2055                                                 &is_mac_forced);
2056                         if (is_mac_exist && is_mac_forced) {
2057                                 DP_INFO(edev, "VF macaddr received from PF\n");
2058                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2059                                                 &eth_dev->data->mac_addrs[0]);
2060                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2061                                                 &adapter->primary_mac);
2062                         } else {
2063                                 DP_NOTICE(edev, false,
2064                                           "No VF macaddr assigned\n");
2065                         }
2066                 }
2067         }
2068
2069         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2070
2071         if (do_once) {
2072                 qede_print_adapter_info(adapter);
2073                 do_once = false;
2074         }
2075
2076         adapter->state = QEDE_DEV_INIT;
2077
2078         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2079                   adapter->primary_mac.addr_bytes[0],
2080                   adapter->primary_mac.addr_bytes[1],
2081                   adapter->primary_mac.addr_bytes[2],
2082                   adapter->primary_mac.addr_bytes[3],
2083                   adapter->primary_mac.addr_bytes[4],
2084                   adapter->primary_mac.addr_bytes[5]);
2085
2086         return rc;
2087 }
2088
2089 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2090 {
2091         return qede_common_dev_init(eth_dev, 1);
2092 }
2093
2094 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2095 {
2096         return qede_common_dev_init(eth_dev, 0);
2097 }
2098
2099 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2100 {
2101         /* only uninitialize in the primary process */
2102         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2103                 return 0;
2104
2105         /* safe to close dev here */
2106         qede_dev_close(eth_dev);
2107
2108         eth_dev->dev_ops = NULL;
2109         eth_dev->rx_pkt_burst = NULL;
2110         eth_dev->tx_pkt_burst = NULL;
2111
2112         if (eth_dev->data->mac_addrs)
2113                 rte_free(eth_dev->data->mac_addrs);
2114
2115         eth_dev->data->mac_addrs = NULL;
2116
2117         return 0;
2118 }
2119
2120 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2121 {
2122         return qede_dev_common_uninit(eth_dev);
2123 }
2124
2125 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2126 {
2127         return qede_dev_common_uninit(eth_dev);
2128 }
2129
2130 static struct rte_pci_id pci_id_qedevf_map[] = {
2131 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2132         {
2133                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
2134         },
2135         {
2136                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
2137         },
2138         {.vendor_id = 0,}
2139 };
2140
2141 static struct rte_pci_id pci_id_qede_map[] = {
2142 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2143         {
2144                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
2145         },
2146         {
2147                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
2148         },
2149         {
2150                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
2151         },
2152         {
2153                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
2154         },
2155         {
2156                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
2157         },
2158         {.vendor_id = 0,}
2159 };
2160
2161 static struct eth_driver rte_qedevf_pmd = {
2162         .pci_drv = {
2163                     .id_table = pci_id_qedevf_map,
2164                     .drv_flags =
2165                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2166                     .probe = rte_eth_dev_pci_probe,
2167                     .remove = rte_eth_dev_pci_remove,
2168                    },
2169         .eth_dev_init = qedevf_eth_dev_init,
2170         .eth_dev_uninit = qedevf_eth_dev_uninit,
2171         .dev_private_size = sizeof(struct qede_dev),
2172 };
2173
2174 static struct eth_driver rte_qede_pmd = {
2175         .pci_drv = {
2176                     .id_table = pci_id_qede_map,
2177                     .drv_flags =
2178                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2179                     .probe = rte_eth_dev_pci_probe,
2180                     .remove = rte_eth_dev_pci_remove,
2181                    },
2182         .eth_dev_init = qede_eth_dev_init,
2183         .eth_dev_uninit = qede_eth_dev_uninit,
2184         .dev_private_size = sizeof(struct qede_dev),
2185 };
2186
2187 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
2188 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2189 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2190 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
2191 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2192 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");