drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 struct rte_qede_xstats_name_off {
  18         char name[RTE_ETH_XSTATS_NAME_SIZE];
  19         uint64_t offset;
  20 };
  21
  22 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  23         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
  24         {"rx_multicast_bytes",
  25                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
  26         {"rx_broadcast_bytes",
  27                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
  28         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
  29         {"rx_multicast_packets",
  30                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
  31         {"rx_broadcast_packets",
  32                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
  33
  34         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
  35         {"tx_multicast_bytes",
  36                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
  37         {"tx_broadcast_bytes",
  38                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
  39         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
  40         {"tx_multicast_packets",
  41                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
  42         {"tx_broadcast_packets",
  43                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
  44
  45         {"rx_64_byte_packets",
  46                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
  47         {"rx_65_to_127_byte_packets",
  48                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
  49         {"rx_128_to_255_byte_packets",
  50                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
  51         {"rx_256_to_511_byte_packets",
  52                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
  53         {"rx_512_to_1023_byte_packets",
  54                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
  55         {"rx_1024_to_1518_byte_packets",
  56                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
  57         {"rx_1519_to_1522_byte_packets",
  58                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
  59         {"rx_1519_to_2047_byte_packets",
  60                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
  61         {"rx_2048_to_4095_byte_packets",
  62                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
  63         {"rx_4096_to_9216_byte_packets",
  64                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
  65         {"rx_9217_to_16383_byte_packets",
  66                 offsetof(struct ecore_eth_stats,
  67                          rx_9217_to_16383_byte_packets)},
  68         {"tx_64_byte_packets",
  69                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
  70         {"tx_65_to_127_byte_packets",
  71                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
  72         {"tx_128_to_255_byte_packets",
  73                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
  74         {"tx_256_to_511_byte_packets",
  75                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
  76         {"tx_512_to_1023_byte_packets",
  77                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
  78         {"tx_1024_to_1518_byte_packets",
  79                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
  80         {"trx_1519_to_1522_byte_packets",
  81                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
  82         {"tx_2048_to_4095_byte_packets",
  83                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
  84         {"tx_4096_to_9216_byte_packets",
  85                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
  86         {"tx_9217_to_16383_byte_packets",
  87                 offsetof(struct ecore_eth_stats,
  88                          tx_9217_to_16383_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
  95         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
  96         {"rx_priority_flow_control_frames",
  97                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
  98         {"tx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 100
 101         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 102         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 103         {"rx_carrier_errors",
 104                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 105         {"rx_oversize_packet_errors",
 106                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 107         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 108         {"rx_undersize_packet_errors",
 109                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 110         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 111         {"rx_host_buffer_not_available",
 112                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 113         /* Number of packets discarded because they are bigger than MTU */
 114         {"rx_packet_too_big_discards",
 115                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 116         {"rx_ttl_zero_discards",
 117                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 118         {"rx_multi_function_tag_filter_discards",
 119                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 120         {"rx_mac_filter_discards",
 121                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 122         {"rx_hw_buffer_truncates",
 123                 offsetof(struct ecore_eth_stats, brb_truncates)},
 124         {"rx_hw_buffer_discards",
 125                 offsetof(struct ecore_eth_stats, brb_discards)},
 126         {"tx_lpi_entry_count",
 127                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 128         {"tx_total_collisions",
 129                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 130         {"tx_error_drop_packets",
 131                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 132
 133         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 134         {"rx_mac_unicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 136         {"rx_mac_multicast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 138         {"rx_mac_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 140         {"rx_mac_frames_ok",
 141                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 142         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 143         {"tx_mac_unicast_packets",
 144                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 145         {"tx_mac_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 147         {"tx_mac_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 149
 150         {"lro_coalesced_packets",
 151                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 152         {"lro_coalesced_events",
 153                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 154         {"lro_aborts_num",
 155                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 156         {"lro_not_coalesced_packets",
 157                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 158         {"lro_coalesced_bytes",
 159                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 160 };
 161
 162 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 163         {"rx_q_segments",
 164                 offsetof(struct qede_rx_queue, rx_segs)},
 165         {"rx_q_hw_errors",
 166                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 167         {"rx_q_allocation_errors",
 168                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 169 };
 170
 171 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 172 {
 173         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 174 }
 175
 176 static void
 177 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
 178 {
 179         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 180         struct qede_dev *qdev = eth_dev->data->dev_private;
 181         struct ecore_dev *edev = &qdev->edev;
 182
 183         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 184         if (rte_intr_enable(handle))
 185                 DP_ERR(edev, "rte_intr_enable failed\n");
 186 }
 187
 188 static void
 189 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 190 {
 191         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 192         qdev->num_tc = qdev->dev_info.num_tc;
 193         qdev->ops = qed_ops;
 194 }
 195
 196 static void qede_print_adapter_info(struct qede_dev *qdev)
 197 {
 198         struct ecore_dev *edev = &qdev->edev;
 199         struct qed_dev_info *info = &qdev->dev_info.common;
 200         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 201         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 202
 203         DP_INFO(edev, "*********************************\n");
 204         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 205         DP_INFO(edev, " Chip details : %s%d\n",
 206                   ECORE_IS_BB(edev) ? "BB" : "AH",
 207                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 208         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 209                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 210         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 211                  ver_str, QEDE_PMD_VERSION);
 212         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 213         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 214
 215         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 216                  "%d.%d.%d.%d",
 217                 (info->mfw_rev >> 24) & 0xff,
 218                 (info->mfw_rev >> 16) & 0xff,
 219                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 220         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 221         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 222         DP_INFO(edev, "*********************************\n");
 223 }
 224
 225 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 226 {
 227         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 228         ucast->is_rx_filter = true;
 229         ucast->is_tx_filter = true;
 230         /* ucast->assert_on_error = true; - For debug */
 231 }
 232
 233 static int
 234 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 235                   bool add)
 236 {
 237         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 238         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 239         struct qede_ucast_entry *tmp = NULL;
 240         struct qede_ucast_entry *u;
 241         struct ether_addr *mac_addr;
 242
 243         mac_addr  = (struct ether_addr *)ucast->mac;
 244         if (add) {
 245                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 246                         if ((memcmp(mac_addr, &tmp->mac,
 247                                     ETHER_ADDR_LEN) == 0) &&
 248                              ucast->vlan == tmp->vlan) {
 249                                 DP_ERR(edev, "Unicast MAC is already added"
 250                                        " with vlan = %u, vni = %u\n",
 251                                        ucast->vlan,  ucast->vni);
 252                                         return -EEXIST;
 253                         }
 254                 }
 255                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 256                                RTE_CACHE_LINE_SIZE);
 257                 if (!u) {
 258                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 259                         return -ENOMEM;
 260                 }
 261                 ether_addr_copy(mac_addr, &u->mac);
 262                 u->vlan = ucast->vlan;
 263                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 264                 qdev->num_uc_addr++;
 265         } else {
 266                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 267                         if ((memcmp(mac_addr, &tmp->mac,
 268                                     ETHER_ADDR_LEN) == 0) &&
 269                             ucast->vlan == tmp->vlan)
 270                         break;
 271                 }
 272                 if (tmp == NULL) {
 273                         DP_INFO(edev, "Unicast MAC is not found\n");
 274                         return -EINVAL;
 275                 }
 276                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 277                 qdev->num_uc_addr--;
 278         }
 279
 280         return 0;
 281 }
 282
 283 static int
 284 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 285                   bool add)
 286 {
 287         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 288         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 289         struct ether_addr *mac_addr;
 290         struct qede_mcast_entry *tmp = NULL;
 291         struct qede_mcast_entry *m;
 292
 293         mac_addr  = (struct ether_addr *)mcast->mac;
 294         if (add) {
 295                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 296                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 297                                 DP_ERR(edev,
 298                                         "Multicast MAC is already added\n");
 299                                 return -EEXIST;
 300                         }
 301                 }
 302                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 303                         RTE_CACHE_LINE_SIZE);
 304                 if (!m) {
 305                         DP_ERR(edev,
 306                                 "Did not allocate memory for mcast\n");
 307                         return -ENOMEM;
 308                 }
 309                 ether_addr_copy(mac_addr, &m->mac);
 310                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 311                 qdev->num_mc_addr++;
 312         } else {
 313                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 314                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 315                                 break;
 316                 }
 317                 if (tmp == NULL) {
 318                         DP_INFO(edev, "Multicast mac is not found\n");
 319                         return -EINVAL;
 320                 }
 321                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 322                              qede_mcast_entry, list);
 323                 qdev->num_mc_addr--;
 324         }
 325
 326         return 0;
 327 }
 328
 329 static enum _ecore_status_t
 330 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 331                  bool add)
 332 {
 333         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 334         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 335         enum _ecore_status_t rc;
 336         struct ecore_filter_mcast mcast;
 337         struct qede_mcast_entry *tmp;
 338         uint16_t j = 0;
 339
 340         /* Multicast */
 341         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 342                 if (add) {
 343                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 344                                 DP_ERR(edev,
 345                                        "Mcast filter table limit exceeded, "
 346                                        "Please enable mcast promisc mode\n");
 347                                 return -ECORE_INVAL;
 348                         }
 349                 }
 350                 rc = qede_mcast_filter(eth_dev, ucast, add);
 351                 if (rc == 0) {
 352                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 353                         memset(&mcast, 0, sizeof(mcast));
 354                         mcast.num_mc_addrs = qdev->num_mc_addr;
 355                         mcast.opcode = ECORE_FILTER_ADD;
 356                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 357                                 ether_addr_copy(&tmp->mac,
 358                                         (struct ether_addr *)&mcast.mac[j]);
 359                                 j++;
 360                         }
 361                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 362                                                     ECORE_SPQ_MODE_CB, NULL);
 363                 }
 364                 if (rc != ECORE_SUCCESS) {
 365                         DP_ERR(edev, "Failed to add multicast filter"
 366                                " rc = %d, op = %d\n", rc, add);
 367                 }
 368         } else { /* Unicast */
 369                 if (add) {
 370                         if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
 371                                 DP_ERR(edev,
 372                                        "Ucast filter table limit exceeded,"
 373                                        " Please enable promisc mode\n");
 374                                 return -ECORE_INVAL;
 375                         }
 376                 }
 377                 rc = qede_ucast_filter(eth_dev, ucast, add);
 378                 if (rc == 0)
 379                         rc = ecore_filter_ucast_cmd(edev, ucast,
 380                                                     ECORE_SPQ_MODE_CB, NULL);
 381                 if (rc != ECORE_SUCCESS) {
 382                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 383                                rc, add);
 384                 }
 385         }
 386
 387         return rc;
 388 }
 389
 390 static void
 391 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 392                   uint32_t index, __rte_unused uint32_t pool)
 393 {
 394         struct ecore_filter_ucast ucast;
 395
 396         qede_set_ucast_cmn_params(&ucast);
 397         ucast.type = ECORE_FILTER_MAC;
 398         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 399         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 400 }
 401
 402 static void
 403 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 404 {
 405         struct qede_dev *qdev = eth_dev->data->dev_private;
 406         struct ecore_dev *edev = &qdev->edev;
 407         struct ether_addr mac_addr;
 408         struct ecore_filter_ucast ucast;
 409         int rc;
 410
 411         PMD_INIT_FUNC_TRACE(edev);
 412
 413         if (index >= qdev->dev_info.num_mac_addrs) {
 414                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 415                        index, qdev->dev_info.num_mac_addrs);
 416                 return;
 417         }
 418
 419         qede_set_ucast_cmn_params(&ucast);
 420         ucast.opcode = ECORE_FILTER_REMOVE;
 421         ucast.type = ECORE_FILTER_MAC;
 422
 423         /* Use the index maintained by rte */
 424         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 425                         (struct ether_addr *)&ucast.mac);
 426
 427         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 428 }
 429
 430 static void
 431 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 432 {
 433         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 434         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 435         struct ecore_filter_ucast ucast;
 436         int rc;
 437
 438         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 439                                                mac_addr->addr_bytes)) {
 440                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 441                 ether_addr_copy(&qdev->primary_mac,
 442                                 &eth_dev->data->mac_addrs[0]);
 443                 return;
 444         }
 445
 446         /* First remove the primary mac */
 447         qede_set_ucast_cmn_params(&ucast);
 448         ucast.opcode = ECORE_FILTER_REMOVE;
 449         ucast.type = ECORE_FILTER_MAC;
 450         ether_addr_copy(&qdev->primary_mac,
 451                         (struct ether_addr *)&ucast.mac);
 452         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 453         if (rc != 0) {
 454                 DP_ERR(edev, "Unable to remove current macaddr"
 455                              " Reverting to previous default mac\n");
 456                 ether_addr_copy(&qdev->primary_mac,
 457                                 &eth_dev->data->mac_addrs[0]);
 458                 return;
 459         }
 460
 461         /* Add new MAC */
 462         ucast.opcode = ECORE_FILTER_ADD;
 463         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 464         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 465         if (rc != 0)
 466                 DP_ERR(edev, "Unable to add new default mac\n");
 467         else
 468                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 469 }
 470
 471 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 472 {
 473         struct ecore_dev *edev = &qdev->edev;
 474         struct qed_update_vport_params params = {
 475                 .vport_id = 0,
 476                 .accept_any_vlan = action,
 477                 .update_accept_any_vlan_flg = 1,
 478         };
 479         int rc;
 480
 481         /* Proceed only if action actually needs to be performed */
 482         if (qdev->accept_any_vlan == action)
 483                 return;
 484
 485         rc = qdev->ops->vport_update(edev, &params);
 486         if (rc) {
 487                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 488                        action ? "enable" : "disable");
 489         } else {
 490                 DP_INFO(edev, "%s accept-any-vlan\n",
 491                         action ? "enabled" : "disabled");
 492                 qdev->accept_any_vlan = action;
 493         }
 494 }
 495
 496 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 497 {
 498         struct qed_update_vport_params vport_update_params;
 499         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 500         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 501         int rc;
 502
 503         memset(&vport_update_params, 0, sizeof(vport_update_params));
 504         vport_update_params.vport_id = 0;
 505         vport_update_params.update_inner_vlan_removal_flg = 1;
 506         vport_update_params.inner_vlan_removal_flg = set_stripping;
 507         rc = qdev->ops->vport_update(edev, &vport_update_params);
 508         if (rc) {
 509                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 510                 return rc;
 511         }
 512
 513         return 0;
 514 }
 515
 516 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 517 {
 518         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 519         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 520         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 521
 522         if (mask & ETH_VLAN_STRIP_MASK) {
 523                 if (rxmode->hw_vlan_strip)
 524                         (void)qede_vlan_stripping(eth_dev, 1);
 525                 else
 526                         (void)qede_vlan_stripping(eth_dev, 0);
 527         }
 528
 529         if (mask & ETH_VLAN_FILTER_MASK) {
 530                 /* VLAN filtering kicks in when a VLAN is added */
 531                 if (rxmode->hw_vlan_filter) {
 532                         qede_vlan_filter_set(eth_dev, 0, 1);
 533                 } else {
 534                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 535                                 DP_NOTICE(edev, false,
 536                                   " Please remove existing VLAN filters"
 537                                   " before disabling VLAN filtering\n");
 538                                 /* Signal app that VLAN filtering is still
 539                                  * enabled
 540                                  */
 541                                 rxmode->hw_vlan_filter = true;
 542                         } else {
 543                                 qede_vlan_filter_set(eth_dev, 0, 0);
 544                         }
 545                 }
 546         }
 547
 548         if (mask & ETH_VLAN_EXTEND_MASK)
 549                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 550                         " and classification is based on outer tag only\n");
 551
 552         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 553                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 554 }
 555
 556 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 557                                 uint16_t vlan_id, int on)
 558 {
 559         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 560         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 561         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 562         struct qede_vlan_entry *tmp = NULL;
 563         struct qede_vlan_entry *vlan;
 564         struct ecore_filter_ucast ucast;
 565         int rc;
 566
 567         if (on) {
 568                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 569                         DP_INFO(edev, "Reached max VLAN filter limit"
 570                                       " enabling accept_any_vlan\n");
 571                         qede_config_accept_any_vlan(qdev, true);
 572                         return 0;
 573                 }
 574
 575                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 576                         if (tmp->vid == vlan_id) {
 577                                 DP_ERR(edev, "VLAN %u already configured\n",
 578                                        vlan_id);
 579                                 return -EEXIST;
 580                         }
 581                 }
 582
 583                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 584                                   RTE_CACHE_LINE_SIZE);
 585
 586                 if (!vlan) {
 587                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 588                         return -ENOMEM;
 589                 }
 590
 591                 qede_set_ucast_cmn_params(&ucast);
 592                 ucast.opcode = ECORE_FILTER_ADD;
 593                 ucast.type = ECORE_FILTER_VLAN;
 594                 ucast.vlan = vlan_id;
 595                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 596                                             NULL);
 597                 if (rc != 0) {
 598                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 599                                rc);
 600                         rte_free(vlan);
 601                 } else {
 602                         vlan->vid = vlan_id;
 603                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 604                         qdev->configured_vlans++;
 605                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 606                                 vlan_id, qdev->configured_vlans);
 607                 }
 608         } else {
 609                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 610                         if (tmp->vid == vlan_id)
 611                                 break;
 612                 }
 613
 614                 if (!tmp) {
 615                         if (qdev->configured_vlans == 0) {
 616                                 DP_INFO(edev,
 617                                         "No VLAN filters configured yet\n");
 618                                 return 0;
 619                         }
 620
 621                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 622                         return -EINVAL;
 623                 }
 624
 625                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 626
 627                 qede_set_ucast_cmn_params(&ucast);
 628                 ucast.opcode = ECORE_FILTER_REMOVE;
 629                 ucast.type = ECORE_FILTER_VLAN;
 630                 ucast.vlan = vlan_id;
 631                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 632                                             NULL);
 633                 if (rc != 0) {
 634                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 635                                vlan_id, rc);
 636                 } else {
 637                         qdev->configured_vlans--;
 638                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 639                                 vlan_id, qdev->configured_vlans);
 640                 }
 641         }
 642
 643         return rc;
 644 }
 645
 646 static int qede_init_vport(struct qede_dev *qdev)
 647 {
 648         struct ecore_dev *edev = &qdev->edev;
 649         struct qed_start_vport_params start = {0};
 650         int rc;
 651
 652         start.remove_inner_vlan = 1;
 653         start.gro_enable = 0;
 654         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 655         start.vport_id = 0;
 656         start.drop_ttl0 = false;
 657         start.clear_stats = 1;
 658         start.handle_ptp_pkts = 0;
 659
 660         rc = qdev->ops->vport_start(edev, &start);
 661         if (rc) {
 662                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 663                 return rc;
 664         }
 665
 666         DP_INFO(edev,
 667                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 668                 start.vport_id, ETHER_MTU);
 669
 670         return 0;
 671 }
 672
 673 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 674 {
 675         struct qede_dev *qdev = eth_dev->data->dev_private;
 676         struct ecore_dev *edev = &qdev->edev;
 677         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 678         int rc, i, j;
 679
 680         PMD_INIT_FUNC_TRACE(edev);
 681
 682         /* Check requirements for 100G mode */
 683         if (edev->num_hwfns > 1) {
 684                 if (eth_dev->data->nb_rx_queues < 2 ||
 685                     eth_dev->data->nb_tx_queues < 2) {
 686                         DP_NOTICE(edev, false,
 687                                   "100G mode needs min. 2 RX/TX queues\n");
 688                         return -EINVAL;
 689                 }
 690
 691                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 692                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 693                         DP_NOTICE(edev, false,
 694                                   "100G mode needs even no. of RX/TX queues\n");
 695                         return -EINVAL;
 696                 }
 697         }
 698
 699         /* Sanity checks and throw warnings */
 700         if (rxmode->enable_scatter == 1)
 701                 eth_dev->data->scattered_rx = 1;
 702
 703         if (rxmode->enable_lro == 1) {
 704                 DP_INFO(edev, "LRO is not supported\n");
 705                 return -EINVAL;
 706         }
 707
 708         if (!rxmode->hw_strip_crc)
 709                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 710
 711         if (!rxmode->hw_ip_checksum)
 712                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 713                               "in hw\n");
 714
 715         /* Check for the port restart case */
 716         if (qdev->state != QEDE_DEV_INIT) {
 717                 rc = qdev->ops->vport_stop(edev, 0);
 718                 if (rc != 0)
 719                         return rc;
 720                 qede_dealloc_fp_resc(eth_dev);
 721         }
 722
 723         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 724         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 725         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 726
 727         /* Fastpath status block should be initialized before sending
 728          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 729          */
 730         rc = qede_alloc_fp_resc(qdev);
 731         if (rc != 0)
 732                 return rc;
 733
 734         /* Issue VPORT-START with default config values to allow
 735          * other port configurations early on.
 736          */
 737         rc = qede_init_vport(qdev);
 738         if (rc != 0)
 739                 return rc;
 740
 741         SLIST_INIT(&qdev->vlan_list_head);
 742
 743         /* Add primary mac for PF */
 744         if (IS_PF(edev))
 745                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 746
 747         /* Enable VLAN offloads by default */
 748         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 749                                        ETH_VLAN_FILTER_MASK |
 750                                        ETH_VLAN_EXTEND_MASK);
 751
 752         qdev->state = QEDE_DEV_CONFIG;
 753
 754         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 755                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 756                 qdev->num_tc);
 757
 758         return 0;
 759 }
 760
 761 /* Info about HW descriptor ring limitations */
 762 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 763         .nb_max = NUM_RX_BDS_MAX,
 764         .nb_min = 128,
 765         .nb_align = 128 /* lowest common multiple */
 766 };
 767
 768 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 769         .nb_max = NUM_TX_BDS_MAX,
 770         .nb_min = 256,
 771         .nb_align = 256
 772 };
 773
 774 static void
 775 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 776                   struct rte_eth_dev_info *dev_info)
 777 {
 778         struct qede_dev *qdev = eth_dev->data->dev_private;
 779         struct ecore_dev *edev = &qdev->edev;
 780         struct qed_link_output link;
 781         uint32_t speed_cap = 0;
 782
 783         PMD_INIT_FUNC_TRACE(edev);
 784
 785         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 786         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 787                                               QEDE_ETH_OVERHEAD);
 788         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 789         dev_info->rx_desc_lim = qede_rx_desc_lim;
 790         dev_info->tx_desc_lim = qede_tx_desc_lim;
 791         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 792         dev_info->max_tx_queues = dev_info->max_rx_queues;
 793         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 794         if (IS_VF(edev))
 795                 dev_info->max_vfs = 0;
 796         else
 797                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 798         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 799         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 800
 801         dev_info->default_txconf = (struct rte_eth_txconf) {
 802                 .txq_flags = QEDE_TXQ_FLAGS,
 803         };
 804
 805         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
 806                                      DEV_RX_OFFLOAD_IPV4_CKSUM |
 807                                      DEV_RX_OFFLOAD_UDP_CKSUM |
 808                                      DEV_RX_OFFLOAD_TCP_CKSUM);
 809         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 810                                      DEV_TX_OFFLOAD_IPV4_CKSUM |
 811                                      DEV_TX_OFFLOAD_UDP_CKSUM |
 812                                      DEV_TX_OFFLOAD_TCP_CKSUM);
 813
 814         memset(&link, 0, sizeof(struct qed_link_output));
 815         qdev->ops->common->get_link(edev, &link);
 816         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 817                 speed_cap |= ETH_LINK_SPEED_1G;
 818         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 819                 speed_cap |= ETH_LINK_SPEED_10G;
 820         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 821                 speed_cap |= ETH_LINK_SPEED_25G;
 822         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 823                 speed_cap |= ETH_LINK_SPEED_40G;
 824         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 825                 speed_cap |= ETH_LINK_SPEED_50G;
 826         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 827                 speed_cap |= ETH_LINK_SPEED_100G;
 828         dev_info->speed_capa = speed_cap;
 829 }
 830
 831 /* return 0 means link status changed, -1 means not changed */
 832 static int
 833 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 834 {
 835         struct qede_dev *qdev = eth_dev->data->dev_private;
 836         struct ecore_dev *edev = &qdev->edev;
 837         uint16_t link_duplex;
 838         struct qed_link_output link;
 839         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 840
 841         memset(&link, 0, sizeof(struct qed_link_output));
 842         qdev->ops->common->get_link(edev, &link);
 843
 844         /* Link Speed */
 845         curr->link_speed = link.speed;
 846
 847         /* Link Mode */
 848         switch (link.duplex) {
 849         case QEDE_DUPLEX_HALF:
 850                 link_duplex = ETH_LINK_HALF_DUPLEX;
 851                 break;
 852         case QEDE_DUPLEX_FULL:
 853                 link_duplex = ETH_LINK_FULL_DUPLEX;
 854                 break;
 855         case QEDE_DUPLEX_UNKNOWN:
 856         default:
 857                 link_duplex = -1;
 858         }
 859         curr->link_duplex = link_duplex;
 860
 861         /* Link Status */
 862         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 863
 864         /* AN */
 865         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 866                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 867
 868         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 869                 curr->link_speed, curr->link_duplex,
 870                 curr->link_autoneg, curr->link_status);
 871
 872         /* return 0 means link status changed, -1 means not changed */
 873         return ((curr->link_status == link.link_up) ? -1 : 0);
 874 }
 875
 876 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 877 {
 878         struct qede_dev *qdev = eth_dev->data->dev_private;
 879         struct ecore_dev *edev = &qdev->edev;
 880
 881         PMD_INIT_FUNC_TRACE(edev);
 882
 883         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
 884
 885         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 886                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
 887
 888         qed_configure_filter_rx_mode(eth_dev, type);
 889 }
 890
 891 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
 892 {
 893         struct qede_dev *qdev = eth_dev->data->dev_private;
 894         struct ecore_dev *edev = &qdev->edev;
 895
 896         PMD_INIT_FUNC_TRACE(edev);
 897
 898         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 899                 qed_configure_filter_rx_mode(eth_dev,
 900                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
 901         else
 902                 qed_configure_filter_rx_mode(eth_dev,
 903                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
 904 }
 905
 906 static void qede_poll_sp_sb_cb(void *param)
 907 {
 908         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 909         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 910         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 911         int rc;
 912
 913         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 914         qede_interrupt_action(&edev->hwfns[1]);
 915
 916         rc = rte_eal_alarm_set(timer_period * US_PER_S,
 917                                qede_poll_sp_sb_cb,
 918                                (void *)eth_dev);
 919         if (rc != 0) {
 920                 DP_ERR(edev, "Unable to start periodic"
 921                              " timer rc %d\n", rc);
 922                 assert(false && "Unable to start periodic timer");
 923         }
 924 }
 925
 926 static void qede_dev_close(struct rte_eth_dev *eth_dev)
 927 {
 928         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 929         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 930         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 931         int rc;
 932
 933         PMD_INIT_FUNC_TRACE(edev);
 934
 935         /* dev_stop() shall cleanup fp resources in hw but without releasing
 936          * dma memories and sw structures so that dev_start() can be called
 937          * by the app without reconfiguration. However, in dev_close() we
 938          * can release all the resources and device can be brought up newly
 939          */
 940         if (qdev->state != QEDE_DEV_STOP)
 941                 qede_dev_stop(eth_dev);
 942         else
 943                 DP_INFO(edev, "Device is already stopped\n");
 944
 945         rc = qdev->ops->vport_stop(edev, 0);
 946         if (rc != 0)
 947                 DP_ERR(edev, "Failed to stop VPORT\n");
 948
 949         qede_dealloc_fp_resc(eth_dev);
 950
 951         qdev->ops->common->slowpath_stop(edev);
 952
 953         qdev->ops->common->remove(edev);
 954
 955         rte_intr_disable(&pci_dev->intr_handle);
 956
 957         rte_intr_callback_unregister(&pci_dev->intr_handle,
 958                                      qede_interrupt_handler, (void *)eth_dev);
 959
 960         if (edev->num_hwfns > 1)
 961                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
 962
 963         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
 964 }
 965
 966 static void
 967 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
 968 {
 969         struct qede_dev *qdev = eth_dev->data->dev_private;
 970         struct ecore_dev *edev = &qdev->edev;
 971         struct ecore_eth_stats stats;
 972         unsigned int i = 0, j = 0, qid;
 973         struct qede_tx_queue *txq;
 974
 975         qdev->ops->get_vport_stats(edev, &stats);
 976
 977         /* RX Stats */
 978         eth_stats->ipackets = stats.rx_ucast_pkts +
 979             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
 980
 981         eth_stats->ibytes = stats.rx_ucast_bytes +
 982             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
 983
 984         eth_stats->ierrors = stats.rx_crc_errors +
 985             stats.rx_align_errors +
 986             stats.rx_carrier_errors +
 987             stats.rx_oversize_packets +
 988             stats.rx_jabbers + stats.rx_undersize_packets;
 989
 990         eth_stats->rx_nombuf = stats.no_buff_discards;
 991
 992         eth_stats->imissed = stats.mftag_filter_discards +
 993             stats.mac_filter_discards +
 994             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
 995
 996         /* TX stats */
 997         eth_stats->opackets = stats.tx_ucast_pkts +
 998             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
 999
1000         eth_stats->obytes = stats.tx_ucast_bytes +
1001             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1002
1003         eth_stats->oerrors = stats.tx_err_drop_pkts;
1004
1005         /* Queue stats */
1006         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1007                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1008                         eth_stats->q_ipackets[i] =
1009                                 *(uint64_t *)(
1010                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1011                                         offsetof(struct qede_rx_queue,
1012                                         rcv_pkts));
1013                         eth_stats->q_errors[i] =
1014                                 *(uint64_t *)(
1015                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1016                                         offsetof(struct qede_rx_queue,
1017                                         rx_hw_errors)) +
1018                                 *(uint64_t *)(
1019                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1020                                         offsetof(struct qede_rx_queue,
1021                                         rx_alloc_errors));
1022                         i++;
1023                 }
1024
1025                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1026                         txq = qdev->fp_array[(qid)].txqs[0];
1027                         eth_stats->q_opackets[j] =
1028                                 *((uint64_t *)(uintptr_t)
1029                                         (((uint64_t)(uintptr_t)(txq)) +
1030                                          offsetof(struct qede_tx_queue,
1031                                                   xmit_pkts)));
1032                         j++;
1033                 }
1034         }
1035 }
1036
1037 static unsigned
1038 qede_get_xstats_count(struct qede_dev *qdev) {
1039         return RTE_DIM(qede_xstats_strings) +
1040                 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev));
1041 }
1042
1043 static int
1044 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1045                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1046 {
1047         struct qede_dev *qdev = dev->data->dev_private;
1048         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1049         unsigned int i, qid, stat_idx = 0;
1050
1051         if (xstats_names != NULL) {
1052                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1053                         snprintf(xstats_names[stat_idx].name,
1054                                 sizeof(xstats_names[stat_idx].name),
1055                                 "%s",
1056                                 qede_xstats_strings[i].name);
1057                         stat_idx++;
1058                 }
1059
1060                 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) {
1061                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1062                                 snprintf(xstats_names[stat_idx].name,
1063                                         sizeof(xstats_names[stat_idx].name),
1064                                         "%.4s%d%s",
1065                                         qede_rxq_xstats_strings[i].name, qid,
1066                                         qede_rxq_xstats_strings[i].name + 4);
1067                                 stat_idx++;
1068                         }
1069                 }
1070         }
1071
1072         return stat_cnt;
1073 }
1074
1075 static int
1076 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1077                 unsigned int n)
1078 {
1079         struct qede_dev *qdev = dev->data->dev_private;
1080         struct ecore_dev *edev = &qdev->edev;
1081         struct ecore_eth_stats stats;
1082         const unsigned int num = qede_get_xstats_count(qdev);
1083         unsigned int i, qid, stat_idx = 0;
1084
1085         if (n < num)
1086                 return num;
1087
1088         qdev->ops->get_vport_stats(edev, &stats);
1089
1090         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1091                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1092                                              qede_xstats_strings[i].offset);
1093                 xstats[stat_idx].id = stat_idx;
1094                 stat_idx++;
1095         }
1096
1097         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1098                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1099                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1100                                 xstats[stat_idx].value = *(uint64_t *)(
1101                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1102                                          qede_rxq_xstats_strings[i].offset);
1103                                 xstats[stat_idx].id = stat_idx;
1104                                 stat_idx++;
1105                         }
1106                 }
1107         }
1108
1109         return stat_idx;
1110 }
1111
1112 static void
1113 qede_reset_xstats(struct rte_eth_dev *dev)
1114 {
1115         struct qede_dev *qdev = dev->data->dev_private;
1116         struct ecore_dev *edev = &qdev->edev;
1117
1118         ecore_reset_vport_stats(edev);
1119 }
1120
1121 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1122 {
1123         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1124         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1125         struct qed_link_params link_params;
1126         int rc;
1127
1128         DP_INFO(edev, "setting link state %d\n", link_up);
1129         memset(&link_params, 0, sizeof(link_params));
1130         link_params.link_up = link_up;
1131         rc = qdev->ops->common->set_link(edev, &link_params);
1132         if (rc != ECORE_SUCCESS)
1133                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1134
1135         return rc;
1136 }
1137
1138 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1139 {
1140         return qede_dev_set_link_state(eth_dev, true);
1141 }
1142
1143 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1144 {
1145         return qede_dev_set_link_state(eth_dev, false);
1146 }
1147
1148 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1149 {
1150         struct qede_dev *qdev = eth_dev->data->dev_private;
1151         struct ecore_dev *edev = &qdev->edev;
1152
1153         ecore_reset_vport_stats(edev);
1154 }
1155
1156 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1157 {
1158         enum qed_filter_rx_mode_type type =
1159             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1160
1161         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1162                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1163
1164         qed_configure_filter_rx_mode(eth_dev, type);
1165 }
1166
1167 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1168 {
1169         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1170                 qed_configure_filter_rx_mode(eth_dev,
1171                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1172         else
1173                 qed_configure_filter_rx_mode(eth_dev,
1174                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1175 }
1176
1177 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1178                               struct rte_eth_fc_conf *fc_conf)
1179 {
1180         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1181         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1182         struct qed_link_output current_link;
1183         struct qed_link_params params;
1184
1185         memset(&current_link, 0, sizeof(current_link));
1186         qdev->ops->common->get_link(edev, &current_link);
1187
1188         memset(&params, 0, sizeof(params));
1189         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1190         if (fc_conf->autoneg) {
1191                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1192                         DP_ERR(edev, "Autoneg not supported\n");
1193                         return -EINVAL;
1194                 }
1195                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1196         }
1197
1198         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1199         if (fc_conf->mode == RTE_FC_FULL)
1200                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1201                                         QED_LINK_PAUSE_RX_ENABLE);
1202         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1203                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1204         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1205                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1206
1207         params.link_up = true;
1208         (void)qdev->ops->common->set_link(edev, &params);
1209
1210         return 0;
1211 }
1212
1213 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1214                               struct rte_eth_fc_conf *fc_conf)
1215 {
1216         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1217         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1218         struct qed_link_output current_link;
1219
1220         memset(&current_link, 0, sizeof(current_link));
1221         qdev->ops->common->get_link(edev, &current_link);
1222
1223         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1224                 fc_conf->autoneg = true;
1225
1226         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1227                                          QED_LINK_PAUSE_TX_ENABLE))
1228                 fc_conf->mode = RTE_FC_FULL;
1229         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1230                 fc_conf->mode = RTE_FC_RX_PAUSE;
1231         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1232                 fc_conf->mode = RTE_FC_TX_PAUSE;
1233         else
1234                 fc_conf->mode = RTE_FC_NONE;
1235
1236         return 0;
1237 }
1238
1239 static const uint32_t *
1240 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1241 {
1242         static const uint32_t ptypes[] = {
1243                 RTE_PTYPE_L3_IPV4,
1244                 RTE_PTYPE_L3_IPV6,
1245                 RTE_PTYPE_UNKNOWN
1246         };
1247
1248         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1249                 return ptypes;
1250
1251         return NULL;
1252 }
1253
1254 void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1255 {
1256         *rss_caps = 0;
1257         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1258         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1259         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1260         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1261         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1262         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1263 }
1264
1265 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1266                                 struct rte_eth_rss_conf *rss_conf)
1267 {
1268         struct qed_update_vport_params vport_update_params;
1269         struct qede_dev *qdev = eth_dev->data->dev_private;
1270         struct ecore_dev *edev = &qdev->edev;
1271         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1272         uint64_t hf = rss_conf->rss_hf;
1273         int i;
1274
1275         memset(&vport_update_params, 0, sizeof(vport_update_params));
1276
1277         if (hf != 0) {
1278                 /* Enable RSS */
1279                 qede_init_rss_caps(&qdev->rss_params.rss_caps, hf);
1280                 memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1281                        sizeof(vport_update_params.rss_params));
1282                 if (key)
1283                         memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1284                                rss_conf->rss_key_len);
1285                 vport_update_params.update_rss_flg = 1;
1286                 qdev->rss_enabled = 1;
1287         } else {
1288                 /* Disable RSS */
1289                 qdev->rss_enabled = 0;
1290         }
1291
1292         /* If the mapping doesn't fit any supported, return */
1293         if (qdev->rss_params.rss_caps == 0 && hf != 0)
1294                 return -EINVAL;
1295
1296         DP_INFO(edev, "%s\n", (vport_update_params.update_rss_flg) ?
1297                                 "Enabling RSS" : "Disabling RSS");
1298
1299         vport_update_params.vport_id = 0;
1300
1301         return qdev->ops->vport_update(edev, &vport_update_params);
1302 }
1303
1304 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1305                            struct rte_eth_rss_conf *rss_conf)
1306 {
1307         struct qede_dev *qdev = eth_dev->data->dev_private;
1308         uint64_t hf;
1309
1310         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1311                 return -EINVAL;
1312
1313         if (rss_conf->rss_key)
1314                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1315                        sizeof(qdev->rss_params.rss_key));
1316
1317         hf = 0;
1318         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1319                         ETH_RSS_IPV4 : 0;
1320         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1321                         ETH_RSS_IPV6 : 0;
1322         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1323                         ETH_RSS_IPV6_EX : 0;
1324         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1325                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1326         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1327                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1328         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1329                         ETH_RSS_IPV6_TCP_EX : 0;
1330
1331         rss_conf->rss_hf = hf;
1332
1333         return 0;
1334 }
1335
1336 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1337                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1338                                 uint16_t reta_size)
1339 {
1340         struct qed_update_vport_params vport_update_params;
1341         struct qede_dev *qdev = eth_dev->data->dev_private;
1342         struct ecore_dev *edev = &qdev->edev;
1343         uint16_t i, idx, shift;
1344
1345         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1346                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1347                        reta_size);
1348                 return -EINVAL;
1349         }
1350
1351         memset(&vport_update_params, 0, sizeof(vport_update_params));
1352         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1353                sizeof(vport_update_params.rss_params));
1354
1355         for (i = 0; i < reta_size; i++) {
1356                 idx = i / RTE_RETA_GROUP_SIZE;
1357                 shift = i % RTE_RETA_GROUP_SIZE;
1358                 if (reta_conf[idx].mask & (1ULL << shift)) {
1359                         uint8_t entry = reta_conf[idx].reta[shift];
1360                         qdev->rss_params.rss_ind_table[i] = entry;
1361                 }
1362         }
1363
1364         vport_update_params.update_rss_flg = 1;
1365         vport_update_params.vport_id = 0;
1366
1367         return qdev->ops->vport_update(edev, &vport_update_params);
1368 }
1369
1370 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1371                         struct rte_eth_rss_reta_entry64 *reta_conf,
1372                         uint16_t reta_size)
1373 {
1374         struct qede_dev *qdev = eth_dev->data->dev_private;
1375         uint16_t i, idx, shift;
1376
1377         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1378                 struct ecore_dev *edev = &qdev->edev;
1379                 DP_ERR(edev, "reta_size %d is not supported\n",
1380                        reta_size);
1381         }
1382
1383         for (i = 0; i < reta_size; i++) {
1384                 idx = i / RTE_RETA_GROUP_SIZE;
1385                 shift = i % RTE_RETA_GROUP_SIZE;
1386                 if (reta_conf[idx].mask & (1ULL << shift)) {
1387                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1388                         reta_conf[idx].reta[shift] = entry;
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1396 {
1397         uint32_t frame_size;
1398         struct qede_dev *qdev = dev->data->dev_private;
1399         struct rte_eth_dev_info dev_info = {0};
1400
1401         qede_dev_info_get(dev, &dev_info);
1402
1403         /* VLAN_TAG = 4 */
1404         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1405
1406         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1407                 return -EINVAL;
1408
1409         if (!dev->data->scattered_rx &&
1410             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1411                 return -EINVAL;
1412
1413         if (frame_size > ETHER_MAX_LEN)
1414                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1415         else
1416                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1417
1418         /* update max frame size */
1419         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1420         qdev->mtu = mtu;
1421         qede_dev_stop(dev);
1422         qede_dev_start(dev);
1423
1424         return 0;
1425 }
1426
1427 static const struct eth_dev_ops qede_eth_dev_ops = {
1428         .dev_configure = qede_dev_configure,
1429         .dev_infos_get = qede_dev_info_get,
1430         .rx_queue_setup = qede_rx_queue_setup,
1431         .rx_queue_release = qede_rx_queue_release,
1432         .tx_queue_setup = qede_tx_queue_setup,
1433         .tx_queue_release = qede_tx_queue_release,
1434         .dev_start = qede_dev_start,
1435         .dev_set_link_up = qede_dev_set_link_up,
1436         .dev_set_link_down = qede_dev_set_link_down,
1437         .link_update = qede_link_update,
1438         .promiscuous_enable = qede_promiscuous_enable,
1439         .promiscuous_disable = qede_promiscuous_disable,
1440         .allmulticast_enable = qede_allmulticast_enable,
1441         .allmulticast_disable = qede_allmulticast_disable,
1442         .dev_stop = qede_dev_stop,
1443         .dev_close = qede_dev_close,
1444         .stats_get = qede_get_stats,
1445         .stats_reset = qede_reset_stats,
1446         .xstats_get = qede_get_xstats,
1447         .xstats_reset = qede_reset_xstats,
1448         .xstats_get_names = qede_get_xstats_names,
1449         .mac_addr_add = qede_mac_addr_add,
1450         .mac_addr_remove = qede_mac_addr_remove,
1451         .mac_addr_set = qede_mac_addr_set,
1452         .vlan_offload_set = qede_vlan_offload_set,
1453         .vlan_filter_set = qede_vlan_filter_set,
1454         .flow_ctrl_set = qede_flow_ctrl_set,
1455         .flow_ctrl_get = qede_flow_ctrl_get,
1456         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1457         .rss_hash_update = qede_rss_hash_update,
1458         .rss_hash_conf_get = qede_rss_hash_conf_get,
1459         .reta_update  = qede_rss_reta_update,
1460         .reta_query  = qede_rss_reta_query,
1461         .mtu_set = qede_set_mtu,
1462 };
1463
1464 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1465         .dev_configure = qede_dev_configure,
1466         .dev_infos_get = qede_dev_info_get,
1467         .rx_queue_setup = qede_rx_queue_setup,
1468         .rx_queue_release = qede_rx_queue_release,
1469         .tx_queue_setup = qede_tx_queue_setup,
1470         .tx_queue_release = qede_tx_queue_release,
1471         .dev_start = qede_dev_start,
1472         .dev_set_link_up = qede_dev_set_link_up,
1473         .dev_set_link_down = qede_dev_set_link_down,
1474         .link_update = qede_link_update,
1475         .promiscuous_enable = qede_promiscuous_enable,
1476         .promiscuous_disable = qede_promiscuous_disable,
1477         .allmulticast_enable = qede_allmulticast_enable,
1478         .allmulticast_disable = qede_allmulticast_disable,
1479         .dev_stop = qede_dev_stop,
1480         .dev_close = qede_dev_close,
1481         .stats_get = qede_get_stats,
1482         .stats_reset = qede_reset_stats,
1483         .xstats_get = qede_get_xstats,
1484         .xstats_reset = qede_reset_xstats,
1485         .xstats_get_names = qede_get_xstats_names,
1486         .vlan_offload_set = qede_vlan_offload_set,
1487         .vlan_filter_set = qede_vlan_filter_set,
1488         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1489         .rss_hash_update = qede_rss_hash_update,
1490         .rss_hash_conf_get = qede_rss_hash_conf_get,
1491         .reta_update  = qede_rss_reta_update,
1492         .reta_query  = qede_rss_reta_query,
1493         .mtu_set = qede_set_mtu,
1494 };
1495
1496 static void qede_update_pf_params(struct ecore_dev *edev)
1497 {
1498         struct ecore_pf_params pf_params;
1499         /* 32 rx + 32 tx */
1500         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1501         pf_params.eth_pf_params.num_cons = 64;
1502         qed_ops->common->update_pf_params(edev, &pf_params);
1503 }
1504
1505 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1506 {
1507         struct rte_pci_device *pci_dev;
1508         struct rte_pci_addr pci_addr;
1509         struct qede_dev *adapter;
1510         struct ecore_dev *edev;
1511         struct qed_dev_eth_info dev_info;
1512         struct qed_slowpath_params params;
1513         static bool do_once = true;
1514         uint8_t bulletin_change;
1515         uint8_t vf_mac[ETHER_ADDR_LEN];
1516         uint8_t is_mac_forced;
1517         bool is_mac_exist;
1518         /* Fix up ecore debug level */
1519         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1520         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1521         uint32_t max_mac_addrs;
1522         int rc;
1523
1524         /* Extract key data structures */
1525         adapter = eth_dev->data->dev_private;
1526         edev = &adapter->edev;
1527         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1528         pci_addr = pci_dev->addr;
1529
1530         PMD_INIT_FUNC_TRACE(edev);
1531
1532         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1533                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1534                  eth_dev->data->port_id);
1535
1536         eth_dev->rx_pkt_burst = qede_recv_pkts;
1537         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1540                 DP_NOTICE(edev, false,
1541                           "Skipping device init from secondary process\n");
1542                 return 0;
1543         }
1544
1545         rte_eth_copy_pci_info(eth_dev, pci_dev);
1546
1547         qed_ops = qed_get_eth_ops();
1548         if (!qed_ops) {
1549                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1550                 return -EINVAL;
1551         }
1552
1553         DP_INFO(edev, "Starting qede probe\n");
1554
1555         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1556                                     dp_module, dp_level, is_vf);
1557
1558         if (rc != 0) {
1559                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1560                 return -ENODEV;
1561         }
1562
1563         qede_update_pf_params(edev);
1564
1565         rte_intr_callback_register(&pci_dev->intr_handle,
1566                                    qede_interrupt_handler, (void *)eth_dev);
1567
1568         if (rte_intr_enable(&pci_dev->intr_handle)) {
1569                 DP_ERR(edev, "rte_intr_enable() failed\n");
1570                 return -ENODEV;
1571         }
1572
1573         /* Start the Slowpath-process */
1574         memset(&params, 0, sizeof(struct qed_slowpath_params));
1575         params.int_mode = ECORE_INT_MODE_MSIX;
1576         params.drv_major = QEDE_PMD_VERSION_MAJOR;
1577         params.drv_minor = QEDE_PMD_VERSION_MINOR;
1578         params.drv_rev = QEDE_PMD_VERSION_REVISION;
1579         params.drv_eng = QEDE_PMD_VERSION_PATCH;
1580         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
1581                 QEDE_PMD_DRV_VER_STR_SIZE);
1582
1583         /* For CMT mode device do periodic polling for slowpath events.
1584          * This is required since uio device uses only one MSI-x
1585          * interrupt vector but we need one for each engine.
1586          */
1587         if (edev->num_hwfns > 1 && IS_PF(edev)) {
1588                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1589                                        qede_poll_sp_sb_cb,
1590                                        (void *)eth_dev);
1591                 if (rc != 0) {
1592                         DP_ERR(edev, "Unable to start periodic"
1593                                      " timer rc %d\n", rc);
1594                         return -EINVAL;
1595                 }
1596         }
1597
1598         rc = qed_ops->common->slowpath_start(edev, &params);
1599         if (rc) {
1600                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1601                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1602                                      (void *)eth_dev);
1603                 return -ENODEV;
1604         }
1605
1606         rc = qed_ops->fill_dev_info(edev, &dev_info);
1607         if (rc) {
1608                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1609                 qed_ops->common->slowpath_stop(edev);
1610                 qed_ops->common->remove(edev);
1611                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1612                                      (void *)eth_dev);
1613                 return -ENODEV;
1614         }
1615
1616         qede_alloc_etherdev(adapter, &dev_info);
1617
1618         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
1619
1620         if (!is_vf)
1621                 adapter->dev_info.num_mac_addrs =
1622                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1623                                             ECORE_MAC);
1624         else
1625                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1626                                              &adapter->dev_info.num_mac_addrs);
1627
1628         /* Allocate memory for storing MAC addr */
1629         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1630                                         (ETHER_ADDR_LEN *
1631                                         adapter->dev_info.num_mac_addrs),
1632                                         RTE_CACHE_LINE_SIZE);
1633
1634         if (eth_dev->data->mac_addrs == NULL) {
1635                 DP_ERR(edev, "Failed to allocate MAC address\n");
1636                 qed_ops->common->slowpath_stop(edev);
1637                 qed_ops->common->remove(edev);
1638                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1639                                      (void *)eth_dev);
1640                 return -ENOMEM;
1641         }
1642
1643         if (!is_vf) {
1644                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1645                                 hw_info.hw_mac_addr,
1646                                 &eth_dev->data->mac_addrs[0]);
1647                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1648                                 &adapter->primary_mac);
1649         } else {
1650                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1651                                        &bulletin_change);
1652                 if (bulletin_change) {
1653                         is_mac_exist =
1654                             ecore_vf_bulletin_get_forced_mac(
1655                                                 ECORE_LEADING_HWFN(edev),
1656                                                 vf_mac,
1657                                                 &is_mac_forced);
1658                         if (is_mac_exist && is_mac_forced) {
1659                                 DP_INFO(edev, "VF macaddr received from PF\n");
1660                                 ether_addr_copy((struct ether_addr *)&vf_mac,
1661                                                 &eth_dev->data->mac_addrs[0]);
1662                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1663                                                 &adapter->primary_mac);
1664                         } else {
1665                                 DP_NOTICE(edev, false,
1666                                           "No VF macaddr assigned\n");
1667                         }
1668                 }
1669         }
1670
1671         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1672
1673         if (do_once) {
1674                 qede_print_adapter_info(adapter);
1675                 do_once = false;
1676         }
1677
1678         adapter->state = QEDE_DEV_INIT;
1679
1680         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1681                   adapter->primary_mac.addr_bytes[0],
1682                   adapter->primary_mac.addr_bytes[1],
1683                   adapter->primary_mac.addr_bytes[2],
1684                   adapter->primary_mac.addr_bytes[3],
1685                   adapter->primary_mac.addr_bytes[4],
1686                   adapter->primary_mac.addr_bytes[5]);
1687
1688         return rc;
1689 }
1690
1691 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1692 {
1693         return qede_common_dev_init(eth_dev, 1);
1694 }
1695
1696 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1697 {
1698         return qede_common_dev_init(eth_dev, 0);
1699 }
1700
1701 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1702 {
1703         /* only uninitialize in the primary process */
1704         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1705                 return 0;
1706
1707         /* safe to close dev here */
1708         qede_dev_close(eth_dev);
1709
1710         eth_dev->dev_ops = NULL;
1711         eth_dev->rx_pkt_burst = NULL;
1712         eth_dev->tx_pkt_burst = NULL;
1713
1714         if (eth_dev->data->mac_addrs)
1715                 rte_free(eth_dev->data->mac_addrs);
1716
1717         eth_dev->data->mac_addrs = NULL;
1718
1719         return 0;
1720 }
1721
1722 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1723 {
1724         return qede_dev_common_uninit(eth_dev);
1725 }
1726
1727 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1728 {
1729         return qede_dev_common_uninit(eth_dev);
1730 }
1731
1732 static struct rte_pci_id pci_id_qedevf_map[] = {
1733 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1734         {
1735                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1736         },
1737         {
1738                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1739         },
1740         {.vendor_id = 0,}
1741 };
1742
1743 static struct rte_pci_id pci_id_qede_map[] = {
1744 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1745         {
1746                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1747         },
1748         {
1749                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1750         },
1751         {
1752                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1753         },
1754         {
1755                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1756         },
1757         {
1758                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1759         },
1760         {.vendor_id = 0,}
1761 };
1762
1763 static struct eth_driver rte_qedevf_pmd = {
1764         .pci_drv = {
1765                     .id_table = pci_id_qedevf_map,
1766                     .drv_flags =
1767                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1768                     .probe = rte_eth_dev_pci_probe,
1769                     .remove = rte_eth_dev_pci_remove,
1770                    },
1771         .eth_dev_init = qedevf_eth_dev_init,
1772         .eth_dev_uninit = qedevf_eth_dev_uninit,
1773         .dev_private_size = sizeof(struct qede_dev),
1774 };
1775
1776 static struct eth_driver rte_qede_pmd = {
1777         .pci_drv = {
1778                     .id_table = pci_id_qede_map,
1779                     .drv_flags =
1780                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1781                     .probe = rte_eth_dev_pci_probe,
1782                     .remove = rte_eth_dev_pci_remove,
1783                    },
1784         .eth_dev_init = qede_eth_dev_init,
1785         .eth_dev_uninit = qede_eth_dev_uninit,
1786         .dev_private_size = sizeof(struct qede_dev),
1787 };
1788
1789 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1790 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1791 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
1792 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1793 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
1794 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");