drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(struct rte_intr_handle *handle, void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329
 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 331 {
 332         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 333         ucast->is_rx_filter = true;
 334         ucast->is_tx_filter = true;
 335         /* ucast->assert_on_error = true; - For debug */
 336 }
 337
 338 static void qede_set_cmn_tunn_param(struct ecore_tunn_update_params *params,
 339                                      uint8_t clss, uint64_t mode, uint64_t mask)
 340 {
 341         memset(params, 0, sizeof(struct ecore_tunn_update_params));
 342         params->tunn_mode = mode;
 343         params->tunn_mode_update_mask = mask;
 344         params->update_tx_pf_clss = 1;
 345         params->update_rx_pf_clss = 1;
 346         params->tunn_clss_vxlan = clss;
 347 }
 348
 349 static int
 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 351                   bool add)
 352 {
 353         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 354         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 355         struct qede_ucast_entry *tmp = NULL;
 356         struct qede_ucast_entry *u;
 357         struct ether_addr *mac_addr;
 358
 359         mac_addr  = (struct ether_addr *)ucast->mac;
 360         if (add) {
 361                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 362                         if ((memcmp(mac_addr, &tmp->mac,
 363                                     ETHER_ADDR_LEN) == 0) &&
 364                              ucast->vlan == tmp->vlan) {
 365                                 DP_ERR(edev, "Unicast MAC is already added"
 366                                        " with vlan = %u, vni = %u\n",
 367                                        ucast->vlan,  ucast->vni);
 368                                         return -EEXIST;
 369                         }
 370                 }
 371                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 372                                RTE_CACHE_LINE_SIZE);
 373                 if (!u) {
 374                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 375                         return -ENOMEM;
 376                 }
 377                 ether_addr_copy(mac_addr, &u->mac);
 378                 u->vlan = ucast->vlan;
 379                 u->vni = ucast->vni;
 380                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 381                 qdev->num_uc_addr++;
 382         } else {
 383                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 384                         if ((memcmp(mac_addr, &tmp->mac,
 385                                     ETHER_ADDR_LEN) == 0) &&
 386                             ucast->vlan == tmp->vlan      &&
 387                             ucast->vni == tmp->vni)
 388                         break;
 389                 }
 390                 if (tmp == NULL) {
 391                         DP_INFO(edev, "Unicast MAC is not found\n");
 392                         return -EINVAL;
 393                 }
 394                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 395                 qdev->num_uc_addr--;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int
 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 403                   bool add)
 404 {
 405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 407         struct ether_addr *mac_addr;
 408         struct qede_mcast_entry *tmp = NULL;
 409         struct qede_mcast_entry *m;
 410
 411         mac_addr  = (struct ether_addr *)mcast->mac;
 412         if (add) {
 413                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 414                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 415                                 DP_ERR(edev,
 416                                         "Multicast MAC is already added\n");
 417                                 return -EEXIST;
 418                         }
 419                 }
 420                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 421                         RTE_CACHE_LINE_SIZE);
 422                 if (!m) {
 423                         DP_ERR(edev,
 424                                 "Did not allocate memory for mcast\n");
 425                         return -ENOMEM;
 426                 }
 427                 ether_addr_copy(mac_addr, &m->mac);
 428                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 429                 qdev->num_mc_addr++;
 430         } else {
 431                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 432                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 433                                 break;
 434                 }
 435                 if (tmp == NULL) {
 436                         DP_INFO(edev, "Multicast mac is not found\n");
 437                         return -EINVAL;
 438                 }
 439                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 440                              qede_mcast_entry, list);
 441                 qdev->num_mc_addr--;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static enum _ecore_status_t
 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 449                  bool add)
 450 {
 451         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 452         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 453         enum _ecore_status_t rc;
 454         struct ecore_filter_mcast mcast;
 455         struct qede_mcast_entry *tmp;
 456         uint16_t j = 0;
 457
 458         /* Multicast */
 459         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 460                 if (add) {
 461                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 462                                 DP_ERR(edev,
 463                                        "Mcast filter table limit exceeded, "
 464                                        "Please enable mcast promisc mode\n");
 465                                 return -ECORE_INVAL;
 466                         }
 467                 }
 468                 rc = qede_mcast_filter(eth_dev, ucast, add);
 469                 if (rc == 0) {
 470                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 471                         memset(&mcast, 0, sizeof(mcast));
 472                         mcast.num_mc_addrs = qdev->num_mc_addr;
 473                         mcast.opcode = ECORE_FILTER_ADD;
 474                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 475                                 ether_addr_copy(&tmp->mac,
 476                                         (struct ether_addr *)&mcast.mac[j]);
 477                                 j++;
 478                         }
 479                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 480                                                     ECORE_SPQ_MODE_CB, NULL);
 481                 }
 482                 if (rc != ECORE_SUCCESS) {
 483                         DP_ERR(edev, "Failed to add multicast filter"
 484                                " rc = %d, op = %d\n", rc, add);
 485                 }
 486         } else { /* Unicast */
 487                 if (add) {
 488                         if (qdev->num_uc_addr >= qdev->dev_info.num_mac_addrs) {
 489                                 DP_ERR(edev,
 490                                        "Ucast filter table limit exceeded,"
 491                                        " Please enable promisc mode\n");
 492                                 return -ECORE_INVAL;
 493                         }
 494                 }
 495                 rc = qede_ucast_filter(eth_dev, ucast, add);
 496                 if (rc == 0)
 497                         rc = ecore_filter_ucast_cmd(edev, ucast,
 498                                                     ECORE_SPQ_MODE_CB, NULL);
 499                 if (rc != ECORE_SUCCESS) {
 500                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 501                                rc, add);
 502                 }
 503         }
 504
 505         return rc;
 506 }
 507
 508 static void
 509 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 510                   uint32_t index, __rte_unused uint32_t pool)
 511 {
 512         struct ecore_filter_ucast ucast;
 513
 514         qede_set_ucast_cmn_params(&ucast);
 515         ucast.type = ECORE_FILTER_MAC;
 516         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 517         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 518 }
 519
 520 static void
 521 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 522 {
 523         struct qede_dev *qdev = eth_dev->data->dev_private;
 524         struct ecore_dev *edev = &qdev->edev;
 525         struct ether_addr mac_addr;
 526         struct ecore_filter_ucast ucast;
 527         int rc;
 528
 529         PMD_INIT_FUNC_TRACE(edev);
 530
 531         if (index >= qdev->dev_info.num_mac_addrs) {
 532                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 533                        index, qdev->dev_info.num_mac_addrs);
 534                 return;
 535         }
 536
 537         qede_set_ucast_cmn_params(&ucast);
 538         ucast.opcode = ECORE_FILTER_REMOVE;
 539         ucast.type = ECORE_FILTER_MAC;
 540
 541         /* Use the index maintained by rte */
 542         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 543                         (struct ether_addr *)&ucast.mac);
 544
 545         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 546 }
 547
 548 static void
 549 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 550 {
 551         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 552         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 553         struct ecore_filter_ucast ucast;
 554         int rc;
 555
 556         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 557                                                mac_addr->addr_bytes)) {
 558                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 559                 ether_addr_copy(&qdev->primary_mac,
 560                                 &eth_dev->data->mac_addrs[0]);
 561                 return;
 562         }
 563
 564         /* First remove the primary mac */
 565         qede_set_ucast_cmn_params(&ucast);
 566         ucast.opcode = ECORE_FILTER_REMOVE;
 567         ucast.type = ECORE_FILTER_MAC;
 568         ether_addr_copy(&qdev->primary_mac,
 569                         (struct ether_addr *)&ucast.mac);
 570         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 571         if (rc != 0) {
 572                 DP_ERR(edev, "Unable to remove current macaddr"
 573                              " Reverting to previous default mac\n");
 574                 ether_addr_copy(&qdev->primary_mac,
 575                                 &eth_dev->data->mac_addrs[0]);
 576                 return;
 577         }
 578
 579         /* Add new MAC */
 580         ucast.opcode = ECORE_FILTER_ADD;
 581         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 582         rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 583         if (rc != 0)
 584                 DP_ERR(edev, "Unable to add new default mac\n");
 585         else
 586                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 587 }
 588
 589 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 590 {
 591         struct ecore_dev *edev = &qdev->edev;
 592         struct qed_update_vport_params params = {
 593                 .vport_id = 0,
 594                 .accept_any_vlan = action,
 595                 .update_accept_any_vlan_flg = 1,
 596         };
 597         int rc;
 598
 599         /* Proceed only if action actually needs to be performed */
 600         if (qdev->accept_any_vlan == action)
 601                 return;
 602
 603         rc = qdev->ops->vport_update(edev, &params);
 604         if (rc) {
 605                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 606                        action ? "enable" : "disable");
 607         } else {
 608                 DP_INFO(edev, "%s accept-any-vlan\n",
 609                         action ? "enabled" : "disabled");
 610                 qdev->accept_any_vlan = action;
 611         }
 612 }
 613
 614 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 615 {
 616         struct qed_update_vport_params vport_update_params;
 617         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 618         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 619         int rc;
 620
 621         memset(&vport_update_params, 0, sizeof(vport_update_params));
 622         vport_update_params.vport_id = 0;
 623         vport_update_params.update_inner_vlan_removal_flg = 1;
 624         vport_update_params.inner_vlan_removal_flg = set_stripping;
 625         rc = qdev->ops->vport_update(edev, &vport_update_params);
 626         if (rc) {
 627                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 628                 return rc;
 629         }
 630
 631         return 0;
 632 }
 633
 634 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 635 {
 636         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 637         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 638         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 639
 640         if (mask & ETH_VLAN_STRIP_MASK) {
 641                 if (rxmode->hw_vlan_strip)
 642                         (void)qede_vlan_stripping(eth_dev, 1);
 643                 else
 644                         (void)qede_vlan_stripping(eth_dev, 0);
 645         }
 646
 647         if (mask & ETH_VLAN_FILTER_MASK) {
 648                 /* VLAN filtering kicks in when a VLAN is added */
 649                 if (rxmode->hw_vlan_filter) {
 650                         qede_vlan_filter_set(eth_dev, 0, 1);
 651                 } else {
 652                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 653                                 DP_NOTICE(edev, false,
 654                                   " Please remove existing VLAN filters"
 655                                   " before disabling VLAN filtering\n");
 656                                 /* Signal app that VLAN filtering is still
 657                                  * enabled
 658                                  */
 659                                 rxmode->hw_vlan_filter = true;
 660                         } else {
 661                                 qede_vlan_filter_set(eth_dev, 0, 0);
 662                         }
 663                 }
 664         }
 665
 666         if (mask & ETH_VLAN_EXTEND_MASK)
 667                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 668                         " and classification is based on outer tag only\n");
 669
 670         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 671                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 672 }
 673
 674 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 675                                 uint16_t vlan_id, int on)
 676 {
 677         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 678         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 679         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 680         struct qede_vlan_entry *tmp = NULL;
 681         struct qede_vlan_entry *vlan;
 682         struct ecore_filter_ucast ucast;
 683         int rc;
 684
 685         if (on) {
 686                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 687                         DP_INFO(edev, "Reached max VLAN filter limit"
 688                                       " enabling accept_any_vlan\n");
 689                         qede_config_accept_any_vlan(qdev, true);
 690                         return 0;
 691                 }
 692
 693                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 694                         if (tmp->vid == vlan_id) {
 695                                 DP_ERR(edev, "VLAN %u already configured\n",
 696                                        vlan_id);
 697                                 return -EEXIST;
 698                         }
 699                 }
 700
 701                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 702                                   RTE_CACHE_LINE_SIZE);
 703
 704                 if (!vlan) {
 705                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 706                         return -ENOMEM;
 707                 }
 708
 709                 qede_set_ucast_cmn_params(&ucast);
 710                 ucast.opcode = ECORE_FILTER_ADD;
 711                 ucast.type = ECORE_FILTER_VLAN;
 712                 ucast.vlan = vlan_id;
 713                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 714                                             NULL);
 715                 if (rc != 0) {
 716                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 717                                rc);
 718                         rte_free(vlan);
 719                 } else {
 720                         vlan->vid = vlan_id;
 721                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 722                         qdev->configured_vlans++;
 723                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 724                                 vlan_id, qdev->configured_vlans);
 725                 }
 726         } else {
 727                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 728                         if (tmp->vid == vlan_id)
 729                                 break;
 730                 }
 731
 732                 if (!tmp) {
 733                         if (qdev->configured_vlans == 0) {
 734                                 DP_INFO(edev,
 735                                         "No VLAN filters configured yet\n");
 736                                 return 0;
 737                         }
 738
 739                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 740                         return -EINVAL;
 741                 }
 742
 743                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 744
 745                 qede_set_ucast_cmn_params(&ucast);
 746                 ucast.opcode = ECORE_FILTER_REMOVE;
 747                 ucast.type = ECORE_FILTER_VLAN;
 748                 ucast.vlan = vlan_id;
 749                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 750                                             NULL);
 751                 if (rc != 0) {
 752                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 753                                vlan_id, rc);
 754                 } else {
 755                         qdev->configured_vlans--;
 756                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 757                                 vlan_id, qdev->configured_vlans);
 758                 }
 759         }
 760
 761         return rc;
 762 }
 763
 764 static int qede_init_vport(struct qede_dev *qdev)
 765 {
 766         struct ecore_dev *edev = &qdev->edev;
 767         struct qed_start_vport_params start = {0};
 768         int rc;
 769
 770         start.remove_inner_vlan = 1;
 771         start.gro_enable = 0;
 772         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 773         start.vport_id = 0;
 774         start.drop_ttl0 = false;
 775         start.clear_stats = 1;
 776         start.handle_ptp_pkts = 0;
 777
 778         rc = qdev->ops->vport_start(edev, &start);
 779         if (rc) {
 780                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 781                 return rc;
 782         }
 783
 784         DP_INFO(edev,
 785                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 786                 start.vport_id, ETHER_MTU);
 787
 788         return 0;
 789 }
 790
 791 static void qede_prandom_bytes(uint32_t *buff)
 792 {
 793         uint8_t i;
 794
 795         srand((unsigned int)time(NULL));
 796         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 797                 buff[i] = rand();
 798 }
 799
 800 static int qede_config_rss(struct rte_eth_dev *eth_dev)
 801 {
 802         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 803         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 804         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 805         struct rte_eth_rss_reta_entry64 reta_conf[2];
 806         struct rte_eth_rss_conf rss_conf;
 807         uint32_t i, id, pos, q;
 808
 809         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 810         if (!rss_conf.rss_key) {
 811                 DP_INFO(edev, "Applying driver default key\n");
 812                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 813                 qede_prandom_bytes(&def_rss_key[0]);
 814                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 815         }
 816
 817         /* Configure RSS hash */
 818         if (qede_rss_hash_update(eth_dev, &rss_conf))
 819                 return -EINVAL;
 820
 821         /* Configure default RETA */
 822         memset(reta_conf, 0, sizeof(reta_conf));
 823         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 824                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 825
 826         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 827                 id = i / RTE_RETA_GROUP_SIZE;
 828                 pos = i % RTE_RETA_GROUP_SIZE;
 829                 q = i % QEDE_RSS_COUNT(qdev);
 830                 reta_conf[id].reta[pos] = q;
 831         }
 832         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 833                                  ECORE_RSS_IND_TABLE_SIZE))
 834                 return -EINVAL;
 835
 836         return 0;
 837 }
 838
 839 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 840 {
 841         struct qede_dev *qdev = eth_dev->data->dev_private;
 842         struct ecore_dev *edev = &qdev->edev;
 843         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 844         int rc, i, j;
 845
 846         PMD_INIT_FUNC_TRACE(edev);
 847
 848         /* Check requirements for 100G mode */
 849         if (edev->num_hwfns > 1) {
 850                 if (eth_dev->data->nb_rx_queues < 2 ||
 851                     eth_dev->data->nb_tx_queues < 2) {
 852                         DP_NOTICE(edev, false,
 853                                   "100G mode needs min. 2 RX/TX queues\n");
 854                         return -EINVAL;
 855                 }
 856
 857                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 858                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 859                         DP_NOTICE(edev, false,
 860                                   "100G mode needs even no. of RX/TX queues\n");
 861                         return -EINVAL;
 862                 }
 863         }
 864
 865         /* Sanity checks and throw warnings */
 866         if (rxmode->enable_scatter == 1)
 867                 eth_dev->data->scattered_rx = 1;
 868
 869         if (rxmode->enable_lro == 1) {
 870                 DP_INFO(edev, "LRO is not supported\n");
 871                 return -EINVAL;
 872         }
 873
 874         if (!rxmode->hw_strip_crc)
 875                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 876
 877         if (!rxmode->hw_ip_checksum)
 878                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 879                               "in hw\n");
 880
 881         /* Check for the port restart case */
 882         if (qdev->state != QEDE_DEV_INIT) {
 883                 rc = qdev->ops->vport_stop(edev, 0);
 884                 if (rc != 0)
 885                         return rc;
 886                 qede_dealloc_fp_resc(eth_dev);
 887         }
 888
 889         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 890         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 891         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 892
 893         /* Fastpath status block should be initialized before sending
 894          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 895          */
 896         rc = qede_alloc_fp_resc(qdev);
 897         if (rc != 0)
 898                 return rc;
 899
 900         /* Issue VPORT-START with default config values to allow
 901          * other port configurations early on.
 902          */
 903         rc = qede_init_vport(qdev);
 904         if (rc != 0)
 905                 return rc;
 906
 907         /* Do RSS configuration after vport-start */
 908         switch (rxmode->mq_mode) {
 909         case ETH_MQ_RX_RSS:
 910                 rc = qede_config_rss(eth_dev);
 911                 if (rc != 0) {
 912                         qdev->ops->vport_stop(edev, 0);
 913                         qede_dealloc_fp_resc(eth_dev);
 914                         return -EINVAL;
 915                 }
 916         break;
 917         case ETH_MQ_RX_NONE:
 918                 DP_INFO(edev, "RSS is disabled\n");
 919         break;
 920         default:
 921                 DP_ERR(edev, "Unsupported RSS mode\n");
 922                 qdev->ops->vport_stop(edev, 0);
 923                 qede_dealloc_fp_resc(eth_dev);
 924                 return -EINVAL;
 925         }
 926
 927         SLIST_INIT(&qdev->vlan_list_head);
 928
 929         /* Add primary mac for PF */
 930         if (IS_PF(edev))
 931                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 932
 933         /* Enable VLAN offloads by default */
 934         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 935                                        ETH_VLAN_FILTER_MASK |
 936                                        ETH_VLAN_EXTEND_MASK);
 937
 938         qdev->state = QEDE_DEV_CONFIG;
 939
 940         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 941                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 942                 qdev->num_tc);
 943
 944         return 0;
 945 }
 946
 947 /* Info about HW descriptor ring limitations */
 948 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 949         .nb_max = NUM_RX_BDS_MAX,
 950         .nb_min = 128,
 951         .nb_align = 128 /* lowest common multiple */
 952 };
 953
 954 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 955         .nb_max = NUM_TX_BDS_MAX,
 956         .nb_min = 256,
 957         .nb_align = 256
 958 };
 959
 960 static void
 961 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 962                   struct rte_eth_dev_info *dev_info)
 963 {
 964         struct qede_dev *qdev = eth_dev->data->dev_private;
 965         struct ecore_dev *edev = &qdev->edev;
 966         struct qed_link_output link;
 967         uint32_t speed_cap = 0;
 968
 969         PMD_INIT_FUNC_TRACE(edev);
 970
 971         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 972         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 973                                               QEDE_ETH_OVERHEAD);
 974         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 975         dev_info->rx_desc_lim = qede_rx_desc_lim;
 976         dev_info->tx_desc_lim = qede_tx_desc_lim;
 977         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 978         dev_info->max_tx_queues = dev_info->max_rx_queues;
 979         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 980         if (IS_VF(edev))
 981                 dev_info->max_vfs = 0;
 982         else
 983                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 984         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 985         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 986         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 987
 988         dev_info->default_txconf = (struct rte_eth_txconf) {
 989                 .txq_flags = QEDE_TXQ_FLAGS,
 990         };
 991
 992         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 993                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 994                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 995                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 996                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM);
 997         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 998                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 999                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1000                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1001                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM);
1002
1003         memset(&link, 0, sizeof(struct qed_link_output));
1004         qdev->ops->common->get_link(edev, &link);
1005         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1006                 speed_cap |= ETH_LINK_SPEED_1G;
1007         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1008                 speed_cap |= ETH_LINK_SPEED_10G;
1009         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1010                 speed_cap |= ETH_LINK_SPEED_25G;
1011         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1012                 speed_cap |= ETH_LINK_SPEED_40G;
1013         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1014                 speed_cap |= ETH_LINK_SPEED_50G;
1015         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1016                 speed_cap |= ETH_LINK_SPEED_100G;
1017         dev_info->speed_capa = speed_cap;
1018 }
1019
1020 /* return 0 means link status changed, -1 means not changed */
1021 static int
1022 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1023 {
1024         struct qede_dev *qdev = eth_dev->data->dev_private;
1025         struct ecore_dev *edev = &qdev->edev;
1026         uint16_t link_duplex;
1027         struct qed_link_output link;
1028         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1029
1030         memset(&link, 0, sizeof(struct qed_link_output));
1031         qdev->ops->common->get_link(edev, &link);
1032
1033         /* Link Speed */
1034         curr->link_speed = link.speed;
1035
1036         /* Link Mode */
1037         switch (link.duplex) {
1038         case QEDE_DUPLEX_HALF:
1039                 link_duplex = ETH_LINK_HALF_DUPLEX;
1040                 break;
1041         case QEDE_DUPLEX_FULL:
1042                 link_duplex = ETH_LINK_FULL_DUPLEX;
1043                 break;
1044         case QEDE_DUPLEX_UNKNOWN:
1045         default:
1046                 link_duplex = -1;
1047         }
1048         curr->link_duplex = link_duplex;
1049
1050         /* Link Status */
1051         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1052
1053         /* AN */
1054         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1055                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1056
1057         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1058                 curr->link_speed, curr->link_duplex,
1059                 curr->link_autoneg, curr->link_status);
1060
1061         /* return 0 means link status changed, -1 means not changed */
1062         return ((curr->link_status == link.link_up) ? -1 : 0);
1063 }
1064
1065 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1066 {
1067         struct qede_dev *qdev = eth_dev->data->dev_private;
1068         struct ecore_dev *edev = &qdev->edev;
1069
1070         PMD_INIT_FUNC_TRACE(edev);
1071
1072         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1073
1074         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1075                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1076
1077         qed_configure_filter_rx_mode(eth_dev, type);
1078 }
1079
1080 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1081 {
1082         struct qede_dev *qdev = eth_dev->data->dev_private;
1083         struct ecore_dev *edev = &qdev->edev;
1084
1085         PMD_INIT_FUNC_TRACE(edev);
1086
1087         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1088                 qed_configure_filter_rx_mode(eth_dev,
1089                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1090         else
1091                 qed_configure_filter_rx_mode(eth_dev,
1092                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1093 }
1094
1095 static void qede_poll_sp_sb_cb(void *param)
1096 {
1097         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1098         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1099         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1100         int rc;
1101
1102         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1103         qede_interrupt_action(&edev->hwfns[1]);
1104
1105         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1106                                qede_poll_sp_sb_cb,
1107                                (void *)eth_dev);
1108         if (rc != 0) {
1109                 DP_ERR(edev, "Unable to start periodic"
1110                              " timer rc %d\n", rc);
1111                 assert(false && "Unable to start periodic timer");
1112         }
1113 }
1114
1115 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1116 {
1117         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1118         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1119         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1120         int rc;
1121
1122         PMD_INIT_FUNC_TRACE(edev);
1123
1124         /* dev_stop() shall cleanup fp resources in hw but without releasing
1125          * dma memories and sw structures so that dev_start() can be called
1126          * by the app without reconfiguration. However, in dev_close() we
1127          * can release all the resources and device can be brought up newly
1128          */
1129         if (qdev->state != QEDE_DEV_STOP)
1130                 qede_dev_stop(eth_dev);
1131         else
1132                 DP_INFO(edev, "Device is already stopped\n");
1133
1134         rc = qdev->ops->vport_stop(edev, 0);
1135         if (rc != 0)
1136                 DP_ERR(edev, "Failed to stop VPORT\n");
1137
1138         qede_dealloc_fp_resc(eth_dev);
1139
1140         qdev->ops->common->slowpath_stop(edev);
1141
1142         qdev->ops->common->remove(edev);
1143
1144         rte_intr_disable(&pci_dev->intr_handle);
1145
1146         rte_intr_callback_unregister(&pci_dev->intr_handle,
1147                                      qede_interrupt_handler, (void *)eth_dev);
1148
1149         if (edev->num_hwfns > 1)
1150                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1151
1152         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1153 }
1154
1155 static void
1156 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1157 {
1158         struct qede_dev *qdev = eth_dev->data->dev_private;
1159         struct ecore_dev *edev = &qdev->edev;
1160         struct ecore_eth_stats stats;
1161         unsigned int i = 0, j = 0, qid;
1162         struct qede_tx_queue *txq;
1163
1164         qdev->ops->get_vport_stats(edev, &stats);
1165
1166         /* RX Stats */
1167         eth_stats->ipackets = stats.rx_ucast_pkts +
1168             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1169
1170         eth_stats->ibytes = stats.rx_ucast_bytes +
1171             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1172
1173         eth_stats->ierrors = stats.rx_crc_errors +
1174             stats.rx_align_errors +
1175             stats.rx_carrier_errors +
1176             stats.rx_oversize_packets +
1177             stats.rx_jabbers + stats.rx_undersize_packets;
1178
1179         eth_stats->rx_nombuf = stats.no_buff_discards;
1180
1181         eth_stats->imissed = stats.mftag_filter_discards +
1182             stats.mac_filter_discards +
1183             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1184
1185         /* TX stats */
1186         eth_stats->opackets = stats.tx_ucast_pkts +
1187             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1188
1189         eth_stats->obytes = stats.tx_ucast_bytes +
1190             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1191
1192         eth_stats->oerrors = stats.tx_err_drop_pkts;
1193
1194         /* Queue stats */
1195         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1196                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1197                         eth_stats->q_ipackets[i] =
1198                                 *(uint64_t *)(
1199                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1200                                         offsetof(struct qede_rx_queue,
1201                                         rcv_pkts));
1202                         eth_stats->q_errors[i] =
1203                                 *(uint64_t *)(
1204                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1205                                         offsetof(struct qede_rx_queue,
1206                                         rx_hw_errors)) +
1207                                 *(uint64_t *)(
1208                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1209                                         offsetof(struct qede_rx_queue,
1210                                         rx_alloc_errors));
1211                         i++;
1212                 }
1213
1214                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1215                         txq = qdev->fp_array[(qid)].txqs[0];
1216                         eth_stats->q_opackets[j] =
1217                                 *((uint64_t *)(uintptr_t)
1218                                         (((uint64_t)(uintptr_t)(txq)) +
1219                                          offsetof(struct qede_tx_queue,
1220                                                   xmit_pkts)));
1221                         j++;
1222                 }
1223         }
1224 }
1225
1226 static unsigned
1227 qede_get_xstats_count(struct qede_dev *qdev) {
1228         return RTE_DIM(qede_xstats_strings) +
1229                 (RTE_DIM(qede_rxq_xstats_strings) * QEDE_RSS_COUNT(qdev));
1230 }
1231
1232 static int
1233 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1234                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1235 {
1236         struct qede_dev *qdev = dev->data->dev_private;
1237         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1238         unsigned int i, qid, stat_idx = 0;
1239
1240         if (xstats_names != NULL) {
1241                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1242                         snprintf(xstats_names[stat_idx].name,
1243                                 sizeof(xstats_names[stat_idx].name),
1244                                 "%s",
1245                                 qede_xstats_strings[i].name);
1246                         stat_idx++;
1247                 }
1248
1249                 for (qid = 0; qid < QEDE_RSS_COUNT(qdev); qid++) {
1250                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1251                                 snprintf(xstats_names[stat_idx].name,
1252                                         sizeof(xstats_names[stat_idx].name),
1253                                         "%.4s%d%s",
1254                                         qede_rxq_xstats_strings[i].name, qid,
1255                                         qede_rxq_xstats_strings[i].name + 4);
1256                                 stat_idx++;
1257                         }
1258                 }
1259         }
1260
1261         return stat_cnt;
1262 }
1263
1264 static int
1265 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1266                 unsigned int n)
1267 {
1268         struct qede_dev *qdev = dev->data->dev_private;
1269         struct ecore_dev *edev = &qdev->edev;
1270         struct ecore_eth_stats stats;
1271         const unsigned int num = qede_get_xstats_count(qdev);
1272         unsigned int i, qid, stat_idx = 0;
1273
1274         if (n < num)
1275                 return num;
1276
1277         qdev->ops->get_vport_stats(edev, &stats);
1278
1279         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1280                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1281                                              qede_xstats_strings[i].offset);
1282                 xstats[stat_idx].id = stat_idx;
1283                 stat_idx++;
1284         }
1285
1286         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1287                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1288                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1289                                 xstats[stat_idx].value = *(uint64_t *)(
1290                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1291                                          qede_rxq_xstats_strings[i].offset);
1292                                 xstats[stat_idx].id = stat_idx;
1293                                 stat_idx++;
1294                         }
1295                 }
1296         }
1297
1298         return stat_idx;
1299 }
1300
1301 static void
1302 qede_reset_xstats(struct rte_eth_dev *dev)
1303 {
1304         struct qede_dev *qdev = dev->data->dev_private;
1305         struct ecore_dev *edev = &qdev->edev;
1306
1307         ecore_reset_vport_stats(edev);
1308 }
1309
1310 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1311 {
1312         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1313         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1314         struct qed_link_params link_params;
1315         int rc;
1316
1317         DP_INFO(edev, "setting link state %d\n", link_up);
1318         memset(&link_params, 0, sizeof(link_params));
1319         link_params.link_up = link_up;
1320         rc = qdev->ops->common->set_link(edev, &link_params);
1321         if (rc != ECORE_SUCCESS)
1322                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1323
1324         return rc;
1325 }
1326
1327 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1328 {
1329         return qede_dev_set_link_state(eth_dev, true);
1330 }
1331
1332 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1333 {
1334         return qede_dev_set_link_state(eth_dev, false);
1335 }
1336
1337 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1338 {
1339         struct qede_dev *qdev = eth_dev->data->dev_private;
1340         struct ecore_dev *edev = &qdev->edev;
1341
1342         ecore_reset_vport_stats(edev);
1343 }
1344
1345 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1346 {
1347         enum qed_filter_rx_mode_type type =
1348             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1349
1350         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1351                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1352
1353         qed_configure_filter_rx_mode(eth_dev, type);
1354 }
1355
1356 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1357 {
1358         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1359                 qed_configure_filter_rx_mode(eth_dev,
1360                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1361         else
1362                 qed_configure_filter_rx_mode(eth_dev,
1363                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1364 }
1365
1366 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1367                               struct rte_eth_fc_conf *fc_conf)
1368 {
1369         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1370         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1371         struct qed_link_output current_link;
1372         struct qed_link_params params;
1373
1374         memset(&current_link, 0, sizeof(current_link));
1375         qdev->ops->common->get_link(edev, &current_link);
1376
1377         memset(&params, 0, sizeof(params));
1378         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1379         if (fc_conf->autoneg) {
1380                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1381                         DP_ERR(edev, "Autoneg not supported\n");
1382                         return -EINVAL;
1383                 }
1384                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1385         }
1386
1387         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1388         if (fc_conf->mode == RTE_FC_FULL)
1389                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1390                                         QED_LINK_PAUSE_RX_ENABLE);
1391         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1392                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1393         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1394                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1395
1396         params.link_up = true;
1397         (void)qdev->ops->common->set_link(edev, &params);
1398
1399         return 0;
1400 }
1401
1402 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1403                               struct rte_eth_fc_conf *fc_conf)
1404 {
1405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1407         struct qed_link_output current_link;
1408
1409         memset(&current_link, 0, sizeof(current_link));
1410         qdev->ops->common->get_link(edev, &current_link);
1411
1412         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1413                 fc_conf->autoneg = true;
1414
1415         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1416                                          QED_LINK_PAUSE_TX_ENABLE))
1417                 fc_conf->mode = RTE_FC_FULL;
1418         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1419                 fc_conf->mode = RTE_FC_RX_PAUSE;
1420         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1421                 fc_conf->mode = RTE_FC_TX_PAUSE;
1422         else
1423                 fc_conf->mode = RTE_FC_NONE;
1424
1425         return 0;
1426 }
1427
1428 static const uint32_t *
1429 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1430 {
1431         static const uint32_t ptypes[] = {
1432                 RTE_PTYPE_L3_IPV4,
1433                 RTE_PTYPE_L3_IPV6,
1434                 RTE_PTYPE_UNKNOWN
1435         };
1436
1437         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1438                 return ptypes;
1439
1440         return NULL;
1441 }
1442
1443 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1444 {
1445         *rss_caps = 0;
1446         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1447         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1448         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1449         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1450         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1451         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1452 }
1453
1454 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1455                                 struct rte_eth_rss_conf *rss_conf)
1456 {
1457         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1458         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1459         struct ecore_sp_vport_update_params vport_update_params;
1460         struct ecore_rss_params rss_params;
1461         struct ecore_rss_params params;
1462         struct ecore_hwfn *p_hwfn;
1463         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1464         uint64_t hf = rss_conf->rss_hf;
1465         uint8_t len = rss_conf->rss_key_len;
1466         uint8_t i;
1467         int rc;
1468
1469         memset(&vport_update_params, 0, sizeof(vport_update_params));
1470         memset(&rss_params, 0, sizeof(rss_params));
1471
1472         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1473                 (unsigned long)hf, len, key);
1474
1475         if (hf != 0) {
1476                 /* Enabling RSS */
1477                 DP_INFO(edev, "Enabling rss\n");
1478
1479                 /* RSS caps */
1480                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1481                 rss_params.update_rss_capabilities = 1;
1482
1483                 /* RSS hash key */
1484                 if (key) {
1485                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1486                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1487                                 return -EINVAL;
1488                         }
1489                         DP_INFO(edev, "Applying user supplied hash key\n");
1490                         rss_params.update_rss_key = 1;
1491                         memcpy(&rss_params.rss_key, key, len);
1492                 }
1493                 rss_params.rss_enable = 1;
1494         }
1495
1496         rss_params.update_rss_config = 1;
1497         /* tbl_size has to be set with capabilities */
1498         rss_params.rss_table_size_log = 7;
1499         vport_update_params.vport_id = 0;
1500         vport_update_params.rss_params = &rss_params;
1501
1502         for_each_hwfn(edev, i) {
1503                 p_hwfn = &edev->hwfns[i];
1504                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1505                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1506                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1507                 if (rc) {
1508                         DP_ERR(edev, "vport-update for RSS failed\n");
1509                         return rc;
1510                 }
1511         }
1512         qdev->rss_enable = rss_params.rss_enable;
1513
1514         /* Update local structure for hash query */
1515         qdev->rss_conf.rss_hf = hf;
1516         qdev->rss_conf.rss_key_len = len;
1517         if (qdev->rss_enable) {
1518                 if  (qdev->rss_conf.rss_key == NULL) {
1519                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1520                         if (qdev->rss_conf.rss_key == NULL) {
1521                                 DP_ERR(edev, "No memory to store RSS key\n");
1522                                 return -ENOMEM;
1523                         }
1524                 }
1525                 if (key && len) {
1526                         DP_INFO(edev, "Storing RSS key\n");
1527                         memcpy(qdev->rss_conf.rss_key, key, len);
1528                 }
1529         } else if (!qdev->rss_enable && len == 0) {
1530                 if (qdev->rss_conf.rss_key) {
1531                         free(qdev->rss_conf.rss_key);
1532                         qdev->rss_conf.rss_key = NULL;
1533                         DP_INFO(edev, "Free RSS key\n");
1534                 }
1535         }
1536
1537         return 0;
1538 }
1539
1540 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1541                            struct rte_eth_rss_conf *rss_conf)
1542 {
1543         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1544
1545         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1546         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1547
1548         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1549                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1550                        rss_conf->rss_key_len);
1551         return 0;
1552 }
1553
1554 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1555                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1556                                 uint16_t reta_size)
1557 {
1558         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1559         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1560         struct ecore_sp_vport_update_params vport_update_params;
1561         struct ecore_rss_params params;
1562         struct ecore_hwfn *p_hwfn;
1563         uint16_t i, idx, shift;
1564         uint8_t entry;
1565         int rc;
1566
1567         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1568                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1569                        reta_size);
1570                 return -EINVAL;
1571         }
1572
1573         memset(&vport_update_params, 0, sizeof(vport_update_params));
1574         memset(&params, 0, sizeof(params));
1575
1576         for (i = 0; i < reta_size; i++) {
1577                 idx = i / RTE_RETA_GROUP_SIZE;
1578                 shift = i % RTE_RETA_GROUP_SIZE;
1579                 if (reta_conf[idx].mask & (1ULL << shift)) {
1580                         entry = reta_conf[idx].reta[shift];
1581                         params.rss_ind_table[i] = entry;
1582                 }
1583         }
1584
1585         /* Fix up RETA for CMT mode device */
1586         if (edev->num_hwfns > 1)
1587                 qdev->rss_enable = qed_update_rss_parm_cmt(edev,
1588                                         &params.rss_ind_table[0]);
1589         params.update_rss_ind_table = 1;
1590         params.rss_table_size_log = 7;
1591         params.update_rss_config = 1;
1592         vport_update_params.vport_id = 0;
1593         /* Use the current value of rss_enable */
1594         params.rss_enable = qdev->rss_enable;
1595         vport_update_params.rss_params = &params;
1596
1597         for_each_hwfn(edev, i) {
1598                 p_hwfn = &edev->hwfns[i];
1599                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1600                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1601                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1602                 if (rc) {
1603                         DP_ERR(edev, "vport-update for RSS failed\n");
1604                         return rc;
1605                 }
1606         }
1607
1608         /* Update the local copy for RETA query command */
1609         memcpy(qdev->rss_ind_table, params.rss_ind_table,
1610                sizeof(params.rss_ind_table));
1611
1612         return 0;
1613 }
1614
1615 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1616                                struct rte_eth_rss_reta_entry64 *reta_conf,
1617                                uint16_t reta_size)
1618 {
1619         struct qede_dev *qdev = eth_dev->data->dev_private;
1620         struct ecore_dev *edev = &qdev->edev;
1621         uint16_t i, idx, shift;
1622         uint8_t entry;
1623
1624         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1625                 DP_ERR(edev, "reta_size %d is not supported\n",
1626                        reta_size);
1627                 return -EINVAL;
1628         }
1629
1630         for (i = 0; i < reta_size; i++) {
1631                 idx = i / RTE_RETA_GROUP_SIZE;
1632                 shift = i % RTE_RETA_GROUP_SIZE;
1633                 if (reta_conf[idx].mask & (1ULL << shift)) {
1634                         entry = qdev->rss_ind_table[i];
1635                         reta_conf[idx].reta[shift] = entry;
1636                 }
1637         }
1638
1639         return 0;
1640 }
1641
1642 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1643 {
1644         uint32_t frame_size;
1645         struct qede_dev *qdev = dev->data->dev_private;
1646         struct rte_eth_dev_info dev_info = {0};
1647
1648         qede_dev_info_get(dev, &dev_info);
1649
1650         /* VLAN_TAG = 4 */
1651         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1652
1653         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1654                 return -EINVAL;
1655
1656         if (!dev->data->scattered_rx &&
1657             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1658                 return -EINVAL;
1659
1660         if (frame_size > ETHER_MAX_LEN)
1661                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1662         else
1663                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1664
1665         /* update max frame size */
1666         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1667         qdev->mtu = mtu;
1668         qede_dev_stop(dev);
1669         qede_dev_start(dev);
1670
1671         return 0;
1672 }
1673
1674 static int
1675 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1676                        struct rte_eth_udp_tunnel *tunnel_udp,
1677                        bool add)
1678 {
1679         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1680         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1681         struct ecore_tunn_update_params params;
1682         struct ecore_hwfn *p_hwfn;
1683         int rc, i;
1684
1685         PMD_INIT_FUNC_TRACE(edev);
1686
1687         memset(&params, 0, sizeof(params));
1688         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1689                 params.update_vxlan_udp_port = 1;
1690                 params.vxlan_udp_port = (add) ? tunnel_udp->udp_port :
1691                                         QEDE_VXLAN_DEF_PORT;
1692                 for_each_hwfn(edev, i) {
1693                         p_hwfn = &edev->hwfns[i];
1694                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &params,
1695                                                 ECORE_SPQ_MODE_CB, NULL);
1696                         if (rc != ECORE_SUCCESS) {
1697                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1698                                         params.vxlan_udp_port);
1699                                 return rc;
1700                         }
1701                 }
1702         }
1703
1704         return 0;
1705 }
1706
1707 int
1708 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1709                       struct rte_eth_udp_tunnel *tunnel_udp)
1710 {
1711         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1712 }
1713
1714 int
1715 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1716                       struct rte_eth_udp_tunnel *tunnel_udp)
1717 {
1718         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1719 }
1720
1721 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1722                                        uint32_t *clss, char *str)
1723 {
1724         uint16_t j;
1725         *clss = MAX_ECORE_TUNN_CLSS;
1726
1727         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1728                 if (filter == qede_tunn_types[j].rte_filter_type) {
1729                         *type = qede_tunn_types[j].qede_type;
1730                         *clss = qede_tunn_types[j].qede_tunn_clss;
1731                         strcpy(str, qede_tunn_types[j].string);
1732                         return;
1733                 }
1734         }
1735 }
1736
1737 static int
1738 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1739                               const struct rte_eth_tunnel_filter_conf *conf,
1740                               uint32_t type)
1741 {
1742         /* Init commmon ucast params first */
1743         qede_set_ucast_cmn_params(ucast);
1744
1745         /* Copy out the required fields based on classification type */
1746         ucast->type = type;
1747
1748         switch (type) {
1749         case ECORE_FILTER_VNI:
1750                 ucast->vni = conf->tenant_id;
1751         break;
1752         case ECORE_FILTER_INNER_VLAN:
1753                 ucast->vlan = conf->inner_vlan;
1754         break;
1755         case ECORE_FILTER_MAC:
1756                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1757                        ETHER_ADDR_LEN);
1758         break;
1759         case ECORE_FILTER_INNER_MAC:
1760                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1761                        ETHER_ADDR_LEN);
1762         break;
1763         case ECORE_FILTER_MAC_VNI_PAIR:
1764                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1765                         ETHER_ADDR_LEN);
1766                 ucast->vni = conf->tenant_id;
1767         break;
1768         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1769                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1770                         ETHER_ADDR_LEN);
1771                 ucast->vni = conf->tenant_id;
1772         break;
1773         case ECORE_FILTER_INNER_PAIR:
1774                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1775                         ETHER_ADDR_LEN);
1776                 ucast->vlan = conf->inner_vlan;
1777         break;
1778         default:
1779                 return -EINVAL;
1780         }
1781
1782         return ECORE_SUCCESS;
1783 }
1784
1785 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1786                                   enum rte_filter_op filter_op,
1787                                   const struct rte_eth_tunnel_filter_conf *conf)
1788 {
1789         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1790         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1791         struct ecore_tunn_update_params params;
1792         struct ecore_hwfn *p_hwfn;
1793         enum ecore_filter_ucast_type type;
1794         enum ecore_tunn_clss clss;
1795         struct ecore_filter_ucast ucast;
1796         char str[80];
1797         uint16_t filter_type;
1798         int rc, i;
1799
1800         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1801         /* First determine if the given filter classification is supported */
1802         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1803         if (clss == MAX_ECORE_TUNN_CLSS) {
1804                 DP_ERR(edev, "Wrong filter type\n");
1805                 return -EINVAL;
1806         }
1807         /* Init tunnel ucast params */
1808         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1809         if (rc != ECORE_SUCCESS) {
1810                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1811                                 conf->filter_type);
1812                 return rc;
1813         }
1814         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1815                 str, filter_op, ucast.type);
1816         switch (filter_op) {
1817         case RTE_ETH_FILTER_ADD:
1818                 ucast.opcode = ECORE_FILTER_ADD;
1819
1820                 /* Skip MAC/VLAN if filter is based on VNI */
1821                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1822                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1823                         if (rc == 0) {
1824                                 /* Enable accept anyvlan */
1825                                 qede_config_accept_any_vlan(qdev, true);
1826                         }
1827                 } else {
1828                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1829                         if (rc == 0)
1830                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1831                                                     ECORE_SPQ_MODE_CB, NULL);
1832                 }
1833
1834                 if (rc != ECORE_SUCCESS)
1835                         return rc;
1836
1837                 qdev->vxlan_filter_type = filter_type;
1838
1839                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1840                 qede_set_cmn_tunn_param(&params, clss,
1841                                         (1 << ECORE_MODE_VXLAN_TUNN),
1842                                         (1 << ECORE_MODE_VXLAN_TUNN));
1843                 for_each_hwfn(edev, i) {
1844                         p_hwfn = &edev->hwfns[i];
1845                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1846                                 &params, ECORE_SPQ_MODE_CB, NULL);
1847                         if (rc != ECORE_SUCCESS) {
1848                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1849                                         params.tunn_clss_vxlan);
1850                         }
1851                 }
1852                 qdev->num_tunn_filters++; /* Filter added successfully */
1853         break;
1854         case RTE_ETH_FILTER_DELETE:
1855                 ucast.opcode = ECORE_FILTER_REMOVE;
1856
1857                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1858                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1859                 } else {
1860                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1861                         if (rc == 0)
1862                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1863                                                     ECORE_SPQ_MODE_CB, NULL);
1864                 }
1865                 if (rc != ECORE_SUCCESS)
1866                         return rc;
1867
1868                 qdev->vxlan_filter_type = filter_type;
1869                 qdev->num_tunn_filters--;
1870
1871                 /* Disable VXLAN if VXLAN filters become 0 */
1872                 if (qdev->num_tunn_filters == 0) {
1873                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1874
1875                         /* Use 0 as tunnel mode */
1876                         qede_set_cmn_tunn_param(&params, clss, 0,
1877                                                 (1 << ECORE_MODE_VXLAN_TUNN));
1878                         for_each_hwfn(edev, i) {
1879                                 p_hwfn = &edev->hwfns[i];
1880                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1881                                         &params, ECORE_SPQ_MODE_CB, NULL);
1882                                 if (rc != ECORE_SUCCESS) {
1883                                         DP_ERR(edev,
1884                                                 "Failed to update tunn_clss %u\n",
1885                                                 params.tunn_clss_vxlan);
1886                                         break;
1887                                 }
1888                         }
1889                 }
1890         break;
1891         default:
1892                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1893                 return -EINVAL;
1894         }
1895         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1896
1897         return 0;
1898 }
1899
1900 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1901                          enum rte_filter_type filter_type,
1902                          enum rte_filter_op filter_op,
1903                          void *arg)
1904 {
1905         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1906         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1907         struct rte_eth_tunnel_filter_conf *filter_conf =
1908                         (struct rte_eth_tunnel_filter_conf *)arg;
1909
1910         switch (filter_type) {
1911         case RTE_ETH_FILTER_TUNNEL:
1912                 switch (filter_conf->tunnel_type) {
1913                 case RTE_TUNNEL_TYPE_VXLAN:
1914                         DP_INFO(edev,
1915                                 "Packet steering to the specified Rx queue"
1916                                 " is not supported with VXLAN tunneling");
1917                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1918                                                       filter_conf));
1919                 /* Place holders for future tunneling support */
1920                 case RTE_TUNNEL_TYPE_GENEVE:
1921                 case RTE_TUNNEL_TYPE_TEREDO:
1922                 case RTE_TUNNEL_TYPE_NVGRE:
1923                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1924                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1925                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1926                                 filter_conf->tunnel_type);
1927                         return -EINVAL;
1928                 case RTE_TUNNEL_TYPE_NONE:
1929                 default:
1930                         return 0;
1931                 }
1932                 break;
1933         case RTE_ETH_FILTER_FDIR:
1934         case RTE_ETH_FILTER_MACVLAN:
1935         case RTE_ETH_FILTER_ETHERTYPE:
1936         case RTE_ETH_FILTER_FLEXIBLE:
1937         case RTE_ETH_FILTER_SYN:
1938         case RTE_ETH_FILTER_NTUPLE:
1939         case RTE_ETH_FILTER_HASH:
1940         case RTE_ETH_FILTER_L2_TUNNEL:
1941         case RTE_ETH_FILTER_MAX:
1942         default:
1943                 DP_ERR(edev, "Unsupported filter type %d\n",
1944                         filter_type);
1945                 return -EINVAL;
1946         }
1947
1948         return 0;
1949 }
1950
1951 static const struct eth_dev_ops qede_eth_dev_ops = {
1952         .dev_configure = qede_dev_configure,
1953         .dev_infos_get = qede_dev_info_get,
1954         .rx_queue_setup = qede_rx_queue_setup,
1955         .rx_queue_release = qede_rx_queue_release,
1956         .tx_queue_setup = qede_tx_queue_setup,
1957         .tx_queue_release = qede_tx_queue_release,
1958         .dev_start = qede_dev_start,
1959         .dev_set_link_up = qede_dev_set_link_up,
1960         .dev_set_link_down = qede_dev_set_link_down,
1961         .link_update = qede_link_update,
1962         .promiscuous_enable = qede_promiscuous_enable,
1963         .promiscuous_disable = qede_promiscuous_disable,
1964         .allmulticast_enable = qede_allmulticast_enable,
1965         .allmulticast_disable = qede_allmulticast_disable,
1966         .dev_stop = qede_dev_stop,
1967         .dev_close = qede_dev_close,
1968         .stats_get = qede_get_stats,
1969         .stats_reset = qede_reset_stats,
1970         .xstats_get = qede_get_xstats,
1971         .xstats_reset = qede_reset_xstats,
1972         .xstats_get_names = qede_get_xstats_names,
1973         .mac_addr_add = qede_mac_addr_add,
1974         .mac_addr_remove = qede_mac_addr_remove,
1975         .mac_addr_set = qede_mac_addr_set,
1976         .vlan_offload_set = qede_vlan_offload_set,
1977         .vlan_filter_set = qede_vlan_filter_set,
1978         .flow_ctrl_set = qede_flow_ctrl_set,
1979         .flow_ctrl_get = qede_flow_ctrl_get,
1980         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1981         .rss_hash_update = qede_rss_hash_update,
1982         .rss_hash_conf_get = qede_rss_hash_conf_get,
1983         .reta_update  = qede_rss_reta_update,
1984         .reta_query  = qede_rss_reta_query,
1985         .mtu_set = qede_set_mtu,
1986         .filter_ctrl = qede_dev_filter_ctrl,
1987         .udp_tunnel_port_add = qede_udp_dst_port_add,
1988         .udp_tunnel_port_del = qede_udp_dst_port_del,
1989 };
1990
1991 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1992         .dev_configure = qede_dev_configure,
1993         .dev_infos_get = qede_dev_info_get,
1994         .rx_queue_setup = qede_rx_queue_setup,
1995         .rx_queue_release = qede_rx_queue_release,
1996         .tx_queue_setup = qede_tx_queue_setup,
1997         .tx_queue_release = qede_tx_queue_release,
1998         .dev_start = qede_dev_start,
1999         .dev_set_link_up = qede_dev_set_link_up,
2000         .dev_set_link_down = qede_dev_set_link_down,
2001         .link_update = qede_link_update,
2002         .promiscuous_enable = qede_promiscuous_enable,
2003         .promiscuous_disable = qede_promiscuous_disable,
2004         .allmulticast_enable = qede_allmulticast_enable,
2005         .allmulticast_disable = qede_allmulticast_disable,
2006         .dev_stop = qede_dev_stop,
2007         .dev_close = qede_dev_close,
2008         .stats_get = qede_get_stats,
2009         .stats_reset = qede_reset_stats,
2010         .xstats_get = qede_get_xstats,
2011         .xstats_reset = qede_reset_xstats,
2012         .xstats_get_names = qede_get_xstats_names,
2013         .vlan_offload_set = qede_vlan_offload_set,
2014         .vlan_filter_set = qede_vlan_filter_set,
2015         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2016         .rss_hash_update = qede_rss_hash_update,
2017         .rss_hash_conf_get = qede_rss_hash_conf_get,
2018         .reta_update  = qede_rss_reta_update,
2019         .reta_query  = qede_rss_reta_query,
2020         .mtu_set = qede_set_mtu,
2021 };
2022
2023 static void qede_update_pf_params(struct ecore_dev *edev)
2024 {
2025         struct ecore_pf_params pf_params;
2026         /* 32 rx + 32 tx */
2027         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2028         pf_params.eth_pf_params.num_cons = 64;
2029         qed_ops->common->update_pf_params(edev, &pf_params);
2030 }
2031
2032 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2033 {
2034         struct rte_pci_device *pci_dev;
2035         struct rte_pci_addr pci_addr;
2036         struct qede_dev *adapter;
2037         struct ecore_dev *edev;
2038         struct qed_dev_eth_info dev_info;
2039         struct qed_slowpath_params params;
2040         static bool do_once = true;
2041         uint8_t bulletin_change;
2042         uint8_t vf_mac[ETHER_ADDR_LEN];
2043         uint8_t is_mac_forced;
2044         bool is_mac_exist;
2045         /* Fix up ecore debug level */
2046         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2047         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2048         uint32_t max_mac_addrs;
2049         int rc;
2050
2051         /* Extract key data structures */
2052         adapter = eth_dev->data->dev_private;
2053         edev = &adapter->edev;
2054         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2055         pci_addr = pci_dev->addr;
2056
2057         PMD_INIT_FUNC_TRACE(edev);
2058
2059         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2060                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2061                  eth_dev->data->port_id);
2062
2063         eth_dev->rx_pkt_burst = qede_recv_pkts;
2064         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2065
2066         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2067                 DP_NOTICE(edev, false,
2068                           "Skipping device init from secondary process\n");
2069                 return 0;
2070         }
2071
2072         rte_eth_copy_pci_info(eth_dev, pci_dev);
2073
2074         qed_ops = qed_get_eth_ops();
2075         if (!qed_ops) {
2076                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2077                 return -EINVAL;
2078         }
2079
2080         DP_INFO(edev, "Starting qede probe\n");
2081
2082         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2083                                     dp_module, dp_level, is_vf);
2084
2085         if (rc != 0) {
2086                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2087                 return -ENODEV;
2088         }
2089
2090         qede_update_pf_params(edev);
2091
2092         rte_intr_callback_register(&pci_dev->intr_handle,
2093                                    qede_interrupt_handler, (void *)eth_dev);
2094
2095         if (rte_intr_enable(&pci_dev->intr_handle)) {
2096                 DP_ERR(edev, "rte_intr_enable() failed\n");
2097                 return -ENODEV;
2098         }
2099
2100         /* Start the Slowpath-process */
2101         memset(&params, 0, sizeof(struct qed_slowpath_params));
2102         params.int_mode = ECORE_INT_MODE_MSIX;
2103         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2104         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2105         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2106         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2107         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2108                 QEDE_PMD_DRV_VER_STR_SIZE);
2109
2110         /* For CMT mode device do periodic polling for slowpath events.
2111          * This is required since uio device uses only one MSI-x
2112          * interrupt vector but we need one for each engine.
2113          */
2114         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2115                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2116                                        qede_poll_sp_sb_cb,
2117                                        (void *)eth_dev);
2118                 if (rc != 0) {
2119                         DP_ERR(edev, "Unable to start periodic"
2120                                      " timer rc %d\n", rc);
2121                         return -EINVAL;
2122                 }
2123         }
2124
2125         rc = qed_ops->common->slowpath_start(edev, &params);
2126         if (rc) {
2127                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2128                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2129                                      (void *)eth_dev);
2130                 return -ENODEV;
2131         }
2132
2133         rc = qed_ops->fill_dev_info(edev, &dev_info);
2134         if (rc) {
2135                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2136                 qed_ops->common->slowpath_stop(edev);
2137                 qed_ops->common->remove(edev);
2138                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2139                                      (void *)eth_dev);
2140                 return -ENODEV;
2141         }
2142
2143         qede_alloc_etherdev(adapter, &dev_info);
2144
2145         adapter->ops->common->set_id(edev, edev->name, QEDE_PMD_VERSION);
2146
2147         if (!is_vf)
2148                 adapter->dev_info.num_mac_addrs =
2149                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2150                                             ECORE_MAC);
2151         else
2152                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2153                                              &adapter->dev_info.num_mac_addrs);
2154
2155         /* Allocate memory for storing MAC addr */
2156         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2157                                         (ETHER_ADDR_LEN *
2158                                         adapter->dev_info.num_mac_addrs),
2159                                         RTE_CACHE_LINE_SIZE);
2160
2161         if (eth_dev->data->mac_addrs == NULL) {
2162                 DP_ERR(edev, "Failed to allocate MAC address\n");
2163                 qed_ops->common->slowpath_stop(edev);
2164                 qed_ops->common->remove(edev);
2165                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2166                                      (void *)eth_dev);
2167                 return -ENOMEM;
2168         }
2169
2170         if (!is_vf) {
2171                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2172                                 hw_info.hw_mac_addr,
2173                                 &eth_dev->data->mac_addrs[0]);
2174                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2175                                 &adapter->primary_mac);
2176         } else {
2177                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2178                                        &bulletin_change);
2179                 if (bulletin_change) {
2180                         is_mac_exist =
2181                             ecore_vf_bulletin_get_forced_mac(
2182                                                 ECORE_LEADING_HWFN(edev),
2183                                                 vf_mac,
2184                                                 &is_mac_forced);
2185                         if (is_mac_exist && is_mac_forced) {
2186                                 DP_INFO(edev, "VF macaddr received from PF\n");
2187                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2188                                                 &eth_dev->data->mac_addrs[0]);
2189                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2190                                                 &adapter->primary_mac);
2191                         } else {
2192                                 DP_NOTICE(edev, false,
2193                                           "No VF macaddr assigned\n");
2194                         }
2195                 }
2196         }
2197
2198         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2199
2200         if (do_once) {
2201                 qede_print_adapter_info(adapter);
2202                 do_once = false;
2203         }
2204
2205         adapter->state = QEDE_DEV_INIT;
2206
2207         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2208                   adapter->primary_mac.addr_bytes[0],
2209                   adapter->primary_mac.addr_bytes[1],
2210                   adapter->primary_mac.addr_bytes[2],
2211                   adapter->primary_mac.addr_bytes[3],
2212                   adapter->primary_mac.addr_bytes[4],
2213                   adapter->primary_mac.addr_bytes[5]);
2214
2215         return rc;
2216 }
2217
2218 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2219 {
2220         return qede_common_dev_init(eth_dev, 1);
2221 }
2222
2223 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2224 {
2225         return qede_common_dev_init(eth_dev, 0);
2226 }
2227
2228 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2229 {
2230         /* only uninitialize in the primary process */
2231         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2232                 return 0;
2233
2234         /* safe to close dev here */
2235         qede_dev_close(eth_dev);
2236
2237         eth_dev->dev_ops = NULL;
2238         eth_dev->rx_pkt_burst = NULL;
2239         eth_dev->tx_pkt_burst = NULL;
2240
2241         if (eth_dev->data->mac_addrs)
2242                 rte_free(eth_dev->data->mac_addrs);
2243
2244         eth_dev->data->mac_addrs = NULL;
2245
2246         return 0;
2247 }
2248
2249 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2250 {
2251         return qede_dev_common_uninit(eth_dev);
2252 }
2253
2254 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2255 {
2256         return qede_dev_common_uninit(eth_dev);
2257 }
2258
2259 static struct rte_pci_id pci_id_qedevf_map[] = {
2260 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2261         {
2262                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
2263         },
2264         {
2265                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
2266         },
2267         {.vendor_id = 0,}
2268 };
2269
2270 static struct rte_pci_id pci_id_qede_map[] = {
2271 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2272         {
2273                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
2274         },
2275         {
2276                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
2277         },
2278         {
2279                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
2280         },
2281         {
2282                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
2283         },
2284         {
2285                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
2286         },
2287         {.vendor_id = 0,}
2288 };
2289
2290 static struct eth_driver rte_qedevf_pmd = {
2291         .pci_drv = {
2292                     .id_table = pci_id_qedevf_map,
2293                     .drv_flags =
2294                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2295                     .probe = rte_eth_dev_pci_probe,
2296                     .remove = rte_eth_dev_pci_remove,
2297                    },
2298         .eth_dev_init = qedevf_eth_dev_init,
2299         .eth_dev_uninit = qedevf_eth_dev_uninit,
2300         .dev_private_size = sizeof(struct qede_dev),
2301 };
2302
2303 static struct eth_driver rte_qede_pmd = {
2304         .pci_drv = {
2305                     .id_table = pci_id_qede_map,
2306                     .drv_flags =
2307                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2308                     .probe = rte_eth_dev_pci_probe,
2309                     .remove = rte_eth_dev_pci_remove,
2310                    },
2311         .eth_dev_init = qede_eth_dev_init,
2312         .eth_dev_uninit = qede_eth_dev_uninit,
2313         .dev_private_size = sizeof(struct qede_dev),
2314 };
2315
2316 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
2317 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2318 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2319 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
2320 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2321 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");