drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 static int64_t timer_period = 1;
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 503 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 504
 505 /* Activate or deactivate vport via vport-update */
 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 507 {
 508         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 509         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 510         struct ecore_sp_vport_update_params params;
 511         struct ecore_hwfn *p_hwfn;
 512         uint8_t i;
 513         int rc = -1;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         params.vport_id = 0;
 517         params.update_vport_active_rx_flg = 1;
 518         params.update_vport_active_tx_flg = 1;
 519         params.vport_active_rx_flg = flg;
 520         params.vport_active_tx_flg = flg;
 521         if (!qdev->enable_tx_switching) {
 522                 if ((QEDE_NPAR_TX_SWITCHING != NULL) ||
 523                     ((QEDE_VF_TX_SWITCHING != NULL) && IS_VF(edev))) {
 524                         params.update_tx_switching_flg = 1;
 525                         params.tx_switching_flg = !flg;
 526                         DP_INFO(edev, "%s tx-switching is disabled\n",
 527                                 QEDE_NPAR_TX_SWITCHING ? "NPAR" : "VF");
 528                 }
 529         }
 530         for_each_hwfn(edev, i) {
 531                 p_hwfn = &edev->hwfns[i];
 532                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 533                 rc = ecore_sp_vport_update(p_hwfn, &params,
 534                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 535                 if (rc != ECORE_SUCCESS) {
 536                         DP_ERR(edev, "Failed to update vport\n");
 537                         break;
 538                 }
 539         }
 540         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 541
 542         return rc;
 543 }
 544
 545 static void
 546 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 547                            uint16_t mtu, bool enable)
 548 {
 549         /* Enable LRO in split mode */
 550         sge_tpa_params->tpa_ipv4_en_flg = enable;
 551         sge_tpa_params->tpa_ipv6_en_flg = enable;
 552         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 553         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 554         /* set if tpa enable changes */
 555         sge_tpa_params->update_tpa_en_flg = 1;
 556         /* set if tpa parameters should be handled */
 557         sge_tpa_params->update_tpa_param_flg = enable;
 558
 559         sge_tpa_params->max_buffers_per_cqe = 20;
 560         /* Enable TPA in split mode. In this mode each TPA segment
 561          * starts on the new BD, so there is one BD per segment.
 562          */
 563         sge_tpa_params->tpa_pkt_split_flg = 1;
 564         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 565         sge_tpa_params->tpa_gro_consistent_flg = 0;
 566         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 567         sge_tpa_params->tpa_max_size = 0x7FFF;
 568         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 569         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 570 }
 571
 572 /* Enable/disable LRO via vport-update */
 573 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct ecore_sp_vport_update_params params;
 578         struct ecore_sge_tpa_params tpa_params;
 579         struct ecore_hwfn *p_hwfn;
 580         int rc;
 581         int i;
 582
 583         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 584         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 585         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 586         params.vport_id = 0;
 587         params.sge_tpa_params = &tpa_params;
 588         for_each_hwfn(edev, i) {
 589                 p_hwfn = &edev->hwfns[i];
 590                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 591                 rc = ecore_sp_vport_update(p_hwfn, &params,
 592                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 593                 if (rc != ECORE_SUCCESS) {
 594                         DP_ERR(edev, "Failed to update LRO\n");
 595                         return -1;
 596                 }
 597         }
 598         qdev->enable_lro = flg;
 599         eth_dev->data->lro = flg;
 600
 601         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 602
 603         return 0;
 604 }
 605
 606 /* Update MTU via vport-update without doing port restart.
 607  * The vport must be deactivated before calling this API.
 608  */
 609 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 610 {
 611         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 612         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 613         struct ecore_sp_vport_update_params params;
 614         struct ecore_hwfn *p_hwfn;
 615         int rc;
 616         int i;
 617
 618         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 619         params.vport_id = 0;
 620         params.mtu = mtu;
 621         params.vport_id = 0;
 622         for_each_hwfn(edev, i) {
 623                 p_hwfn = &edev->hwfns[i];
 624                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 625                 rc = ecore_sp_vport_update(p_hwfn, &params,
 626                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 627                 if (rc != ECORE_SUCCESS) {
 628                         DP_ERR(edev, "Failed to update MTU\n");
 629                         return -1;
 630                 }
 631         }
 632         DP_INFO(edev, "MTU updated to %u\n", mtu);
 633
 634         return 0;
 635 }
 636
 637 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 638 {
 639         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 640         ucast->is_rx_filter = true;
 641         ucast->is_tx_filter = true;
 642         /* ucast->assert_on_error = true; - For debug */
 643 }
 644
 645 static int
 646 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 647                              enum qed_filter_rx_mode_type type)
 648 {
 649         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 650         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 651         struct ecore_filter_accept_flags flags;
 652
 653         memset(&flags, 0, sizeof(flags));
 654
 655         flags.update_rx_mode_config = 1;
 656         flags.update_tx_mode_config = 1;
 657         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 658                 ECORE_ACCEPT_MCAST_MATCHED |
 659                 ECORE_ACCEPT_BCAST;
 660
 661         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 662                 ECORE_ACCEPT_MCAST_MATCHED |
 663                 ECORE_ACCEPT_BCAST;
 664
 665         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 666                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 667                 if (IS_VF(edev)) {
 668                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 669                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 670                 }
 671         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 672                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 673         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 674                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 675                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 676                         ECORE_ACCEPT_MCAST_UNMATCHED;
 677         }
 678
 679         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 680                         ECORE_SPQ_MODE_CB, NULL);
 681 }
 682
 683 static int
 684 qede_tunnel_update(struct qede_dev *qdev,
 685                    struct ecore_tunnel_info *tunn_info)
 686 {
 687         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 688         enum _ecore_status_t rc = ECORE_INVAL;
 689         struct ecore_hwfn *p_hwfn;
 690         struct ecore_ptt *p_ptt;
 691         int i;
 692
 693         for_each_hwfn(edev, i) {
 694                 p_hwfn = &edev->hwfns[i];
 695                 if (IS_PF(edev)) {
 696                         p_ptt = ecore_ptt_acquire(p_hwfn);
 697                         if (!p_ptt) {
 698                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 699                                 return -EAGAIN;
 700                         }
 701                 } else {
 702                         p_ptt = NULL;
 703                 }
 704
 705                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 706                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 707                 if (IS_PF(edev))
 708                         ecore_ptt_release(p_hwfn, p_ptt);
 709
 710                 if (rc != ECORE_SUCCESS)
 711                         break;
 712         }
 713
 714         return rc;
 715 }
 716
 717 static int
 718 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 719                   bool enable)
 720 {
 721         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 722         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 723         enum _ecore_status_t rc = ECORE_INVAL;
 724         struct ecore_tunnel_info tunn;
 725
 726         if (qdev->vxlan.enable == enable)
 727                 return ECORE_SUCCESS;
 728
 729         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 730         tunn.vxlan.b_update_mode = true;
 731         tunn.vxlan.b_mode_enabled = enable;
 732         tunn.b_update_rx_cls = true;
 733         tunn.b_update_tx_cls = true;
 734         tunn.vxlan.tun_cls = clss;
 735
 736         tunn.vxlan_port.b_update_port = true;
 737         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 738
 739         rc = qede_tunnel_update(qdev, &tunn);
 740         if (rc == ECORE_SUCCESS) {
 741                 qdev->vxlan.enable = enable;
 742                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 743                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 744                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 745         } else {
 746                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 747                        tunn.vxlan.tun_cls);
 748         }
 749
 750         return rc;
 751 }
 752
 753 static int
 754 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 755                   bool enable)
 756 {
 757         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 758         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 759         enum _ecore_status_t rc = ECORE_INVAL;
 760         struct ecore_tunnel_info tunn;
 761
 762         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 763         tunn.l2_geneve.b_update_mode = true;
 764         tunn.l2_geneve.b_mode_enabled = enable;
 765         tunn.ip_geneve.b_update_mode = true;
 766         tunn.ip_geneve.b_mode_enabled = enable;
 767         tunn.l2_geneve.tun_cls = clss;
 768         tunn.ip_geneve.tun_cls = clss;
 769         tunn.b_update_rx_cls = true;
 770         tunn.b_update_tx_cls = true;
 771
 772         tunn.geneve_port.b_update_port = true;
 773         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 774
 775         rc = qede_tunnel_update(qdev, &tunn);
 776         if (rc == ECORE_SUCCESS) {
 777                 qdev->geneve.enable = enable;
 778                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 779                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 780                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 781         } else {
 782                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 783                        clss);
 784         }
 785
 786         return rc;
 787 }
 788
 789 static int
 790 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 791                   bool enable)
 792 {
 793         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 794         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 795         enum _ecore_status_t rc = ECORE_INVAL;
 796         struct ecore_tunnel_info tunn;
 797
 798         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 799         tunn.ip_gre.b_update_mode = true;
 800         tunn.ip_gre.b_mode_enabled = enable;
 801         tunn.ip_gre.tun_cls = clss;
 802         tunn.ip_gre.tun_cls = clss;
 803         tunn.b_update_rx_cls = true;
 804         tunn.b_update_tx_cls = true;
 805
 806         rc = qede_tunnel_update(qdev, &tunn);
 807         if (rc == ECORE_SUCCESS) {
 808                 qdev->ipgre.enable = enable;
 809                 DP_INFO(edev, "IPGRE is %s\n",
 810                         enable ? "enabled" : "disabled");
 811         } else {
 812                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 813                        clss);
 814         }
 815
 816         return rc;
 817 }
 818
 819 static int
 820 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 821                  enum rte_eth_tunnel_type tunn_type, bool enable)
 822 {
 823         int rc = -EINVAL;
 824
 825         switch (tunn_type) {
 826         case RTE_TUNNEL_TYPE_VXLAN:
 827                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 828                 break;
 829         case RTE_TUNNEL_TYPE_GENEVE:
 830                 rc = qede_geneve_enable(eth_dev, clss, enable);
 831                 break;
 832         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 833                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 834                 break;
 835         default:
 836                 rc = -EINVAL;
 837                 break;
 838         }
 839
 840         return rc;
 841 }
 842
 843 static int
 844 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 845                   bool add)
 846 {
 847         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 848         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 849         struct qede_ucast_entry *tmp = NULL;
 850         struct qede_ucast_entry *u;
 851         struct ether_addr *mac_addr;
 852
 853         mac_addr  = (struct ether_addr *)ucast->mac;
 854         if (add) {
 855                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 856                         if ((memcmp(mac_addr, &tmp->mac,
 857                                     ETHER_ADDR_LEN) == 0) &&
 858                              ucast->vni == tmp->vni &&
 859                              ucast->vlan == tmp->vlan) {
 860                                 DP_ERR(edev, "Unicast MAC is already added"
 861                                        " with vlan = %u, vni = %u\n",
 862                                        ucast->vlan,  ucast->vni);
 863                                         return -EEXIST;
 864                         }
 865                 }
 866                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 867                                RTE_CACHE_LINE_SIZE);
 868                 if (!u) {
 869                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 870                         return -ENOMEM;
 871                 }
 872                 ether_addr_copy(mac_addr, &u->mac);
 873                 u->vlan = ucast->vlan;
 874                 u->vni = ucast->vni;
 875                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 876                 qdev->num_uc_addr++;
 877         } else {
 878                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 879                         if ((memcmp(mac_addr, &tmp->mac,
 880                                     ETHER_ADDR_LEN) == 0) &&
 881                             ucast->vlan == tmp->vlan      &&
 882                             ucast->vni == tmp->vni)
 883                         break;
 884                 }
 885                 if (tmp == NULL) {
 886                         DP_INFO(edev, "Unicast MAC is not found\n");
 887                         return -EINVAL;
 888                 }
 889                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 890                 qdev->num_uc_addr--;
 891         }
 892
 893         return 0;
 894 }
 895
 896 static int
 897 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 898                   bool add)
 899 {
 900         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 901         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 902         struct ether_addr *mac_addr;
 903         struct qede_mcast_entry *tmp = NULL;
 904         struct qede_mcast_entry *m;
 905
 906         mac_addr  = (struct ether_addr *)mcast->mac;
 907         if (add) {
 908                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 909                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 910                                 DP_ERR(edev,
 911                                         "Multicast MAC is already added\n");
 912                                 return -EEXIST;
 913                         }
 914                 }
 915                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 916                         RTE_CACHE_LINE_SIZE);
 917                 if (!m) {
 918                         DP_ERR(edev,
 919                                 "Did not allocate memory for mcast\n");
 920                         return -ENOMEM;
 921                 }
 922                 ether_addr_copy(mac_addr, &m->mac);
 923                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 924                 qdev->num_mc_addr++;
 925         } else {
 926                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 927                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 928                                 break;
 929                 }
 930                 if (tmp == NULL) {
 931                         DP_INFO(edev, "Multicast mac is not found\n");
 932                         return -EINVAL;
 933                 }
 934                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 935                              qede_mcast_entry, list);
 936                 qdev->num_mc_addr--;
 937         }
 938
 939         return 0;
 940 }
 941
 942 static enum _ecore_status_t
 943 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 944                  bool add)
 945 {
 946         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 947         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 948         enum _ecore_status_t rc;
 949         struct ecore_filter_mcast mcast;
 950         struct qede_mcast_entry *tmp;
 951         uint16_t j = 0;
 952
 953         /* Multicast */
 954         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 955                 if (add) {
 956                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 957                                 DP_ERR(edev,
 958                                        "Mcast filter table limit exceeded, "
 959                                        "Please enable mcast promisc mode\n");
 960                                 return -ECORE_INVAL;
 961                         }
 962                 }
 963                 rc = qede_mcast_filter(eth_dev, ucast, add);
 964                 if (rc == 0) {
 965                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 966                         memset(&mcast, 0, sizeof(mcast));
 967                         mcast.num_mc_addrs = qdev->num_mc_addr;
 968                         mcast.opcode = ECORE_FILTER_ADD;
 969                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 970                                 ether_addr_copy(&tmp->mac,
 971                                         (struct ether_addr *)&mcast.mac[j]);
 972                                 j++;
 973                         }
 974                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 975                                                     ECORE_SPQ_MODE_CB, NULL);
 976                 }
 977                 if (rc != ECORE_SUCCESS) {
 978                         DP_ERR(edev, "Failed to add multicast filter"
 979                                " rc = %d, op = %d\n", rc, add);
 980                 }
 981         } else { /* Unicast */
 982                 if (add) {
 983                         if (qdev->num_uc_addr >=
 984                             qdev->dev_info.num_mac_filters) {
 985                                 DP_ERR(edev,
 986                                        "Ucast filter table limit exceeded,"
 987                                        " Please enable promisc mode\n");
 988                                 return -ECORE_INVAL;
 989                         }
 990                 }
 991                 rc = qede_ucast_filter(eth_dev, ucast, add);
 992                 if (rc == 0)
 993                         rc = ecore_filter_ucast_cmd(edev, ucast,
 994                                                     ECORE_SPQ_MODE_CB, NULL);
 995                 if (rc != ECORE_SUCCESS) {
 996                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 997                                rc, add);
 998                 }
 999         }
1000
1001         return rc;
1002 }
1003
1004 static int
1005 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
1006                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
1007 {
1008         struct ecore_filter_ucast ucast;
1009         int re;
1010
1011         qede_set_ucast_cmn_params(&ucast);
1012         ucast.type = ECORE_FILTER_MAC;
1013         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
1014         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
1015         return re;
1016 }
1017
1018 static void
1019 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
1020 {
1021         struct qede_dev *qdev = eth_dev->data->dev_private;
1022         struct ecore_dev *edev = &qdev->edev;
1023         struct ecore_filter_ucast ucast;
1024
1025         PMD_INIT_FUNC_TRACE(edev);
1026
1027         if (index >= qdev->dev_info.num_mac_filters) {
1028                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1029                        index, qdev->dev_info.num_mac_filters);
1030                 return;
1031         }
1032
1033         qede_set_ucast_cmn_params(&ucast);
1034         ucast.opcode = ECORE_FILTER_REMOVE;
1035         ucast.type = ECORE_FILTER_MAC;
1036
1037         /* Use the index maintained by rte */
1038         ether_addr_copy(&eth_dev->data->mac_addrs[index],
1039                         (struct ether_addr *)&ucast.mac);
1040
1041         qede_mac_int_ops(eth_dev, &ucast, false);
1042 }
1043
1044 static void
1045 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1046 {
1047         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1048         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1049
1050         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1051                                                mac_addr->addr_bytes)) {
1052                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1053                 ether_addr_copy(&qdev->primary_mac,
1054                                 &eth_dev->data->mac_addrs[0]);
1055                 return;
1056         }
1057
1058         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1059 }
1060
1061 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1062 {
1063         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1064         struct ecore_sp_vport_update_params params;
1065         struct ecore_hwfn *p_hwfn;
1066         uint8_t i;
1067         int rc;
1068
1069         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1070         params.vport_id = 0;
1071         params.update_accept_any_vlan_flg = 1;
1072         params.accept_any_vlan = flg;
1073         for_each_hwfn(edev, i) {
1074                 p_hwfn = &edev->hwfns[i];
1075                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1076                 rc = ecore_sp_vport_update(p_hwfn, &params,
1077                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1078                 if (rc != ECORE_SUCCESS) {
1079                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1080                         return;
1081                 }
1082         }
1083
1084         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1085 }
1086
1087 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1088 {
1089         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1090         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1091         struct ecore_sp_vport_update_params params;
1092         struct ecore_hwfn *p_hwfn;
1093         uint8_t i;
1094         int rc;
1095
1096         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1097         params.vport_id = 0;
1098         params.update_inner_vlan_removal_flg = 1;
1099         params.inner_vlan_removal_flg = flg;
1100         for_each_hwfn(edev, i) {
1101                 p_hwfn = &edev->hwfns[i];
1102                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1103                 rc = ecore_sp_vport_update(p_hwfn, &params,
1104                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1105                 if (rc != ECORE_SUCCESS) {
1106                         DP_ERR(edev, "Failed to update vport\n");
1107                         return -1;
1108                 }
1109         }
1110
1111         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1112         return 0;
1113 }
1114
1115 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1116                                 uint16_t vlan_id, int on)
1117 {
1118         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1119         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1120         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1121         struct qede_vlan_entry *tmp = NULL;
1122         struct qede_vlan_entry *vlan;
1123         struct ecore_filter_ucast ucast;
1124         int rc;
1125
1126         if (on) {
1127                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1128                         DP_ERR(edev, "Reached max VLAN filter limit"
1129                                       " enabling accept_any_vlan\n");
1130                         qede_config_accept_any_vlan(qdev, true);
1131                         return 0;
1132                 }
1133
1134                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1135                         if (tmp->vid == vlan_id) {
1136                                 DP_ERR(edev, "VLAN %u already configured\n",
1137                                        vlan_id);
1138                                 return -EEXIST;
1139                         }
1140                 }
1141
1142                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1143                                   RTE_CACHE_LINE_SIZE);
1144
1145                 if (!vlan) {
1146                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1147                         return -ENOMEM;
1148                 }
1149
1150                 qede_set_ucast_cmn_params(&ucast);
1151                 ucast.opcode = ECORE_FILTER_ADD;
1152                 ucast.type = ECORE_FILTER_VLAN;
1153                 ucast.vlan = vlan_id;
1154                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1155                                             NULL);
1156                 if (rc != 0) {
1157                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1158                                rc);
1159                         rte_free(vlan);
1160                 } else {
1161                         vlan->vid = vlan_id;
1162                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1163                         qdev->configured_vlans++;
1164                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1165                                 vlan_id, qdev->configured_vlans);
1166                 }
1167         } else {
1168                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1169                         if (tmp->vid == vlan_id)
1170                                 break;
1171                 }
1172
1173                 if (!tmp) {
1174                         if (qdev->configured_vlans == 0) {
1175                                 DP_INFO(edev,
1176                                         "No VLAN filters configured yet\n");
1177                                 return 0;
1178                         }
1179
1180                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1181                         return -EINVAL;
1182                 }
1183
1184                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1185
1186                 qede_set_ucast_cmn_params(&ucast);
1187                 ucast.opcode = ECORE_FILTER_REMOVE;
1188                 ucast.type = ECORE_FILTER_VLAN;
1189                 ucast.vlan = vlan_id;
1190                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1191                                             NULL);
1192                 if (rc != 0) {
1193                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1194                                vlan_id, rc);
1195                 } else {
1196                         qdev->configured_vlans--;
1197                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1198                                 vlan_id, qdev->configured_vlans);
1199                 }
1200         }
1201
1202         return rc;
1203 }
1204
1205 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1206 {
1207         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1208         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1209         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1210
1211         if (mask & ETH_VLAN_STRIP_MASK) {
1212                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1213                         (void)qede_vlan_stripping(eth_dev, 1);
1214                 else
1215                         (void)qede_vlan_stripping(eth_dev, 0);
1216         }
1217
1218         if (mask & ETH_VLAN_FILTER_MASK) {
1219                 /* VLAN filtering kicks in when a VLAN is added */
1220                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1221                         qede_vlan_filter_set(eth_dev, 0, 1);
1222                 } else {
1223                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1224                                 DP_ERR(edev,
1225                                   " Please remove existing VLAN filters"
1226                                   " before disabling VLAN filtering\n");
1227                                 /* Signal app that VLAN filtering is still
1228                                  * enabled
1229                                  */
1230                                 eth_dev->data->dev_conf.rxmode.offloads |=
1231                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1232                         } else {
1233                                 qede_vlan_filter_set(eth_dev, 0, 0);
1234                         }
1235                 }
1236         }
1237
1238         if (mask & ETH_VLAN_EXTEND_MASK)
1239                 DP_ERR(edev, "Extend VLAN not supported\n");
1240
1241         qdev->vlan_offload_mask = mask;
1242
1243         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1244
1245         return 0;
1246 }
1247
1248 static void qede_prandom_bytes(uint32_t *buff)
1249 {
1250         uint8_t i;
1251
1252         srand((unsigned int)time(NULL));
1253         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1254                 buff[i] = rand();
1255 }
1256
1257 int qede_config_rss(struct rte_eth_dev *eth_dev)
1258 {
1259         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1260         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1261         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1262         struct rte_eth_rss_reta_entry64 reta_conf[2];
1263         struct rte_eth_rss_conf rss_conf;
1264         uint32_t i, id, pos, q;
1265
1266         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1267         if (!rss_conf.rss_key) {
1268                 DP_INFO(edev, "Applying driver default key\n");
1269                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1270                 qede_prandom_bytes(&def_rss_key[0]);
1271                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1272         }
1273
1274         /* Configure RSS hash */
1275         if (qede_rss_hash_update(eth_dev, &rss_conf))
1276                 return -EINVAL;
1277
1278         /* Configure default RETA */
1279         memset(reta_conf, 0, sizeof(reta_conf));
1280         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1281                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1282
1283         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1284                 id = i / RTE_RETA_GROUP_SIZE;
1285                 pos = i % RTE_RETA_GROUP_SIZE;
1286                 q = i % QEDE_RSS_COUNT(qdev);
1287                 reta_conf[id].reta[pos] = q;
1288         }
1289         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1290                                  ECORE_RSS_IND_TABLE_SIZE))
1291                 return -EINVAL;
1292
1293         return 0;
1294 }
1295
1296 static void qede_fastpath_start(struct ecore_dev *edev)
1297 {
1298         struct ecore_hwfn *p_hwfn;
1299         int i;
1300
1301         for_each_hwfn(edev, i) {
1302                 p_hwfn = &edev->hwfns[i];
1303                 ecore_hw_start_fastpath(p_hwfn);
1304         }
1305 }
1306
1307 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1308 {
1309         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1310         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1311         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1312
1313         PMD_INIT_FUNC_TRACE(edev);
1314
1315         /* Configure TPA parameters */
1316         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1317                 if (qede_enable_tpa(eth_dev, true))
1318                         return -EINVAL;
1319                 /* Enable scatter mode for LRO */
1320                 if (!eth_dev->data->scattered_rx)
1321                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1322         }
1323
1324         /* Start queues */
1325         if (qede_start_queues(eth_dev))
1326                 goto err;
1327
1328         if (IS_PF(edev))
1329                 qede_reset_queue_stats(qdev, true);
1330
1331         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1332          * enabling RSS. Hence RSS configuration is deferred upto this point.
1333          * Also, we would like to retain similar behavior in PF case, so we
1334          * don't do PF/VF specific check here.
1335          */
1336         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1337                 if (qede_config_rss(eth_dev))
1338                         goto err;
1339
1340         /* Enable vport*/
1341         if (qede_activate_vport(eth_dev, true))
1342                 goto err;
1343
1344         /* Update link status */
1345         qede_link_update(eth_dev, 0);
1346
1347         /* Start/resume traffic */
1348         qede_fastpath_start(edev);
1349
1350         DP_INFO(edev, "Device started\n");
1351
1352         return 0;
1353 err:
1354         DP_ERR(edev, "Device start fails\n");
1355         return -1; /* common error code is < 0 */
1356 }
1357
1358 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1359 {
1360         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1361         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1362
1363         PMD_INIT_FUNC_TRACE(edev);
1364
1365         /* Disable vport */
1366         if (qede_activate_vport(eth_dev, false))
1367                 return;
1368
1369         if (qdev->enable_lro)
1370                 qede_enable_tpa(eth_dev, false);
1371
1372         /* Stop queues */
1373         qede_stop_queues(eth_dev);
1374
1375         /* Disable traffic */
1376         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1377
1378         if (IS_PF(edev))
1379                 qede_mac_addr_remove(eth_dev, 0);
1380
1381         DP_INFO(edev, "Device is stopped\n");
1382 }
1383
1384 const char *valid_args[] = {
1385         QEDE_NPAR_TX_SWITCHING,
1386         QEDE_VF_TX_SWITCHING,
1387         NULL,
1388 };
1389
1390 static int qede_args_check(const char *key, const char *val, void *opaque)
1391 {
1392         unsigned long tmp;
1393         int ret = 0;
1394         struct rte_eth_dev *eth_dev = opaque;
1395         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1396         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1397
1398         errno = 0;
1399         tmp = strtoul(val, NULL, 0);
1400         if (errno) {
1401                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1402                 return errno;
1403         }
1404
1405         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1406             (strcmp(QEDE_VF_TX_SWITCHING, key) == 0))
1407                 qdev->enable_tx_switching = !!tmp;
1408
1409         return ret;
1410 }
1411
1412 static int qede_args(struct rte_eth_dev *eth_dev)
1413 {
1414         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1415         struct rte_kvargs *kvlist;
1416         struct rte_devargs *devargs;
1417         int ret;
1418         int i;
1419
1420         devargs = pci_dev->device.devargs;
1421         if (!devargs)
1422                 return 0; /* return success */
1423
1424         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1425         if (kvlist == NULL)
1426                 return -EINVAL;
1427
1428          /* Process parameters. */
1429         for (i = 0; (valid_args[i] != NULL); ++i) {
1430                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1431                         ret = rte_kvargs_process(kvlist, valid_args[i],
1432                                                  qede_args_check, eth_dev);
1433                         if (ret != ECORE_SUCCESS) {
1434                                 rte_kvargs_free(kvlist);
1435                                 return ret;
1436                         }
1437                 }
1438         }
1439         rte_kvargs_free(kvlist);
1440
1441         return 0;
1442 }
1443
1444 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1445 {
1446         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1447         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1448         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1449         int ret;
1450
1451         PMD_INIT_FUNC_TRACE(edev);
1452
1453         /* Check requirements for 100G mode */
1454         if (ECORE_IS_CMT(edev)) {
1455                 if (eth_dev->data->nb_rx_queues < 2 ||
1456                     eth_dev->data->nb_tx_queues < 2) {
1457                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1458                         return -EINVAL;
1459                 }
1460
1461                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1462                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1463                         DP_ERR(edev,
1464                                "100G mode needs even no. of RX/TX queues\n");
1465                         return -EINVAL;
1466                 }
1467         }
1468
1469         /* We need to have min 1 RX queue.There is no min check in
1470          * rte_eth_dev_configure(), so we are checking it here.
1471          */
1472         if (eth_dev->data->nb_rx_queues == 0) {
1473                 DP_ERR(edev, "Minimum one RX queue is required\n");
1474                 return -EINVAL;
1475         }
1476
1477         /* Enable Tx switching by default */
1478         qdev->enable_tx_switching = 1;
1479
1480         /* Parse devargs and fix up rxmode */
1481         if (qede_args(eth_dev))
1482                 return -ENOTSUP;
1483
1484         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1485               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1486                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1487                 return -ENOTSUP;
1488         }
1489         /* Flow director mode check */
1490         if (qede_check_fdir_support(eth_dev))
1491                 return -ENOTSUP;
1492
1493         qede_dealloc_fp_resc(eth_dev);
1494         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1495         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1496         if (qede_alloc_fp_resc(qdev))
1497                 return -ENOMEM;
1498
1499         /* If jumbo enabled adjust MTU */
1500         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1501                 eth_dev->data->mtu =
1502                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1503                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1504
1505         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1506                 eth_dev->data->scattered_rx = 1;
1507
1508         if (qede_start_vport(qdev, eth_dev->data->mtu))
1509                 return -1;
1510
1511         qdev->mtu = eth_dev->data->mtu;
1512
1513         /* Enable VLAN offloads by default */
1514         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1515                                              ETH_VLAN_FILTER_MASK |
1516                                              ETH_VLAN_EXTEND_MASK);
1517         if (ret)
1518                 return ret;
1519
1520         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1521                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1522
1523         return 0;
1524 }
1525
1526 /* Info about HW descriptor ring limitations */
1527 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1528         .nb_max = 0x8000, /* 32K */
1529         .nb_min = 128,
1530         .nb_align = 128 /* lowest common multiple */
1531 };
1532
1533 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1534         .nb_max = 0x8000, /* 32K */
1535         .nb_min = 256,
1536         .nb_align = 256,
1537         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1538         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1539 };
1540
1541 static void
1542 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1543                   struct rte_eth_dev_info *dev_info)
1544 {
1545         struct qede_dev *qdev = eth_dev->data->dev_private;
1546         struct ecore_dev *edev = &qdev->edev;
1547         struct qed_link_output link;
1548         uint32_t speed_cap = 0;
1549
1550         PMD_INIT_FUNC_TRACE(edev);
1551
1552         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1553         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1554         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1555         dev_info->rx_desc_lim = qede_rx_desc_lim;
1556         dev_info->tx_desc_lim = qede_tx_desc_lim;
1557
1558         if (IS_PF(edev))
1559                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1560                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1561         else
1562                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1563                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1564         dev_info->max_tx_queues = dev_info->max_rx_queues;
1565
1566         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1567         dev_info->max_vfs = 0;
1568         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1569         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1570         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1571         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1572                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1573                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1574                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1575                                      DEV_RX_OFFLOAD_TCP_LRO     |
1576                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1577                                      DEV_RX_OFFLOAD_SCATTER     |
1578                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1579                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1580                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1581         dev_info->rx_queue_offload_capa = 0;
1582
1583         /* TX offloads are on a per-packet basis, so it is applicable
1584          * to both at port and queue levels.
1585          */
1586         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1587                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1588                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1589                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1590                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1591                                      DEV_TX_OFFLOAD_QINQ_INSERT |
1592                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1593                                      DEV_TX_OFFLOAD_TCP_TSO     |
1594                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1595                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1596         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1597
1598         dev_info->default_txconf = (struct rte_eth_txconf) {
1599                 .txq_flags = DEV_TX_OFFLOAD_MULTI_SEGS,
1600         };
1601
1602         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1603                 /* Packets are always dropped if no descriptors are available */
1604                 .rx_drop_en = 1,
1605                 /* The below RX offloads are always enabled */
1606                 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP  |
1607                              DEV_RX_OFFLOAD_IPV4_CKSUM |
1608                              DEV_RX_OFFLOAD_TCP_CKSUM  |
1609                              DEV_RX_OFFLOAD_UDP_CKSUM),
1610         };
1611
1612         memset(&link, 0, sizeof(struct qed_link_output));
1613         qdev->ops->common->get_link(edev, &link);
1614         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1615                 speed_cap |= ETH_LINK_SPEED_1G;
1616         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1617                 speed_cap |= ETH_LINK_SPEED_10G;
1618         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1619                 speed_cap |= ETH_LINK_SPEED_25G;
1620         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1621                 speed_cap |= ETH_LINK_SPEED_40G;
1622         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1623                 speed_cap |= ETH_LINK_SPEED_50G;
1624         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1625                 speed_cap |= ETH_LINK_SPEED_100G;
1626         dev_info->speed_capa = speed_cap;
1627 }
1628
1629 /* return 0 means link status changed, -1 means not changed */
1630 int
1631 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1632 {
1633         struct qede_dev *qdev = eth_dev->data->dev_private;
1634         struct ecore_dev *edev = &qdev->edev;
1635         uint16_t link_duplex;
1636         struct qed_link_output link;
1637         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1638
1639         memset(&link, 0, sizeof(struct qed_link_output));
1640         qdev->ops->common->get_link(edev, &link);
1641
1642         /* Link Speed */
1643         curr->link_speed = link.speed;
1644
1645         /* Link Mode */
1646         switch (link.duplex) {
1647         case QEDE_DUPLEX_HALF:
1648                 link_duplex = ETH_LINK_HALF_DUPLEX;
1649                 break;
1650         case QEDE_DUPLEX_FULL:
1651                 link_duplex = ETH_LINK_FULL_DUPLEX;
1652                 break;
1653         case QEDE_DUPLEX_UNKNOWN:
1654         default:
1655                 link_duplex = -1;
1656         }
1657         curr->link_duplex = link_duplex;
1658
1659         /* Link Status */
1660         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1661
1662         /* AN */
1663         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1664                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1665
1666         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1667                 curr->link_speed, curr->link_duplex,
1668                 curr->link_autoneg, curr->link_status);
1669
1670         /* return 0 means link status changed, -1 means not changed */
1671         return ((curr->link_status == link.link_up) ? -1 : 0);
1672 }
1673
1674 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1675 {
1676 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1677         struct qede_dev *qdev = eth_dev->data->dev_private;
1678         struct ecore_dev *edev = &qdev->edev;
1679
1680         PMD_INIT_FUNC_TRACE(edev);
1681 #endif
1682
1683         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1684
1685         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1686                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1687
1688         qed_configure_filter_rx_mode(eth_dev, type);
1689 }
1690
1691 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1692 {
1693 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1694         struct qede_dev *qdev = eth_dev->data->dev_private;
1695         struct ecore_dev *edev = &qdev->edev;
1696
1697         PMD_INIT_FUNC_TRACE(edev);
1698 #endif
1699
1700         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1701                 qed_configure_filter_rx_mode(eth_dev,
1702                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1703         else
1704                 qed_configure_filter_rx_mode(eth_dev,
1705                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1706 }
1707
1708 static void qede_poll_sp_sb_cb(void *param)
1709 {
1710         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1711         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1712         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1713         int rc;
1714
1715         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1716         qede_interrupt_action(&edev->hwfns[1]);
1717
1718         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1719                                qede_poll_sp_sb_cb,
1720                                (void *)eth_dev);
1721         if (rc != 0) {
1722                 DP_ERR(edev, "Unable to start periodic"
1723                              " timer rc %d\n", rc);
1724                 assert(false && "Unable to start periodic timer");
1725         }
1726 }
1727
1728 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1729 {
1730         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1731         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1732         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1733
1734         PMD_INIT_FUNC_TRACE(edev);
1735
1736         /* dev_stop() shall cleanup fp resources in hw but without releasing
1737          * dma memories and sw structures so that dev_start() can be called
1738          * by the app without reconfiguration. However, in dev_close() we
1739          * can release all the resources and device can be brought up newly
1740          */
1741         if (eth_dev->data->dev_started)
1742                 qede_dev_stop(eth_dev);
1743
1744         qede_stop_vport(edev);
1745         qdev->vport_started = false;
1746         qede_fdir_dealloc_resc(eth_dev);
1747         qede_dealloc_fp_resc(eth_dev);
1748
1749         eth_dev->data->nb_rx_queues = 0;
1750         eth_dev->data->nb_tx_queues = 0;
1751
1752         /* Bring the link down */
1753         qede_dev_set_link_state(eth_dev, false);
1754         qdev->ops->common->slowpath_stop(edev);
1755         qdev->ops->common->remove(edev);
1756         rte_intr_disable(&pci_dev->intr_handle);
1757         rte_intr_callback_unregister(&pci_dev->intr_handle,
1758                                      qede_interrupt_handler, (void *)eth_dev);
1759         if (ECORE_IS_CMT(edev))
1760                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1761 }
1762
1763 static int
1764 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1765 {
1766         struct qede_dev *qdev = eth_dev->data->dev_private;
1767         struct ecore_dev *edev = &qdev->edev;
1768         struct ecore_eth_stats stats;
1769         unsigned int i = 0, j = 0, qid;
1770         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1771         struct qede_tx_queue *txq;
1772
1773         ecore_get_vport_stats(edev, &stats);
1774
1775         /* RX Stats */
1776         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1777             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1778
1779         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1780             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1781
1782         eth_stats->ierrors = stats.common.rx_crc_errors +
1783             stats.common.rx_align_errors +
1784             stats.common.rx_carrier_errors +
1785             stats.common.rx_oversize_packets +
1786             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1787
1788         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1789
1790         eth_stats->imissed = stats.common.mftag_filter_discards +
1791             stats.common.mac_filter_discards +
1792             stats.common.no_buff_discards +
1793             stats.common.brb_truncates + stats.common.brb_discards;
1794
1795         /* TX stats */
1796         eth_stats->opackets = stats.common.tx_ucast_pkts +
1797             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1798
1799         eth_stats->obytes = stats.common.tx_ucast_bytes +
1800             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1801
1802         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1803
1804         /* Queue stats */
1805         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1806                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1807         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1808                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1809         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1810             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1811                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1812                        "Not all the queue stats will be displayed. Set"
1813                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1814                        " appropriately and retry.\n");
1815
1816         for_each_rss(qid) {
1817                 eth_stats->q_ipackets[i] =
1818                         *(uint64_t *)(
1819                                 ((char *)(qdev->fp_array[qid].rxq)) +
1820                                 offsetof(struct qede_rx_queue,
1821                                 rcv_pkts));
1822                 eth_stats->q_errors[i] =
1823                         *(uint64_t *)(
1824                                 ((char *)(qdev->fp_array[qid].rxq)) +
1825                                 offsetof(struct qede_rx_queue,
1826                                 rx_hw_errors)) +
1827                         *(uint64_t *)(
1828                                 ((char *)(qdev->fp_array[qid].rxq)) +
1829                                 offsetof(struct qede_rx_queue,
1830                                 rx_alloc_errors));
1831                 i++;
1832                 if (i == rxq_stat_cntrs)
1833                         break;
1834         }
1835
1836         for_each_tss(qid) {
1837                 txq = qdev->fp_array[qid].txq;
1838                 eth_stats->q_opackets[j] =
1839                         *((uint64_t *)(uintptr_t)
1840                                 (((uint64_t)(uintptr_t)(txq)) +
1841                                  offsetof(struct qede_tx_queue,
1842                                           xmit_pkts)));
1843                 j++;
1844                 if (j == txq_stat_cntrs)
1845                         break;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static unsigned
1852 qede_get_xstats_count(struct qede_dev *qdev) {
1853         if (ECORE_IS_BB(&qdev->edev))
1854                 return RTE_DIM(qede_xstats_strings) +
1855                        RTE_DIM(qede_bb_xstats_strings) +
1856                        (RTE_DIM(qede_rxq_xstats_strings) *
1857                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1858                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1859         else
1860                 return RTE_DIM(qede_xstats_strings) +
1861                        RTE_DIM(qede_ah_xstats_strings) +
1862                        (RTE_DIM(qede_rxq_xstats_strings) *
1863                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1864                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1865 }
1866
1867 static int
1868 qede_get_xstats_names(struct rte_eth_dev *dev,
1869                       struct rte_eth_xstat_name *xstats_names,
1870                       __rte_unused unsigned int limit)
1871 {
1872         struct qede_dev *qdev = dev->data->dev_private;
1873         struct ecore_dev *edev = &qdev->edev;
1874         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1875         unsigned int i, qid, stat_idx = 0;
1876         unsigned int rxq_stat_cntrs;
1877
1878         if (xstats_names != NULL) {
1879                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1880                         snprintf(xstats_names[stat_idx].name,
1881                                 sizeof(xstats_names[stat_idx].name),
1882                                 "%s",
1883                                 qede_xstats_strings[i].name);
1884                         stat_idx++;
1885                 }
1886
1887                 if (ECORE_IS_BB(edev)) {
1888                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1889                                 snprintf(xstats_names[stat_idx].name,
1890                                         sizeof(xstats_names[stat_idx].name),
1891                                         "%s",
1892                                         qede_bb_xstats_strings[i].name);
1893                                 stat_idx++;
1894                         }
1895                 } else {
1896                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1897                                 snprintf(xstats_names[stat_idx].name,
1898                                         sizeof(xstats_names[stat_idx].name),
1899                                         "%s",
1900                                         qede_ah_xstats_strings[i].name);
1901                                 stat_idx++;
1902                         }
1903                 }
1904
1905                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1906                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1907                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1908                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1909                                 snprintf(xstats_names[stat_idx].name,
1910                                         sizeof(xstats_names[stat_idx].name),
1911                                         "%.4s%d%s",
1912                                         qede_rxq_xstats_strings[i].name, qid,
1913                                         qede_rxq_xstats_strings[i].name + 4);
1914                                 stat_idx++;
1915                         }
1916                 }
1917         }
1918
1919         return stat_cnt;
1920 }
1921
1922 static int
1923 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1924                 unsigned int n)
1925 {
1926         struct qede_dev *qdev = dev->data->dev_private;
1927         struct ecore_dev *edev = &qdev->edev;
1928         struct ecore_eth_stats stats;
1929         const unsigned int num = qede_get_xstats_count(qdev);
1930         unsigned int i, qid, stat_idx = 0;
1931         unsigned int rxq_stat_cntrs;
1932
1933         if (n < num)
1934                 return num;
1935
1936         ecore_get_vport_stats(edev, &stats);
1937
1938         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1939                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1940                                              qede_xstats_strings[i].offset);
1941                 xstats[stat_idx].id = stat_idx;
1942                 stat_idx++;
1943         }
1944
1945         if (ECORE_IS_BB(edev)) {
1946                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1947                         xstats[stat_idx].value =
1948                                         *(uint64_t *)(((char *)&stats) +
1949                                         qede_bb_xstats_strings[i].offset);
1950                         xstats[stat_idx].id = stat_idx;
1951                         stat_idx++;
1952                 }
1953         } else {
1954                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1955                         xstats[stat_idx].value =
1956                                         *(uint64_t *)(((char *)&stats) +
1957                                         qede_ah_xstats_strings[i].offset);
1958                         xstats[stat_idx].id = stat_idx;
1959                         stat_idx++;
1960                 }
1961         }
1962
1963         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1964                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1965         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1966                 for_each_rss(qid) {
1967                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1968                                 xstats[stat_idx].value = *(uint64_t *)(
1969                                         ((char *)(qdev->fp_array[qid].rxq)) +
1970                                          qede_rxq_xstats_strings[i].offset);
1971                                 xstats[stat_idx].id = stat_idx;
1972                                 stat_idx++;
1973                         }
1974                 }
1975         }
1976
1977         return stat_idx;
1978 }
1979
1980 static void
1981 qede_reset_xstats(struct rte_eth_dev *dev)
1982 {
1983         struct qede_dev *qdev = dev->data->dev_private;
1984         struct ecore_dev *edev = &qdev->edev;
1985
1986         ecore_reset_vport_stats(edev);
1987         qede_reset_queue_stats(qdev, true);
1988 }
1989
1990 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1991 {
1992         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1993         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1994         struct qed_link_params link_params;
1995         int rc;
1996
1997         DP_INFO(edev, "setting link state %d\n", link_up);
1998         memset(&link_params, 0, sizeof(link_params));
1999         link_params.link_up = link_up;
2000         rc = qdev->ops->common->set_link(edev, &link_params);
2001         if (rc != ECORE_SUCCESS)
2002                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
2003
2004         return rc;
2005 }
2006
2007 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
2008 {
2009         return qede_dev_set_link_state(eth_dev, true);
2010 }
2011
2012 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2013 {
2014         return qede_dev_set_link_state(eth_dev, false);
2015 }
2016
2017 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2018 {
2019         struct qede_dev *qdev = eth_dev->data->dev_private;
2020         struct ecore_dev *edev = &qdev->edev;
2021
2022         ecore_reset_vport_stats(edev);
2023         qede_reset_queue_stats(qdev, false);
2024 }
2025
2026 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2027 {
2028         enum qed_filter_rx_mode_type type =
2029             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2030
2031         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2032                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2033
2034         qed_configure_filter_rx_mode(eth_dev, type);
2035 }
2036
2037 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2038 {
2039         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2040                 qed_configure_filter_rx_mode(eth_dev,
2041                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2042         else
2043                 qed_configure_filter_rx_mode(eth_dev,
2044                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2045 }
2046
2047 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2048                               struct rte_eth_fc_conf *fc_conf)
2049 {
2050         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2051         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2052         struct qed_link_output current_link;
2053         struct qed_link_params params;
2054
2055         memset(&current_link, 0, sizeof(current_link));
2056         qdev->ops->common->get_link(edev, &current_link);
2057
2058         memset(&params, 0, sizeof(params));
2059         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2060         if (fc_conf->autoneg) {
2061                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2062                         DP_ERR(edev, "Autoneg not supported\n");
2063                         return -EINVAL;
2064                 }
2065                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2066         }
2067
2068         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2069         if (fc_conf->mode == RTE_FC_FULL)
2070                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2071                                         QED_LINK_PAUSE_RX_ENABLE);
2072         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2073                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2074         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2075                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2076
2077         params.link_up = true;
2078         (void)qdev->ops->common->set_link(edev, &params);
2079
2080         return 0;
2081 }
2082
2083 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2084                               struct rte_eth_fc_conf *fc_conf)
2085 {
2086         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2087         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2088         struct qed_link_output current_link;
2089
2090         memset(&current_link, 0, sizeof(current_link));
2091         qdev->ops->common->get_link(edev, &current_link);
2092
2093         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2094                 fc_conf->autoneg = true;
2095
2096         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2097                                          QED_LINK_PAUSE_TX_ENABLE))
2098                 fc_conf->mode = RTE_FC_FULL;
2099         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2100                 fc_conf->mode = RTE_FC_RX_PAUSE;
2101         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2102                 fc_conf->mode = RTE_FC_TX_PAUSE;
2103         else
2104                 fc_conf->mode = RTE_FC_NONE;
2105
2106         return 0;
2107 }
2108
2109 static const uint32_t *
2110 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2111 {
2112         static const uint32_t ptypes[] = {
2113                 RTE_PTYPE_L2_ETHER,
2114                 RTE_PTYPE_L2_ETHER_VLAN,
2115                 RTE_PTYPE_L3_IPV4,
2116                 RTE_PTYPE_L3_IPV6,
2117                 RTE_PTYPE_L4_TCP,
2118                 RTE_PTYPE_L4_UDP,
2119                 RTE_PTYPE_TUNNEL_VXLAN,
2120                 RTE_PTYPE_L4_FRAG,
2121                 RTE_PTYPE_TUNNEL_GENEVE,
2122                 RTE_PTYPE_TUNNEL_GRE,
2123                 /* Inner */
2124                 RTE_PTYPE_INNER_L2_ETHER,
2125                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2126                 RTE_PTYPE_INNER_L3_IPV4,
2127                 RTE_PTYPE_INNER_L3_IPV6,
2128                 RTE_PTYPE_INNER_L4_TCP,
2129                 RTE_PTYPE_INNER_L4_UDP,
2130                 RTE_PTYPE_INNER_L4_FRAG,
2131                 RTE_PTYPE_UNKNOWN
2132         };
2133
2134         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2135                 return ptypes;
2136
2137         return NULL;
2138 }
2139
2140 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2141 {
2142         *rss_caps = 0;
2143         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2144         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2145         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2146         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2147         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2148         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2149         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2150         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2151 }
2152
2153 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2154                          struct rte_eth_rss_conf *rss_conf)
2155 {
2156         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2157         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2158         struct ecore_sp_vport_update_params vport_update_params;
2159         struct ecore_rss_params rss_params;
2160         struct ecore_hwfn *p_hwfn;
2161         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2162         uint64_t hf = rss_conf->rss_hf;
2163         uint8_t len = rss_conf->rss_key_len;
2164         uint8_t idx;
2165         uint8_t i;
2166         int rc;
2167
2168         memset(&vport_update_params, 0, sizeof(vport_update_params));
2169         memset(&rss_params, 0, sizeof(rss_params));
2170
2171         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2172                 (unsigned long)hf, len, key);
2173
2174         if (hf != 0) {
2175                 /* Enabling RSS */
2176                 DP_INFO(edev, "Enabling rss\n");
2177
2178                 /* RSS caps */
2179                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2180                 rss_params.update_rss_capabilities = 1;
2181
2182                 /* RSS hash key */
2183                 if (key) {
2184                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2185                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2186                                 return -EINVAL;
2187                         }
2188                         DP_INFO(edev, "Applying user supplied hash key\n");
2189                         rss_params.update_rss_key = 1;
2190                         memcpy(&rss_params.rss_key, key, len);
2191                 }
2192                 rss_params.rss_enable = 1;
2193         }
2194
2195         rss_params.update_rss_config = 1;
2196         /* tbl_size has to be set with capabilities */
2197         rss_params.rss_table_size_log = 7;
2198         vport_update_params.vport_id = 0;
2199         /* pass the L2 handles instead of qids */
2200         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2201                 idx = qdev->rss_ind_table[i];
2202                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2203         }
2204         vport_update_params.rss_params = &rss_params;
2205
2206         for_each_hwfn(edev, i) {
2207                 p_hwfn = &edev->hwfns[i];
2208                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2209                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2210                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2211                 if (rc) {
2212                         DP_ERR(edev, "vport-update for RSS failed\n");
2213                         return rc;
2214                 }
2215         }
2216         qdev->rss_enable = rss_params.rss_enable;
2217
2218         /* Update local structure for hash query */
2219         qdev->rss_conf.rss_hf = hf;
2220         qdev->rss_conf.rss_key_len = len;
2221         if (qdev->rss_enable) {
2222                 if  (qdev->rss_conf.rss_key == NULL) {
2223                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2224                         if (qdev->rss_conf.rss_key == NULL) {
2225                                 DP_ERR(edev, "No memory to store RSS key\n");
2226                                 return -ENOMEM;
2227                         }
2228                 }
2229                 if (key && len) {
2230                         DP_INFO(edev, "Storing RSS key\n");
2231                         memcpy(qdev->rss_conf.rss_key, key, len);
2232                 }
2233         } else if (!qdev->rss_enable && len == 0) {
2234                 if (qdev->rss_conf.rss_key) {
2235                         free(qdev->rss_conf.rss_key);
2236                         qdev->rss_conf.rss_key = NULL;
2237                         DP_INFO(edev, "Free RSS key\n");
2238                 }
2239         }
2240
2241         return 0;
2242 }
2243
2244 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2245                            struct rte_eth_rss_conf *rss_conf)
2246 {
2247         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2248
2249         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2250         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2251
2252         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2253                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2254                        rss_conf->rss_key_len);
2255         return 0;
2256 }
2257
2258 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2259                                     struct ecore_rss_params *rss)
2260 {
2261         int i, fn;
2262         bool rss_mode = 1; /* enable */
2263         struct ecore_queue_cid *cid;
2264         struct ecore_rss_params *t_rss;
2265
2266         /* In regular scenario, we'd simply need to take input handlers.
2267          * But in CMT, we'd have to split the handlers according to the
2268          * engine they were configured on. We'd then have to understand
2269          * whether RSS is really required, since 2-queues on CMT doesn't
2270          * require RSS.
2271          */
2272
2273         /* CMT should be round-robin */
2274         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2275                 cid = rss->rss_ind_table[i];
2276
2277                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2278                         t_rss = &rss[0];
2279                 else
2280                         t_rss = &rss[1];
2281
2282                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2283         }
2284
2285         t_rss = &rss[1];
2286         t_rss->update_rss_ind_table = 1;
2287         t_rss->rss_table_size_log = 7;
2288         t_rss->update_rss_config = 1;
2289
2290         /* Make sure RSS is actually required */
2291         for_each_hwfn(edev, fn) {
2292                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2293                      i++) {
2294                         if (rss[fn].rss_ind_table[i] !=
2295                             rss[fn].rss_ind_table[0])
2296                                 break;
2297                 }
2298
2299                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2300                         DP_INFO(edev,
2301                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2302                         rss_mode = 0;
2303                         goto out;
2304                 }
2305         }
2306
2307 out:
2308         t_rss->rss_enable = rss_mode;
2309
2310         return rss_mode;
2311 }
2312
2313 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2314                          struct rte_eth_rss_reta_entry64 *reta_conf,
2315                          uint16_t reta_size)
2316 {
2317         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2318         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2319         struct ecore_sp_vport_update_params vport_update_params;
2320         struct ecore_rss_params *params;
2321         struct ecore_hwfn *p_hwfn;
2322         uint16_t i, idx, shift;
2323         uint8_t entry;
2324         int rc = 0;
2325
2326         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2327                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2328                        reta_size);
2329                 return -EINVAL;
2330         }
2331
2332         memset(&vport_update_params, 0, sizeof(vport_update_params));
2333         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2334                              RTE_CACHE_LINE_SIZE);
2335         if (params == NULL) {
2336                 DP_ERR(edev, "failed to allocate memory\n");
2337                 return -ENOMEM;
2338         }
2339
2340         for (i = 0; i < reta_size; i++) {
2341                 idx = i / RTE_RETA_GROUP_SIZE;
2342                 shift = i % RTE_RETA_GROUP_SIZE;
2343                 if (reta_conf[idx].mask & (1ULL << shift)) {
2344                         entry = reta_conf[idx].reta[shift];
2345                         /* Pass rxq handles to ecore */
2346                         params->rss_ind_table[i] =
2347                                         qdev->fp_array[entry].rxq->handle;
2348                         /* Update the local copy for RETA query command */
2349                         qdev->rss_ind_table[i] = entry;
2350                 }
2351         }
2352
2353         params->update_rss_ind_table = 1;
2354         params->rss_table_size_log = 7;
2355         params->update_rss_config = 1;
2356
2357         /* Fix up RETA for CMT mode device */
2358         if (ECORE_IS_CMT(edev))
2359                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2360                                                             params);
2361         vport_update_params.vport_id = 0;
2362         /* Use the current value of rss_enable */
2363         params->rss_enable = qdev->rss_enable;
2364         vport_update_params.rss_params = params;
2365
2366         for_each_hwfn(edev, i) {
2367                 p_hwfn = &edev->hwfns[i];
2368                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2369                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2370                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2371                 if (rc) {
2372                         DP_ERR(edev, "vport-update for RSS failed\n");
2373                         goto out;
2374                 }
2375         }
2376
2377 out:
2378         rte_free(params);
2379         return rc;
2380 }
2381
2382 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2383                                struct rte_eth_rss_reta_entry64 *reta_conf,
2384                                uint16_t reta_size)
2385 {
2386         struct qede_dev *qdev = eth_dev->data->dev_private;
2387         struct ecore_dev *edev = &qdev->edev;
2388         uint16_t i, idx, shift;
2389         uint8_t entry;
2390
2391         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2392                 DP_ERR(edev, "reta_size %d is not supported\n",
2393                        reta_size);
2394                 return -EINVAL;
2395         }
2396
2397         for (i = 0; i < reta_size; i++) {
2398                 idx = i / RTE_RETA_GROUP_SIZE;
2399                 shift = i % RTE_RETA_GROUP_SIZE;
2400                 if (reta_conf[idx].mask & (1ULL << shift)) {
2401                         entry = qdev->rss_ind_table[i];
2402                         reta_conf[idx].reta[shift] = entry;
2403                 }
2404         }
2405
2406         return 0;
2407 }
2408
2409
2410
2411 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2412 {
2413         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2414         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2415         struct rte_eth_dev_info dev_info = {0};
2416         struct qede_fastpath *fp;
2417         uint32_t max_rx_pkt_len;
2418         uint32_t frame_size;
2419         uint16_t rx_buf_size;
2420         uint16_t bufsz;
2421         bool restart = false;
2422         int i;
2423
2424         PMD_INIT_FUNC_TRACE(edev);
2425         qede_dev_info_get(dev, &dev_info);
2426         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2427         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2428         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2429                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2430                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2431                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2432                 return -EINVAL;
2433         }
2434         if (!dev->data->scattered_rx &&
2435             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2436                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2437                         dev->data->min_rx_buf_size);
2438                 return -EINVAL;
2439         }
2440         /* Temporarily replace I/O functions with dummy ones. It cannot
2441          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2442          */
2443         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2444         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2445         if (dev->data->dev_started) {
2446                 dev->data->dev_started = 0;
2447                 qede_dev_stop(dev);
2448                 restart = true;
2449         } else {
2450                 if (IS_PF(edev))
2451                         qede_mac_addr_remove(dev, 0);
2452         }
2453         rte_delay_ms(1000);
2454         qede_start_vport(qdev, mtu); /* Recreate vport */
2455         qdev->mtu = mtu;
2456
2457         /* Fix up RX buf size for all queues of the port */
2458         for_each_rss(i) {
2459                 fp = &qdev->fp_array[i];
2460                 if (fp->rxq != NULL) {
2461                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2462                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2463                         if (dev->data->scattered_rx)
2464                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2465                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2466                         else
2467                                 rx_buf_size = frame_size;
2468                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2469                         fp->rxq->rx_buf_size = rx_buf_size;
2470                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2471                 }
2472         }
2473         if (max_rx_pkt_len > ETHER_MAX_LEN)
2474                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2475         else
2476                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2477
2478         /* Restore config lost due to vport stop */
2479         if (IS_PF(edev))
2480                 qede_mac_addr_set(dev, &qdev->primary_mac);
2481
2482         if (dev->data->promiscuous)
2483                 qede_promiscuous_enable(dev);
2484         else
2485                 qede_promiscuous_disable(dev);
2486
2487         if (dev->data->all_multicast)
2488                 qede_allmulticast_enable(dev);
2489         else
2490                 qede_allmulticast_disable(dev);
2491
2492         qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2493
2494         if (!dev->data->dev_started && restart) {
2495                 qede_dev_start(dev);
2496                 dev->data->dev_started = 1;
2497         }
2498
2499         /* update max frame size */
2500         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2501         /* Reassign back */
2502         dev->rx_pkt_burst = qede_recv_pkts;
2503         dev->tx_pkt_burst = qede_xmit_pkts;
2504
2505         return 0;
2506 }
2507
2508 static int
2509 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2510                       struct rte_eth_udp_tunnel *tunnel_udp)
2511 {
2512         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2513         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2514         struct ecore_tunnel_info tunn; /* @DPDK */
2515         uint16_t udp_port;
2516         int rc;
2517
2518         PMD_INIT_FUNC_TRACE(edev);
2519
2520         memset(&tunn, 0, sizeof(tunn));
2521
2522         switch (tunnel_udp->prot_type) {
2523         case RTE_TUNNEL_TYPE_VXLAN:
2524                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2525                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2526                                 tunnel_udp->udp_port);
2527                         return ECORE_INVAL;
2528                 }
2529                 udp_port = 0;
2530
2531                 tunn.vxlan_port.b_update_port = true;
2532                 tunn.vxlan_port.port = udp_port;
2533
2534                 rc = qede_tunnel_update(qdev, &tunn);
2535                 if (rc != ECORE_SUCCESS) {
2536                         DP_ERR(edev, "Unable to config UDP port %u\n",
2537                                tunn.vxlan_port.port);
2538                         return rc;
2539                 }
2540
2541                 qdev->vxlan.udp_port = udp_port;
2542                 /* If the request is to delete UDP port and if the number of
2543                  * VXLAN filters have reached 0 then VxLAN offload can be be
2544                  * disabled.
2545                  */
2546                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2547                         return qede_vxlan_enable(eth_dev,
2548                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2549
2550                 break;
2551         case RTE_TUNNEL_TYPE_GENEVE:
2552                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2553                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2554                                 tunnel_udp->udp_port);
2555                         return ECORE_INVAL;
2556                 }
2557
2558                 udp_port = 0;
2559
2560                 tunn.geneve_port.b_update_port = true;
2561                 tunn.geneve_port.port = udp_port;
2562
2563                 rc = qede_tunnel_update(qdev, &tunn);
2564                 if (rc != ECORE_SUCCESS) {
2565                         DP_ERR(edev, "Unable to config UDP port %u\n",
2566                                tunn.vxlan_port.port);
2567                         return rc;
2568                 }
2569
2570                 qdev->vxlan.udp_port = udp_port;
2571                 /* If the request is to delete UDP port and if the number of
2572                  * GENEVE filters have reached 0 then GENEVE offload can be be
2573                  * disabled.
2574                  */
2575                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2576                         return qede_geneve_enable(eth_dev,
2577                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2578
2579                 break;
2580
2581         default:
2582                 return ECORE_INVAL;
2583         }
2584
2585         return 0;
2586
2587 }
2588 static int
2589 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2590                       struct rte_eth_udp_tunnel *tunnel_udp)
2591 {
2592         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2593         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2594         struct ecore_tunnel_info tunn; /* @DPDK */
2595         uint16_t udp_port;
2596         int rc;
2597
2598         PMD_INIT_FUNC_TRACE(edev);
2599
2600         memset(&tunn, 0, sizeof(tunn));
2601
2602         switch (tunnel_udp->prot_type) {
2603         case RTE_TUNNEL_TYPE_VXLAN:
2604                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2605                         DP_INFO(edev,
2606                                 "UDP port %u for VXLAN was already configured\n",
2607                                 tunnel_udp->udp_port);
2608                         return ECORE_SUCCESS;
2609                 }
2610
2611                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2612                  * it was not enabled while adding VXLAN filter before UDP port
2613                  * update.
2614                  */
2615                 if (!qdev->vxlan.enable) {
2616                         rc = qede_vxlan_enable(eth_dev,
2617                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2618                         if (rc != ECORE_SUCCESS) {
2619                                 DP_ERR(edev, "Failed to enable VXLAN "
2620                                         "prior to updating UDP port\n");
2621                                 return rc;
2622                         }
2623                 }
2624                 udp_port = tunnel_udp->udp_port;
2625
2626                 tunn.vxlan_port.b_update_port = true;
2627                 tunn.vxlan_port.port = udp_port;
2628
2629                 rc = qede_tunnel_update(qdev, &tunn);
2630                 if (rc != ECORE_SUCCESS) {
2631                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2632                                udp_port);
2633                         return rc;
2634                 }
2635
2636                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2637
2638                 qdev->vxlan.udp_port = udp_port;
2639                 break;
2640         case RTE_TUNNEL_TYPE_GENEVE:
2641                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2642                         DP_INFO(edev,
2643                                 "UDP port %u for GENEVE was already configured\n",
2644                                 tunnel_udp->udp_port);
2645                         return ECORE_SUCCESS;
2646                 }
2647
2648                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2649                  * it was not enabled while adding GENEVE filter before UDP port
2650                  * update.
2651                  */
2652                 if (!qdev->geneve.enable) {
2653                         rc = qede_geneve_enable(eth_dev,
2654                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2655                         if (rc != ECORE_SUCCESS) {
2656                                 DP_ERR(edev, "Failed to enable GENEVE "
2657                                         "prior to updating UDP port\n");
2658                                 return rc;
2659                         }
2660                 }
2661                 udp_port = tunnel_udp->udp_port;
2662
2663                 tunn.geneve_port.b_update_port = true;
2664                 tunn.geneve_port.port = udp_port;
2665
2666                 rc = qede_tunnel_update(qdev, &tunn);
2667                 if (rc != ECORE_SUCCESS) {
2668                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2669                                udp_port);
2670                         return rc;
2671                 }
2672
2673                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2674
2675                 qdev->geneve.udp_port = udp_port;
2676                 break;
2677         default:
2678                 return ECORE_INVAL;
2679         }
2680
2681         return 0;
2682 }
2683
2684 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2685                                        uint32_t *clss, char *str)
2686 {
2687         uint16_t j;
2688         *clss = MAX_ECORE_TUNN_CLSS;
2689
2690         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2691                 if (filter == qede_tunn_types[j].rte_filter_type) {
2692                         *type = qede_tunn_types[j].qede_type;
2693                         *clss = qede_tunn_types[j].qede_tunn_clss;
2694                         strcpy(str, qede_tunn_types[j].string);
2695                         return;
2696                 }
2697         }
2698 }
2699
2700 static int
2701 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2702                               const struct rte_eth_tunnel_filter_conf *conf,
2703                               uint32_t type)
2704 {
2705         /* Init commmon ucast params first */
2706         qede_set_ucast_cmn_params(ucast);
2707
2708         /* Copy out the required fields based on classification type */
2709         ucast->type = type;
2710
2711         switch (type) {
2712         case ECORE_FILTER_VNI:
2713                 ucast->vni = conf->tenant_id;
2714         break;
2715         case ECORE_FILTER_INNER_VLAN:
2716                 ucast->vlan = conf->inner_vlan;
2717         break;
2718         case ECORE_FILTER_MAC:
2719                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2720                        ETHER_ADDR_LEN);
2721         break;
2722         case ECORE_FILTER_INNER_MAC:
2723                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2724                        ETHER_ADDR_LEN);
2725         break;
2726         case ECORE_FILTER_MAC_VNI_PAIR:
2727                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2728                         ETHER_ADDR_LEN);
2729                 ucast->vni = conf->tenant_id;
2730         break;
2731         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2732                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2733                         ETHER_ADDR_LEN);
2734                 ucast->vni = conf->tenant_id;
2735         break;
2736         case ECORE_FILTER_INNER_PAIR:
2737                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2738                         ETHER_ADDR_LEN);
2739                 ucast->vlan = conf->inner_vlan;
2740         break;
2741         default:
2742                 return -EINVAL;
2743         }
2744
2745         return ECORE_SUCCESS;
2746 }
2747
2748 static int
2749 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2750                          const struct rte_eth_tunnel_filter_conf *conf,
2751                          __attribute__((unused)) enum rte_filter_op filter_op,
2752                          enum ecore_tunn_clss *clss,
2753                          bool add)
2754 {
2755         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2756         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2757         struct ecore_filter_ucast ucast = {0};
2758         enum ecore_filter_ucast_type type;
2759         uint16_t filter_type = 0;
2760         char str[80];
2761         int rc;
2762
2763         filter_type = conf->filter_type;
2764         /* Determine if the given filter classification is supported */
2765         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2766         if (*clss == MAX_ECORE_TUNN_CLSS) {
2767                 DP_ERR(edev, "Unsupported filter type\n");
2768                 return -EINVAL;
2769         }
2770         /* Init tunnel ucast params */
2771         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2772         if (rc != ECORE_SUCCESS) {
2773                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2774                 conf->filter_type);
2775                 return rc;
2776         }
2777         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2778                 str, filter_op, ucast.type);
2779
2780         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2781
2782         /* Skip MAC/VLAN if filter is based on VNI */
2783         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2784                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2785                 if ((rc == 0) && add) {
2786                         /* Enable accept anyvlan */
2787                         qede_config_accept_any_vlan(qdev, true);
2788                 }
2789         } else {
2790                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2791                 if (rc == 0)
2792                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2793                                             ECORE_SPQ_MODE_CB, NULL);
2794         }
2795
2796         return rc;
2797 }
2798
2799 static int
2800 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2801                         enum rte_filter_op filter_op,
2802                         const struct rte_eth_tunnel_filter_conf *conf)
2803 {
2804         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2805         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2806         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2807         bool add;
2808         int rc;
2809
2810         PMD_INIT_FUNC_TRACE(edev);
2811
2812         switch (filter_op) {
2813         case RTE_ETH_FILTER_ADD:
2814                 add = true;
2815                 break;
2816         case RTE_ETH_FILTER_DELETE:
2817                 add = false;
2818                 break;
2819         default:
2820                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2821                 return -EINVAL;
2822         }
2823
2824         if (IS_VF(edev))
2825                 return qede_tunn_enable(eth_dev,
2826                                         ECORE_TUNN_CLSS_MAC_VLAN,
2827                                         conf->tunnel_type, add);
2828
2829         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2830         if (rc != ECORE_SUCCESS)
2831                 return rc;
2832
2833         if (add) {
2834                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2835                         qdev->vxlan.num_filters++;
2836                         qdev->vxlan.filter_type = conf->filter_type;
2837                 } else { /* GENEVE */
2838                         qdev->geneve.num_filters++;
2839                         qdev->geneve.filter_type = conf->filter_type;
2840                 }
2841
2842                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2843                     !qdev->ipgre.enable)
2844                         return qede_tunn_enable(eth_dev, clss,
2845                                                 conf->tunnel_type,
2846                                                 true);
2847         } else {
2848                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2849                         qdev->vxlan.num_filters--;
2850                 else /*GENEVE*/
2851                         qdev->geneve.num_filters--;
2852
2853                 /* Disable VXLAN if VXLAN filters become 0 */
2854                 if ((qdev->vxlan.num_filters == 0) ||
2855                     (qdev->geneve.num_filters == 0))
2856                         return qede_tunn_enable(eth_dev, clss,
2857                                                 conf->tunnel_type,
2858                                                 false);
2859         }
2860
2861         return 0;
2862 }
2863
2864 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2865                          enum rte_filter_type filter_type,
2866                          enum rte_filter_op filter_op,
2867                          void *arg)
2868 {
2869         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2870         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2871         struct rte_eth_tunnel_filter_conf *filter_conf =
2872                         (struct rte_eth_tunnel_filter_conf *)arg;
2873
2874         switch (filter_type) {
2875         case RTE_ETH_FILTER_TUNNEL:
2876                 switch (filter_conf->tunnel_type) {
2877                 case RTE_TUNNEL_TYPE_VXLAN:
2878                 case RTE_TUNNEL_TYPE_GENEVE:
2879                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2880                         DP_INFO(edev,
2881                                 "Packet steering to the specified Rx queue"
2882                                 " is not supported with UDP tunneling");
2883                         return(qede_tunn_filter_config(eth_dev, filter_op,
2884                                                       filter_conf));
2885                 case RTE_TUNNEL_TYPE_TEREDO:
2886                 case RTE_TUNNEL_TYPE_NVGRE:
2887                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2888                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2889                                 filter_conf->tunnel_type);
2890                         return -EINVAL;
2891                 case RTE_TUNNEL_TYPE_NONE:
2892                 default:
2893                         return 0;
2894                 }
2895                 break;
2896         case RTE_ETH_FILTER_FDIR:
2897                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2898         case RTE_ETH_FILTER_NTUPLE:
2899                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2900         case RTE_ETH_FILTER_MACVLAN:
2901         case RTE_ETH_FILTER_ETHERTYPE:
2902         case RTE_ETH_FILTER_FLEXIBLE:
2903         case RTE_ETH_FILTER_SYN:
2904         case RTE_ETH_FILTER_HASH:
2905         case RTE_ETH_FILTER_L2_TUNNEL:
2906         case RTE_ETH_FILTER_MAX:
2907         default:
2908                 DP_ERR(edev, "Unsupported filter type %d\n",
2909                         filter_type);
2910                 return -EINVAL;
2911         }
2912
2913         return 0;
2914 }
2915
2916 static const struct eth_dev_ops qede_eth_dev_ops = {
2917         .dev_configure = qede_dev_configure,
2918         .dev_infos_get = qede_dev_info_get,
2919         .rx_queue_setup = qede_rx_queue_setup,
2920         .rx_queue_release = qede_rx_queue_release,
2921         .tx_queue_setup = qede_tx_queue_setup,
2922         .tx_queue_release = qede_tx_queue_release,
2923         .dev_start = qede_dev_start,
2924         .dev_set_link_up = qede_dev_set_link_up,
2925         .dev_set_link_down = qede_dev_set_link_down,
2926         .link_update = qede_link_update,
2927         .promiscuous_enable = qede_promiscuous_enable,
2928         .promiscuous_disable = qede_promiscuous_disable,
2929         .allmulticast_enable = qede_allmulticast_enable,
2930         .allmulticast_disable = qede_allmulticast_disable,
2931         .dev_stop = qede_dev_stop,
2932         .dev_close = qede_dev_close,
2933         .stats_get = qede_get_stats,
2934         .stats_reset = qede_reset_stats,
2935         .xstats_get = qede_get_xstats,
2936         .xstats_reset = qede_reset_xstats,
2937         .xstats_get_names = qede_get_xstats_names,
2938         .mac_addr_add = qede_mac_addr_add,
2939         .mac_addr_remove = qede_mac_addr_remove,
2940         .mac_addr_set = qede_mac_addr_set,
2941         .vlan_offload_set = qede_vlan_offload_set,
2942         .vlan_filter_set = qede_vlan_filter_set,
2943         .flow_ctrl_set = qede_flow_ctrl_set,
2944         .flow_ctrl_get = qede_flow_ctrl_get,
2945         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2946         .rss_hash_update = qede_rss_hash_update,
2947         .rss_hash_conf_get = qede_rss_hash_conf_get,
2948         .reta_update  = qede_rss_reta_update,
2949         .reta_query  = qede_rss_reta_query,
2950         .mtu_set = qede_set_mtu,
2951         .filter_ctrl = qede_dev_filter_ctrl,
2952         .udp_tunnel_port_add = qede_udp_dst_port_add,
2953         .udp_tunnel_port_del = qede_udp_dst_port_del,
2954 };
2955
2956 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2957         .dev_configure = qede_dev_configure,
2958         .dev_infos_get = qede_dev_info_get,
2959         .rx_queue_setup = qede_rx_queue_setup,
2960         .rx_queue_release = qede_rx_queue_release,
2961         .tx_queue_setup = qede_tx_queue_setup,
2962         .tx_queue_release = qede_tx_queue_release,
2963         .dev_start = qede_dev_start,
2964         .dev_set_link_up = qede_dev_set_link_up,
2965         .dev_set_link_down = qede_dev_set_link_down,
2966         .link_update = qede_link_update,
2967         .promiscuous_enable = qede_promiscuous_enable,
2968         .promiscuous_disable = qede_promiscuous_disable,
2969         .allmulticast_enable = qede_allmulticast_enable,
2970         .allmulticast_disable = qede_allmulticast_disable,
2971         .dev_stop = qede_dev_stop,
2972         .dev_close = qede_dev_close,
2973         .stats_get = qede_get_stats,
2974         .stats_reset = qede_reset_stats,
2975         .xstats_get = qede_get_xstats,
2976         .xstats_reset = qede_reset_xstats,
2977         .xstats_get_names = qede_get_xstats_names,
2978         .vlan_offload_set = qede_vlan_offload_set,
2979         .vlan_filter_set = qede_vlan_filter_set,
2980         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2981         .rss_hash_update = qede_rss_hash_update,
2982         .rss_hash_conf_get = qede_rss_hash_conf_get,
2983         .reta_update  = qede_rss_reta_update,
2984         .reta_query  = qede_rss_reta_query,
2985         .mtu_set = qede_set_mtu,
2986         .udp_tunnel_port_add = qede_udp_dst_port_add,
2987         .udp_tunnel_port_del = qede_udp_dst_port_del,
2988 };
2989
2990 static void qede_update_pf_params(struct ecore_dev *edev)
2991 {
2992         struct ecore_pf_params pf_params;
2993
2994         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2995         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2996         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2997         qed_ops->common->update_pf_params(edev, &pf_params);
2998 }
2999
3000 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3001 {
3002         struct rte_pci_device *pci_dev;
3003         struct rte_pci_addr pci_addr;
3004         struct qede_dev *adapter;
3005         struct ecore_dev *edev;
3006         struct qed_dev_eth_info dev_info;
3007         struct qed_slowpath_params params;
3008         static bool do_once = true;
3009         uint8_t bulletin_change;
3010         uint8_t vf_mac[ETHER_ADDR_LEN];
3011         uint8_t is_mac_forced;
3012         bool is_mac_exist;
3013         /* Fix up ecore debug level */
3014         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3015         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3016         int rc;
3017
3018         /* Extract key data structures */
3019         adapter = eth_dev->data->dev_private;
3020         adapter->ethdev = eth_dev;
3021         edev = &adapter->edev;
3022         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3023         pci_addr = pci_dev->addr;
3024
3025         PMD_INIT_FUNC_TRACE(edev);
3026
3027         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3028                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3029                  eth_dev->data->port_id);
3030
3031         eth_dev->rx_pkt_burst = qede_recv_pkts;
3032         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3033         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3034
3035         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3036                 DP_ERR(edev, "Skipping device init from secondary process\n");
3037                 return 0;
3038         }
3039
3040         rte_eth_copy_pci_info(eth_dev, pci_dev);
3041
3042         /* @DPDK */
3043         edev->vendor_id = pci_dev->id.vendor_id;
3044         edev->device_id = pci_dev->id.device_id;
3045
3046         qed_ops = qed_get_eth_ops();
3047         if (!qed_ops) {
3048                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3049                 return -EINVAL;
3050         }
3051
3052         DP_INFO(edev, "Starting qede probe\n");
3053         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3054                                     dp_level, is_vf);
3055         if (rc != 0) {
3056                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3057                 return -ENODEV;
3058         }
3059         qede_update_pf_params(edev);
3060         rte_intr_callback_register(&pci_dev->intr_handle,
3061                                    qede_interrupt_handler, (void *)eth_dev);
3062         if (rte_intr_enable(&pci_dev->intr_handle)) {
3063                 DP_ERR(edev, "rte_intr_enable() failed\n");
3064                 return -ENODEV;
3065         }
3066
3067         /* Start the Slowpath-process */
3068         memset(&params, 0, sizeof(struct qed_slowpath_params));
3069         params.int_mode = ECORE_INT_MODE_MSIX;
3070         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3071         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3072         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3073         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3074         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3075                 QEDE_PMD_DRV_VER_STR_SIZE);
3076
3077         /* For CMT mode device do periodic polling for slowpath events.
3078          * This is required since uio device uses only one MSI-x
3079          * interrupt vector but we need one for each engine.
3080          */
3081         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3082                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3083                                        qede_poll_sp_sb_cb,
3084                                        (void *)eth_dev);
3085                 if (rc != 0) {
3086                         DP_ERR(edev, "Unable to start periodic"
3087                                      " timer rc %d\n", rc);
3088                         return -EINVAL;
3089                 }
3090         }
3091
3092         rc = qed_ops->common->slowpath_start(edev, &params);
3093         if (rc) {
3094                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3095                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3096                                      (void *)eth_dev);
3097                 return -ENODEV;
3098         }
3099
3100         rc = qed_ops->fill_dev_info(edev, &dev_info);
3101         if (rc) {
3102                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3103                 qed_ops->common->slowpath_stop(edev);
3104                 qed_ops->common->remove(edev);
3105                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3106                                      (void *)eth_dev);
3107                 return -ENODEV;
3108         }
3109
3110         qede_alloc_etherdev(adapter, &dev_info);
3111
3112         adapter->ops->common->set_name(edev, edev->name);
3113
3114         if (!is_vf)
3115                 adapter->dev_info.num_mac_filters =
3116                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3117                                             ECORE_MAC);
3118         else
3119                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3120                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3121
3122         /* Allocate memory for storing MAC addr */
3123         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3124                                         (ETHER_ADDR_LEN *
3125                                         adapter->dev_info.num_mac_filters),
3126                                         RTE_CACHE_LINE_SIZE);
3127
3128         if (eth_dev->data->mac_addrs == NULL) {
3129                 DP_ERR(edev, "Failed to allocate MAC address\n");
3130                 qed_ops->common->slowpath_stop(edev);
3131                 qed_ops->common->remove(edev);
3132                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3133                                      (void *)eth_dev);
3134                 return -ENOMEM;
3135         }
3136
3137         if (!is_vf) {
3138                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3139                                 hw_info.hw_mac_addr,
3140                                 &eth_dev->data->mac_addrs[0]);
3141                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3142                                 &adapter->primary_mac);
3143         } else {
3144                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3145                                        &bulletin_change);
3146                 if (bulletin_change) {
3147                         is_mac_exist =
3148                             ecore_vf_bulletin_get_forced_mac(
3149                                                 ECORE_LEADING_HWFN(edev),
3150                                                 vf_mac,
3151                                                 &is_mac_forced);
3152                         if (is_mac_exist && is_mac_forced) {
3153                                 DP_INFO(edev, "VF macaddr received from PF\n");
3154                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3155                                                 &eth_dev->data->mac_addrs[0]);
3156                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3157                                                 &adapter->primary_mac);
3158                         } else {
3159                                 DP_ERR(edev, "No VF macaddr assigned\n");
3160                         }
3161                 }
3162         }
3163
3164         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3165
3166         if (do_once) {
3167                 qede_print_adapter_info(adapter);
3168                 do_once = false;
3169         }
3170
3171         /* Bring-up the link */
3172         qede_dev_set_link_state(eth_dev, true);
3173
3174         adapter->num_tx_queues = 0;
3175         adapter->num_rx_queues = 0;
3176         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3177         SLIST_INIT(&adapter->vlan_list_head);
3178         SLIST_INIT(&adapter->uc_list_head);
3179         adapter->mtu = ETHER_MTU;
3180         adapter->vport_started = false;
3181
3182         /* VF tunnel offloads is enabled by default in PF driver */
3183         adapter->vxlan.num_filters = 0;
3184         adapter->geneve.num_filters = 0;
3185         adapter->ipgre.num_filters = 0;
3186         if (is_vf) {
3187                 adapter->vxlan.enable = true;
3188                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3189                                              ETH_TUNNEL_FILTER_IVLAN;
3190                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3191                 adapter->geneve.enable = true;
3192                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3193                                               ETH_TUNNEL_FILTER_IVLAN;
3194                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3195                 adapter->ipgre.enable = true;
3196                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3197                                              ETH_TUNNEL_FILTER_IVLAN;
3198         } else {
3199                 adapter->vxlan.enable = false;
3200                 adapter->geneve.enable = false;
3201                 adapter->ipgre.enable = false;
3202         }
3203
3204         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3205                 adapter->primary_mac.addr_bytes[0],
3206                 adapter->primary_mac.addr_bytes[1],
3207                 adapter->primary_mac.addr_bytes[2],
3208                 adapter->primary_mac.addr_bytes[3],
3209                 adapter->primary_mac.addr_bytes[4],
3210                 adapter->primary_mac.addr_bytes[5]);
3211
3212         DP_INFO(edev, "Device initialized\n");
3213
3214         return 0;
3215 }
3216
3217 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3218 {
3219         return qede_common_dev_init(eth_dev, 1);
3220 }
3221
3222 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3223 {
3224         return qede_common_dev_init(eth_dev, 0);
3225 }
3226
3227 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3228 {
3229 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3230         struct qede_dev *qdev = eth_dev->data->dev_private;
3231         struct ecore_dev *edev = &qdev->edev;
3232
3233         PMD_INIT_FUNC_TRACE(edev);
3234 #endif
3235
3236         /* only uninitialize in the primary process */
3237         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3238                 return 0;
3239
3240         /* safe to close dev here */
3241         qede_dev_close(eth_dev);
3242
3243         eth_dev->dev_ops = NULL;
3244         eth_dev->rx_pkt_burst = NULL;
3245         eth_dev->tx_pkt_burst = NULL;
3246
3247         if (eth_dev->data->mac_addrs)
3248                 rte_free(eth_dev->data->mac_addrs);
3249
3250         eth_dev->data->mac_addrs = NULL;
3251
3252         return 0;
3253 }
3254
3255 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3256 {
3257         return qede_dev_common_uninit(eth_dev);
3258 }
3259
3260 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3261 {
3262         return qede_dev_common_uninit(eth_dev);
3263 }
3264
3265 static const struct rte_pci_id pci_id_qedevf_map[] = {
3266 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3267         {
3268                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3269         },
3270         {
3271                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3272         },
3273         {
3274                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3275         },
3276         {.vendor_id = 0,}
3277 };
3278
3279 static const struct rte_pci_id pci_id_qede_map[] = {
3280 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3281         {
3282                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3283         },
3284         {
3285                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3286         },
3287         {
3288                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3289         },
3290         {
3291                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3292         },
3293         {
3294                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3295         },
3296         {
3297                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3298         },
3299         {
3300                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3301         },
3302         {
3303                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3304         },
3305         {
3306                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3307         },
3308         {
3309                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3310         },
3311         {.vendor_id = 0,}
3312 };
3313
3314 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3315         struct rte_pci_device *pci_dev)
3316 {
3317         return rte_eth_dev_pci_generic_probe(pci_dev,
3318                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3319 }
3320
3321 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3322 {
3323         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3324 }
3325
3326 static struct rte_pci_driver rte_qedevf_pmd = {
3327         .id_table = pci_id_qedevf_map,
3328         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3329         .probe = qedevf_eth_dev_pci_probe,
3330         .remove = qedevf_eth_dev_pci_remove,
3331 };
3332
3333 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3334         struct rte_pci_device *pci_dev)
3335 {
3336         return rte_eth_dev_pci_generic_probe(pci_dev,
3337                 sizeof(struct qede_dev), qede_eth_dev_init);
3338 }
3339
3340 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3341 {
3342         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3343 }
3344
3345 static struct rte_pci_driver rte_qede_pmd = {
3346         .id_table = pci_id_qede_map,
3347         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3348         .probe = qede_eth_dev_pci_probe,
3349         .remove = qede_eth_dev_pci_remove,
3350 };
3351
3352 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3353 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3354 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3355 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3356 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3357 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3358
3359 RTE_INIT(qede_init_log);
3360 static void
3361 qede_init_log(void)
3362 {
3363         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3364         if (qede_logtype_init >= 0)
3365                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3366         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3367         if (qede_logtype_driver >= 0)
3368                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3369 }