drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes",
 129                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 130         {"rx_multicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 132         {"rx_broadcast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 134         {"rx_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 136         {"rx_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 138         {"rx_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 140
 141         {"tx_unicast_bytes",
 142                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 143         {"tx_multicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 145         {"tx_broadcast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 147         {"tx_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 149         {"tx_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 151         {"tx_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 153
 154         {"rx_64_byte_packets",
 155                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 156         {"rx_65_to_127_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          rx_65_to_127_byte_packets)},
 159         {"rx_128_to_255_byte_packets",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          rx_128_to_255_byte_packets)},
 162         {"rx_256_to_511_byte_packets",
 163                 offsetof(struct ecore_eth_stats_common,
 164                          rx_256_to_511_byte_packets)},
 165         {"rx_512_to_1023_byte_packets",
 166                 offsetof(struct ecore_eth_stats_common,
 167                          rx_512_to_1023_byte_packets)},
 168         {"rx_1024_to_1518_byte_packets",
 169                 offsetof(struct ecore_eth_stats_common,
 170                          rx_1024_to_1518_byte_packets)},
 171         {"tx_64_byte_packets",
 172                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 173         {"tx_65_to_127_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common,
 175                          tx_65_to_127_byte_packets)},
 176         {"tx_128_to_255_byte_packets",
 177                 offsetof(struct ecore_eth_stats_common,
 178                          tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats_common,
 181                          tx_256_to_511_byte_packets)},
 182         {"tx_512_to_1023_byte_packets",
 183                 offsetof(struct ecore_eth_stats_common,
 184                          tx_512_to_1023_byte_packets)},
 185         {"tx_1024_to_1518_byte_packets",
 186                 offsetof(struct ecore_eth_stats_common,
 187                          tx_1024_to_1518_byte_packets)},
 188
 189         {"rx_mac_crtl_frames",
 190                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 191         {"tx_mac_control_frames",
 192                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 193         {"rx_pause_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 195         {"tx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 197         {"rx_priority_flow_control_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 199         {"tx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 201
 202         {"rx_crc_errors",
 203                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 204         {"rx_align_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 206         {"rx_carrier_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 208         {"rx_oversize_packet_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 210         {"rx_jabber_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 212         {"rx_undersize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 214         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 215         {"rx_host_buffer_not_available",
 216                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 217         /* Number of packets discarded because they are bigger than MTU */
 218         {"rx_packet_too_big_discards",
 219                 offsetof(struct ecore_eth_stats_common,
 220                          packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 231         {"tx_error_drop_packets",
 232                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 233
 234         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 235         {"rx_mac_unicast_packets",
 236                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 237         {"rx_mac_multicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 239         {"rx_mac_broadcast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 241         {"rx_mac_frames_ok",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 243         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 244         {"tx_mac_unicast_packets",
 245                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 246         {"tx_mac_multicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 248         {"tx_mac_broadcast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 250
 251         {"lro_coalesced_packets",
 252                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 253         {"lro_coalesced_events",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 255         {"lro_aborts_num",
 256                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 257         {"lro_not_coalesced_packets",
 258                 offsetof(struct ecore_eth_stats_common,
 259                          tpa_not_coalesced_pkts)},
 260         {"lro_coalesced_bytes",
 261                 offsetof(struct ecore_eth_stats_common,
 262                          tpa_coalesced_bytes)},
 263 };
 264
 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 266         {"rx_1519_to_1522_byte_packets",
 267                 offsetof(struct ecore_eth_stats, bb) +
 268                 offsetof(struct ecore_eth_stats_bb,
 269                          rx_1519_to_1522_byte_packets)},
 270         {"rx_1519_to_2047_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_2047_byte_packets)},
 274         {"rx_2048_to_4095_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_2048_to_4095_byte_packets)},
 278         {"rx_4096_to_9216_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_4096_to_9216_byte_packets)},
 282         {"rx_9217_to_16383_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_9217_to_16383_byte_packets)},
 286
 287         {"tx_1519_to_2047_byte_packets",
 288                 offsetof(struct ecore_eth_stats, bb) +
 289                 offsetof(struct ecore_eth_stats_bb,
 290                          tx_1519_to_2047_byte_packets)},
 291         {"tx_2048_to_4095_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_2048_to_4095_byte_packets)},
 295         {"tx_4096_to_9216_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_4096_to_9216_byte_packets)},
 299         {"tx_9217_to_16383_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_9217_to_16383_byte_packets)},
 303
 304         {"tx_lpi_entry_count",
 305                 offsetof(struct ecore_eth_stats, bb) +
 306                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 307         {"tx_total_collisions",
 308                 offsetof(struct ecore_eth_stats, bb) +
 309                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 310 };
 311
 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 313         {"rx_1519_to_max_byte_packets",
 314                 offsetof(struct ecore_eth_stats, ah) +
 315                 offsetof(struct ecore_eth_stats_ah,
 316                          rx_1519_to_max_byte_packets)},
 317         {"tx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          tx_1519_to_max_byte_packets)},
 321 };
 322
 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 324         {"rx_q_segments",
 325                 offsetof(struct qede_rx_queue, rx_segs)},
 326         {"rx_q_hw_errors",
 327                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 328         {"rx_q_allocation_errors",
 329                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 330 };
 331
 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 333 {
 334         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 335 }
 336
 337 static void
 338 qede_interrupt_handler(void *param)
 339 {
 340         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 341         struct qede_dev *qdev = eth_dev->data->dev_private;
 342         struct ecore_dev *edev = &qdev->edev;
 343
 344         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 345         if (rte_intr_enable(eth_dev->intr_handle))
 346                 DP_ERR(edev, "rte_intr_enable failed\n");
 347 }
 348
 349 static void
 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 351 {
 352         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 353         qdev->ops = qed_ops;
 354 }
 355
 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 357 static void qede_print_adapter_info(struct qede_dev *qdev)
 358 {
 359         struct ecore_dev *edev = &qdev->edev;
 360         struct qed_dev_info *info = &qdev->dev_info.common;
 361         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 362         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 363
 364         DP_INFO(edev, "*********************************\n");
 365         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 366         DP_INFO(edev, " Chip details : %s %c%d\n",
 367                   ECORE_IS_BB(edev) ? "BB" : "AH",
 368                   'A' + edev->chip_rev,
 369                   (int)edev->chip_metal);
 370         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 371                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 372         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 373                  ver_str, QEDE_PMD_VERSION);
 374         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 375         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 376
 377         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 378                  "%d.%d.%d.%d",
 379                 (info->mfw_rev >> 24) & 0xff,
 380                 (info->mfw_rev >> 16) & 0xff,
 381                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 382         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 383         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 384         DP_INFO(edev, "*********************************\n");
 385 }
 386 #endif
 387
 388 static int
 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 390 {
 391         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 392         struct ecore_sp_vport_start_params params;
 393         struct ecore_hwfn *p_hwfn;
 394         int rc;
 395         int i;
 396
 397         memset(&params, 0, sizeof(params));
 398         params.vport_id = 0;
 399         params.mtu = mtu;
 400         /* @DPDK - Disable FW placement */
 401         params.zero_placement_offset = 1;
 402         for_each_hwfn(edev, i) {
 403                 p_hwfn = &edev->hwfns[i];
 404                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 405                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 406                 rc = ecore_sp_vport_start(p_hwfn, &params);
 407                 if (rc != ECORE_SUCCESS) {
 408                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 409                         return rc;
 410                 }
 411         }
 412         ecore_reset_vport_stats(edev);
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 static int
 419 qede_stop_vport(struct ecore_dev *edev)
 420 {
 421         struct ecore_hwfn *p_hwfn;
 422         uint8_t vport_id;
 423         int rc;
 424         int i;
 425
 426         vport_id = 0;
 427         for_each_hwfn(edev, i) {
 428                 p_hwfn = &edev->hwfns[i];
 429                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 430                                          vport_id);
 431                 if (rc != ECORE_SUCCESS) {
 432                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 433                         return rc;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Activate or deactivate vport via vport-update */
 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_hwfn *p_hwfn;
 447         uint8_t i;
 448         int rc = -1;
 449
 450         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 451         params.vport_id = 0;
 452         params.update_vport_active_rx_flg = 1;
 453         params.update_vport_active_tx_flg = 1;
 454         params.vport_active_rx_flg = flg;
 455         params.vport_active_tx_flg = flg;
 456 #ifndef RTE_LIBRTE_QEDE_VF_TX_SWITCH
 457         if (IS_VF(edev)) {
 458                 params.update_tx_switching_flg = 1;
 459                 params.tx_switching_flg = !flg;
 460         }
 461 #endif
 462         for_each_hwfn(edev, i) {
 463                 p_hwfn = &edev->hwfns[i];
 464                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 465                 rc = ecore_sp_vport_update(p_hwfn, &params,
 466                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 467                 if (rc != ECORE_SUCCESS) {
 468                         DP_ERR(edev, "Failed to update vport\n");
 469                         break;
 470                 }
 471         }
 472         DP_INFO(edev, "vport %s VF tx-switch %s\n", flg ? "activated" : "deactivated",
 473                         params.tx_switching_flg ? "enabled" : "disabled");
 474         return rc;
 475 }
 476
 477 static void
 478 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 479                            uint16_t mtu, bool enable)
 480 {
 481         /* Enable LRO in split mode */
 482         sge_tpa_params->tpa_ipv4_en_flg = enable;
 483         sge_tpa_params->tpa_ipv6_en_flg = enable;
 484         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 485         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 486         /* set if tpa enable changes */
 487         sge_tpa_params->update_tpa_en_flg = 1;
 488         /* set if tpa parameters should be handled */
 489         sge_tpa_params->update_tpa_param_flg = enable;
 490
 491         sge_tpa_params->max_buffers_per_cqe = 20;
 492         /* Enable TPA in split mode. In this mode each TPA segment
 493          * starts on the new BD, so there is one BD per segment.
 494          */
 495         sge_tpa_params->tpa_pkt_split_flg = 1;
 496         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 497         sge_tpa_params->tpa_gro_consistent_flg = 0;
 498         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 499         sge_tpa_params->tpa_max_size = 0x7FFF;
 500         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 501         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 502 }
 503
 504 /* Enable/disable LRO via vport-update */
 505 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 506 {
 507         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 508         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 509         struct ecore_sp_vport_update_params params;
 510         struct ecore_sge_tpa_params tpa_params;
 511         struct ecore_hwfn *p_hwfn;
 512         int rc;
 513         int i;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 517         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 518         params.vport_id = 0;
 519         params.sge_tpa_params = &tpa_params;
 520         for_each_hwfn(edev, i) {
 521                 p_hwfn = &edev->hwfns[i];
 522                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 523                 rc = ecore_sp_vport_update(p_hwfn, &params,
 524                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 525                 if (rc != ECORE_SUCCESS) {
 526                         DP_ERR(edev, "Failed to update LRO\n");
 527                         return -1;
 528                 }
 529         }
 530         qdev->enable_lro = flg;
 531         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 532
 533         return 0;
 534 }
 535
 536 /* Update MTU via vport-update without doing port restart.
 537  * The vport must be deactivated before calling this API.
 538  */
 539 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 540 {
 541         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 542         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 543         struct ecore_sp_vport_update_params params;
 544         struct ecore_hwfn *p_hwfn;
 545         int rc;
 546         int i;
 547
 548         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 549         params.vport_id = 0;
 550         params.mtu = mtu;
 551         params.vport_id = 0;
 552         for_each_hwfn(edev, i) {
 553                 p_hwfn = &edev->hwfns[i];
 554                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 555                 rc = ecore_sp_vport_update(p_hwfn, &params,
 556                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 557                 if (rc != ECORE_SUCCESS) {
 558                         DP_ERR(edev, "Failed to update MTU\n");
 559                         return -1;
 560                 }
 561         }
 562         DP_INFO(edev, "MTU updated to %u\n", mtu);
 563
 564         return 0;
 565 }
 566
 567 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 568 {
 569         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 570         ucast->is_rx_filter = true;
 571         ucast->is_tx_filter = true;
 572         /* ucast->assert_on_error = true; - For debug */
 573 }
 574
 575 static int
 576 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 577                              enum qed_filter_rx_mode_type type)
 578 {
 579         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 580         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 581         struct ecore_filter_accept_flags flags;
 582
 583         memset(&flags, 0, sizeof(flags));
 584
 585         flags.update_rx_mode_config = 1;
 586         flags.update_tx_mode_config = 1;
 587         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 588                 ECORE_ACCEPT_MCAST_MATCHED |
 589                 ECORE_ACCEPT_BCAST;
 590
 591         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 592                 ECORE_ACCEPT_MCAST_MATCHED |
 593                 ECORE_ACCEPT_BCAST;
 594
 595         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 596                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 597                 if (IS_VF(edev)) {
 598                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 599                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 600                 }
 601         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 602                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 603         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 604                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 605                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 606                         ECORE_ACCEPT_MCAST_UNMATCHED;
 607         }
 608
 609         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 610                         ECORE_SPQ_MODE_CB, NULL);
 611 }
 612
 613 static int
 614 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 615                   bool enable, bool mask)
 616 {
 617         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 618         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 619         enum _ecore_status_t rc = ECORE_INVAL;
 620         struct ecore_ptt *p_ptt;
 621         struct ecore_tunnel_info tunn;
 622         struct ecore_hwfn *p_hwfn;
 623         int i;
 624
 625         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 626         tunn.vxlan.b_update_mode = enable;
 627         tunn.vxlan.b_mode_enabled = mask;
 628         tunn.b_update_rx_cls = true;
 629         tunn.b_update_tx_cls = true;
 630         tunn.vxlan.tun_cls = clss;
 631
 632         for_each_hwfn(edev, i) {
 633                 p_hwfn = &edev->hwfns[i];
 634                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 635                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 636                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
 637                 if (rc != ECORE_SUCCESS) {
 638                         DP_ERR(edev, "Failed to update tunn_clss %u\n",
 639                                         tunn.vxlan.tun_cls);
 640                         break;
 641                 }
 642         }
 643
 644         if (rc == ECORE_SUCCESS) {
 645                 qdev->vxlan.enable = enable;
 646                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 647                 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
 648         }
 649
 650         return rc;
 651 }
 652
 653 static int
 654 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 655                   bool add)
 656 {
 657         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 658         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 659         struct qede_ucast_entry *tmp = NULL;
 660         struct qede_ucast_entry *u;
 661         struct ether_addr *mac_addr;
 662
 663         mac_addr  = (struct ether_addr *)ucast->mac;
 664         if (add) {
 665                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 666                         if ((memcmp(mac_addr, &tmp->mac,
 667                                     ETHER_ADDR_LEN) == 0) &&
 668                              ucast->vni == tmp->vni &&
 669                              ucast->vlan == tmp->vlan) {
 670                                 DP_ERR(edev, "Unicast MAC is already added"
 671                                        " with vlan = %u, vni = %u\n",
 672                                        ucast->vlan,  ucast->vni);
 673                                         return -EEXIST;
 674                         }
 675                 }
 676                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 677                                RTE_CACHE_LINE_SIZE);
 678                 if (!u) {
 679                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 680                         return -ENOMEM;
 681                 }
 682                 ether_addr_copy(mac_addr, &u->mac);
 683                 u->vlan = ucast->vlan;
 684                 u->vni = ucast->vni;
 685                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 686                 qdev->num_uc_addr++;
 687         } else {
 688                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 689                         if ((memcmp(mac_addr, &tmp->mac,
 690                                     ETHER_ADDR_LEN) == 0) &&
 691                             ucast->vlan == tmp->vlan      &&
 692                             ucast->vni == tmp->vni)
 693                         break;
 694                 }
 695                 if (tmp == NULL) {
 696                         DP_INFO(edev, "Unicast MAC is not found\n");
 697                         return -EINVAL;
 698                 }
 699                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 700                 qdev->num_uc_addr--;
 701         }
 702
 703         return 0;
 704 }
 705
 706 static int
 707 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 708                   bool add)
 709 {
 710         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 711         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 712         struct ether_addr *mac_addr;
 713         struct qede_mcast_entry *tmp = NULL;
 714         struct qede_mcast_entry *m;
 715
 716         mac_addr  = (struct ether_addr *)mcast->mac;
 717         if (add) {
 718                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 719                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 720                                 DP_ERR(edev,
 721                                         "Multicast MAC is already added\n");
 722                                 return -EEXIST;
 723                         }
 724                 }
 725                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 726                         RTE_CACHE_LINE_SIZE);
 727                 if (!m) {
 728                         DP_ERR(edev,
 729                                 "Did not allocate memory for mcast\n");
 730                         return -ENOMEM;
 731                 }
 732                 ether_addr_copy(mac_addr, &m->mac);
 733                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 734                 qdev->num_mc_addr++;
 735         } else {
 736                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 737                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 738                                 break;
 739                 }
 740                 if (tmp == NULL) {
 741                         DP_INFO(edev, "Multicast mac is not found\n");
 742                         return -EINVAL;
 743                 }
 744                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 745                              qede_mcast_entry, list);
 746                 qdev->num_mc_addr--;
 747         }
 748
 749         return 0;
 750 }
 751
 752 static enum _ecore_status_t
 753 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 754                  bool add)
 755 {
 756         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 757         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 758         enum _ecore_status_t rc;
 759         struct ecore_filter_mcast mcast;
 760         struct qede_mcast_entry *tmp;
 761         uint16_t j = 0;
 762
 763         /* Multicast */
 764         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 765                 if (add) {
 766                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 767                                 DP_ERR(edev,
 768                                        "Mcast filter table limit exceeded, "
 769                                        "Please enable mcast promisc mode\n");
 770                                 return -ECORE_INVAL;
 771                         }
 772                 }
 773                 rc = qede_mcast_filter(eth_dev, ucast, add);
 774                 if (rc == 0) {
 775                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 776                         memset(&mcast, 0, sizeof(mcast));
 777                         mcast.num_mc_addrs = qdev->num_mc_addr;
 778                         mcast.opcode = ECORE_FILTER_ADD;
 779                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 780                                 ether_addr_copy(&tmp->mac,
 781                                         (struct ether_addr *)&mcast.mac[j]);
 782                                 j++;
 783                         }
 784                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 785                                                     ECORE_SPQ_MODE_CB, NULL);
 786                 }
 787                 if (rc != ECORE_SUCCESS) {
 788                         DP_ERR(edev, "Failed to add multicast filter"
 789                                " rc = %d, op = %d\n", rc, add);
 790                 }
 791         } else { /* Unicast */
 792                 if (add) {
 793                         if (qdev->num_uc_addr >=
 794                             qdev->dev_info.num_mac_filters) {
 795                                 DP_ERR(edev,
 796                                        "Ucast filter table limit exceeded,"
 797                                        " Please enable promisc mode\n");
 798                                 return -ECORE_INVAL;
 799                         }
 800                 }
 801                 rc = qede_ucast_filter(eth_dev, ucast, add);
 802                 if (rc == 0)
 803                         rc = ecore_filter_ucast_cmd(edev, ucast,
 804                                                     ECORE_SPQ_MODE_CB, NULL);
 805                 if (rc != ECORE_SUCCESS) {
 806                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 807                                rc, add);
 808                 }
 809         }
 810
 811         return rc;
 812 }
 813
 814 static int
 815 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 816                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 817 {
 818         struct ecore_filter_ucast ucast;
 819         int re;
 820
 821         qede_set_ucast_cmn_params(&ucast);
 822         ucast.type = ECORE_FILTER_MAC;
 823         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 824         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 825         return re;
 826 }
 827
 828 static void
 829 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 830 {
 831         struct qede_dev *qdev = eth_dev->data->dev_private;
 832         struct ecore_dev *edev = &qdev->edev;
 833         struct ecore_filter_ucast ucast;
 834
 835         PMD_INIT_FUNC_TRACE(edev);
 836
 837         if (index >= qdev->dev_info.num_mac_filters) {
 838                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 839                        index, qdev->dev_info.num_mac_filters);
 840                 return;
 841         }
 842
 843         qede_set_ucast_cmn_params(&ucast);
 844         ucast.opcode = ECORE_FILTER_REMOVE;
 845         ucast.type = ECORE_FILTER_MAC;
 846
 847         /* Use the index maintained by rte */
 848         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 849                         (struct ether_addr *)&ucast.mac);
 850
 851         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 852 }
 853
 854 static void
 855 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 856 {
 857         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 858         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 859
 860         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 861                                                mac_addr->addr_bytes)) {
 862                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 863                 ether_addr_copy(&qdev->primary_mac,
 864                                 &eth_dev->data->mac_addrs[0]);
 865                 return;
 866         }
 867
 868         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 869 }
 870
 871 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 872 {
 873         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 874         struct ecore_sp_vport_update_params params;
 875         struct ecore_hwfn *p_hwfn;
 876         uint8_t i;
 877         int rc;
 878
 879         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 880         params.vport_id = 0;
 881         params.update_accept_any_vlan_flg = 1;
 882         params.accept_any_vlan = flg;
 883         for_each_hwfn(edev, i) {
 884                 p_hwfn = &edev->hwfns[i];
 885                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 886                 rc = ecore_sp_vport_update(p_hwfn, &params,
 887                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 888                 if (rc != ECORE_SUCCESS) {
 889                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 890                         return;
 891                 }
 892         }
 893
 894         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 895 }
 896
 897 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 898 {
 899         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 900         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 901         struct ecore_sp_vport_update_params params;
 902         struct ecore_hwfn *p_hwfn;
 903         uint8_t i;
 904         int rc;
 905
 906         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 907         params.vport_id = 0;
 908         params.update_inner_vlan_removal_flg = 1;
 909         params.inner_vlan_removal_flg = flg;
 910         for_each_hwfn(edev, i) {
 911                 p_hwfn = &edev->hwfns[i];
 912                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 913                 rc = ecore_sp_vport_update(p_hwfn, &params,
 914                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 915                 if (rc != ECORE_SUCCESS) {
 916                         DP_ERR(edev, "Failed to update vport\n");
 917                         return -1;
 918                 }
 919         }
 920
 921         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 922         return 0;
 923 }
 924
 925 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 926                                 uint16_t vlan_id, int on)
 927 {
 928         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 929         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 930         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 931         struct qede_vlan_entry *tmp = NULL;
 932         struct qede_vlan_entry *vlan;
 933         struct ecore_filter_ucast ucast;
 934         int rc;
 935
 936         if (on) {
 937                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 938                         DP_ERR(edev, "Reached max VLAN filter limit"
 939                                       " enabling accept_any_vlan\n");
 940                         qede_config_accept_any_vlan(qdev, true);
 941                         return 0;
 942                 }
 943
 944                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 945                         if (tmp->vid == vlan_id) {
 946                                 DP_ERR(edev, "VLAN %u already configured\n",
 947                                        vlan_id);
 948                                 return -EEXIST;
 949                         }
 950                 }
 951
 952                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 953                                   RTE_CACHE_LINE_SIZE);
 954
 955                 if (!vlan) {
 956                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 957                         return -ENOMEM;
 958                 }
 959
 960                 qede_set_ucast_cmn_params(&ucast);
 961                 ucast.opcode = ECORE_FILTER_ADD;
 962                 ucast.type = ECORE_FILTER_VLAN;
 963                 ucast.vlan = vlan_id;
 964                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 965                                             NULL);
 966                 if (rc != 0) {
 967                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 968                                rc);
 969                         rte_free(vlan);
 970                 } else {
 971                         vlan->vid = vlan_id;
 972                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 973                         qdev->configured_vlans++;
 974                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 975                                 vlan_id, qdev->configured_vlans);
 976                 }
 977         } else {
 978                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 979                         if (tmp->vid == vlan_id)
 980                                 break;
 981                 }
 982
 983                 if (!tmp) {
 984                         if (qdev->configured_vlans == 0) {
 985                                 DP_INFO(edev,
 986                                         "No VLAN filters configured yet\n");
 987                                 return 0;
 988                         }
 989
 990                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 991                         return -EINVAL;
 992                 }
 993
 994                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 995
 996                 qede_set_ucast_cmn_params(&ucast);
 997                 ucast.opcode = ECORE_FILTER_REMOVE;
 998                 ucast.type = ECORE_FILTER_VLAN;
 999                 ucast.vlan = vlan_id;
1000                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1001                                             NULL);
1002                 if (rc != 0) {
1003                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1004                                vlan_id, rc);
1005                 } else {
1006                         qdev->configured_vlans--;
1007                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1008                                 vlan_id, qdev->configured_vlans);
1009                 }
1010         }
1011
1012         return rc;
1013 }
1014
1015 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1016 {
1017         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1018         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1019         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1020
1021         if (mask & ETH_VLAN_STRIP_MASK) {
1022                 if (rxmode->hw_vlan_strip)
1023                         (void)qede_vlan_stripping(eth_dev, 1);
1024                 else
1025                         (void)qede_vlan_stripping(eth_dev, 0);
1026         }
1027
1028         if (mask & ETH_VLAN_FILTER_MASK) {
1029                 /* VLAN filtering kicks in when a VLAN is added */
1030                 if (rxmode->hw_vlan_filter) {
1031                         qede_vlan_filter_set(eth_dev, 0, 1);
1032                 } else {
1033                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1034                                 DP_ERR(edev,
1035                                   " Please remove existing VLAN filters"
1036                                   " before disabling VLAN filtering\n");
1037                                 /* Signal app that VLAN filtering is still
1038                                  * enabled
1039                                  */
1040                                 rxmode->hw_vlan_filter = true;
1041                         } else {
1042                                 qede_vlan_filter_set(eth_dev, 0, 0);
1043                         }
1044                 }
1045         }
1046
1047         if (mask & ETH_VLAN_EXTEND_MASK)
1048                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1049                         " and classification is based on outer tag only\n");
1050
1051         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1052                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1053
1054         return 0;
1055 }
1056
1057 static void qede_prandom_bytes(uint32_t *buff)
1058 {
1059         uint8_t i;
1060
1061         srand((unsigned int)time(NULL));
1062         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1063                 buff[i] = rand();
1064 }
1065
1066 int qede_config_rss(struct rte_eth_dev *eth_dev)
1067 {
1068         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1069 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1070         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1071 #endif
1072         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1073         struct rte_eth_rss_reta_entry64 reta_conf[2];
1074         struct rte_eth_rss_conf rss_conf;
1075         uint32_t i, id, pos, q;
1076
1077         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1078         if (!rss_conf.rss_key) {
1079                 DP_INFO(edev, "Applying driver default key\n");
1080                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1081                 qede_prandom_bytes(&def_rss_key[0]);
1082                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1083         }
1084
1085         /* Configure RSS hash */
1086         if (qede_rss_hash_update(eth_dev, &rss_conf))
1087                 return -EINVAL;
1088
1089         /* Configure default RETA */
1090         memset(reta_conf, 0, sizeof(reta_conf));
1091         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1092                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1093
1094         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1095                 id = i / RTE_RETA_GROUP_SIZE;
1096                 pos = i % RTE_RETA_GROUP_SIZE;
1097                 q = i % QEDE_RSS_COUNT(qdev);
1098                 reta_conf[id].reta[pos] = q;
1099         }
1100         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1101                                  ECORE_RSS_IND_TABLE_SIZE))
1102                 return -EINVAL;
1103
1104         return 0;
1105 }
1106
1107 static void qede_fastpath_start(struct ecore_dev *edev)
1108 {
1109         struct ecore_hwfn *p_hwfn;
1110         int i;
1111
1112         for_each_hwfn(edev, i) {
1113                 p_hwfn = &edev->hwfns[i];
1114                 ecore_hw_start_fastpath(p_hwfn);
1115         }
1116 }
1117
1118 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1119 {
1120         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1121         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1122         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1123
1124         PMD_INIT_FUNC_TRACE(edev);
1125
1126         /* Update MTU only if it has changed */
1127         if (qdev->mtu != qdev->new_mtu) {
1128                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1129                         goto err;
1130                 qdev->mtu = qdev->new_mtu;
1131         }
1132
1133         /* Configure TPA parameters */
1134         if (rxmode->enable_lro) {
1135                 if (qede_enable_tpa(eth_dev, true))
1136                         return -EINVAL;
1137                 /* Enable scatter mode for LRO */
1138                 if (!rxmode->enable_scatter)
1139                         eth_dev->data->scattered_rx = 1;
1140         }
1141
1142         /* Start queues */
1143         if (qede_start_queues(eth_dev))
1144                 goto err;
1145
1146         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1147          * enabling RSS. Hence RSS configuration is deferred upto this point.
1148          * Also, we would like to retain similar behavior in PF case, so we
1149          * don't do PF/VF specific check here.
1150          */
1151         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1152                 if (qede_config_rss(eth_dev))
1153                         goto err;
1154
1155         /* Enable vport*/
1156         if (qede_activate_vport(eth_dev, true))
1157                 goto err;
1158
1159         /* Bring-up the link */
1160         qede_dev_set_link_state(eth_dev, true);
1161
1162         /* Update link status */
1163         qede_link_update(eth_dev, 0);
1164
1165         /* Start/resume traffic */
1166         qede_fastpath_start(edev);
1167
1168         DP_INFO(edev, "Device started\n");
1169
1170         return 0;
1171 err:
1172         DP_ERR(edev, "Device start fails\n");
1173         return -1; /* common error code is < 0 */
1174 }
1175
1176 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1177 {
1178         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1179         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1180
1181         PMD_INIT_FUNC_TRACE(edev);
1182
1183         /* Disable vport */
1184         if (qede_activate_vport(eth_dev, false))
1185                 return;
1186
1187         if (qdev->enable_lro)
1188                 qede_enable_tpa(eth_dev, false);
1189
1190         /* Stop queues */
1191         qede_stop_queues(eth_dev);
1192
1193         /* Disable traffic */
1194         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1195
1196         /* Bring the link down */
1197         qede_dev_set_link_state(eth_dev, false);
1198
1199         DP_INFO(edev, "Device is stopped\n");
1200 }
1201
1202 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1203 {
1204         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1205         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1206         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1207         int ret;
1208
1209         PMD_INIT_FUNC_TRACE(edev);
1210
1211         /* Check requirements for 100G mode */
1212         if (ECORE_IS_CMT(edev)) {
1213                 if (eth_dev->data->nb_rx_queues < 2 ||
1214                                 eth_dev->data->nb_tx_queues < 2) {
1215                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1216                         return -EINVAL;
1217                 }
1218
1219                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1220                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1221                         DP_ERR(edev,
1222                                         "100G mode needs even no. of RX/TX queues\n");
1223                         return -EINVAL;
1224                 }
1225         }
1226
1227         /* Sanity checks and throw warnings */
1228         if (rxmode->enable_scatter)
1229                 eth_dev->data->scattered_rx = 1;
1230
1231         if (!rxmode->hw_strip_crc)
1232                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1233
1234         if (!rxmode->hw_ip_checksum)
1235                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1236                                 "in hw\n");
1237         if (rxmode->header_split)
1238                 DP_INFO(edev, "Header split enable is not supported\n");
1239         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1240                                 ETH_MQ_RX_RSS)) {
1241                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1242                 return -ENOTSUP;
1243         }
1244         /* Flow director mode check */
1245         if (qede_check_fdir_support(eth_dev))
1246                 return -ENOTSUP;
1247
1248         /* Deallocate resources if held previously. It is needed only if the
1249          * queue count has been changed from previous configuration. If its
1250          * going to change then it means RX/TX queue setup will be called
1251          * again and the fastpath pointers will be reinitialized there.
1252          */
1253         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1254             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1255                 qede_dealloc_fp_resc(eth_dev);
1256                 /* Proceed with updated queue count */
1257                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1258                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1259                 if (qede_alloc_fp_resc(qdev))
1260                         return -ENOMEM;
1261         }
1262
1263         /* VF's MTU has to be set using vport-start where as
1264          * PF's MTU can be updated via vport-update.
1265          */
1266         if (IS_VF(edev)) {
1267                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1268                         return -1;
1269         } else {
1270                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1271                         return -1;
1272         }
1273
1274         qdev->mtu = rxmode->max_rx_pkt_len;
1275         qdev->new_mtu = qdev->mtu;
1276
1277         /* Enable VLAN offloads by default */
1278         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1279                         ETH_VLAN_FILTER_MASK |
1280                         ETH_VLAN_EXTEND_MASK);
1281         if (ret)
1282                 return ret;
1283
1284         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1285                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1286
1287         return 0;
1288 }
1289
1290 /* Info about HW descriptor ring limitations */
1291 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1292         .nb_max = 0x8000, /* 32K */
1293         .nb_min = 128,
1294         .nb_align = 128 /* lowest common multiple */
1295 };
1296
1297 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1298         .nb_max = 0x8000, /* 32K */
1299         .nb_min = 256,
1300         .nb_align = 256,
1301         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1302         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1303 };
1304
1305 static void
1306 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1307                   struct rte_eth_dev_info *dev_info)
1308 {
1309         struct qede_dev *qdev = eth_dev->data->dev_private;
1310         struct ecore_dev *edev = &qdev->edev;
1311         struct qed_link_output link;
1312         uint32_t speed_cap = 0;
1313
1314         PMD_INIT_FUNC_TRACE(edev);
1315
1316         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1317         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1318         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1319         dev_info->rx_desc_lim = qede_rx_desc_lim;
1320         dev_info->tx_desc_lim = qede_tx_desc_lim;
1321
1322         if (IS_PF(edev))
1323                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1324                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1325         else
1326                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1327                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1328         dev_info->max_tx_queues = dev_info->max_rx_queues;
1329
1330         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1331         dev_info->max_vfs = 0;
1332         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1333         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1334         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1335
1336         dev_info->default_txconf = (struct rte_eth_txconf) {
1337                 .txq_flags = QEDE_TXQ_FLAGS,
1338         };
1339
1340         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1341                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1342                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1343                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1344                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1345                                      DEV_RX_OFFLOAD_TCP_LRO);
1346
1347         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1348                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1349                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1350                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1351                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1352                                      DEV_TX_OFFLOAD_TCP_TSO |
1353                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1354
1355         memset(&link, 0, sizeof(struct qed_link_output));
1356         qdev->ops->common->get_link(edev, &link);
1357         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1358                 speed_cap |= ETH_LINK_SPEED_1G;
1359         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1360                 speed_cap |= ETH_LINK_SPEED_10G;
1361         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1362                 speed_cap |= ETH_LINK_SPEED_25G;
1363         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1364                 speed_cap |= ETH_LINK_SPEED_40G;
1365         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1366                 speed_cap |= ETH_LINK_SPEED_50G;
1367         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1368                 speed_cap |= ETH_LINK_SPEED_100G;
1369         dev_info->speed_capa = speed_cap;
1370 }
1371
1372 /* return 0 means link status changed, -1 means not changed */
1373 int
1374 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1375 {
1376         struct qede_dev *qdev = eth_dev->data->dev_private;
1377         struct ecore_dev *edev = &qdev->edev;
1378         uint16_t link_duplex;
1379         struct qed_link_output link;
1380         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1381
1382         memset(&link, 0, sizeof(struct qed_link_output));
1383         qdev->ops->common->get_link(edev, &link);
1384
1385         /* Link Speed */
1386         curr->link_speed = link.speed;
1387
1388         /* Link Mode */
1389         switch (link.duplex) {
1390         case QEDE_DUPLEX_HALF:
1391                 link_duplex = ETH_LINK_HALF_DUPLEX;
1392                 break;
1393         case QEDE_DUPLEX_FULL:
1394                 link_duplex = ETH_LINK_FULL_DUPLEX;
1395                 break;
1396         case QEDE_DUPLEX_UNKNOWN:
1397         default:
1398                 link_duplex = -1;
1399         }
1400         curr->link_duplex = link_duplex;
1401
1402         /* Link Status */
1403         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1404
1405         /* AN */
1406         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1407                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1408
1409         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1410                 curr->link_speed, curr->link_duplex,
1411                 curr->link_autoneg, curr->link_status);
1412
1413         /* return 0 means link status changed, -1 means not changed */
1414         return ((curr->link_status == link.link_up) ? -1 : 0);
1415 }
1416
1417 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1418 {
1419 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1420         struct qede_dev *qdev = eth_dev->data->dev_private;
1421         struct ecore_dev *edev = &qdev->edev;
1422
1423         PMD_INIT_FUNC_TRACE(edev);
1424 #endif
1425
1426         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1427
1428         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1429                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1430
1431         qed_configure_filter_rx_mode(eth_dev, type);
1432 }
1433
1434 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1435 {
1436 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1437         struct qede_dev *qdev = eth_dev->data->dev_private;
1438         struct ecore_dev *edev = &qdev->edev;
1439
1440         PMD_INIT_FUNC_TRACE(edev);
1441 #endif
1442
1443         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1444                 qed_configure_filter_rx_mode(eth_dev,
1445                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1446         else
1447                 qed_configure_filter_rx_mode(eth_dev,
1448                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1449 }
1450
1451 static void qede_poll_sp_sb_cb(void *param)
1452 {
1453         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1454         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1455         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1456         int rc;
1457
1458         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1459         qede_interrupt_action(&edev->hwfns[1]);
1460
1461         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1462                                qede_poll_sp_sb_cb,
1463                                (void *)eth_dev);
1464         if (rc != 0) {
1465                 DP_ERR(edev, "Unable to start periodic"
1466                              " timer rc %d\n", rc);
1467                 assert(false && "Unable to start periodic timer");
1468         }
1469 }
1470
1471 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1472 {
1473         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1474         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1475         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1476
1477         PMD_INIT_FUNC_TRACE(edev);
1478
1479         /* dev_stop() shall cleanup fp resources in hw but without releasing
1480          * dma memories and sw structures so that dev_start() can be called
1481          * by the app without reconfiguration. However, in dev_close() we
1482          * can release all the resources and device can be brought up newly
1483          */
1484         if (eth_dev->data->dev_started)
1485                 qede_dev_stop(eth_dev);
1486
1487         qede_stop_vport(edev);
1488         qede_fdir_dealloc_resc(eth_dev);
1489         qede_dealloc_fp_resc(eth_dev);
1490
1491         eth_dev->data->nb_rx_queues = 0;
1492         eth_dev->data->nb_tx_queues = 0;
1493
1494         qdev->ops->common->slowpath_stop(edev);
1495         qdev->ops->common->remove(edev);
1496         rte_intr_disable(&pci_dev->intr_handle);
1497         rte_intr_callback_unregister(&pci_dev->intr_handle,
1498                                      qede_interrupt_handler, (void *)eth_dev);
1499         if (ECORE_IS_CMT(edev))
1500                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1501 }
1502
1503 static int
1504 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1505 {
1506         struct qede_dev *qdev = eth_dev->data->dev_private;
1507         struct ecore_dev *edev = &qdev->edev;
1508         struct ecore_eth_stats stats;
1509         unsigned int i = 0, j = 0, qid;
1510         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1511         struct qede_tx_queue *txq;
1512
1513         ecore_get_vport_stats(edev, &stats);
1514
1515         /* RX Stats */
1516         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1517             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1518
1519         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1520             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1521
1522         eth_stats->ierrors = stats.common.rx_crc_errors +
1523             stats.common.rx_align_errors +
1524             stats.common.rx_carrier_errors +
1525             stats.common.rx_oversize_packets +
1526             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1527
1528         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1529
1530         eth_stats->imissed = stats.common.mftag_filter_discards +
1531             stats.common.mac_filter_discards +
1532             stats.common.no_buff_discards +
1533             stats.common.brb_truncates + stats.common.brb_discards;
1534
1535         /* TX stats */
1536         eth_stats->opackets = stats.common.tx_ucast_pkts +
1537             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1538
1539         eth_stats->obytes = stats.common.tx_ucast_bytes +
1540             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1541
1542         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1543
1544         /* Queue stats */
1545         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1546                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1547         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1548                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1549         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1550             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1551                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1552                        "Not all the queue stats will be displayed. Set"
1553                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1554                        " appropriately and retry.\n");
1555
1556         for_each_rss(qid) {
1557                 eth_stats->q_ipackets[i] =
1558                         *(uint64_t *)(
1559                                 ((char *)(qdev->fp_array[qid].rxq)) +
1560                                 offsetof(struct qede_rx_queue,
1561                                 rcv_pkts));
1562                 eth_stats->q_errors[i] =
1563                         *(uint64_t *)(
1564                                 ((char *)(qdev->fp_array[qid].rxq)) +
1565                                 offsetof(struct qede_rx_queue,
1566                                 rx_hw_errors)) +
1567                         *(uint64_t *)(
1568                                 ((char *)(qdev->fp_array[qid].rxq)) +
1569                                 offsetof(struct qede_rx_queue,
1570                                 rx_alloc_errors));
1571                 i++;
1572                 if (i == rxq_stat_cntrs)
1573                         break;
1574         }
1575
1576         for_each_tss(qid) {
1577                 txq = qdev->fp_array[qid].txq;
1578                 eth_stats->q_opackets[j] =
1579                         *((uint64_t *)(uintptr_t)
1580                                 (((uint64_t)(uintptr_t)(txq)) +
1581                                  offsetof(struct qede_tx_queue,
1582                                           xmit_pkts)));
1583                 j++;
1584                 if (j == txq_stat_cntrs)
1585                         break;
1586         }
1587
1588         return 0;
1589 }
1590
1591 static unsigned
1592 qede_get_xstats_count(struct qede_dev *qdev) {
1593         if (ECORE_IS_BB(&qdev->edev))
1594                 return RTE_DIM(qede_xstats_strings) +
1595                        RTE_DIM(qede_bb_xstats_strings) +
1596                        (RTE_DIM(qede_rxq_xstats_strings) *
1597                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1598                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1599         else
1600                 return RTE_DIM(qede_xstats_strings) +
1601                        RTE_DIM(qede_ah_xstats_strings) +
1602                        (RTE_DIM(qede_rxq_xstats_strings) *
1603                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1604                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1605 }
1606
1607 static int
1608 qede_get_xstats_names(struct rte_eth_dev *dev,
1609                       struct rte_eth_xstat_name *xstats_names,
1610                       __rte_unused unsigned int limit)
1611 {
1612         struct qede_dev *qdev = dev->data->dev_private;
1613         struct ecore_dev *edev = &qdev->edev;
1614         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1615         unsigned int i, qid, stat_idx = 0;
1616         unsigned int rxq_stat_cntrs;
1617
1618         if (xstats_names != NULL) {
1619                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1620                         snprintf(xstats_names[stat_idx].name,
1621                                 sizeof(xstats_names[stat_idx].name),
1622                                 "%s",
1623                                 qede_xstats_strings[i].name);
1624                         stat_idx++;
1625                 }
1626
1627                 if (ECORE_IS_BB(edev)) {
1628                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1629                                 snprintf(xstats_names[stat_idx].name,
1630                                         sizeof(xstats_names[stat_idx].name),
1631                                         "%s",
1632                                         qede_bb_xstats_strings[i].name);
1633                                 stat_idx++;
1634                         }
1635                 } else {
1636                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1637                                 snprintf(xstats_names[stat_idx].name,
1638                                         sizeof(xstats_names[stat_idx].name),
1639                                         "%s",
1640                                         qede_ah_xstats_strings[i].name);
1641                                 stat_idx++;
1642                         }
1643                 }
1644
1645                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1646                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1647                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1648                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1649                                 snprintf(xstats_names[stat_idx].name,
1650                                         sizeof(xstats_names[stat_idx].name),
1651                                         "%.4s%d%s",
1652                                         qede_rxq_xstats_strings[i].name, qid,
1653                                         qede_rxq_xstats_strings[i].name + 4);
1654                                 stat_idx++;
1655                         }
1656                 }
1657         }
1658
1659         return stat_cnt;
1660 }
1661
1662 static int
1663 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1664                 unsigned int n)
1665 {
1666         struct qede_dev *qdev = dev->data->dev_private;
1667         struct ecore_dev *edev = &qdev->edev;
1668         struct ecore_eth_stats stats;
1669         const unsigned int num = qede_get_xstats_count(qdev);
1670         unsigned int i, qid, stat_idx = 0;
1671         unsigned int rxq_stat_cntrs;
1672
1673         if (n < num)
1674                 return num;
1675
1676         ecore_get_vport_stats(edev, &stats);
1677
1678         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1679                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1680                                              qede_xstats_strings[i].offset);
1681                 xstats[stat_idx].id = stat_idx;
1682                 stat_idx++;
1683         }
1684
1685         if (ECORE_IS_BB(edev)) {
1686                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1687                         xstats[stat_idx].value =
1688                                         *(uint64_t *)(((char *)&stats) +
1689                                         qede_bb_xstats_strings[i].offset);
1690                         xstats[stat_idx].id = stat_idx;
1691                         stat_idx++;
1692                 }
1693         } else {
1694                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1695                         xstats[stat_idx].value =
1696                                         *(uint64_t *)(((char *)&stats) +
1697                                         qede_ah_xstats_strings[i].offset);
1698                         xstats[stat_idx].id = stat_idx;
1699                         stat_idx++;
1700                 }
1701         }
1702
1703         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1704                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1705         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1706                 for_each_rss(qid) {
1707                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1708                                 xstats[stat_idx].value = *(uint64_t *)(
1709                                         ((char *)(qdev->fp_array[qid].rxq)) +
1710                                          qede_rxq_xstats_strings[i].offset);
1711                                 xstats[stat_idx].id = stat_idx;
1712                                 stat_idx++;
1713                         }
1714                 }
1715         }
1716
1717         return stat_idx;
1718 }
1719
1720 static void
1721 qede_reset_xstats(struct rte_eth_dev *dev)
1722 {
1723         struct qede_dev *qdev = dev->data->dev_private;
1724         struct ecore_dev *edev = &qdev->edev;
1725
1726         ecore_reset_vport_stats(edev);
1727 }
1728
1729 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1730 {
1731         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1732         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1733         struct qed_link_params link_params;
1734         int rc;
1735
1736         DP_INFO(edev, "setting link state %d\n", link_up);
1737         memset(&link_params, 0, sizeof(link_params));
1738         link_params.link_up = link_up;
1739         rc = qdev->ops->common->set_link(edev, &link_params);
1740         if (rc != ECORE_SUCCESS)
1741                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1742
1743         return rc;
1744 }
1745
1746 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1747 {
1748         return qede_dev_set_link_state(eth_dev, true);
1749 }
1750
1751 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1752 {
1753         return qede_dev_set_link_state(eth_dev, false);
1754 }
1755
1756 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1757 {
1758         struct qede_dev *qdev = eth_dev->data->dev_private;
1759         struct ecore_dev *edev = &qdev->edev;
1760
1761         ecore_reset_vport_stats(edev);
1762 }
1763
1764 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1765 {
1766         enum qed_filter_rx_mode_type type =
1767             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1768
1769         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1770                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1771
1772         qed_configure_filter_rx_mode(eth_dev, type);
1773 }
1774
1775 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1776 {
1777         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1778                 qed_configure_filter_rx_mode(eth_dev,
1779                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1780         else
1781                 qed_configure_filter_rx_mode(eth_dev,
1782                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1783 }
1784
1785 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1786                               struct rte_eth_fc_conf *fc_conf)
1787 {
1788         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1789         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1790         struct qed_link_output current_link;
1791         struct qed_link_params params;
1792
1793         memset(&current_link, 0, sizeof(current_link));
1794         qdev->ops->common->get_link(edev, &current_link);
1795
1796         memset(&params, 0, sizeof(params));
1797         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1798         if (fc_conf->autoneg) {
1799                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1800                         DP_ERR(edev, "Autoneg not supported\n");
1801                         return -EINVAL;
1802                 }
1803                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1804         }
1805
1806         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1807         if (fc_conf->mode == RTE_FC_FULL)
1808                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1809                                         QED_LINK_PAUSE_RX_ENABLE);
1810         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1811                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1812         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1813                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1814
1815         params.link_up = true;
1816         (void)qdev->ops->common->set_link(edev, &params);
1817
1818         return 0;
1819 }
1820
1821 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1822                               struct rte_eth_fc_conf *fc_conf)
1823 {
1824         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1825         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1826         struct qed_link_output current_link;
1827
1828         memset(&current_link, 0, sizeof(current_link));
1829         qdev->ops->common->get_link(edev, &current_link);
1830
1831         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1832                 fc_conf->autoneg = true;
1833
1834         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1835                                          QED_LINK_PAUSE_TX_ENABLE))
1836                 fc_conf->mode = RTE_FC_FULL;
1837         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1838                 fc_conf->mode = RTE_FC_RX_PAUSE;
1839         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1840                 fc_conf->mode = RTE_FC_TX_PAUSE;
1841         else
1842                 fc_conf->mode = RTE_FC_NONE;
1843
1844         return 0;
1845 }
1846
1847 static const uint32_t *
1848 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1849 {
1850         static const uint32_t ptypes[] = {
1851                 RTE_PTYPE_L2_ETHER,
1852                 RTE_PTYPE_L2_ETHER_VLAN,
1853                 RTE_PTYPE_L3_IPV4,
1854                 RTE_PTYPE_L3_IPV6,
1855                 RTE_PTYPE_L4_TCP,
1856                 RTE_PTYPE_L4_UDP,
1857                 RTE_PTYPE_TUNNEL_VXLAN,
1858                 RTE_PTYPE_L4_FRAG,
1859                 /* Inner */
1860                 RTE_PTYPE_INNER_L2_ETHER,
1861                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1862                 RTE_PTYPE_INNER_L3_IPV4,
1863                 RTE_PTYPE_INNER_L3_IPV6,
1864                 RTE_PTYPE_INNER_L4_TCP,
1865                 RTE_PTYPE_INNER_L4_UDP,
1866                 RTE_PTYPE_INNER_L4_FRAG,
1867                 RTE_PTYPE_UNKNOWN
1868         };
1869
1870         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1871                 return ptypes;
1872
1873         return NULL;
1874 }
1875
1876 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1877 {
1878         *rss_caps = 0;
1879         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1880         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1881         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1882         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1883         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1884         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1885         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1886         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1887 }
1888
1889 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1890                          struct rte_eth_rss_conf *rss_conf)
1891 {
1892         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1893         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1894         struct ecore_sp_vport_update_params vport_update_params;
1895         struct ecore_rss_params rss_params;
1896         struct ecore_hwfn *p_hwfn;
1897         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1898         uint64_t hf = rss_conf->rss_hf;
1899         uint8_t len = rss_conf->rss_key_len;
1900         uint8_t idx;
1901         uint8_t i;
1902         int rc;
1903
1904         memset(&vport_update_params, 0, sizeof(vport_update_params));
1905         memset(&rss_params, 0, sizeof(rss_params));
1906
1907         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1908                 (unsigned long)hf, len, key);
1909
1910         if (hf != 0) {
1911                 /* Enabling RSS */
1912                 DP_INFO(edev, "Enabling rss\n");
1913
1914                 /* RSS caps */
1915                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1916                 rss_params.update_rss_capabilities = 1;
1917
1918                 /* RSS hash key */
1919                 if (key) {
1920                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1921                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1922                                 return -EINVAL;
1923                         }
1924                         DP_INFO(edev, "Applying user supplied hash key\n");
1925                         rss_params.update_rss_key = 1;
1926                         memcpy(&rss_params.rss_key, key, len);
1927                 }
1928                 rss_params.rss_enable = 1;
1929         }
1930
1931         rss_params.update_rss_config = 1;
1932         /* tbl_size has to be set with capabilities */
1933         rss_params.rss_table_size_log = 7;
1934         vport_update_params.vport_id = 0;
1935         /* pass the L2 handles instead of qids */
1936         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1937                 idx = qdev->rss_ind_table[i];
1938                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1939         }
1940         vport_update_params.rss_params = &rss_params;
1941
1942         for_each_hwfn(edev, i) {
1943                 p_hwfn = &edev->hwfns[i];
1944                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1945                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1946                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1947                 if (rc) {
1948                         DP_ERR(edev, "vport-update for RSS failed\n");
1949                         return rc;
1950                 }
1951         }
1952         qdev->rss_enable = rss_params.rss_enable;
1953
1954         /* Update local structure for hash query */
1955         qdev->rss_conf.rss_hf = hf;
1956         qdev->rss_conf.rss_key_len = len;
1957         if (qdev->rss_enable) {
1958                 if  (qdev->rss_conf.rss_key == NULL) {
1959                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1960                         if (qdev->rss_conf.rss_key == NULL) {
1961                                 DP_ERR(edev, "No memory to store RSS key\n");
1962                                 return -ENOMEM;
1963                         }
1964                 }
1965                 if (key && len) {
1966                         DP_INFO(edev, "Storing RSS key\n");
1967                         memcpy(qdev->rss_conf.rss_key, key, len);
1968                 }
1969         } else if (!qdev->rss_enable && len == 0) {
1970                 if (qdev->rss_conf.rss_key) {
1971                         free(qdev->rss_conf.rss_key);
1972                         qdev->rss_conf.rss_key = NULL;
1973                         DP_INFO(edev, "Free RSS key\n");
1974                 }
1975         }
1976
1977         return 0;
1978 }
1979
1980 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1981                            struct rte_eth_rss_conf *rss_conf)
1982 {
1983         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1984
1985         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1986         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1987
1988         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1989                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1990                        rss_conf->rss_key_len);
1991         return 0;
1992 }
1993
1994 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1995                                     struct ecore_rss_params *rss)
1996 {
1997         int i, fn;
1998         bool rss_mode = 1; /* enable */
1999         struct ecore_queue_cid *cid;
2000         struct ecore_rss_params *t_rss;
2001
2002         /* In regular scenario, we'd simply need to take input handlers.
2003          * But in CMT, we'd have to split the handlers according to the
2004          * engine they were configured on. We'd then have to understand
2005          * whether RSS is really required, since 2-queues on CMT doesn't
2006          * require RSS.
2007          */
2008
2009         /* CMT should be round-robin */
2010         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2011                 cid = rss->rss_ind_table[i];
2012
2013                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2014                         t_rss = &rss[0];
2015                 else
2016                         t_rss = &rss[1];
2017
2018                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2019         }
2020
2021         t_rss = &rss[1];
2022         t_rss->update_rss_ind_table = 1;
2023         t_rss->rss_table_size_log = 7;
2024         t_rss->update_rss_config = 1;
2025
2026         /* Make sure RSS is actually required */
2027         for_each_hwfn(edev, fn) {
2028                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2029                      i++) {
2030                         if (rss[fn].rss_ind_table[i] !=
2031                             rss[fn].rss_ind_table[0])
2032                                 break;
2033                 }
2034
2035                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2036                         DP_INFO(edev,
2037                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2038                         rss_mode = 0;
2039                         goto out;
2040                 }
2041         }
2042
2043 out:
2044         t_rss->rss_enable = rss_mode;
2045
2046         return rss_mode;
2047 }
2048
2049 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2050                          struct rte_eth_rss_reta_entry64 *reta_conf,
2051                          uint16_t reta_size)
2052 {
2053         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2054         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2055         struct ecore_sp_vport_update_params vport_update_params;
2056         struct ecore_rss_params *params;
2057         struct ecore_hwfn *p_hwfn;
2058         uint16_t i, idx, shift;
2059         uint8_t entry;
2060         int rc = 0;
2061
2062         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2063                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2064                        reta_size);
2065                 return -EINVAL;
2066         }
2067
2068         memset(&vport_update_params, 0, sizeof(vport_update_params));
2069         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2070                              RTE_CACHE_LINE_SIZE);
2071         if (params == NULL) {
2072                 DP_ERR(edev, "failed to allocate memory\n");
2073                 return -ENOMEM;
2074         }
2075
2076         for (i = 0; i < reta_size; i++) {
2077                 idx = i / RTE_RETA_GROUP_SIZE;
2078                 shift = i % RTE_RETA_GROUP_SIZE;
2079                 if (reta_conf[idx].mask & (1ULL << shift)) {
2080                         entry = reta_conf[idx].reta[shift];
2081                         /* Pass rxq handles to ecore */
2082                         params->rss_ind_table[i] =
2083                                         qdev->fp_array[entry].rxq->handle;
2084                         /* Update the local copy for RETA query command */
2085                         qdev->rss_ind_table[i] = entry;
2086                 }
2087         }
2088
2089         params->update_rss_ind_table = 1;
2090         params->rss_table_size_log = 7;
2091         params->update_rss_config = 1;
2092
2093         /* Fix up RETA for CMT mode device */
2094         if (ECORE_IS_CMT(edev))
2095                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2096                                                             params);
2097         vport_update_params.vport_id = 0;
2098         /* Use the current value of rss_enable */
2099         params->rss_enable = qdev->rss_enable;
2100         vport_update_params.rss_params = params;
2101
2102         for_each_hwfn(edev, i) {
2103                 p_hwfn = &edev->hwfns[i];
2104                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2105                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2106                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2107                 if (rc) {
2108                         DP_ERR(edev, "vport-update for RSS failed\n");
2109                         goto out;
2110                 }
2111         }
2112
2113 out:
2114         rte_free(params);
2115         return rc;
2116 }
2117
2118 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2119                                struct rte_eth_rss_reta_entry64 *reta_conf,
2120                                uint16_t reta_size)
2121 {
2122         struct qede_dev *qdev = eth_dev->data->dev_private;
2123         struct ecore_dev *edev = &qdev->edev;
2124         uint16_t i, idx, shift;
2125         uint8_t entry;
2126
2127         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2128                 DP_ERR(edev, "reta_size %d is not supported\n",
2129                        reta_size);
2130                 return -EINVAL;
2131         }
2132
2133         for (i = 0; i < reta_size; i++) {
2134                 idx = i / RTE_RETA_GROUP_SIZE;
2135                 shift = i % RTE_RETA_GROUP_SIZE;
2136                 if (reta_conf[idx].mask & (1ULL << shift)) {
2137                         entry = qdev->rss_ind_table[i];
2138                         reta_conf[idx].reta[shift] = entry;
2139                 }
2140         }
2141
2142         return 0;
2143 }
2144
2145
2146
2147 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2148 {
2149         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2150         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2151         struct rte_eth_dev_info dev_info = {0};
2152         struct qede_fastpath *fp;
2153         uint32_t frame_size;
2154         uint16_t rx_buf_size;
2155         uint16_t bufsz;
2156         int i;
2157
2158         PMD_INIT_FUNC_TRACE(edev);
2159         qede_dev_info_get(dev, &dev_info);
2160         frame_size = mtu + QEDE_ETH_OVERHEAD;
2161         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2162                 DP_ERR(edev, "MTU %u out of range\n", mtu);
2163                 return -EINVAL;
2164         }
2165         if (!dev->data->scattered_rx &&
2166             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2167                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2168                         dev->data->min_rx_buf_size);
2169                 return -EINVAL;
2170         }
2171         /* Temporarily replace I/O functions with dummy ones. It cannot
2172          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2173          */
2174         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2175         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2176         qede_dev_stop(dev);
2177         rte_delay_ms(1000);
2178         qdev->mtu = mtu;
2179         /* Fix up RX buf size for all queues of the port */
2180         for_each_rss(i) {
2181                 fp = &qdev->fp_array[i];
2182                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2183                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2184                 if (dev->data->scattered_rx)
2185                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2186                 else
2187                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2188                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2189                 fp->rxq->rx_buf_size = rx_buf_size;
2190                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2191         }
2192         qede_dev_start(dev);
2193         if (frame_size > ETHER_MAX_LEN)
2194                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2195         else
2196                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2197         /* update max frame size */
2198         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2199         /* Reassign back */
2200         dev->rx_pkt_burst = qede_recv_pkts;
2201         dev->tx_pkt_burst = qede_xmit_pkts;
2202
2203         return 0;
2204 }
2205
2206 static int
2207 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2208                        struct rte_eth_udp_tunnel *tunnel_udp,
2209                        bool add)
2210 {
2211         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2212         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2213         struct ecore_tunnel_info tunn; /* @DPDK */
2214         struct ecore_hwfn *p_hwfn;
2215         struct ecore_ptt *p_ptt;
2216         uint16_t udp_port;
2217         int rc, i;
2218
2219         PMD_INIT_FUNC_TRACE(edev);
2220
2221         memset(&tunn, 0, sizeof(tunn));
2222         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2223                 /* Enable VxLAN tunnel if needed before UDP port update using
2224                  * default MAC/VLAN classification.
2225                  */
2226                 if (add) {
2227                         if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2228                                 DP_INFO(edev,
2229                                         "UDP port %u was already configured\n",
2230                                         tunnel_udp->udp_port);
2231                                 return ECORE_SUCCESS;
2232                         }
2233                         /* Enable VXLAN if it was not enabled while adding
2234                          * VXLAN filter.
2235                          */
2236                         if (!qdev->vxlan.enable) {
2237                                 rc = qede_vxlan_enable(eth_dev,
2238                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2239                                 if (rc != ECORE_SUCCESS) {
2240                                         DP_ERR(edev, "Failed to enable VXLAN "
2241                                                 "prior to updating UDP port\n");
2242                                         return rc;
2243                                 }
2244                         }
2245                         udp_port = tunnel_udp->udp_port;
2246                 } else {
2247                         if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2248                                 DP_ERR(edev, "UDP port %u doesn't exist\n",
2249                                         tunnel_udp->udp_port);
2250                                 return ECORE_INVAL;
2251                         }
2252                         udp_port = 0;
2253                 }
2254
2255                 tunn.vxlan_port.b_update_port = true;
2256                 tunn.vxlan_port.port = udp_port;
2257                 for_each_hwfn(edev, i) {
2258                         p_hwfn = &edev->hwfns[i];
2259                         p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
2260                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2261                                                 ECORE_SPQ_MODE_CB, NULL);
2262                         if (rc != ECORE_SUCCESS) {
2263                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2264                                        tunn.vxlan_port.port);
2265                                 if (IS_PF(edev))
2266                                         ecore_ptt_release(p_hwfn, p_ptt);
2267                                 return rc;
2268                         }
2269                 }
2270
2271                 qdev->vxlan.udp_port = udp_port;
2272                 /* If the request is to delete UDP port and if the number of
2273                  * VXLAN filters have reached 0 then VxLAN offload can be be
2274                  * disabled.
2275                  */
2276                 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2277                         return qede_vxlan_enable(eth_dev,
2278                                         ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2279         }
2280
2281         return 0;
2282 }
2283
2284 static int
2285 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2286                       struct rte_eth_udp_tunnel *tunnel_udp)
2287 {
2288         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2289 }
2290
2291 static int
2292 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2293                       struct rte_eth_udp_tunnel *tunnel_udp)
2294 {
2295         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2296 }
2297
2298 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2299                                        uint32_t *clss, char *str)
2300 {
2301         uint16_t j;
2302         *clss = MAX_ECORE_TUNN_CLSS;
2303
2304         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2305                 if (filter == qede_tunn_types[j].rte_filter_type) {
2306                         *type = qede_tunn_types[j].qede_type;
2307                         *clss = qede_tunn_types[j].qede_tunn_clss;
2308                         strcpy(str, qede_tunn_types[j].string);
2309                         return;
2310                 }
2311         }
2312 }
2313
2314 static int
2315 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2316                               const struct rte_eth_tunnel_filter_conf *conf,
2317                               uint32_t type)
2318 {
2319         /* Init commmon ucast params first */
2320         qede_set_ucast_cmn_params(ucast);
2321
2322         /* Copy out the required fields based on classification type */
2323         ucast->type = type;
2324
2325         switch (type) {
2326         case ECORE_FILTER_VNI:
2327                 ucast->vni = conf->tenant_id;
2328         break;
2329         case ECORE_FILTER_INNER_VLAN:
2330                 ucast->vlan = conf->inner_vlan;
2331         break;
2332         case ECORE_FILTER_MAC:
2333                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2334                        ETHER_ADDR_LEN);
2335         break;
2336         case ECORE_FILTER_INNER_MAC:
2337                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2338                        ETHER_ADDR_LEN);
2339         break;
2340         case ECORE_FILTER_MAC_VNI_PAIR:
2341                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2342                         ETHER_ADDR_LEN);
2343                 ucast->vni = conf->tenant_id;
2344         break;
2345         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2346                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2347                         ETHER_ADDR_LEN);
2348                 ucast->vni = conf->tenant_id;
2349         break;
2350         case ECORE_FILTER_INNER_PAIR:
2351                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2352                         ETHER_ADDR_LEN);
2353                 ucast->vlan = conf->inner_vlan;
2354         break;
2355         default:
2356                 return -EINVAL;
2357         }
2358
2359         return ECORE_SUCCESS;
2360 }
2361
2362 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2363                                   enum rte_filter_op filter_op,
2364                                   const struct rte_eth_tunnel_filter_conf *conf)
2365 {
2366         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2367         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2368         enum ecore_filter_ucast_type type;
2369         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2370         struct ecore_filter_ucast ucast = {0};
2371         char str[80];
2372         uint16_t filter_type = 0;
2373         int rc;
2374
2375         PMD_INIT_FUNC_TRACE(edev);
2376
2377         switch (filter_op) {
2378         case RTE_ETH_FILTER_ADD:
2379                 if (IS_VF(edev))
2380                         return qede_vxlan_enable(eth_dev,
2381                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2382
2383                 filter_type = conf->filter_type;
2384                 /* Determine if the given filter classification is supported */
2385                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2386                 if (clss == MAX_ECORE_TUNN_CLSS) {
2387                         DP_ERR(edev, "Unsupported filter type\n");
2388                         return -EINVAL;
2389                 }
2390                 /* Init tunnel ucast params */
2391                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2392                 if (rc != ECORE_SUCCESS) {
2393                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2394                         conf->filter_type);
2395                         return rc;
2396                 }
2397                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2398                         str, filter_op, ucast.type);
2399
2400                 ucast.opcode = ECORE_FILTER_ADD;
2401
2402                 /* Skip MAC/VLAN if filter is based on VNI */
2403                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2404                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2405                         if (rc == 0) {
2406                                 /* Enable accept anyvlan */
2407                                 qede_config_accept_any_vlan(qdev, true);
2408                         }
2409                 } else {
2410                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2411                         if (rc == 0)
2412                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2413                                                     ECORE_SPQ_MODE_CB, NULL);
2414                 }
2415
2416                 if (rc != ECORE_SUCCESS)
2417                         return rc;
2418
2419                 qdev->vxlan.num_filters++;
2420                 qdev->vxlan.filter_type = filter_type;
2421                 if (!qdev->vxlan.enable)
2422                         return qede_vxlan_enable(eth_dev, clss, true, true);
2423
2424         break;
2425         case RTE_ETH_FILTER_DELETE:
2426                 if (IS_VF(edev))
2427                         return qede_vxlan_enable(eth_dev,
2428                                 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2429
2430                 filter_type = conf->filter_type;
2431                 /* Determine if the given filter classification is supported */
2432                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2433                 if (clss == MAX_ECORE_TUNN_CLSS) {
2434                         DP_ERR(edev, "Unsupported filter type\n");
2435                         return -EINVAL;
2436                 }
2437                 /* Init tunnel ucast params */
2438                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2439                 if (rc != ECORE_SUCCESS) {
2440                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2441                         conf->filter_type);
2442                         return rc;
2443                 }
2444                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2445                         str, filter_op, ucast.type);
2446
2447                 ucast.opcode = ECORE_FILTER_REMOVE;
2448
2449                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2450                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2451                 } else {
2452                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2453                         if (rc == 0)
2454                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2455                                                     ECORE_SPQ_MODE_CB, NULL);
2456                 }
2457                 if (rc != ECORE_SUCCESS)
2458                         return rc;
2459
2460                 qdev->vxlan.num_filters--;
2461
2462                 /* Disable VXLAN if VXLAN filters become 0 */
2463                 if (qdev->vxlan.num_filters == 0)
2464                         return qede_vxlan_enable(eth_dev, clss, false, true);
2465         break;
2466         default:
2467                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2468                 return -EINVAL;
2469         }
2470
2471         return 0;
2472 }
2473
2474 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2475                          enum rte_filter_type filter_type,
2476                          enum rte_filter_op filter_op,
2477                          void *arg)
2478 {
2479         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2480         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2481         struct rte_eth_tunnel_filter_conf *filter_conf =
2482                         (struct rte_eth_tunnel_filter_conf *)arg;
2483
2484         switch (filter_type) {
2485         case RTE_ETH_FILTER_TUNNEL:
2486                 switch (filter_conf->tunnel_type) {
2487                 case RTE_TUNNEL_TYPE_VXLAN:
2488                         DP_INFO(edev,
2489                                 "Packet steering to the specified Rx queue"
2490                                 " is not supported with VXLAN tunneling");
2491                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2492                                                       filter_conf));
2493                 /* Place holders for future tunneling support */
2494                 case RTE_TUNNEL_TYPE_GENEVE:
2495                 case RTE_TUNNEL_TYPE_TEREDO:
2496                 case RTE_TUNNEL_TYPE_NVGRE:
2497                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2498                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2499                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2500                                 filter_conf->tunnel_type);
2501                         return -EINVAL;
2502                 case RTE_TUNNEL_TYPE_NONE:
2503                 default:
2504                         return 0;
2505                 }
2506                 break;
2507         case RTE_ETH_FILTER_FDIR:
2508                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2509         case RTE_ETH_FILTER_NTUPLE:
2510                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2511         case RTE_ETH_FILTER_MACVLAN:
2512         case RTE_ETH_FILTER_ETHERTYPE:
2513         case RTE_ETH_FILTER_FLEXIBLE:
2514         case RTE_ETH_FILTER_SYN:
2515         case RTE_ETH_FILTER_HASH:
2516         case RTE_ETH_FILTER_L2_TUNNEL:
2517         case RTE_ETH_FILTER_MAX:
2518         default:
2519                 DP_ERR(edev, "Unsupported filter type %d\n",
2520                         filter_type);
2521                 return -EINVAL;
2522         }
2523
2524         return 0;
2525 }
2526
2527 static const struct eth_dev_ops qede_eth_dev_ops = {
2528         .dev_configure = qede_dev_configure,
2529         .dev_infos_get = qede_dev_info_get,
2530         .rx_queue_setup = qede_rx_queue_setup,
2531         .rx_queue_release = qede_rx_queue_release,
2532         .tx_queue_setup = qede_tx_queue_setup,
2533         .tx_queue_release = qede_tx_queue_release,
2534         .dev_start = qede_dev_start,
2535         .dev_set_link_up = qede_dev_set_link_up,
2536         .dev_set_link_down = qede_dev_set_link_down,
2537         .link_update = qede_link_update,
2538         .promiscuous_enable = qede_promiscuous_enable,
2539         .promiscuous_disable = qede_promiscuous_disable,
2540         .allmulticast_enable = qede_allmulticast_enable,
2541         .allmulticast_disable = qede_allmulticast_disable,
2542         .dev_stop = qede_dev_stop,
2543         .dev_close = qede_dev_close,
2544         .stats_get = qede_get_stats,
2545         .stats_reset = qede_reset_stats,
2546         .xstats_get = qede_get_xstats,
2547         .xstats_reset = qede_reset_xstats,
2548         .xstats_get_names = qede_get_xstats_names,
2549         .mac_addr_add = qede_mac_addr_add,
2550         .mac_addr_remove = qede_mac_addr_remove,
2551         .mac_addr_set = qede_mac_addr_set,
2552         .vlan_offload_set = qede_vlan_offload_set,
2553         .vlan_filter_set = qede_vlan_filter_set,
2554         .flow_ctrl_set = qede_flow_ctrl_set,
2555         .flow_ctrl_get = qede_flow_ctrl_get,
2556         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2557         .rss_hash_update = qede_rss_hash_update,
2558         .rss_hash_conf_get = qede_rss_hash_conf_get,
2559         .reta_update  = qede_rss_reta_update,
2560         .reta_query  = qede_rss_reta_query,
2561         .mtu_set = qede_set_mtu,
2562         .filter_ctrl = qede_dev_filter_ctrl,
2563         .udp_tunnel_port_add = qede_udp_dst_port_add,
2564         .udp_tunnel_port_del = qede_udp_dst_port_del,
2565 };
2566
2567 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2568         .dev_configure = qede_dev_configure,
2569         .dev_infos_get = qede_dev_info_get,
2570         .rx_queue_setup = qede_rx_queue_setup,
2571         .rx_queue_release = qede_rx_queue_release,
2572         .tx_queue_setup = qede_tx_queue_setup,
2573         .tx_queue_release = qede_tx_queue_release,
2574         .dev_start = qede_dev_start,
2575         .dev_set_link_up = qede_dev_set_link_up,
2576         .dev_set_link_down = qede_dev_set_link_down,
2577         .link_update = qede_link_update,
2578         .promiscuous_enable = qede_promiscuous_enable,
2579         .promiscuous_disable = qede_promiscuous_disable,
2580         .allmulticast_enable = qede_allmulticast_enable,
2581         .allmulticast_disable = qede_allmulticast_disable,
2582         .dev_stop = qede_dev_stop,
2583         .dev_close = qede_dev_close,
2584         .stats_get = qede_get_stats,
2585         .stats_reset = qede_reset_stats,
2586         .xstats_get = qede_get_xstats,
2587         .xstats_reset = qede_reset_xstats,
2588         .xstats_get_names = qede_get_xstats_names,
2589         .vlan_offload_set = qede_vlan_offload_set,
2590         .vlan_filter_set = qede_vlan_filter_set,
2591         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2592         .rss_hash_update = qede_rss_hash_update,
2593         .rss_hash_conf_get = qede_rss_hash_conf_get,
2594         .reta_update  = qede_rss_reta_update,
2595         .reta_query  = qede_rss_reta_query,
2596         .mtu_set = qede_set_mtu,
2597         .udp_tunnel_port_add = qede_udp_dst_port_add,
2598         .udp_tunnel_port_del = qede_udp_dst_port_del,
2599 };
2600
2601 static void qede_update_pf_params(struct ecore_dev *edev)
2602 {
2603         struct ecore_pf_params pf_params;
2604
2605         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2606         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2607         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2608         qed_ops->common->update_pf_params(edev, &pf_params);
2609 }
2610
2611 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2612 {
2613         struct rte_pci_device *pci_dev;
2614         struct rte_pci_addr pci_addr;
2615         struct qede_dev *adapter;
2616         struct ecore_dev *edev;
2617         struct qed_dev_eth_info dev_info;
2618         struct qed_slowpath_params params;
2619         static bool do_once = true;
2620         uint8_t bulletin_change;
2621         uint8_t vf_mac[ETHER_ADDR_LEN];
2622         uint8_t is_mac_forced;
2623         bool is_mac_exist;
2624         /* Fix up ecore debug level */
2625         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2626         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2627         int rc;
2628
2629         /* Extract key data structures */
2630         adapter = eth_dev->data->dev_private;
2631         adapter->ethdev = eth_dev;
2632         edev = &adapter->edev;
2633         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2634         pci_addr = pci_dev->addr;
2635
2636         PMD_INIT_FUNC_TRACE(edev);
2637
2638         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2639                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2640                  eth_dev->data->port_id);
2641
2642         eth_dev->rx_pkt_burst = qede_recv_pkts;
2643         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2644         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2645
2646         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2647                 DP_ERR(edev, "Skipping device init from secondary process\n");
2648                 return 0;
2649         }
2650
2651         rte_eth_copy_pci_info(eth_dev, pci_dev);
2652
2653         /* @DPDK */
2654         edev->vendor_id = pci_dev->id.vendor_id;
2655         edev->device_id = pci_dev->id.device_id;
2656
2657         qed_ops = qed_get_eth_ops();
2658         if (!qed_ops) {
2659                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2660                 return -EINVAL;
2661         }
2662
2663         DP_INFO(edev, "Starting qede probe\n");
2664         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2665                                     dp_level, is_vf);
2666         if (rc != 0) {
2667                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2668                 return -ENODEV;
2669         }
2670         qede_update_pf_params(edev);
2671         rte_intr_callback_register(&pci_dev->intr_handle,
2672                                    qede_interrupt_handler, (void *)eth_dev);
2673         if (rte_intr_enable(&pci_dev->intr_handle)) {
2674                 DP_ERR(edev, "rte_intr_enable() failed\n");
2675                 return -ENODEV;
2676         }
2677
2678         /* Start the Slowpath-process */
2679         memset(&params, 0, sizeof(struct qed_slowpath_params));
2680         params.int_mode = ECORE_INT_MODE_MSIX;
2681         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2682         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2683         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2684         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2685         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2686                 QEDE_PMD_DRV_VER_STR_SIZE);
2687
2688         /* For CMT mode device do periodic polling for slowpath events.
2689          * This is required since uio device uses only one MSI-x
2690          * interrupt vector but we need one for each engine.
2691          */
2692         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2693                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2694                                        qede_poll_sp_sb_cb,
2695                                        (void *)eth_dev);
2696                 if (rc != 0) {
2697                         DP_ERR(edev, "Unable to start periodic"
2698                                      " timer rc %d\n", rc);
2699                         return -EINVAL;
2700                 }
2701         }
2702
2703         rc = qed_ops->common->slowpath_start(edev, &params);
2704         if (rc) {
2705                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2706                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2707                                      (void *)eth_dev);
2708                 return -ENODEV;
2709         }
2710
2711         rc = qed_ops->fill_dev_info(edev, &dev_info);
2712         if (rc) {
2713                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2714                 qed_ops->common->slowpath_stop(edev);
2715                 qed_ops->common->remove(edev);
2716                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2717                                      (void *)eth_dev);
2718                 return -ENODEV;
2719         }
2720
2721         qede_alloc_etherdev(adapter, &dev_info);
2722
2723         adapter->ops->common->set_name(edev, edev->name);
2724
2725         if (!is_vf)
2726                 adapter->dev_info.num_mac_filters =
2727                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2728                                             ECORE_MAC);
2729         else
2730                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2731                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2732
2733         /* Allocate memory for storing MAC addr */
2734         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2735                                         (ETHER_ADDR_LEN *
2736                                         adapter->dev_info.num_mac_filters),
2737                                         RTE_CACHE_LINE_SIZE);
2738
2739         if (eth_dev->data->mac_addrs == NULL) {
2740                 DP_ERR(edev, "Failed to allocate MAC address\n");
2741                 qed_ops->common->slowpath_stop(edev);
2742                 qed_ops->common->remove(edev);
2743                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2744                                      (void *)eth_dev);
2745                 return -ENOMEM;
2746         }
2747
2748         if (!is_vf) {
2749                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2750                                 hw_info.hw_mac_addr,
2751                                 &eth_dev->data->mac_addrs[0]);
2752                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2753                                 &adapter->primary_mac);
2754         } else {
2755                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2756                                        &bulletin_change);
2757                 if (bulletin_change) {
2758                         is_mac_exist =
2759                             ecore_vf_bulletin_get_forced_mac(
2760                                                 ECORE_LEADING_HWFN(edev),
2761                                                 vf_mac,
2762                                                 &is_mac_forced);
2763                         if (is_mac_exist && is_mac_forced) {
2764                                 DP_INFO(edev, "VF macaddr received from PF\n");
2765                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2766                                                 &eth_dev->data->mac_addrs[0]);
2767                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2768                                                 &adapter->primary_mac);
2769                         } else {
2770                                 DP_ERR(edev, "No VF macaddr assigned\n");
2771                         }
2772                 }
2773         }
2774
2775         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2776
2777         if (do_once) {
2778 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2779                 qede_print_adapter_info(adapter);
2780 #endif
2781                 do_once = false;
2782         }
2783
2784         adapter->num_tx_queues = 0;
2785         adapter->num_rx_queues = 0;
2786         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2787         SLIST_INIT(&adapter->vlan_list_head);
2788         SLIST_INIT(&adapter->uc_list_head);
2789         adapter->mtu = ETHER_MTU;
2790         adapter->new_mtu = ETHER_MTU;
2791         if (!is_vf)
2792                 if (qede_start_vport(adapter, adapter->mtu))
2793                         return -1;
2794
2795         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2796                 adapter->primary_mac.addr_bytes[0],
2797                 adapter->primary_mac.addr_bytes[1],
2798                 adapter->primary_mac.addr_bytes[2],
2799                 adapter->primary_mac.addr_bytes[3],
2800                 adapter->primary_mac.addr_bytes[4],
2801                 adapter->primary_mac.addr_bytes[5]);
2802
2803         DP_INFO(edev, "Device initialized\n");
2804
2805         return 0;
2806 }
2807
2808 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2809 {
2810         return qede_common_dev_init(eth_dev, 1);
2811 }
2812
2813 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2814 {
2815         return qede_common_dev_init(eth_dev, 0);
2816 }
2817
2818 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2819 {
2820 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2821         struct qede_dev *qdev = eth_dev->data->dev_private;
2822         struct ecore_dev *edev = &qdev->edev;
2823
2824         PMD_INIT_FUNC_TRACE(edev);
2825 #endif
2826
2827         /* only uninitialize in the primary process */
2828         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2829                 return 0;
2830
2831         /* safe to close dev here */
2832         qede_dev_close(eth_dev);
2833
2834         eth_dev->dev_ops = NULL;
2835         eth_dev->rx_pkt_burst = NULL;
2836         eth_dev->tx_pkt_burst = NULL;
2837
2838         if (eth_dev->data->mac_addrs)
2839                 rte_free(eth_dev->data->mac_addrs);
2840
2841         eth_dev->data->mac_addrs = NULL;
2842
2843         return 0;
2844 }
2845
2846 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2847 {
2848         return qede_dev_common_uninit(eth_dev);
2849 }
2850
2851 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2852 {
2853         return qede_dev_common_uninit(eth_dev);
2854 }
2855
2856 static const struct rte_pci_id pci_id_qedevf_map[] = {
2857 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2858         {
2859                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2860         },
2861         {
2862                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2863         },
2864         {
2865                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2866         },
2867         {.vendor_id = 0,}
2868 };
2869
2870 static const struct rte_pci_id pci_id_qede_map[] = {
2871 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2872         {
2873                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2874         },
2875         {
2876                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2877         },
2878         {
2879                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2880         },
2881         {
2882                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2883         },
2884         {
2885                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2886         },
2887         {
2888                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2889         },
2890         {
2891                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2892         },
2893         {
2894                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2895         },
2896         {
2897                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2898         },
2899         {
2900                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2901         },
2902         {.vendor_id = 0,}
2903 };
2904
2905 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2906         struct rte_pci_device *pci_dev)
2907 {
2908         return rte_eth_dev_pci_generic_probe(pci_dev,
2909                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2910 }
2911
2912 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2913 {
2914         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2915 }
2916
2917 static struct rte_pci_driver rte_qedevf_pmd = {
2918         .id_table = pci_id_qedevf_map,
2919         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2920         .probe = qedevf_eth_dev_pci_probe,
2921         .remove = qedevf_eth_dev_pci_remove,
2922 };
2923
2924 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2925         struct rte_pci_device *pci_dev)
2926 {
2927         return rte_eth_dev_pci_generic_probe(pci_dev,
2928                 sizeof(struct qede_dev), qede_eth_dev_init);
2929 }
2930
2931 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2932 {
2933         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2934 }
2935
2936 static struct rte_pci_driver rte_qede_pmd = {
2937         .id_table = pci_id_qede_map,
2938         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2939         .probe = qede_eth_dev_pci_probe,
2940         .remove = qede_eth_dev_pci_remove,
2941 };
2942
2943 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2944 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2945 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2946 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2947 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2948 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");