drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_gft_filter_drop",
 129                 offsetof(struct ecore_eth_stats_common, gft_filter_drop)},
 130         {"rx_hw_buffer_truncates",
 131                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 132         {"rx_hw_buffer_discards",
 133                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 134         {"tx_error_drop_packets",
 135                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 136
 137         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 138         {"rx_mac_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 140         {"rx_mac_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 142         {"rx_mac_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 144         {"rx_mac_frames_ok",
 145                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 146         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 147         {"tx_mac_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 149         {"tx_mac_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 151         {"tx_mac_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 153
 154         {"lro_coalesced_packets",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 156         {"lro_coalesced_events",
 157                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 158         {"lro_aborts_num",
 159                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 160         {"lro_not_coalesced_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          tpa_not_coalesced_pkts)},
 163         {"lro_coalesced_bytes",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          tpa_coalesced_bytes)},
 166 };
 167
 168 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 169         {"rx_1519_to_1522_byte_packets",
 170                 offsetof(struct ecore_eth_stats, bb) +
 171                 offsetof(struct ecore_eth_stats_bb,
 172                          rx_1519_to_1522_byte_packets)},
 173         {"rx_1519_to_2047_byte_packets",
 174                 offsetof(struct ecore_eth_stats, bb) +
 175                 offsetof(struct ecore_eth_stats_bb,
 176                          rx_1519_to_2047_byte_packets)},
 177         {"rx_2048_to_4095_byte_packets",
 178                 offsetof(struct ecore_eth_stats, bb) +
 179                 offsetof(struct ecore_eth_stats_bb,
 180                          rx_2048_to_4095_byte_packets)},
 181         {"rx_4096_to_9216_byte_packets",
 182                 offsetof(struct ecore_eth_stats, bb) +
 183                 offsetof(struct ecore_eth_stats_bb,
 184                          rx_4096_to_9216_byte_packets)},
 185         {"rx_9217_to_16383_byte_packets",
 186                 offsetof(struct ecore_eth_stats, bb) +
 187                 offsetof(struct ecore_eth_stats_bb,
 188                          rx_9217_to_16383_byte_packets)},
 189
 190         {"tx_1519_to_2047_byte_packets",
 191                 offsetof(struct ecore_eth_stats, bb) +
 192                 offsetof(struct ecore_eth_stats_bb,
 193                          tx_1519_to_2047_byte_packets)},
 194         {"tx_2048_to_4095_byte_packets",
 195                 offsetof(struct ecore_eth_stats, bb) +
 196                 offsetof(struct ecore_eth_stats_bb,
 197                          tx_2048_to_4095_byte_packets)},
 198         {"tx_4096_to_9216_byte_packets",
 199                 offsetof(struct ecore_eth_stats, bb) +
 200                 offsetof(struct ecore_eth_stats_bb,
 201                          tx_4096_to_9216_byte_packets)},
 202         {"tx_9217_to_16383_byte_packets",
 203                 offsetof(struct ecore_eth_stats, bb) +
 204                 offsetof(struct ecore_eth_stats_bb,
 205                          tx_9217_to_16383_byte_packets)},
 206
 207         {"tx_lpi_entry_count",
 208                 offsetof(struct ecore_eth_stats, bb) +
 209                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 210         {"tx_total_collisions",
 211                 offsetof(struct ecore_eth_stats, bb) +
 212                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 213 };
 214
 215 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 216         {"rx_1519_to_max_byte_packets",
 217                 offsetof(struct ecore_eth_stats, ah) +
 218                 offsetof(struct ecore_eth_stats_ah,
 219                          rx_1519_to_max_byte_packets)},
 220         {"tx_1519_to_max_byte_packets",
 221                 offsetof(struct ecore_eth_stats, ah) +
 222                 offsetof(struct ecore_eth_stats_ah,
 223                          tx_1519_to_max_byte_packets)},
 224 };
 225
 226 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 227         {"rx_q_segments",
 228                 offsetof(struct qede_rx_queue, rx_segs)},
 229         {"rx_q_hw_errors",
 230                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 231         {"rx_q_allocation_errors",
 232                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 233 };
 234
 235 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 236 {
 237         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 238 }
 239
 240 static void
 241 qede_interrupt_handler_intx(void *param)
 242 {
 243         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 244         struct qede_dev *qdev = eth_dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         u64 status;
 247
 248         /* Check if our device actually raised an interrupt */
 249         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 250         if (status & 0x1) {
 251                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 252
 253                 if (rte_intr_ack(eth_dev->intr_handle))
 254                         DP_ERR(edev, "rte_intr_ack failed\n");
 255         }
 256 }
 257
 258 static void
 259 qede_interrupt_handler(void *param)
 260 {
 261         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 262         struct qede_dev *qdev = eth_dev->data->dev_private;
 263         struct ecore_dev *edev = &qdev->edev;
 264
 265         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 266         if (rte_intr_ack(eth_dev->intr_handle))
 267                 DP_ERR(edev, "rte_intr_ack failed\n");
 268 }
 269
 270 static void
 271 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 272 {
 273         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 274         qdev->ops = qed_ops;
 275 }
 276
 277 static void qede_print_adapter_info(struct qede_dev *qdev)
 278 {
 279         struct ecore_dev *edev = &qdev->edev;
 280         struct qed_dev_info *info = &qdev->dev_info.common;
 281         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 282
 283         DP_INFO(edev, "**************************************************\n");
 284         DP_INFO(edev, " DPDK version\t\t\t: %s\n", rte_version());
 285         DP_INFO(edev, " Chip details\t\t\t: %s %c%d\n",
 286                   ECORE_IS_BB(edev) ? "BB" : "AH",
 287                   'A' + edev->chip_rev,
 288                   (int)edev->chip_metal);
 289         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 290                  QEDE_PMD_DRV_VERSION);
 291         DP_INFO(edev, " Driver version\t\t\t: %s\n", ver_str);
 292
 293         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 294                  QEDE_PMD_BASE_VERSION);
 295         DP_INFO(edev, " Base version\t\t\t: %s\n", ver_str);
 296
 297         if (!IS_VF(edev))
 298                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%s",
 299                          QEDE_PMD_FW_VERSION);
 300         else
 301                 snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 302                          info->fw_major, info->fw_minor,
 303                          info->fw_rev, info->fw_eng);
 304         DP_INFO(edev, " Firmware version\t\t\t: %s\n", ver_str);
 305
 306         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 307                  "%d.%d.%d.%d",
 308                  (info->mfw_rev & QED_MFW_VERSION_3_MASK) >>
 309                  QED_MFW_VERSION_3_OFFSET,
 310                  (info->mfw_rev & QED_MFW_VERSION_2_MASK) >>
 311                  QED_MFW_VERSION_2_OFFSET,
 312                  (info->mfw_rev & QED_MFW_VERSION_1_MASK) >>
 313                  QED_MFW_VERSION_1_OFFSET,
 314                  (info->mfw_rev & QED_MFW_VERSION_0_MASK) >>
 315                  QED_MFW_VERSION_0_OFFSET);
 316         DP_INFO(edev, " Management Firmware version\t: %s\n", ver_str);
 317         DP_INFO(edev, " Firmware file\t\t\t: %s\n", qede_fw_file);
 318         DP_INFO(edev, "**************************************************\n");
 319 }
 320
 321 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 322 {
 323         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
 324         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 325         unsigned int i = 0, j = 0, qid;
 326         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 327         struct qede_tx_queue *txq;
 328
 329         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 330
 331         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(dev),
 332                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 333         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(dev),
 334                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 335
 336         for (qid = 0; qid < qdev->num_rx_queues; qid++) {
 337                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 338                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 339                             sizeof(uint64_t));
 340                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 341                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 342                             sizeof(uint64_t));
 343                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 344                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 345                             sizeof(uint64_t));
 346
 347                 if (xstats)
 348                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 349                                 OSAL_MEMSET((((char *)
 350                                               (qdev->fp_array[qid].rxq)) +
 351                                              qede_rxq_xstats_strings[j].offset),
 352                                             0,
 353                                             sizeof(uint64_t));
 354
 355                 i++;
 356                 if (i == rxq_stat_cntrs)
 357                         break;
 358         }
 359
 360         i = 0;
 361
 362         for (qid = 0; qid < qdev->num_tx_queues; qid++) {
 363                 txq = qdev->fp_array[qid].txq;
 364
 365                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 366                                 (((uint64_t)(uintptr_t)(txq)) +
 367                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 368                             sizeof(uint64_t));
 369
 370                 i++;
 371                 if (i == txq_stat_cntrs)
 372                         break;
 373         }
 374 }
 375
 376 static int
 377 qede_stop_vport(struct ecore_dev *edev)
 378 {
 379         struct ecore_hwfn *p_hwfn;
 380         uint8_t vport_id;
 381         int rc;
 382         int i;
 383
 384         vport_id = 0;
 385         for_each_hwfn(edev, i) {
 386                 p_hwfn = &edev->hwfns[i];
 387                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 388                                          vport_id);
 389                 if (rc != ECORE_SUCCESS) {
 390                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 391                         return rc;
 392                 }
 393         }
 394
 395         DP_INFO(edev, "vport stopped\n");
 396
 397         return 0;
 398 }
 399
 400 static int
 401 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 402 {
 403         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 404         struct ecore_sp_vport_start_params params;
 405         struct ecore_hwfn *p_hwfn;
 406         int rc;
 407         int i;
 408
 409         if (qdev->vport_started)
 410                 qede_stop_vport(edev);
 411
 412         memset(&params, 0, sizeof(params));
 413         params.vport_id = 0;
 414         params.mtu = mtu;
 415         /* @DPDK - Disable FW placement */
 416         params.zero_placement_offset = 1;
 417         for_each_hwfn(edev, i) {
 418                 p_hwfn = &edev->hwfns[i];
 419                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 420                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 421                 rc = ecore_sp_vport_start(p_hwfn, &params);
 422                 if (rc != ECORE_SUCCESS) {
 423                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 424                         return rc;
 425                 }
 426         }
 427         ecore_reset_vport_stats(edev);
 428         qdev->vport_started = true;
 429         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 430
 431         return 0;
 432 }
 433
 434 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 435 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 436
 437 /* Activate or deactivate vport via vport-update */
 438 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 439 {
 440         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 441         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 442         struct ecore_sp_vport_update_params params;
 443         struct ecore_hwfn *p_hwfn;
 444         uint8_t i;
 445         int rc = -1;
 446
 447         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 448         params.vport_id = 0;
 449         params.update_vport_active_rx_flg = 1;
 450         params.update_vport_active_tx_flg = 1;
 451         params.vport_active_rx_flg = flg;
 452         params.vport_active_tx_flg = flg;
 453         if (~qdev->enable_tx_switching & flg) {
 454                 params.update_tx_switching_flg = 1;
 455                 params.tx_switching_flg = !flg;
 456         }
 457         for_each_hwfn(edev, i) {
 458                 p_hwfn = &edev->hwfns[i];
 459                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 460                 rc = ecore_sp_vport_update(p_hwfn, &params,
 461                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 462                 if (rc != ECORE_SUCCESS) {
 463                         DP_ERR(edev, "Failed to update vport\n");
 464                         break;
 465                 }
 466         }
 467         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 468
 469         return rc;
 470 }
 471
 472 static void
 473 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 474                            uint16_t mtu, bool enable)
 475 {
 476         /* Enable LRO in split mode */
 477         sge_tpa_params->tpa_ipv4_en_flg = enable;
 478         sge_tpa_params->tpa_ipv6_en_flg = enable;
 479         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 480         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 481         /* set if tpa enable changes */
 482         sge_tpa_params->update_tpa_en_flg = 1;
 483         /* set if tpa parameters should be handled */
 484         sge_tpa_params->update_tpa_param_flg = enable;
 485
 486         sge_tpa_params->max_buffers_per_cqe = 20;
 487         /* Enable TPA in split mode. In this mode each TPA segment
 488          * starts on the new BD, so there is one BD per segment.
 489          */
 490         sge_tpa_params->tpa_pkt_split_flg = 1;
 491         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 492         sge_tpa_params->tpa_gro_consistent_flg = 0;
 493         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 494         sge_tpa_params->tpa_max_size = 0x7FFF;
 495         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 496         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 497 }
 498
 499 /* Enable/disable LRO via vport-update */
 500 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 501 {
 502         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 503         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 504         struct ecore_sp_vport_update_params params;
 505         struct ecore_sge_tpa_params tpa_params;
 506         struct ecore_hwfn *p_hwfn;
 507         int rc;
 508         int i;
 509
 510         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 511         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 512         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 513         params.vport_id = 0;
 514         params.sge_tpa_params = &tpa_params;
 515         for_each_hwfn(edev, i) {
 516                 p_hwfn = &edev->hwfns[i];
 517                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 518                 rc = ecore_sp_vport_update(p_hwfn, &params,
 519                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 520                 if (rc != ECORE_SUCCESS) {
 521                         DP_ERR(edev, "Failed to update LRO\n");
 522                         return -1;
 523                 }
 524         }
 525         qdev->enable_lro = flg;
 526         eth_dev->data->lro = flg;
 527
 528         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 529
 530         return 0;
 531 }
 532
 533 static int
 534 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 535                              enum qed_filter_rx_mode_type type)
 536 {
 537         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 538         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 539         struct ecore_filter_accept_flags flags;
 540
 541         memset(&flags, 0, sizeof(flags));
 542
 543         flags.update_rx_mode_config = 1;
 544         flags.update_tx_mode_config = 1;
 545         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 546                 ECORE_ACCEPT_MCAST_MATCHED |
 547                 ECORE_ACCEPT_BCAST;
 548
 549         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 550                 ECORE_ACCEPT_MCAST_MATCHED |
 551                 ECORE_ACCEPT_BCAST;
 552
 553         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 554                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 555                 if (IS_VF(edev)) {
 556                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 557                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 558                 }
 559         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 560                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 561         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 562                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 563                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 564                         ECORE_ACCEPT_MCAST_UNMATCHED;
 565         }
 566
 567         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 568                         ECORE_SPQ_MODE_CB, NULL);
 569 }
 570
 571 int
 572 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 573                   bool add)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct qede_ucast_entry *tmp = NULL;
 578         struct qede_ucast_entry *u;
 579         struct rte_ether_addr *mac_addr;
 580
 581         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 582         if (add) {
 583                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 584                         if ((memcmp(mac_addr, &tmp->mac,
 585                                     RTE_ETHER_ADDR_LEN) == 0) &&
 586                              ucast->vni == tmp->vni &&
 587                              ucast->vlan == tmp->vlan) {
 588                                 DP_INFO(edev, "Unicast MAC is already added"
 589                                         " with vlan = %u, vni = %u\n",
 590                                         ucast->vlan,  ucast->vni);
 591                                         return 0;
 592                         }
 593                 }
 594                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 595                                RTE_CACHE_LINE_SIZE);
 596                 if (!u) {
 597                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 598                         return -ENOMEM;
 599                 }
 600                 rte_ether_addr_copy(mac_addr, &u->mac);
 601                 u->vlan = ucast->vlan;
 602                 u->vni = ucast->vni;
 603                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 604                 qdev->num_uc_addr++;
 605         } else {
 606                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 607                         if ((memcmp(mac_addr, &tmp->mac,
 608                                     RTE_ETHER_ADDR_LEN) == 0) &&
 609                             ucast->vlan == tmp->vlan      &&
 610                             ucast->vni == tmp->vni)
 611                         break;
 612                 }
 613                 if (tmp == NULL) {
 614                         DP_INFO(edev, "Unicast MAC is not found\n");
 615                         return -EINVAL;
 616                 }
 617                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 618                 qdev->num_uc_addr--;
 619         }
 620
 621         return 0;
 622 }
 623
 624 static int
 625 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 626                 struct rte_ether_addr *mc_addrs,
 627                 uint32_t mc_addrs_num)
 628 {
 629         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 630         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 631         struct ecore_filter_mcast mcast;
 632         struct qede_mcast_entry *m = NULL;
 633         uint8_t i;
 634         int rc;
 635
 636         for (i = 0; i < mc_addrs_num; i++) {
 637                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 638                                RTE_CACHE_LINE_SIZE);
 639                 if (!m) {
 640                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 641                         return -ENOMEM;
 642                 }
 643                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 644                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 645         }
 646         memset(&mcast, 0, sizeof(mcast));
 647         mcast.num_mc_addrs = mc_addrs_num;
 648         mcast.opcode = ECORE_FILTER_ADD;
 649         for (i = 0; i < mc_addrs_num; i++)
 650                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 651                                                         &mcast.mac[i]);
 652         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 653         if (rc != ECORE_SUCCESS) {
 654                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 655                 return -1;
 656         }
 657
 658         return 0;
 659 }
 660
 661 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 662 {
 663         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 664         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 665         struct qede_mcast_entry *tmp = NULL;
 666         struct ecore_filter_mcast mcast;
 667         int j;
 668         int rc;
 669
 670         memset(&mcast, 0, sizeof(mcast));
 671         mcast.num_mc_addrs = qdev->num_mc_addr;
 672         mcast.opcode = ECORE_FILTER_REMOVE;
 673         j = 0;
 674         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 675                 rte_ether_addr_copy(&tmp->mac,
 676                                 (struct rte_ether_addr *)&mcast.mac[j]);
 677                 j++;
 678         }
 679         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 680         if (rc != ECORE_SUCCESS) {
 681                 DP_ERR(edev, "Failed to delete multicast filter\n");
 682                 return -1;
 683         }
 684         /* Init the list */
 685         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 686                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 687                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 688         }
 689         SLIST_INIT(&qdev->mc_list_head);
 690
 691         return 0;
 692 }
 693
 694 enum _ecore_status_t
 695 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 696                  bool add)
 697 {
 698         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 699         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 700         enum _ecore_status_t rc = ECORE_INVAL;
 701
 702         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 703                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 704                               " Please enable promisc mode\n");
 705                         return ECORE_INVAL;
 706         }
 707
 708         rc = qede_ucast_filter(eth_dev, ucast, add);
 709         if (rc == 0)
 710                 rc = ecore_filter_ucast_cmd(edev, ucast,
 711                                             ECORE_SPQ_MODE_CB, NULL);
 712         /* Indicate error only for add filter operation.
 713          * Delete filter operations are not severe.
 714          */
 715         if ((rc != ECORE_SUCCESS) && add)
 716                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 717                        rc, add);
 718
 719         return rc;
 720 }
 721
 722 static int
 723 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 724                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 725 {
 726         struct ecore_filter_ucast ucast;
 727         int re;
 728
 729         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 730                 return -EINVAL;
 731
 732         qede_set_ucast_cmn_params(&ucast);
 733         ucast.opcode = ECORE_FILTER_ADD;
 734         ucast.type = ECORE_FILTER_MAC;
 735         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 736         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 737         return re;
 738 }
 739
 740 static void
 741 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 742 {
 743         struct qede_dev *qdev = eth_dev->data->dev_private;
 744         struct ecore_dev *edev = &qdev->edev;
 745         struct ecore_filter_ucast ucast;
 746
 747         PMD_INIT_FUNC_TRACE(edev);
 748
 749         if (index >= qdev->dev_info.num_mac_filters) {
 750                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 751                        index, qdev->dev_info.num_mac_filters);
 752                 return;
 753         }
 754
 755         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 756                 return;
 757
 758         qede_set_ucast_cmn_params(&ucast);
 759         ucast.opcode = ECORE_FILTER_REMOVE;
 760         ucast.type = ECORE_FILTER_MAC;
 761
 762         /* Use the index maintained by rte */
 763         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 764                         (struct rte_ether_addr *)&ucast.mac);
 765
 766         qede_mac_int_ops(eth_dev, &ucast, false);
 767 }
 768
 769 static int
 770 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 771 {
 772         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 773         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 774
 775         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 776                                                mac_addr->addr_bytes)) {
 777                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 778                 return -EPERM;
 779         }
 780
 781         qede_mac_addr_remove(eth_dev, 0);
 782
 783         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 784 }
 785
 786 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 787 {
 788         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 789         struct ecore_sp_vport_update_params params;
 790         struct ecore_hwfn *p_hwfn;
 791         uint8_t i;
 792         int rc;
 793
 794         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 795         params.vport_id = 0;
 796         params.update_accept_any_vlan_flg = 1;
 797         params.accept_any_vlan = flg;
 798         for_each_hwfn(edev, i) {
 799                 p_hwfn = &edev->hwfns[i];
 800                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 801                 rc = ecore_sp_vport_update(p_hwfn, &params,
 802                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 803                 if (rc != ECORE_SUCCESS) {
 804                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 805                         return;
 806                 }
 807         }
 808
 809         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 810 }
 811
 812 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 813 {
 814         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 815         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 816         struct ecore_sp_vport_update_params params;
 817         struct ecore_hwfn *p_hwfn;
 818         uint8_t i;
 819         int rc;
 820
 821         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 822         params.vport_id = 0;
 823         params.update_inner_vlan_removal_flg = 1;
 824         params.inner_vlan_removal_flg = flg;
 825         for_each_hwfn(edev, i) {
 826                 p_hwfn = &edev->hwfns[i];
 827                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 828                 rc = ecore_sp_vport_update(p_hwfn, &params,
 829                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 830                 if (rc != ECORE_SUCCESS) {
 831                         DP_ERR(edev, "Failed to update vport\n");
 832                         return -1;
 833                 }
 834         }
 835
 836         qdev->vlan_strip_flg = flg;
 837
 838         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 839         return 0;
 840 }
 841
 842 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 843                                 uint16_t vlan_id, int on)
 844 {
 845         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 846         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 847         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 848         struct qede_vlan_entry *tmp = NULL;
 849         struct qede_vlan_entry *vlan;
 850         struct ecore_filter_ucast ucast;
 851         int rc;
 852
 853         if (on) {
 854                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 855                         DP_ERR(edev, "Reached max VLAN filter limit"
 856                                       " enabling accept_any_vlan\n");
 857                         qede_config_accept_any_vlan(qdev, true);
 858                         return 0;
 859                 }
 860
 861                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 862                         if (tmp->vid == vlan_id) {
 863                                 DP_INFO(edev, "VLAN %u already configured\n",
 864                                         vlan_id);
 865                                 return 0;
 866                         }
 867                 }
 868
 869                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 870                                   RTE_CACHE_LINE_SIZE);
 871
 872                 if (!vlan) {
 873                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 874                         return -ENOMEM;
 875                 }
 876
 877                 qede_set_ucast_cmn_params(&ucast);
 878                 ucast.opcode = ECORE_FILTER_ADD;
 879                 ucast.type = ECORE_FILTER_VLAN;
 880                 ucast.vlan = vlan_id;
 881                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 882                                             NULL);
 883                 if (rc != 0) {
 884                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 885                                rc);
 886                         rte_free(vlan);
 887                 } else {
 888                         vlan->vid = vlan_id;
 889                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 890                         qdev->configured_vlans++;
 891                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 892                                 vlan_id, qdev->configured_vlans);
 893                 }
 894         } else {
 895                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 896                         if (tmp->vid == vlan_id)
 897                                 break;
 898                 }
 899
 900                 if (!tmp) {
 901                         if (qdev->configured_vlans == 0) {
 902                                 DP_INFO(edev,
 903                                         "No VLAN filters configured yet\n");
 904                                 return 0;
 905                         }
 906
 907                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 908                         return -EINVAL;
 909                 }
 910
 911                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 912
 913                 qede_set_ucast_cmn_params(&ucast);
 914                 ucast.opcode = ECORE_FILTER_REMOVE;
 915                 ucast.type = ECORE_FILTER_VLAN;
 916                 ucast.vlan = vlan_id;
 917                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 918                                             NULL);
 919                 if (rc != 0) {
 920                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 921                                vlan_id, rc);
 922                 } else {
 923                         qdev->configured_vlans--;
 924                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 925                                 vlan_id, qdev->configured_vlans);
 926                 }
 927         }
 928
 929         return rc;
 930 }
 931
 932 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 933 {
 934         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 935         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 936         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 937
 938         if (mask & ETH_VLAN_STRIP_MASK) {
 939                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 940                         (void)qede_vlan_stripping(eth_dev, 1);
 941                 else
 942                         (void)qede_vlan_stripping(eth_dev, 0);
 943         }
 944
 945         if (mask & ETH_VLAN_FILTER_MASK) {
 946                 /* VLAN filtering kicks in when a VLAN is added */
 947                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 948                         qede_vlan_filter_set(eth_dev, 0, 1);
 949                 } else {
 950                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 951                                 DP_ERR(edev,
 952                                   " Please remove existing VLAN filters"
 953                                   " before disabling VLAN filtering\n");
 954                                 /* Signal app that VLAN filtering is still
 955                                  * enabled
 956                                  */
 957                                 eth_dev->data->dev_conf.rxmode.offloads |=
 958                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 959                         } else {
 960                                 qede_vlan_filter_set(eth_dev, 0, 0);
 961                         }
 962                 }
 963         }
 964
 965         if (mask & ETH_VLAN_EXTEND_MASK)
 966                 DP_ERR(edev, "Extend VLAN not supported\n");
 967
 968         qdev->vlan_offload_mask = mask;
 969
 970         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 971
 972         return 0;
 973 }
 974
 975 static void qede_prandom_bytes(uint32_t *buff)
 976 {
 977         uint8_t i;
 978
 979         srand((unsigned int)time(NULL));
 980         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 981                 buff[i] = rand();
 982 }
 983
 984 int qede_config_rss(struct rte_eth_dev *eth_dev)
 985 {
 986         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 987         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 988         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 989         struct rte_eth_rss_reta_entry64 reta_conf[2];
 990         struct rte_eth_rss_conf rss_conf;
 991         uint32_t i, id, pos, q;
 992
 993         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 994         if (!rss_conf.rss_key) {
 995                 DP_INFO(edev, "Applying driver default key\n");
 996                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 997                 qede_prandom_bytes(&def_rss_key[0]);
 998                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 999         }
1000
1001         /* Configure RSS hash */
1002         if (qede_rss_hash_update(eth_dev, &rss_conf))
1003                 return -EINVAL;
1004
1005         /* Configure default RETA */
1006         memset(reta_conf, 0, sizeof(reta_conf));
1007         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1008                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1009
1010         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1011                 id = i / RTE_RETA_GROUP_SIZE;
1012                 pos = i % RTE_RETA_GROUP_SIZE;
1013                 q = i % QEDE_RSS_COUNT(eth_dev);
1014                 reta_conf[id].reta[pos] = q;
1015         }
1016         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1017                                  ECORE_RSS_IND_TABLE_SIZE))
1018                 return -EINVAL;
1019
1020         return 0;
1021 }
1022
1023 static void qede_fastpath_start(struct ecore_dev *edev)
1024 {
1025         struct ecore_hwfn *p_hwfn;
1026         int i;
1027
1028         for_each_hwfn(edev, i) {
1029                 p_hwfn = &edev->hwfns[i];
1030                 ecore_hw_start_fastpath(p_hwfn);
1031         }
1032 }
1033
1034 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1035 {
1036         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1037         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1038         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1039
1040         PMD_INIT_FUNC_TRACE(edev);
1041
1042         /* Update MTU only if it has changed */
1043         if (qdev->new_mtu && qdev->new_mtu != qdev->mtu) {
1044                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1045                         goto err;
1046                 qdev->mtu = qdev->new_mtu;
1047                 qdev->new_mtu = 0;
1048         }
1049
1050         /* Configure TPA parameters */
1051         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1052                 if (qede_enable_tpa(eth_dev, true))
1053                         return -EINVAL;
1054                 /* Enable scatter mode for LRO */
1055                 if (!eth_dev->data->scattered_rx)
1056                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1057         }
1058
1059         /* Start queues */
1060         if (qede_start_queues(eth_dev))
1061                 goto err;
1062
1063         if (IS_PF(edev))
1064                 qede_reset_queue_stats(qdev, true);
1065
1066         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1067          * enabling RSS. Hence RSS configuration is deferred upto this point.
1068          * Also, we would like to retain similar behavior in PF case, so we
1069          * don't do PF/VF specific check here.
1070          */
1071         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1072                 if (qede_config_rss(eth_dev))
1073                         goto err;
1074
1075         /* Enable vport*/
1076         if (qede_activate_vport(eth_dev, true))
1077                 goto err;
1078
1079         /* Update link status */
1080         qede_link_update(eth_dev, 0);
1081
1082         /* Start/resume traffic */
1083         qede_fastpath_start(edev);
1084
1085         DP_INFO(edev, "Device started\n");
1086
1087         return 0;
1088 err:
1089         DP_ERR(edev, "Device start fails\n");
1090         return -1; /* common error code is < 0 */
1091 }
1092
1093 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1094 {
1095         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1096         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1097
1098         PMD_INIT_FUNC_TRACE(edev);
1099
1100         /* Disable vport */
1101         if (qede_activate_vport(eth_dev, false))
1102                 return;
1103
1104         if (qdev->enable_lro)
1105                 qede_enable_tpa(eth_dev, false);
1106
1107         /* Stop queues */
1108         qede_stop_queues(eth_dev);
1109
1110         /* Disable traffic */
1111         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1112
1113         DP_INFO(edev, "Device is stopped\n");
1114 }
1115
1116 static const char * const valid_args[] = {
1117         QEDE_NPAR_TX_SWITCHING,
1118         QEDE_VF_TX_SWITCHING,
1119         NULL,
1120 };
1121
1122 static int qede_args_check(const char *key, const char *val, void *opaque)
1123 {
1124         unsigned long tmp;
1125         int ret = 0;
1126         struct rte_eth_dev *eth_dev = opaque;
1127         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1128         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1129
1130         errno = 0;
1131         tmp = strtoul(val, NULL, 0);
1132         if (errno) {
1133                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1134                 return errno;
1135         }
1136
1137         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1138             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1139                 qdev->enable_tx_switching = !!tmp;
1140                 DP_INFO(edev, "Disabling %s tx-switching\n",
1141                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1142                         "VF" : "NPAR");
1143         }
1144
1145         return ret;
1146 }
1147
1148 static int qede_args(struct rte_eth_dev *eth_dev)
1149 {
1150         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1151         struct rte_kvargs *kvlist;
1152         struct rte_devargs *devargs;
1153         int ret;
1154         int i;
1155
1156         devargs = pci_dev->device.devargs;
1157         if (!devargs)
1158                 return 0; /* return success */
1159
1160         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1161         if (kvlist == NULL)
1162                 return -EINVAL;
1163
1164          /* Process parameters. */
1165         for (i = 0; (valid_args[i] != NULL); ++i) {
1166                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1167                         ret = rte_kvargs_process(kvlist, valid_args[i],
1168                                                  qede_args_check, eth_dev);
1169                         if (ret != ECORE_SUCCESS) {
1170                                 rte_kvargs_free(kvlist);
1171                                 return ret;
1172                         }
1173                 }
1174         }
1175         rte_kvargs_free(kvlist);
1176
1177         return 0;
1178 }
1179
1180 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1181 {
1182         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1183         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1184         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1185         int ret;
1186
1187         PMD_INIT_FUNC_TRACE(edev);
1188
1189         rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1190
1191         /* We need to have min 1 RX queue.There is no min check in
1192          * rte_eth_dev_configure(), so we are checking it here.
1193          */
1194         if (eth_dev->data->nb_rx_queues == 0) {
1195                 DP_ERR(edev, "Minimum one RX queue is required\n");
1196                 return -EINVAL;
1197         }
1198
1199         /* Enable Tx switching by default */
1200         qdev->enable_tx_switching = 1;
1201
1202         /* Parse devargs and fix up rxmode */
1203         if (qede_args(eth_dev))
1204                 DP_NOTICE(edev, false,
1205                           "Invalid devargs supplied, requested change will not take effect\n");
1206
1207         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1208               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1209                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1210                 return -ENOTSUP;
1211         }
1212         /* Flow director mode check */
1213         if (qede_check_fdir_support(eth_dev))
1214                 return -ENOTSUP;
1215
1216         qede_dealloc_fp_resc(eth_dev);
1217         qdev->num_tx_queues = eth_dev->data->nb_tx_queues * edev->num_hwfns;
1218         qdev->num_rx_queues = eth_dev->data->nb_rx_queues * edev->num_hwfns;
1219
1220         if (qede_alloc_fp_resc(qdev))
1221                 return -ENOMEM;
1222
1223         /* If jumbo enabled adjust MTU */
1224         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1225                 eth_dev->data->mtu =
1226                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1227                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1228
1229         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1230                 eth_dev->data->scattered_rx = 1;
1231
1232         if (qede_start_vport(qdev, eth_dev->data->mtu))
1233                 return -1;
1234
1235         qdev->mtu = eth_dev->data->mtu;
1236
1237         /* Enable VLAN offloads by default */
1238         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1239                                              ETH_VLAN_FILTER_MASK);
1240         if (ret)
1241                 return ret;
1242
1243         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1244                         QEDE_RSS_COUNT(eth_dev), QEDE_TSS_COUNT(eth_dev));
1245
1246         if (ECORE_IS_CMT(edev))
1247                 DP_INFO(edev, "Actual HW queues for CMT mode - RX = %d TX = %d\n",
1248                         qdev->num_rx_queues, qdev->num_tx_queues);
1249
1250
1251         return 0;
1252 }
1253
1254 /* Info about HW descriptor ring limitations */
1255 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1256         .nb_max = 0x8000, /* 32K */
1257         .nb_min = 128,
1258         .nb_align = 128 /* lowest common multiple */
1259 };
1260
1261 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1262         .nb_max = 0x8000, /* 32K */
1263         .nb_min = 256,
1264         .nb_align = 256,
1265         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1266         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1267 };
1268
1269 static int
1270 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1271                   struct rte_eth_dev_info *dev_info)
1272 {
1273         struct qede_dev *qdev = eth_dev->data->dev_private;
1274         struct ecore_dev *edev = &qdev->edev;
1275         struct qed_link_output link;
1276         uint32_t speed_cap = 0;
1277
1278         PMD_INIT_FUNC_TRACE(edev);
1279
1280         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1281         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1282         dev_info->rx_desc_lim = qede_rx_desc_lim;
1283         dev_info->tx_desc_lim = qede_tx_desc_lim;
1284
1285         if (IS_PF(edev))
1286                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1287                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1288         else
1289                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1290                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1291         /* Since CMT mode internally doubles the number of queues */
1292         if (ECORE_IS_CMT(edev))
1293                 dev_info->max_rx_queues  = dev_info->max_rx_queues / 2;
1294
1295         dev_info->max_tx_queues = dev_info->max_rx_queues;
1296
1297         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1298         dev_info->max_vfs = 0;
1299         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1300         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1301         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1302         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1303                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1304                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1305                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1306                                      DEV_RX_OFFLOAD_TCP_LRO     |
1307                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1308                                      DEV_RX_OFFLOAD_SCATTER     |
1309                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1310                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1311                                      DEV_RX_OFFLOAD_VLAN_STRIP  |
1312                                      DEV_RX_OFFLOAD_RSS_HASH);
1313         dev_info->rx_queue_offload_capa = 0;
1314
1315         /* TX offloads are on a per-packet basis, so it is applicable
1316          * to both at port and queue levels.
1317          */
1318         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1319                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1320                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1321                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1322                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1323                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1324                                      DEV_TX_OFFLOAD_TCP_TSO     |
1325                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1326                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1327         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1328
1329         dev_info->default_txconf = (struct rte_eth_txconf) {
1330                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1331         };
1332
1333         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1334                 /* Packets are always dropped if no descriptors are available */
1335                 .rx_drop_en = 1,
1336                 .offloads = 0,
1337         };
1338
1339         memset(&link, 0, sizeof(struct qed_link_output));
1340         qdev->ops->common->get_link(edev, &link);
1341         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1342                 speed_cap |= ETH_LINK_SPEED_1G;
1343         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1344                 speed_cap |= ETH_LINK_SPEED_10G;
1345         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1346                 speed_cap |= ETH_LINK_SPEED_25G;
1347         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1348                 speed_cap |= ETH_LINK_SPEED_40G;
1349         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1350                 speed_cap |= ETH_LINK_SPEED_50G;
1351         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1352                 speed_cap |= ETH_LINK_SPEED_100G;
1353         dev_info->speed_capa = speed_cap;
1354
1355         return 0;
1356 }
1357
1358 /* return 0 means link status changed, -1 means not changed */
1359 int
1360 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1361 {
1362         struct qede_dev *qdev = eth_dev->data->dev_private;
1363         struct ecore_dev *edev = &qdev->edev;
1364         struct qed_link_output q_link;
1365         struct rte_eth_link link;
1366         uint16_t link_duplex;
1367
1368         memset(&q_link, 0, sizeof(q_link));
1369         memset(&link, 0, sizeof(link));
1370
1371         qdev->ops->common->get_link(edev, &q_link);
1372
1373         /* Link Speed */
1374         link.link_speed = q_link.speed;
1375
1376         /* Link Mode */
1377         switch (q_link.duplex) {
1378         case QEDE_DUPLEX_HALF:
1379                 link_duplex = ETH_LINK_HALF_DUPLEX;
1380                 break;
1381         case QEDE_DUPLEX_FULL:
1382                 link_duplex = ETH_LINK_FULL_DUPLEX;
1383                 break;
1384         case QEDE_DUPLEX_UNKNOWN:
1385         default:
1386                 link_duplex = -1;
1387         }
1388         link.link_duplex = link_duplex;
1389
1390         /* Link Status */
1391         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1392
1393         /* AN */
1394         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1395                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1396
1397         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1398                 link.link_speed, link.link_duplex,
1399                 link.link_autoneg, link.link_status);
1400
1401         return rte_eth_linkstatus_set(eth_dev, &link);
1402 }
1403
1404 static int qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1405 {
1406         struct qede_dev *qdev = eth_dev->data->dev_private;
1407         struct ecore_dev *edev = &qdev->edev;
1408         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1409         enum _ecore_status_t ecore_status;
1410
1411         PMD_INIT_FUNC_TRACE(edev);
1412
1413         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1414                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1415
1416         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1417
1418         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1419 }
1420
1421 static int qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1422 {
1423         struct qede_dev *qdev = eth_dev->data->dev_private;
1424         struct ecore_dev *edev = &qdev->edev;
1425         enum _ecore_status_t ecore_status;
1426
1427         PMD_INIT_FUNC_TRACE(edev);
1428
1429         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1430                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1431                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1432         else
1433                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1434                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1435
1436         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1437 }
1438
1439 static void qede_poll_sp_sb_cb(void *param)
1440 {
1441         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1442         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1443         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1444         int rc;
1445
1446         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1447         qede_interrupt_action(&edev->hwfns[1]);
1448
1449         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1450                                qede_poll_sp_sb_cb,
1451                                (void *)eth_dev);
1452         if (rc != 0) {
1453                 DP_ERR(edev, "Unable to start periodic"
1454                              " timer rc %d\n", rc);
1455         }
1456 }
1457
1458 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1459 {
1460         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1461         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1462         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1463
1464         PMD_INIT_FUNC_TRACE(edev);
1465
1466         /* dev_stop() shall cleanup fp resources in hw but without releasing
1467          * dma memories and sw structures so that dev_start() can be called
1468          * by the app without reconfiguration. However, in dev_close() we
1469          * can release all the resources and device can be brought up newly
1470          */
1471         if (eth_dev->data->dev_started)
1472                 qede_dev_stop(eth_dev);
1473
1474         qede_stop_vport(edev);
1475         qdev->vport_started = false;
1476         qede_fdir_dealloc_resc(eth_dev);
1477         qede_dealloc_fp_resc(eth_dev);
1478
1479         eth_dev->data->nb_rx_queues = 0;
1480         eth_dev->data->nb_tx_queues = 0;
1481
1482         /* Bring the link down */
1483         qede_dev_set_link_state(eth_dev, false);
1484         qdev->ops->common->slowpath_stop(edev);
1485         qdev->ops->common->remove(edev);
1486         rte_intr_disable(&pci_dev->intr_handle);
1487
1488         switch (pci_dev->intr_handle.type) {
1489         case RTE_INTR_HANDLE_UIO_INTX:
1490         case RTE_INTR_HANDLE_VFIO_LEGACY:
1491                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1492                                              qede_interrupt_handler_intx,
1493                                              (void *)eth_dev);
1494                 break;
1495         default:
1496                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1497                                            qede_interrupt_handler,
1498                                            (void *)eth_dev);
1499         }
1500
1501         if (ECORE_IS_CMT(edev))
1502                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1503 }
1504
1505 static int
1506 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1507 {
1508         struct qede_dev *qdev = eth_dev->data->dev_private;
1509         struct ecore_dev *edev = &qdev->edev;
1510         struct ecore_eth_stats stats;
1511         unsigned int i = 0, j = 0, qid, idx, hw_fn;
1512         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1513         struct qede_tx_queue *txq;
1514
1515         ecore_get_vport_stats(edev, &stats);
1516
1517         /* RX Stats */
1518         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1519             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1520
1521         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1522             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1523
1524         eth_stats->ierrors = stats.common.rx_crc_errors +
1525             stats.common.rx_align_errors +
1526             stats.common.rx_carrier_errors +
1527             stats.common.rx_oversize_packets +
1528             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1529
1530         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1531
1532         eth_stats->imissed = stats.common.mftag_filter_discards +
1533             stats.common.mac_filter_discards +
1534             stats.common.no_buff_discards +
1535             stats.common.brb_truncates + stats.common.brb_discards;
1536
1537         /* TX stats */
1538         eth_stats->opackets = stats.common.tx_ucast_pkts +
1539             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1540
1541         eth_stats->obytes = stats.common.tx_ucast_bytes +
1542             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1543
1544         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1545
1546         /* Queue stats */
1547         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(eth_dev),
1548                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1549         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(eth_dev),
1550                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1551         if (rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(eth_dev) ||
1552             txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(eth_dev))
1553                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1554                        "Not all the queue stats will be displayed. Set"
1555                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1556                        " appropriately and retry.\n");
1557
1558         for (qid = 0; qid < eth_dev->data->nb_rx_queues; qid++) {
1559                 eth_stats->q_ipackets[i] = 0;
1560                 eth_stats->q_errors[i] = 0;
1561
1562                 for_each_hwfn(edev, hw_fn) {
1563                         idx = qid * edev->num_hwfns + hw_fn;
1564
1565                         eth_stats->q_ipackets[i] +=
1566                                 *(uint64_t *)
1567                                         (((char *)(qdev->fp_array[idx].rxq)) +
1568                                          offsetof(struct qede_rx_queue,
1569                                          rcv_pkts));
1570                         eth_stats->q_errors[i] +=
1571                                 *(uint64_t *)
1572                                         (((char *)(qdev->fp_array[idx].rxq)) +
1573                                          offsetof(struct qede_rx_queue,
1574                                          rx_hw_errors)) +
1575                                 *(uint64_t *)
1576                                         (((char *)(qdev->fp_array[idx].rxq)) +
1577                                          offsetof(struct qede_rx_queue,
1578                                          rx_alloc_errors));
1579                 }
1580
1581                 i++;
1582                 if (i == rxq_stat_cntrs)
1583                         break;
1584         }
1585
1586         for (qid = 0; qid < eth_dev->data->nb_tx_queues; qid++) {
1587                 eth_stats->q_opackets[j] = 0;
1588
1589                 for_each_hwfn(edev, hw_fn) {
1590                         idx = qid * edev->num_hwfns + hw_fn;
1591
1592                         txq = qdev->fp_array[idx].txq;
1593                         eth_stats->q_opackets[j] +=
1594                                 *((uint64_t *)(uintptr_t)
1595                                         (((uint64_t)(uintptr_t)(txq)) +
1596                                          offsetof(struct qede_tx_queue,
1597                                                   xmit_pkts)));
1598                 }
1599
1600                 j++;
1601                 if (j == txq_stat_cntrs)
1602                         break;
1603         }
1604
1605         return 0;
1606 }
1607
1608 static unsigned
1609 qede_get_xstats_count(struct qede_dev *qdev) {
1610         struct rte_eth_dev *dev = (struct rte_eth_dev *)qdev->ethdev;
1611
1612         if (ECORE_IS_BB(&qdev->edev))
1613                 return RTE_DIM(qede_xstats_strings) +
1614                        RTE_DIM(qede_bb_xstats_strings) +
1615                        (RTE_DIM(qede_rxq_xstats_strings) *
1616                         QEDE_RSS_COUNT(dev) * qdev->edev.num_hwfns);
1617         else
1618                 return RTE_DIM(qede_xstats_strings) +
1619                        RTE_DIM(qede_ah_xstats_strings) +
1620                        (RTE_DIM(qede_rxq_xstats_strings) *
1621                         QEDE_RSS_COUNT(dev));
1622 }
1623
1624 static int
1625 qede_get_xstats_names(struct rte_eth_dev *dev,
1626                       struct rte_eth_xstat_name *xstats_names,
1627                       __rte_unused unsigned int limit)
1628 {
1629         struct qede_dev *qdev = dev->data->dev_private;
1630         struct ecore_dev *edev = &qdev->edev;
1631         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1632         unsigned int i, qid, hw_fn, stat_idx = 0;
1633
1634         if (xstats_names == NULL)
1635                 return stat_cnt;
1636
1637         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1638                 strlcpy(xstats_names[stat_idx].name,
1639                         qede_xstats_strings[i].name,
1640                         sizeof(xstats_names[stat_idx].name));
1641                 stat_idx++;
1642         }
1643
1644         if (ECORE_IS_BB(edev)) {
1645                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1646                         strlcpy(xstats_names[stat_idx].name,
1647                                 qede_bb_xstats_strings[i].name,
1648                                 sizeof(xstats_names[stat_idx].name));
1649                         stat_idx++;
1650                 }
1651         } else {
1652                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1653                         strlcpy(xstats_names[stat_idx].name,
1654                                 qede_ah_xstats_strings[i].name,
1655                                 sizeof(xstats_names[stat_idx].name));
1656                         stat_idx++;
1657                 }
1658         }
1659
1660         for (qid = 0; qid < QEDE_RSS_COUNT(dev); qid++) {
1661                 for_each_hwfn(edev, hw_fn) {
1662                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1663                                 snprintf(xstats_names[stat_idx].name,
1664                                          RTE_ETH_XSTATS_NAME_SIZE,
1665                                          "%.4s%d.%d%s",
1666                                          qede_rxq_xstats_strings[i].name,
1667                                          hw_fn, qid,
1668                                          qede_rxq_xstats_strings[i].name + 4);
1669                                 stat_idx++;
1670                         }
1671                 }
1672         }
1673
1674         return stat_cnt;
1675 }
1676
1677 static int
1678 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1679                 unsigned int n)
1680 {
1681         struct qede_dev *qdev = dev->data->dev_private;
1682         struct ecore_dev *edev = &qdev->edev;
1683         struct ecore_eth_stats stats;
1684         const unsigned int num = qede_get_xstats_count(qdev);
1685         unsigned int i, qid, hw_fn, fpidx, stat_idx = 0;
1686
1687         if (n < num)
1688                 return num;
1689
1690         ecore_get_vport_stats(edev, &stats);
1691
1692         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1693                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1694                                              qede_xstats_strings[i].offset);
1695                 xstats[stat_idx].id = stat_idx;
1696                 stat_idx++;
1697         }
1698
1699         if (ECORE_IS_BB(edev)) {
1700                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1701                         xstats[stat_idx].value =
1702                                         *(uint64_t *)(((char *)&stats) +
1703                                         qede_bb_xstats_strings[i].offset);
1704                         xstats[stat_idx].id = stat_idx;
1705                         stat_idx++;
1706                 }
1707         } else {
1708                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1709                         xstats[stat_idx].value =
1710                                         *(uint64_t *)(((char *)&stats) +
1711                                         qede_ah_xstats_strings[i].offset);
1712                         xstats[stat_idx].id = stat_idx;
1713                         stat_idx++;
1714                 }
1715         }
1716
1717         for (qid = 0; qid < dev->data->nb_rx_queues; qid++) {
1718                 for_each_hwfn(edev, hw_fn) {
1719                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1720                                 fpidx = qid * edev->num_hwfns + hw_fn;
1721                                 xstats[stat_idx].value = *(uint64_t *)
1722                                         (((char *)(qdev->fp_array[fpidx].rxq)) +
1723                                          qede_rxq_xstats_strings[i].offset);
1724                                 xstats[stat_idx].id = stat_idx;
1725                                 stat_idx++;
1726                         }
1727
1728                 }
1729         }
1730
1731         return stat_idx;
1732 }
1733
1734 static int
1735 qede_reset_xstats(struct rte_eth_dev *dev)
1736 {
1737         struct qede_dev *qdev = dev->data->dev_private;
1738         struct ecore_dev *edev = &qdev->edev;
1739
1740         ecore_reset_vport_stats(edev);
1741         qede_reset_queue_stats(qdev, true);
1742
1743         return 0;
1744 }
1745
1746 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1747 {
1748         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1749         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1750         struct qed_link_params link_params;
1751         int rc;
1752
1753         DP_INFO(edev, "setting link state %d\n", link_up);
1754         memset(&link_params, 0, sizeof(link_params));
1755         link_params.link_up = link_up;
1756         rc = qdev->ops->common->set_link(edev, &link_params);
1757         if (rc != ECORE_SUCCESS)
1758                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1759
1760         return rc;
1761 }
1762
1763 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1764 {
1765         return qede_dev_set_link_state(eth_dev, true);
1766 }
1767
1768 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1769 {
1770         return qede_dev_set_link_state(eth_dev, false);
1771 }
1772
1773 static int qede_reset_stats(struct rte_eth_dev *eth_dev)
1774 {
1775         struct qede_dev *qdev = eth_dev->data->dev_private;
1776         struct ecore_dev *edev = &qdev->edev;
1777
1778         ecore_reset_vport_stats(edev);
1779         qede_reset_queue_stats(qdev, false);
1780
1781         return 0;
1782 }
1783
1784 static int qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1785 {
1786         enum qed_filter_rx_mode_type type =
1787             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1788         enum _ecore_status_t ecore_status;
1789
1790         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1791                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1792
1793         ecore_status = qed_configure_filter_rx_mode(eth_dev, type);
1794
1795         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1796 }
1797
1798 static int qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1799 {
1800         enum _ecore_status_t ecore_status;
1801
1802         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1803                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1804                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1805         else
1806                 ecore_status = qed_configure_filter_rx_mode(eth_dev,
1807                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1808
1809         return ecore_status >= ECORE_SUCCESS ? 0 : -EAGAIN;
1810 }
1811
1812 static int
1813 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1814                 struct rte_ether_addr *mc_addrs,
1815                 uint32_t mc_addrs_num)
1816 {
1817         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1818         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1819         uint8_t i;
1820
1821         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1822                 DP_ERR(edev, "Reached max multicast filters limit,"
1823                              "Please enable multicast promisc mode\n");
1824                 return -ENOSPC;
1825         }
1826
1827         for (i = 0; i < mc_addrs_num; i++) {
1828                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1829                         DP_ERR(edev, "Not a valid multicast MAC\n");
1830                         return -EINVAL;
1831                 }
1832         }
1833
1834         /* Flush all existing entries */
1835         if (qede_del_mcast_filters(eth_dev))
1836                 return -1;
1837
1838         /* Set new mcast list */
1839         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1840 }
1841
1842 /* Update MTU via vport-update without doing port restart.
1843  * The vport must be deactivated before calling this API.
1844  */
1845 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1846 {
1847         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1848         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1849         struct ecore_hwfn *p_hwfn;
1850         int rc;
1851         int i;
1852
1853         if (IS_PF(edev)) {
1854                 struct ecore_sp_vport_update_params params;
1855
1856                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1857                 params.vport_id = 0;
1858                 params.mtu = mtu;
1859                 params.vport_id = 0;
1860                 for_each_hwfn(edev, i) {
1861                         p_hwfn = &edev->hwfns[i];
1862                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1863                         rc = ecore_sp_vport_update(p_hwfn, &params,
1864                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1865                         if (rc != ECORE_SUCCESS)
1866                                 goto err;
1867                 }
1868         } else {
1869                 for_each_hwfn(edev, i) {
1870                         p_hwfn = &edev->hwfns[i];
1871                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1872                         if (rc == ECORE_INVAL) {
1873                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1874                                 /* Recreate vport */
1875                                 rc = qede_start_vport(qdev, mtu);
1876                                 if (rc != ECORE_SUCCESS)
1877                                         goto err;
1878
1879                                 /* Restore config lost due to vport stop */
1880                                 if (eth_dev->data->promiscuous)
1881                                         qede_promiscuous_enable(eth_dev);
1882                                 else
1883                                         qede_promiscuous_disable(eth_dev);
1884
1885                                 if (eth_dev->data->all_multicast)
1886                                         qede_allmulticast_enable(eth_dev);
1887                                 else
1888                                         qede_allmulticast_disable(eth_dev);
1889
1890                                 qede_vlan_offload_set(eth_dev,
1891                                                       qdev->vlan_offload_mask);
1892                         } else if (rc != ECORE_SUCCESS) {
1893                                 goto err;
1894                         }
1895                 }
1896         }
1897         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1898
1899         return 0;
1900
1901 err:
1902         DP_ERR(edev, "Failed to update MTU\n");
1903         return -1;
1904 }
1905
1906 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1907                               struct rte_eth_fc_conf *fc_conf)
1908 {
1909         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1910         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1911         struct qed_link_output current_link;
1912         struct qed_link_params params;
1913
1914         memset(&current_link, 0, sizeof(current_link));
1915         qdev->ops->common->get_link(edev, &current_link);
1916
1917         memset(&params, 0, sizeof(params));
1918         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1919         if (fc_conf->autoneg) {
1920                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1921                         DP_ERR(edev, "Autoneg not supported\n");
1922                         return -EINVAL;
1923                 }
1924                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1925         }
1926
1927         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1928         if (fc_conf->mode == RTE_FC_FULL)
1929                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1930                                         QED_LINK_PAUSE_RX_ENABLE);
1931         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1932                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1933         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1934                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1935
1936         params.link_up = true;
1937         (void)qdev->ops->common->set_link(edev, &params);
1938
1939         return 0;
1940 }
1941
1942 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1943                               struct rte_eth_fc_conf *fc_conf)
1944 {
1945         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1946         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1947         struct qed_link_output current_link;
1948
1949         memset(&current_link, 0, sizeof(current_link));
1950         qdev->ops->common->get_link(edev, &current_link);
1951
1952         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1953                 fc_conf->autoneg = true;
1954
1955         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1956                                          QED_LINK_PAUSE_TX_ENABLE))
1957                 fc_conf->mode = RTE_FC_FULL;
1958         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1959                 fc_conf->mode = RTE_FC_RX_PAUSE;
1960         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1961                 fc_conf->mode = RTE_FC_TX_PAUSE;
1962         else
1963                 fc_conf->mode = RTE_FC_NONE;
1964
1965         return 0;
1966 }
1967
1968 static const uint32_t *
1969 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1970 {
1971         static const uint32_t ptypes[] = {
1972                 RTE_PTYPE_L2_ETHER,
1973                 RTE_PTYPE_L2_ETHER_VLAN,
1974                 RTE_PTYPE_L3_IPV4,
1975                 RTE_PTYPE_L3_IPV6,
1976                 RTE_PTYPE_L4_TCP,
1977                 RTE_PTYPE_L4_UDP,
1978                 RTE_PTYPE_TUNNEL_VXLAN,
1979                 RTE_PTYPE_L4_FRAG,
1980                 RTE_PTYPE_TUNNEL_GENEVE,
1981                 RTE_PTYPE_TUNNEL_GRE,
1982                 /* Inner */
1983                 RTE_PTYPE_INNER_L2_ETHER,
1984                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1985                 RTE_PTYPE_INNER_L3_IPV4,
1986                 RTE_PTYPE_INNER_L3_IPV6,
1987                 RTE_PTYPE_INNER_L4_TCP,
1988                 RTE_PTYPE_INNER_L4_UDP,
1989                 RTE_PTYPE_INNER_L4_FRAG,
1990                 RTE_PTYPE_UNKNOWN
1991         };
1992
1993         if (eth_dev->rx_pkt_burst == qede_recv_pkts ||
1994             eth_dev->rx_pkt_burst == qede_recv_pkts_cmt)
1995                 return ptypes;
1996
1997         return NULL;
1998 }
1999
2000 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2001 {
2002         *rss_caps = 0;
2003         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2004         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2005         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2006         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2007         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2008         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2009         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2010         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2011 }
2012
2013 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2014                          struct rte_eth_rss_conf *rss_conf)
2015 {
2016         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2017         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2018         struct ecore_sp_vport_update_params vport_update_params;
2019         struct ecore_rss_params rss_params;
2020         struct ecore_hwfn *p_hwfn;
2021         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2022         uint64_t hf = rss_conf->rss_hf;
2023         uint8_t len = rss_conf->rss_key_len;
2024         uint8_t idx, i, j, fpidx;
2025         int rc;
2026
2027         memset(&vport_update_params, 0, sizeof(vport_update_params));
2028         memset(&rss_params, 0, sizeof(rss_params));
2029
2030         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2031                 (unsigned long)hf, len, key);
2032
2033         if (hf != 0) {
2034                 /* Enabling RSS */
2035                 DP_INFO(edev, "Enabling rss\n");
2036
2037                 /* RSS caps */
2038                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2039                 rss_params.update_rss_capabilities = 1;
2040
2041                 /* RSS hash key */
2042                 if (key) {
2043                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2044                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2045                                 return -EINVAL;
2046                         }
2047                         DP_INFO(edev, "Applying user supplied hash key\n");
2048                         rss_params.update_rss_key = 1;
2049                         memcpy(&rss_params.rss_key, key, len);
2050                 }
2051                 rss_params.rss_enable = 1;
2052         }
2053
2054         rss_params.update_rss_config = 1;
2055         /* tbl_size has to be set with capabilities */
2056         rss_params.rss_table_size_log = 7;
2057         vport_update_params.vport_id = 0;
2058
2059         for_each_hwfn(edev, i) {
2060                 /* pass the L2 handles instead of qids */
2061                 for (j = 0 ; j < ECORE_RSS_IND_TABLE_SIZE ; j++) {
2062                         idx = j % QEDE_RSS_COUNT(eth_dev);
2063                         fpidx = idx * edev->num_hwfns + i;
2064                         rss_params.rss_ind_table[j] =
2065                                 qdev->fp_array[fpidx].rxq->handle;
2066                 }
2067
2068                 vport_update_params.rss_params = &rss_params;
2069
2070                 p_hwfn = &edev->hwfns[i];
2071                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2072                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2073                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2074                 if (rc) {
2075                         DP_ERR(edev, "vport-update for RSS failed\n");
2076                         return rc;
2077                 }
2078         }
2079         qdev->rss_enable = rss_params.rss_enable;
2080
2081         /* Update local structure for hash query */
2082         qdev->rss_conf.rss_hf = hf;
2083         qdev->rss_conf.rss_key_len = len;
2084         if (qdev->rss_enable) {
2085                 if  (qdev->rss_conf.rss_key == NULL) {
2086                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2087                         if (qdev->rss_conf.rss_key == NULL) {
2088                                 DP_ERR(edev, "No memory to store RSS key\n");
2089                                 return -ENOMEM;
2090                         }
2091                 }
2092                 if (key && len) {
2093                         DP_INFO(edev, "Storing RSS key\n");
2094                         memcpy(qdev->rss_conf.rss_key, key, len);
2095                 }
2096         } else if (!qdev->rss_enable && len == 0) {
2097                 if (qdev->rss_conf.rss_key) {
2098                         free(qdev->rss_conf.rss_key);
2099                         qdev->rss_conf.rss_key = NULL;
2100                         DP_INFO(edev, "Free RSS key\n");
2101                 }
2102         }
2103
2104         return 0;
2105 }
2106
2107 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2108                            struct rte_eth_rss_conf *rss_conf)
2109 {
2110         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2111
2112         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2113         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2114
2115         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2116                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2117                        rss_conf->rss_key_len);
2118         return 0;
2119 }
2120
2121 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2122                          struct rte_eth_rss_reta_entry64 *reta_conf,
2123                          uint16_t reta_size)
2124 {
2125         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2126         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2127         struct ecore_sp_vport_update_params vport_update_params;
2128         struct ecore_rss_params *params;
2129         uint16_t i, j, idx, fid, shift;
2130         struct ecore_hwfn *p_hwfn;
2131         uint8_t entry;
2132         int rc = 0;
2133
2134         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2135                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2136                        reta_size);
2137                 return -EINVAL;
2138         }
2139
2140         memset(&vport_update_params, 0, sizeof(vport_update_params));
2141         params = rte_zmalloc("qede_rss", sizeof(*params), RTE_CACHE_LINE_SIZE);
2142         if (params == NULL) {
2143                 DP_ERR(edev, "failed to allocate memory\n");
2144                 return -ENOMEM;
2145         }
2146
2147         params->update_rss_ind_table = 1;
2148         params->rss_table_size_log = 7;
2149         params->update_rss_config = 1;
2150
2151         vport_update_params.vport_id = 0;
2152         /* Use the current value of rss_enable */
2153         params->rss_enable = qdev->rss_enable;
2154         vport_update_params.rss_params = params;
2155
2156         for_each_hwfn(edev, i) {
2157                 for (j = 0; j < reta_size; j++) {
2158                         idx = j / RTE_RETA_GROUP_SIZE;
2159                         shift = j % RTE_RETA_GROUP_SIZE;
2160                         if (reta_conf[idx].mask & (1ULL << shift)) {
2161                                 entry = reta_conf[idx].reta[shift];
2162                                 fid = entry * edev->num_hwfns + i;
2163                                 /* Pass rxq handles to ecore */
2164                                 params->rss_ind_table[j] =
2165                                                 qdev->fp_array[fid].rxq->handle;
2166                                 /* Update the local copy for RETA query cmd */
2167                                 qdev->rss_ind_table[j] = entry;
2168                         }
2169                 }
2170
2171                 p_hwfn = &edev->hwfns[i];
2172                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2173                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2174                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2175                 if (rc) {
2176                         DP_ERR(edev, "vport-update for RSS failed\n");
2177                         goto out;
2178                 }
2179         }
2180
2181 out:
2182         rte_free(params);
2183         return rc;
2184 }
2185
2186 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2187                                struct rte_eth_rss_reta_entry64 *reta_conf,
2188                                uint16_t reta_size)
2189 {
2190         struct qede_dev *qdev = eth_dev->data->dev_private;
2191         struct ecore_dev *edev = &qdev->edev;
2192         uint16_t i, idx, shift;
2193         uint8_t entry;
2194
2195         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2196                 DP_ERR(edev, "reta_size %d is not supported\n",
2197                        reta_size);
2198                 return -EINVAL;
2199         }
2200
2201         for (i = 0; i < reta_size; i++) {
2202                 idx = i / RTE_RETA_GROUP_SIZE;
2203                 shift = i % RTE_RETA_GROUP_SIZE;
2204                 if (reta_conf[idx].mask & (1ULL << shift)) {
2205                         entry = qdev->rss_ind_table[i];
2206                         reta_conf[idx].reta[shift] = entry;
2207                 }
2208         }
2209
2210         return 0;
2211 }
2212
2213
2214
2215 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2216 {
2217         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2218         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2219         struct rte_eth_dev_info dev_info = {0};
2220         struct qede_fastpath *fp;
2221         uint32_t max_rx_pkt_len;
2222         uint32_t frame_size;
2223         uint16_t bufsz;
2224         bool restart = false;
2225         int i, rc;
2226
2227         PMD_INIT_FUNC_TRACE(edev);
2228         rc = qede_dev_info_get(dev, &dev_info);
2229         if (rc != 0) {
2230                 DP_ERR(edev, "Error during getting ethernet device info\n");
2231                 return rc;
2232         }
2233         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2234         frame_size = max_rx_pkt_len;
2235         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2236                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2237                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2238                        QEDE_ETH_OVERHEAD);
2239                 return -EINVAL;
2240         }
2241         if (!dev->data->scattered_rx &&
2242             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2243                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2244                         dev->data->min_rx_buf_size);
2245                 return -EINVAL;
2246         }
2247         /* Temporarily replace I/O functions with dummy ones. It cannot
2248          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2249          */
2250         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2251         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2252         if (dev->data->dev_started) {
2253                 dev->data->dev_started = 0;
2254                 qede_dev_stop(dev);
2255                 restart = true;
2256         }
2257         rte_delay_ms(1000);
2258         qdev->new_mtu = mtu;
2259
2260         /* Fix up RX buf size for all queues of the port */
2261         for (i = 0; i < qdev->num_rx_queues; i++) {
2262                 fp = &qdev->fp_array[i];
2263                 if (fp->rxq != NULL) {
2264                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2265                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2266                         /* cache align the mbuf size to simplfy rx_buf_size
2267                          * calculation
2268                          */
2269                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2270                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2271                         if (rc < 0)
2272                                 return rc;
2273
2274                         fp->rxq->rx_buf_size = rc;
2275                 }
2276         }
2277         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2278                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2279         else
2280                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2281
2282         if (!dev->data->dev_started && restart) {
2283                 qede_dev_start(dev);
2284                 dev->data->dev_started = 1;
2285         }
2286
2287         /* update max frame size */
2288         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2289         /* Reassign back */
2290         if (ECORE_IS_CMT(edev)) {
2291                 dev->rx_pkt_burst = qede_recv_pkts_cmt;
2292                 dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2293         } else {
2294                 dev->rx_pkt_burst = qede_recv_pkts;
2295                 dev->tx_pkt_burst = qede_xmit_pkts;
2296         }
2297         return 0;
2298 }
2299
2300 static int
2301 qede_dev_reset(struct rte_eth_dev *dev)
2302 {
2303         int ret;
2304
2305         ret = qede_eth_dev_uninit(dev);
2306         if (ret)
2307                 return ret;
2308
2309         return qede_eth_dev_init(dev);
2310 }
2311
2312 static const struct eth_dev_ops qede_eth_dev_ops = {
2313         .dev_configure = qede_dev_configure,
2314         .dev_infos_get = qede_dev_info_get,
2315         .rx_queue_setup = qede_rx_queue_setup,
2316         .rx_queue_release = qede_rx_queue_release,
2317         .rx_descriptor_status = qede_rx_descriptor_status,
2318         .tx_queue_setup = qede_tx_queue_setup,
2319         .tx_queue_release = qede_tx_queue_release,
2320         .dev_start = qede_dev_start,
2321         .dev_reset = qede_dev_reset,
2322         .dev_set_link_up = qede_dev_set_link_up,
2323         .dev_set_link_down = qede_dev_set_link_down,
2324         .link_update = qede_link_update,
2325         .promiscuous_enable = qede_promiscuous_enable,
2326         .promiscuous_disable = qede_promiscuous_disable,
2327         .allmulticast_enable = qede_allmulticast_enable,
2328         .allmulticast_disable = qede_allmulticast_disable,
2329         .set_mc_addr_list = qede_set_mc_addr_list,
2330         .dev_stop = qede_dev_stop,
2331         .dev_close = qede_dev_close,
2332         .stats_get = qede_get_stats,
2333         .stats_reset = qede_reset_stats,
2334         .xstats_get = qede_get_xstats,
2335         .xstats_reset = qede_reset_xstats,
2336         .xstats_get_names = qede_get_xstats_names,
2337         .mac_addr_add = qede_mac_addr_add,
2338         .mac_addr_remove = qede_mac_addr_remove,
2339         .mac_addr_set = qede_mac_addr_set,
2340         .vlan_offload_set = qede_vlan_offload_set,
2341         .vlan_filter_set = qede_vlan_filter_set,
2342         .flow_ctrl_set = qede_flow_ctrl_set,
2343         .flow_ctrl_get = qede_flow_ctrl_get,
2344         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2345         .rss_hash_update = qede_rss_hash_update,
2346         .rss_hash_conf_get = qede_rss_hash_conf_get,
2347         .reta_update  = qede_rss_reta_update,
2348         .reta_query  = qede_rss_reta_query,
2349         .mtu_set = qede_set_mtu,
2350         .filter_ctrl = qede_dev_filter_ctrl,
2351         .udp_tunnel_port_add = qede_udp_dst_port_add,
2352         .udp_tunnel_port_del = qede_udp_dst_port_del,
2353 };
2354
2355 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2356         .dev_configure = qede_dev_configure,
2357         .dev_infos_get = qede_dev_info_get,
2358         .rx_queue_setup = qede_rx_queue_setup,
2359         .rx_queue_release = qede_rx_queue_release,
2360         .rx_descriptor_status = qede_rx_descriptor_status,
2361         .tx_queue_setup = qede_tx_queue_setup,
2362         .tx_queue_release = qede_tx_queue_release,
2363         .dev_start = qede_dev_start,
2364         .dev_reset = qede_dev_reset,
2365         .dev_set_link_up = qede_dev_set_link_up,
2366         .dev_set_link_down = qede_dev_set_link_down,
2367         .link_update = qede_link_update,
2368         .promiscuous_enable = qede_promiscuous_enable,
2369         .promiscuous_disable = qede_promiscuous_disable,
2370         .allmulticast_enable = qede_allmulticast_enable,
2371         .allmulticast_disable = qede_allmulticast_disable,
2372         .set_mc_addr_list = qede_set_mc_addr_list,
2373         .dev_stop = qede_dev_stop,
2374         .dev_close = qede_dev_close,
2375         .stats_get = qede_get_stats,
2376         .stats_reset = qede_reset_stats,
2377         .xstats_get = qede_get_xstats,
2378         .xstats_reset = qede_reset_xstats,
2379         .xstats_get_names = qede_get_xstats_names,
2380         .vlan_offload_set = qede_vlan_offload_set,
2381         .vlan_filter_set = qede_vlan_filter_set,
2382         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2383         .rss_hash_update = qede_rss_hash_update,
2384         .rss_hash_conf_get = qede_rss_hash_conf_get,
2385         .reta_update  = qede_rss_reta_update,
2386         .reta_query  = qede_rss_reta_query,
2387         .mtu_set = qede_set_mtu,
2388         .udp_tunnel_port_add = qede_udp_dst_port_add,
2389         .udp_tunnel_port_del = qede_udp_dst_port_del,
2390         .mac_addr_add = qede_mac_addr_add,
2391         .mac_addr_remove = qede_mac_addr_remove,
2392         .mac_addr_set = qede_mac_addr_set,
2393 };
2394
2395 static void qede_update_pf_params(struct ecore_dev *edev)
2396 {
2397         struct ecore_pf_params pf_params;
2398
2399         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2400         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2401         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2402         qed_ops->common->update_pf_params(edev, &pf_params);
2403 }
2404
2405 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2406 {
2407         struct rte_pci_device *pci_dev;
2408         struct rte_pci_addr pci_addr;
2409         struct qede_dev *adapter;
2410         struct ecore_dev *edev;
2411         struct qed_dev_eth_info dev_info;
2412         struct qed_slowpath_params params;
2413         static bool do_once = true;
2414         uint8_t bulletin_change;
2415         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2416         uint8_t is_mac_forced;
2417         bool is_mac_exist;
2418         /* Fix up ecore debug level */
2419         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2420         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2421         uint32_t int_mode;
2422         int rc;
2423
2424         /* Extract key data structures */
2425         adapter = eth_dev->data->dev_private;
2426         adapter->ethdev = eth_dev;
2427         edev = &adapter->edev;
2428         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2429         pci_addr = pci_dev->addr;
2430
2431         PMD_INIT_FUNC_TRACE(edev);
2432
2433         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2434                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2435                  eth_dev->data->port_id);
2436
2437         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2438                 DP_ERR(edev, "Skipping device init from secondary process\n");
2439                 return 0;
2440         }
2441
2442         rte_eth_copy_pci_info(eth_dev, pci_dev);
2443
2444         /* @DPDK */
2445         edev->vendor_id = pci_dev->id.vendor_id;
2446         edev->device_id = pci_dev->id.device_id;
2447
2448         qed_ops = qed_get_eth_ops();
2449         if (!qed_ops) {
2450                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2451                 rc = -EINVAL;
2452                 goto err;
2453         }
2454
2455         DP_INFO(edev, "Starting qede probe\n");
2456         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2457                                     dp_level, is_vf);
2458         if (rc != 0) {
2459                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2460                 rc = -ENODEV;
2461                 goto err;
2462         }
2463         qede_update_pf_params(edev);
2464
2465         switch (pci_dev->intr_handle.type) {
2466         case RTE_INTR_HANDLE_UIO_INTX:
2467         case RTE_INTR_HANDLE_VFIO_LEGACY:
2468                 int_mode = ECORE_INT_MODE_INTA;
2469                 rte_intr_callback_register(&pci_dev->intr_handle,
2470                                            qede_interrupt_handler_intx,
2471                                            (void *)eth_dev);
2472                 break;
2473         default:
2474                 int_mode = ECORE_INT_MODE_MSIX;
2475                 rte_intr_callback_register(&pci_dev->intr_handle,
2476                                            qede_interrupt_handler,
2477                                            (void *)eth_dev);
2478         }
2479
2480         if (rte_intr_enable(&pci_dev->intr_handle)) {
2481                 DP_ERR(edev, "rte_intr_enable() failed\n");
2482                 rc = -ENODEV;
2483                 goto err;
2484         }
2485
2486         /* Start the Slowpath-process */
2487         memset(&params, 0, sizeof(struct qed_slowpath_params));
2488
2489         params.int_mode = int_mode;
2490         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2491         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2492         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2493         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2494         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2495                 QEDE_PMD_DRV_VER_STR_SIZE);
2496
2497         if (ECORE_IS_CMT(edev)) {
2498                 eth_dev->rx_pkt_burst = qede_recv_pkts_cmt;
2499                 eth_dev->tx_pkt_burst = qede_xmit_pkts_cmt;
2500         } else {
2501                 eth_dev->rx_pkt_burst = qede_recv_pkts;
2502                 eth_dev->tx_pkt_burst = qede_xmit_pkts;
2503         }
2504
2505         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2506
2507         /* For CMT mode device do periodic polling for slowpath events.
2508          * This is required since uio device uses only one MSI-x
2509          * interrupt vector but we need one for each engine.
2510          */
2511         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2512                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2513                                        qede_poll_sp_sb_cb,
2514                                        (void *)eth_dev);
2515                 if (rc != 0) {
2516                         DP_ERR(edev, "Unable to start periodic"
2517                                      " timer rc %d\n", rc);
2518                         rc = -EINVAL;
2519                         goto err;
2520                 }
2521         }
2522
2523         rc = qed_ops->common->slowpath_start(edev, &params);
2524         if (rc) {
2525                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2526                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2527                                      (void *)eth_dev);
2528                 rc = -ENODEV;
2529                 goto err;
2530         }
2531
2532         rc = qed_ops->fill_dev_info(edev, &dev_info);
2533         if (rc) {
2534                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2535                 qed_ops->common->slowpath_stop(edev);
2536                 qed_ops->common->remove(edev);
2537                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2538                                      (void *)eth_dev);
2539                 rc = -ENODEV;
2540                 goto err;
2541         }
2542
2543         qede_alloc_etherdev(adapter, &dev_info);
2544
2545         if (do_once) {
2546                 qede_print_adapter_info(adapter);
2547                 do_once = false;
2548         }
2549
2550         adapter->ops->common->set_name(edev, edev->name);
2551
2552         if (!is_vf)
2553                 adapter->dev_info.num_mac_filters =
2554                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2555                                             ECORE_MAC);
2556         else
2557                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2558                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2559
2560         /* Allocate memory for storing MAC addr */
2561         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2562                                         (RTE_ETHER_ADDR_LEN *
2563                                         adapter->dev_info.num_mac_filters),
2564                                         RTE_CACHE_LINE_SIZE);
2565
2566         if (eth_dev->data->mac_addrs == NULL) {
2567                 DP_ERR(edev, "Failed to allocate MAC address\n");
2568                 qed_ops->common->slowpath_stop(edev);
2569                 qed_ops->common->remove(edev);
2570                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2571                                      (void *)eth_dev);
2572                 return -ENOMEM;
2573         }
2574
2575         if (!is_vf) {
2576                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2577                                 hw_info.hw_mac_addr,
2578                                 &eth_dev->data->mac_addrs[0]);
2579                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2580                                 &adapter->primary_mac);
2581         } else {
2582                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2583                                        &bulletin_change);
2584                 if (bulletin_change) {
2585                         is_mac_exist =
2586                             ecore_vf_bulletin_get_forced_mac(
2587                                                 ECORE_LEADING_HWFN(edev),
2588                                                 vf_mac,
2589                                                 &is_mac_forced);
2590                         if (is_mac_exist) {
2591                                 DP_INFO(edev, "VF macaddr received from PF\n");
2592                                 rte_ether_addr_copy(
2593                                         (struct rte_ether_addr *)&vf_mac,
2594                                         &eth_dev->data->mac_addrs[0]);
2595                                 rte_ether_addr_copy(
2596                                         &eth_dev->data->mac_addrs[0],
2597                                         &adapter->primary_mac);
2598                         } else {
2599                                 DP_ERR(edev, "No VF macaddr assigned\n");
2600                         }
2601                 }
2602         }
2603
2604         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2605
2606         /* Bring-up the link */
2607         qede_dev_set_link_state(eth_dev, true);
2608
2609         adapter->num_tx_queues = 0;
2610         adapter->num_rx_queues = 0;
2611         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2612         SLIST_INIT(&adapter->vlan_list_head);
2613         SLIST_INIT(&adapter->uc_list_head);
2614         SLIST_INIT(&adapter->mc_list_head);
2615         adapter->mtu = RTE_ETHER_MTU;
2616         adapter->vport_started = false;
2617
2618         /* VF tunnel offloads is enabled by default in PF driver */
2619         adapter->vxlan.num_filters = 0;
2620         adapter->geneve.num_filters = 0;
2621         adapter->ipgre.num_filters = 0;
2622         if (is_vf) {
2623                 adapter->vxlan.enable = true;
2624                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2625                                              ETH_TUNNEL_FILTER_IVLAN;
2626                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2627                 adapter->geneve.enable = true;
2628                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2629                                               ETH_TUNNEL_FILTER_IVLAN;
2630                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2631                 adapter->ipgre.enable = true;
2632                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2633                                              ETH_TUNNEL_FILTER_IVLAN;
2634         } else {
2635                 adapter->vxlan.enable = false;
2636                 adapter->geneve.enable = false;
2637                 adapter->ipgre.enable = false;
2638         }
2639
2640         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2641                 adapter->primary_mac.addr_bytes[0],
2642                 adapter->primary_mac.addr_bytes[1],
2643                 adapter->primary_mac.addr_bytes[2],
2644                 adapter->primary_mac.addr_bytes[3],
2645                 adapter->primary_mac.addr_bytes[4],
2646                 adapter->primary_mac.addr_bytes[5]);
2647
2648         DP_INFO(edev, "Device initialized\n");
2649
2650         return 0;
2651
2652 err:
2653         if (do_once) {
2654                 qede_print_adapter_info(adapter);
2655                 do_once = false;
2656         }
2657         return rc;
2658 }
2659
2660 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2661 {
2662         return qede_common_dev_init(eth_dev, 1);
2663 }
2664
2665 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2666 {
2667         return qede_common_dev_init(eth_dev, 0);
2668 }
2669
2670 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2671 {
2672         struct qede_dev *qdev = eth_dev->data->dev_private;
2673         struct ecore_dev *edev = &qdev->edev;
2674
2675         PMD_INIT_FUNC_TRACE(edev);
2676
2677         /* only uninitialize in the primary process */
2678         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2679                 return 0;
2680
2681         /* safe to close dev here */
2682         qede_dev_close(eth_dev);
2683
2684         eth_dev->dev_ops = NULL;
2685         eth_dev->rx_pkt_burst = NULL;
2686         eth_dev->tx_pkt_burst = NULL;
2687
2688         return 0;
2689 }
2690
2691 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2692 {
2693         return qede_dev_common_uninit(eth_dev);
2694 }
2695
2696 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2697 {
2698         return qede_dev_common_uninit(eth_dev);
2699 }
2700
2701 static const struct rte_pci_id pci_id_qedevf_map[] = {
2702 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2703         {
2704                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2705         },
2706         {
2707                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2708         },
2709         {
2710                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2711         },
2712         {.vendor_id = 0,}
2713 };
2714
2715 static const struct rte_pci_id pci_id_qede_map[] = {
2716 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2717         {
2718                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2719         },
2720         {
2721                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2722         },
2723         {
2724                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2725         },
2726         {
2727                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2728         },
2729         {
2730                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2731         },
2732         {
2733                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2734         },
2735         {
2736                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2737         },
2738         {
2739                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2740         },
2741         {
2742                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2743         },
2744         {
2745                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2746         },
2747         {.vendor_id = 0,}
2748 };
2749
2750 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2751         struct rte_pci_device *pci_dev)
2752 {
2753         return rte_eth_dev_pci_generic_probe(pci_dev,
2754                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2755 }
2756
2757 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2758 {
2759         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2760 }
2761
2762 static struct rte_pci_driver rte_qedevf_pmd = {
2763         .id_table = pci_id_qedevf_map,
2764         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2765         .probe = qedevf_eth_dev_pci_probe,
2766         .remove = qedevf_eth_dev_pci_remove,
2767 };
2768
2769 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2770         struct rte_pci_device *pci_dev)
2771 {
2772         return rte_eth_dev_pci_generic_probe(pci_dev,
2773                 sizeof(struct qede_dev), qede_eth_dev_init);
2774 }
2775
2776 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2777 {
2778         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2779 }
2780
2781 static struct rte_pci_driver rte_qede_pmd = {
2782         .id_table = pci_id_qede_map,
2783         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2784         .probe = qede_eth_dev_pci_probe,
2785         .remove = qede_eth_dev_pci_remove,
2786 };
2787
2788 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2789 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2790 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2791 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2792 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2793 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2794
2795 RTE_INIT(qede_init_log)
2796 {
2797         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2798         if (qede_logtype_init >= 0)
2799                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2800         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2801         if (qede_logtype_driver >= 0)
2802                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2803 }