drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 static int64_t timer_period = 1;
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static int
 391 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 392 {
 393         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 394         struct ecore_sp_vport_start_params params;
 395         struct ecore_hwfn *p_hwfn;
 396         int rc;
 397         int i;
 398
 399         memset(&params, 0, sizeof(params));
 400         params.vport_id = 0;
 401         params.mtu = mtu;
 402         /* @DPDK - Disable FW placement */
 403         params.zero_placement_offset = 1;
 404         for_each_hwfn(edev, i) {
 405                 p_hwfn = &edev->hwfns[i];
 406                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 407                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 408                 rc = ecore_sp_vport_start(p_hwfn, &params);
 409                 if (rc != ECORE_SUCCESS) {
 410                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 411                         return rc;
 412                 }
 413         }
 414         ecore_reset_vport_stats(edev);
 415         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 416
 417         return 0;
 418 }
 419
 420 static int
 421 qede_stop_vport(struct ecore_dev *edev)
 422 {
 423         struct ecore_hwfn *p_hwfn;
 424         uint8_t vport_id;
 425         int rc;
 426         int i;
 427
 428         vport_id = 0;
 429         for_each_hwfn(edev, i) {
 430                 p_hwfn = &edev->hwfns[i];
 431                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 432                                          vport_id);
 433                 if (rc != ECORE_SUCCESS) {
 434                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 435                         return rc;
 436                 }
 437         }
 438
 439         return 0;
 440 }
 441
 442 /* Activate or deactivate vport via vport-update */
 443 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 444 {
 445         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 446         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 447         struct ecore_sp_vport_update_params params;
 448         struct ecore_hwfn *p_hwfn;
 449         uint8_t i;
 450         int rc = -1;
 451
 452         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 453         params.vport_id = 0;
 454         params.update_vport_active_rx_flg = 1;
 455         params.update_vport_active_tx_flg = 1;
 456         params.vport_active_rx_flg = flg;
 457         params.vport_active_tx_flg = flg;
 458         if (!qdev->enable_tx_switching) {
 459                 if (IS_VF(edev)) {
 460                         params.update_tx_switching_flg = 1;
 461                         params.tx_switching_flg = !flg;
 462                         DP_INFO(edev, "VF tx-switching is disabled\n");
 463                 }
 464         }
 465         for_each_hwfn(edev, i) {
 466                 p_hwfn = &edev->hwfns[i];
 467                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 468                 rc = ecore_sp_vport_update(p_hwfn, &params,
 469                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 470                 if (rc != ECORE_SUCCESS) {
 471                         DP_ERR(edev, "Failed to update vport\n");
 472                         break;
 473                 }
 474         }
 475         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 476
 477         return rc;
 478 }
 479
 480 static void
 481 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 482                            uint16_t mtu, bool enable)
 483 {
 484         /* Enable LRO in split mode */
 485         sge_tpa_params->tpa_ipv4_en_flg = enable;
 486         sge_tpa_params->tpa_ipv6_en_flg = enable;
 487         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 488         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 489         /* set if tpa enable changes */
 490         sge_tpa_params->update_tpa_en_flg = 1;
 491         /* set if tpa parameters should be handled */
 492         sge_tpa_params->update_tpa_param_flg = enable;
 493
 494         sge_tpa_params->max_buffers_per_cqe = 20;
 495         /* Enable TPA in split mode. In this mode each TPA segment
 496          * starts on the new BD, so there is one BD per segment.
 497          */
 498         sge_tpa_params->tpa_pkt_split_flg = 1;
 499         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 500         sge_tpa_params->tpa_gro_consistent_flg = 0;
 501         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 502         sge_tpa_params->tpa_max_size = 0x7FFF;
 503         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 504         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 505 }
 506
 507 /* Enable/disable LRO via vport-update */
 508 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 509 {
 510         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 511         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 512         struct ecore_sp_vport_update_params params;
 513         struct ecore_sge_tpa_params tpa_params;
 514         struct ecore_hwfn *p_hwfn;
 515         int rc;
 516         int i;
 517
 518         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 519         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 520         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 521         params.vport_id = 0;
 522         params.sge_tpa_params = &tpa_params;
 523         for_each_hwfn(edev, i) {
 524                 p_hwfn = &edev->hwfns[i];
 525                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 526                 rc = ecore_sp_vport_update(p_hwfn, &params,
 527                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 528                 if (rc != ECORE_SUCCESS) {
 529                         DP_ERR(edev, "Failed to update LRO\n");
 530                         return -1;
 531                 }
 532         }
 533         qdev->enable_lro = flg;
 534         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 535
 536         return 0;
 537 }
 538
 539 /* Update MTU via vport-update without doing port restart.
 540  * The vport must be deactivated before calling this API.
 541  */
 542 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 543 {
 544         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 545         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 546         struct ecore_sp_vport_update_params params;
 547         struct ecore_hwfn *p_hwfn;
 548         int rc;
 549         int i;
 550
 551         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 552         params.vport_id = 0;
 553         params.mtu = mtu;
 554         params.vport_id = 0;
 555         for_each_hwfn(edev, i) {
 556                 p_hwfn = &edev->hwfns[i];
 557                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 558                 rc = ecore_sp_vport_update(p_hwfn, &params,
 559                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 560                 if (rc != ECORE_SUCCESS) {
 561                         DP_ERR(edev, "Failed to update MTU\n");
 562                         return -1;
 563                 }
 564         }
 565         DP_INFO(edev, "MTU updated to %u\n", mtu);
 566
 567         return 0;
 568 }
 569
 570 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 571 {
 572         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 573         ucast->is_rx_filter = true;
 574         ucast->is_tx_filter = true;
 575         /* ucast->assert_on_error = true; - For debug */
 576 }
 577
 578 static int
 579 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 580                              enum qed_filter_rx_mode_type type)
 581 {
 582         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 583         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 584         struct ecore_filter_accept_flags flags;
 585
 586         memset(&flags, 0, sizeof(flags));
 587
 588         flags.update_rx_mode_config = 1;
 589         flags.update_tx_mode_config = 1;
 590         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 591                 ECORE_ACCEPT_MCAST_MATCHED |
 592                 ECORE_ACCEPT_BCAST;
 593
 594         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 595                 ECORE_ACCEPT_MCAST_MATCHED |
 596                 ECORE_ACCEPT_BCAST;
 597
 598         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 599                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 600                 if (IS_VF(edev)) {
 601                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 602                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 603                 }
 604         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 605                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 606         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 607                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 608                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 609                         ECORE_ACCEPT_MCAST_UNMATCHED;
 610         }
 611
 612         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 613                         ECORE_SPQ_MODE_CB, NULL);
 614 }
 615
 616 static int
 617 qede_tunnel_update(struct qede_dev *qdev,
 618                    struct ecore_tunnel_info *tunn_info)
 619 {
 620         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 621         enum _ecore_status_t rc = ECORE_INVAL;
 622         struct ecore_hwfn *p_hwfn;
 623         struct ecore_ptt *p_ptt;
 624         int i;
 625
 626         for_each_hwfn(edev, i) {
 627                 p_hwfn = &edev->hwfns[i];
 628                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 629                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 630                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 631                 if (IS_PF(edev))
 632                         ecore_ptt_release(p_hwfn, p_ptt);
 633
 634                 if (rc != ECORE_SUCCESS)
 635                         break;
 636         }
 637
 638         return rc;
 639 }
 640
 641 static int
 642 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 643                   bool enable)
 644 {
 645         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 646         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 647         enum _ecore_status_t rc = ECORE_INVAL;
 648         struct ecore_tunnel_info tunn;
 649
 650         if (qdev->vxlan.enable == enable)
 651                 return ECORE_SUCCESS;
 652
 653         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 654         tunn.vxlan.b_update_mode = true;
 655         tunn.vxlan.b_mode_enabled = enable;
 656         tunn.b_update_rx_cls = true;
 657         tunn.b_update_tx_cls = true;
 658         tunn.vxlan.tun_cls = clss;
 659
 660         tunn.vxlan_port.b_update_port = true;
 661         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 662
 663         rc = qede_tunnel_update(qdev, &tunn);
 664         if (rc == ECORE_SUCCESS) {
 665                 qdev->vxlan.enable = enable;
 666                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 667                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 668                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 669         } else {
 670                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 671                        tunn.vxlan.tun_cls);
 672         }
 673
 674         return rc;
 675 }
 676
 677 static int
 678 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 679                   bool enable)
 680 {
 681         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 682         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 683         enum _ecore_status_t rc = ECORE_INVAL;
 684         struct ecore_tunnel_info tunn;
 685
 686         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 687         tunn.l2_geneve.b_update_mode = true;
 688         tunn.l2_geneve.b_mode_enabled = enable;
 689         tunn.ip_geneve.b_update_mode = true;
 690         tunn.ip_geneve.b_mode_enabled = enable;
 691         tunn.l2_geneve.tun_cls = clss;
 692         tunn.ip_geneve.tun_cls = clss;
 693         tunn.b_update_rx_cls = true;
 694         tunn.b_update_tx_cls = true;
 695
 696         tunn.geneve_port.b_update_port = true;
 697         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 698
 699         rc = qede_tunnel_update(qdev, &tunn);
 700         if (rc == ECORE_SUCCESS) {
 701                 qdev->geneve.enable = enable;
 702                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 703                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 704                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 705         } else {
 706                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 707                        clss);
 708         }
 709
 710         return rc;
 711 }
 712
 713 static int
 714 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 715                  enum rte_eth_tunnel_type tunn_type, bool enable)
 716 {
 717         int rc = -EINVAL;
 718
 719         switch (tunn_type) {
 720         case RTE_TUNNEL_TYPE_VXLAN:
 721                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 722                 break;
 723         case RTE_TUNNEL_TYPE_GENEVE:
 724                 rc = qede_geneve_enable(eth_dev, clss, enable);
 725                 break;
 726         default:
 727                 rc = -EINVAL;
 728                 break;
 729         }
 730
 731         return rc;
 732 }
 733
 734 static int
 735 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 736                   bool add)
 737 {
 738         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 739         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 740         struct qede_ucast_entry *tmp = NULL;
 741         struct qede_ucast_entry *u;
 742         struct ether_addr *mac_addr;
 743
 744         mac_addr  = (struct ether_addr *)ucast->mac;
 745         if (add) {
 746                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 747                         if ((memcmp(mac_addr, &tmp->mac,
 748                                     ETHER_ADDR_LEN) == 0) &&
 749                              ucast->vni == tmp->vni &&
 750                              ucast->vlan == tmp->vlan) {
 751                                 DP_ERR(edev, "Unicast MAC is already added"
 752                                        " with vlan = %u, vni = %u\n",
 753                                        ucast->vlan,  ucast->vni);
 754                                         return -EEXIST;
 755                         }
 756                 }
 757                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 758                                RTE_CACHE_LINE_SIZE);
 759                 if (!u) {
 760                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 761                         return -ENOMEM;
 762                 }
 763                 ether_addr_copy(mac_addr, &u->mac);
 764                 u->vlan = ucast->vlan;
 765                 u->vni = ucast->vni;
 766                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 767                 qdev->num_uc_addr++;
 768         } else {
 769                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 770                         if ((memcmp(mac_addr, &tmp->mac,
 771                                     ETHER_ADDR_LEN) == 0) &&
 772                             ucast->vlan == tmp->vlan      &&
 773                             ucast->vni == tmp->vni)
 774                         break;
 775                 }
 776                 if (tmp == NULL) {
 777                         DP_INFO(edev, "Unicast MAC is not found\n");
 778                         return -EINVAL;
 779                 }
 780                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 781                 qdev->num_uc_addr--;
 782         }
 783
 784         return 0;
 785 }
 786
 787 static int
 788 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 789                   bool add)
 790 {
 791         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 792         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 793         struct ether_addr *mac_addr;
 794         struct qede_mcast_entry *tmp = NULL;
 795         struct qede_mcast_entry *m;
 796
 797         mac_addr  = (struct ether_addr *)mcast->mac;
 798         if (add) {
 799                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 800                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 801                                 DP_ERR(edev,
 802                                         "Multicast MAC is already added\n");
 803                                 return -EEXIST;
 804                         }
 805                 }
 806                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 807                         RTE_CACHE_LINE_SIZE);
 808                 if (!m) {
 809                         DP_ERR(edev,
 810                                 "Did not allocate memory for mcast\n");
 811                         return -ENOMEM;
 812                 }
 813                 ether_addr_copy(mac_addr, &m->mac);
 814                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 815                 qdev->num_mc_addr++;
 816         } else {
 817                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 818                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 819                                 break;
 820                 }
 821                 if (tmp == NULL) {
 822                         DP_INFO(edev, "Multicast mac is not found\n");
 823                         return -EINVAL;
 824                 }
 825                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 826                              qede_mcast_entry, list);
 827                 qdev->num_mc_addr--;
 828         }
 829
 830         return 0;
 831 }
 832
 833 static enum _ecore_status_t
 834 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 835                  bool add)
 836 {
 837         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 838         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 839         enum _ecore_status_t rc;
 840         struct ecore_filter_mcast mcast;
 841         struct qede_mcast_entry *tmp;
 842         uint16_t j = 0;
 843
 844         /* Multicast */
 845         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 846                 if (add) {
 847                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 848                                 DP_ERR(edev,
 849                                        "Mcast filter table limit exceeded, "
 850                                        "Please enable mcast promisc mode\n");
 851                                 return -ECORE_INVAL;
 852                         }
 853                 }
 854                 rc = qede_mcast_filter(eth_dev, ucast, add);
 855                 if (rc == 0) {
 856                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 857                         memset(&mcast, 0, sizeof(mcast));
 858                         mcast.num_mc_addrs = qdev->num_mc_addr;
 859                         mcast.opcode = ECORE_FILTER_ADD;
 860                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 861                                 ether_addr_copy(&tmp->mac,
 862                                         (struct ether_addr *)&mcast.mac[j]);
 863                                 j++;
 864                         }
 865                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 866                                                     ECORE_SPQ_MODE_CB, NULL);
 867                 }
 868                 if (rc != ECORE_SUCCESS) {
 869                         DP_ERR(edev, "Failed to add multicast filter"
 870                                " rc = %d, op = %d\n", rc, add);
 871                 }
 872         } else { /* Unicast */
 873                 if (add) {
 874                         if (qdev->num_uc_addr >=
 875                             qdev->dev_info.num_mac_filters) {
 876                                 DP_ERR(edev,
 877                                        "Ucast filter table limit exceeded,"
 878                                        " Please enable promisc mode\n");
 879                                 return -ECORE_INVAL;
 880                         }
 881                 }
 882                 rc = qede_ucast_filter(eth_dev, ucast, add);
 883                 if (rc == 0)
 884                         rc = ecore_filter_ucast_cmd(edev, ucast,
 885                                                     ECORE_SPQ_MODE_CB, NULL);
 886                 if (rc != ECORE_SUCCESS) {
 887                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 888                                rc, add);
 889                 }
 890         }
 891
 892         return rc;
 893 }
 894
 895 static int
 896 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 897                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 898 {
 899         struct ecore_filter_ucast ucast;
 900         int re;
 901
 902         qede_set_ucast_cmn_params(&ucast);
 903         ucast.type = ECORE_FILTER_MAC;
 904         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 905         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 906         return re;
 907 }
 908
 909 static void
 910 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 911 {
 912         struct qede_dev *qdev = eth_dev->data->dev_private;
 913         struct ecore_dev *edev = &qdev->edev;
 914         struct ecore_filter_ucast ucast;
 915
 916         PMD_INIT_FUNC_TRACE(edev);
 917
 918         if (index >= qdev->dev_info.num_mac_filters) {
 919                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 920                        index, qdev->dev_info.num_mac_filters);
 921                 return;
 922         }
 923
 924         qede_set_ucast_cmn_params(&ucast);
 925         ucast.opcode = ECORE_FILTER_REMOVE;
 926         ucast.type = ECORE_FILTER_MAC;
 927
 928         /* Use the index maintained by rte */
 929         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 930                         (struct ether_addr *)&ucast.mac);
 931
 932         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 933 }
 934
 935 static void
 936 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 937 {
 938         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 939         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 940
 941         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 942                                                mac_addr->addr_bytes)) {
 943                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 944                 ether_addr_copy(&qdev->primary_mac,
 945                                 &eth_dev->data->mac_addrs[0]);
 946                 return;
 947         }
 948
 949         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 950 }
 951
 952 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 953 {
 954         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 955         struct ecore_sp_vport_update_params params;
 956         struct ecore_hwfn *p_hwfn;
 957         uint8_t i;
 958         int rc;
 959
 960         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 961         params.vport_id = 0;
 962         params.update_accept_any_vlan_flg = 1;
 963         params.accept_any_vlan = flg;
 964         for_each_hwfn(edev, i) {
 965                 p_hwfn = &edev->hwfns[i];
 966                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 967                 rc = ecore_sp_vport_update(p_hwfn, &params,
 968                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 969                 if (rc != ECORE_SUCCESS) {
 970                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 971                         return;
 972                 }
 973         }
 974
 975         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 976 }
 977
 978 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 979 {
 980         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 981         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 982         struct ecore_sp_vport_update_params params;
 983         struct ecore_hwfn *p_hwfn;
 984         uint8_t i;
 985         int rc;
 986
 987         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 988         params.vport_id = 0;
 989         params.update_inner_vlan_removal_flg = 1;
 990         params.inner_vlan_removal_flg = flg;
 991         for_each_hwfn(edev, i) {
 992                 p_hwfn = &edev->hwfns[i];
 993                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 994                 rc = ecore_sp_vport_update(p_hwfn, &params,
 995                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 996                 if (rc != ECORE_SUCCESS) {
 997                         DP_ERR(edev, "Failed to update vport\n");
 998                         return -1;
 999                 }
1000         }
1001
1002         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1003         return 0;
1004 }
1005
1006 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1007                                 uint16_t vlan_id, int on)
1008 {
1009         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1010         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1011         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1012         struct qede_vlan_entry *tmp = NULL;
1013         struct qede_vlan_entry *vlan;
1014         struct ecore_filter_ucast ucast;
1015         int rc;
1016
1017         if (on) {
1018                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1019                         DP_ERR(edev, "Reached max VLAN filter limit"
1020                                       " enabling accept_any_vlan\n");
1021                         qede_config_accept_any_vlan(qdev, true);
1022                         return 0;
1023                 }
1024
1025                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1026                         if (tmp->vid == vlan_id) {
1027                                 DP_ERR(edev, "VLAN %u already configured\n",
1028                                        vlan_id);
1029                                 return -EEXIST;
1030                         }
1031                 }
1032
1033                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1034                                   RTE_CACHE_LINE_SIZE);
1035
1036                 if (!vlan) {
1037                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1038                         return -ENOMEM;
1039                 }
1040
1041                 qede_set_ucast_cmn_params(&ucast);
1042                 ucast.opcode = ECORE_FILTER_ADD;
1043                 ucast.type = ECORE_FILTER_VLAN;
1044                 ucast.vlan = vlan_id;
1045                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1046                                             NULL);
1047                 if (rc != 0) {
1048                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1049                                rc);
1050                         rte_free(vlan);
1051                 } else {
1052                         vlan->vid = vlan_id;
1053                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1054                         qdev->configured_vlans++;
1055                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1056                                 vlan_id, qdev->configured_vlans);
1057                 }
1058         } else {
1059                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1060                         if (tmp->vid == vlan_id)
1061                                 break;
1062                 }
1063
1064                 if (!tmp) {
1065                         if (qdev->configured_vlans == 0) {
1066                                 DP_INFO(edev,
1067                                         "No VLAN filters configured yet\n");
1068                                 return 0;
1069                         }
1070
1071                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1072                         return -EINVAL;
1073                 }
1074
1075                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1076
1077                 qede_set_ucast_cmn_params(&ucast);
1078                 ucast.opcode = ECORE_FILTER_REMOVE;
1079                 ucast.type = ECORE_FILTER_VLAN;
1080                 ucast.vlan = vlan_id;
1081                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1082                                             NULL);
1083                 if (rc != 0) {
1084                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1085                                vlan_id, rc);
1086                 } else {
1087                         qdev->configured_vlans--;
1088                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1089                                 vlan_id, qdev->configured_vlans);
1090                 }
1091         }
1092
1093         return rc;
1094 }
1095
1096 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1097 {
1098         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1099         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1100         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1101
1102         if (mask & ETH_VLAN_STRIP_MASK) {
1103                 if (rxmode->hw_vlan_strip)
1104                         (void)qede_vlan_stripping(eth_dev, 1);
1105                 else
1106                         (void)qede_vlan_stripping(eth_dev, 0);
1107         }
1108
1109         if (mask & ETH_VLAN_FILTER_MASK) {
1110                 /* VLAN filtering kicks in when a VLAN is added */
1111                 if (rxmode->hw_vlan_filter) {
1112                         qede_vlan_filter_set(eth_dev, 0, 1);
1113                 } else {
1114                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1115                                 DP_ERR(edev,
1116                                   " Please remove existing VLAN filters"
1117                                   " before disabling VLAN filtering\n");
1118                                 /* Signal app that VLAN filtering is still
1119                                  * enabled
1120                                  */
1121                                 rxmode->hw_vlan_filter = true;
1122                         } else {
1123                                 qede_vlan_filter_set(eth_dev, 0, 0);
1124                         }
1125                 }
1126         }
1127
1128         if (mask & ETH_VLAN_EXTEND_MASK)
1129                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1130                         " and classification is based on outer tag only\n");
1131
1132         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1133                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1134
1135         return 0;
1136 }
1137
1138 static void qede_prandom_bytes(uint32_t *buff)
1139 {
1140         uint8_t i;
1141
1142         srand((unsigned int)time(NULL));
1143         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1144                 buff[i] = rand();
1145 }
1146
1147 int qede_config_rss(struct rte_eth_dev *eth_dev)
1148 {
1149         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1150         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1151         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1152         struct rte_eth_rss_reta_entry64 reta_conf[2];
1153         struct rte_eth_rss_conf rss_conf;
1154         uint32_t i, id, pos, q;
1155
1156         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1157         if (!rss_conf.rss_key) {
1158                 DP_INFO(edev, "Applying driver default key\n");
1159                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1160                 qede_prandom_bytes(&def_rss_key[0]);
1161                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1162         }
1163
1164         /* Configure RSS hash */
1165         if (qede_rss_hash_update(eth_dev, &rss_conf))
1166                 return -EINVAL;
1167
1168         /* Configure default RETA */
1169         memset(reta_conf, 0, sizeof(reta_conf));
1170         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1171                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1172
1173         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1174                 id = i / RTE_RETA_GROUP_SIZE;
1175                 pos = i % RTE_RETA_GROUP_SIZE;
1176                 q = i % QEDE_RSS_COUNT(qdev);
1177                 reta_conf[id].reta[pos] = q;
1178         }
1179         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1180                                  ECORE_RSS_IND_TABLE_SIZE))
1181                 return -EINVAL;
1182
1183         return 0;
1184 }
1185
1186 static void qede_fastpath_start(struct ecore_dev *edev)
1187 {
1188         struct ecore_hwfn *p_hwfn;
1189         int i;
1190
1191         for_each_hwfn(edev, i) {
1192                 p_hwfn = &edev->hwfns[i];
1193                 ecore_hw_start_fastpath(p_hwfn);
1194         }
1195 }
1196
1197 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1198 {
1199         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1200         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1201         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1202
1203         PMD_INIT_FUNC_TRACE(edev);
1204
1205         /* Update MTU only if it has changed */
1206         if (qdev->mtu != qdev->new_mtu) {
1207                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1208                         goto err;
1209                 qdev->mtu = qdev->new_mtu;
1210         }
1211
1212         /* Configure TPA parameters */
1213         if (rxmode->enable_lro) {
1214                 if (qede_enable_tpa(eth_dev, true))
1215                         return -EINVAL;
1216                 /* Enable scatter mode for LRO */
1217                 if (!rxmode->enable_scatter)
1218                         eth_dev->data->scattered_rx = 1;
1219         }
1220
1221         /* Start queues */
1222         if (qede_start_queues(eth_dev))
1223                 goto err;
1224
1225         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1226          * enabling RSS. Hence RSS configuration is deferred upto this point.
1227          * Also, we would like to retain similar behavior in PF case, so we
1228          * don't do PF/VF specific check here.
1229          */
1230         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1231                 if (qede_config_rss(eth_dev))
1232                         goto err;
1233
1234         /* Enable vport*/
1235         if (qede_activate_vport(eth_dev, true))
1236                 goto err;
1237
1238         /* Bring-up the link */
1239         qede_dev_set_link_state(eth_dev, true);
1240
1241         /* Update link status */
1242         qede_link_update(eth_dev, 0);
1243
1244         /* Start/resume traffic */
1245         qede_fastpath_start(edev);
1246
1247         DP_INFO(edev, "Device started\n");
1248
1249         return 0;
1250 err:
1251         DP_ERR(edev, "Device start fails\n");
1252         return -1; /* common error code is < 0 */
1253 }
1254
1255 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1256 {
1257         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1258         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1259
1260         PMD_INIT_FUNC_TRACE(edev);
1261
1262         /* Disable vport */
1263         if (qede_activate_vport(eth_dev, false))
1264                 return;
1265
1266         if (qdev->enable_lro)
1267                 qede_enable_tpa(eth_dev, false);
1268
1269         /* Stop queues */
1270         qede_stop_queues(eth_dev);
1271
1272         /* Disable traffic */
1273         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1274
1275         /* Bring the link down */
1276         qede_dev_set_link_state(eth_dev, false);
1277
1278         DP_INFO(edev, "Device is stopped\n");
1279 }
1280
1281 #define QEDE_TX_SWITCHING               "vf_txswitch"
1282
1283 const char *valid_args[] = {
1284         QEDE_TX_SWITCHING,
1285         NULL,
1286 };
1287
1288 static int qede_args_check(const char *key, const char *val, void *opaque)
1289 {
1290         unsigned long tmp;
1291         int ret = 0;
1292         struct rte_eth_dev *eth_dev = opaque;
1293         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1294         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1295
1296         errno = 0;
1297         tmp = strtoul(val, NULL, 0);
1298         if (errno) {
1299                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1300                 return errno;
1301         }
1302
1303         if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1304                 qdev->enable_tx_switching = !!tmp;
1305
1306         return ret;
1307 }
1308
1309 static int qede_args(struct rte_eth_dev *eth_dev)
1310 {
1311         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1312         struct rte_kvargs *kvlist;
1313         struct rte_devargs *devargs;
1314         int ret;
1315         int i;
1316
1317         devargs = pci_dev->device.devargs;
1318         if (!devargs)
1319                 return 0; /* return success */
1320
1321         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1322         if (kvlist == NULL)
1323                 return -EINVAL;
1324
1325          /* Process parameters. */
1326         for (i = 0; (valid_args[i] != NULL); ++i) {
1327                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1328                         ret = rte_kvargs_process(kvlist, valid_args[i],
1329                                                  qede_args_check, eth_dev);
1330                         if (ret != ECORE_SUCCESS) {
1331                                 rte_kvargs_free(kvlist);
1332                                 return ret;
1333                         }
1334                 }
1335         }
1336         rte_kvargs_free(kvlist);
1337
1338         return 0;
1339 }
1340
1341 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1342 {
1343         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1344         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1345         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1346         int ret;
1347
1348         PMD_INIT_FUNC_TRACE(edev);
1349
1350         /* Check requirements for 100G mode */
1351         if (ECORE_IS_CMT(edev)) {
1352                 if (eth_dev->data->nb_rx_queues < 2 ||
1353                                 eth_dev->data->nb_tx_queues < 2) {
1354                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1355                         return -EINVAL;
1356                 }
1357
1358                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1359                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1360                         DP_ERR(edev,
1361                                         "100G mode needs even no. of RX/TX queues\n");
1362                         return -EINVAL;
1363                 }
1364         }
1365
1366         /* We need to have min 1 RX queue.There is no min check in
1367          * rte_eth_dev_configure(), so we are checking it here.
1368          */
1369         if (eth_dev->data->nb_rx_queues == 0) {
1370                 DP_ERR(edev, "Minimum one RX queue is required\n");
1371                 return -EINVAL;
1372         }
1373
1374         /* Enable Tx switching by default */
1375         qdev->enable_tx_switching = 1;
1376
1377         /* Parse devargs and fix up rxmode */
1378         if (qede_args(eth_dev))
1379                 return -ENOTSUP;
1380
1381         /* Sanity checks and throw warnings */
1382         if (rxmode->enable_scatter)
1383                 eth_dev->data->scattered_rx = 1;
1384
1385         if (!rxmode->hw_strip_crc)
1386                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1387
1388         if (!rxmode->hw_ip_checksum)
1389                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1390                                 "in hw\n");
1391         if (rxmode->header_split)
1392                 DP_INFO(edev, "Header split enable is not supported\n");
1393         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1394                                 ETH_MQ_RX_RSS)) {
1395                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1396                 return -ENOTSUP;
1397         }
1398         /* Flow director mode check */
1399         if (qede_check_fdir_support(eth_dev))
1400                 return -ENOTSUP;
1401
1402         /* Deallocate resources if held previously. It is needed only if the
1403          * queue count has been changed from previous configuration. If its
1404          * going to change then it means RX/TX queue setup will be called
1405          * again and the fastpath pointers will be reinitialized there.
1406          */
1407         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1408             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1409                 qede_dealloc_fp_resc(eth_dev);
1410                 /* Proceed with updated queue count */
1411                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1412                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1413                 if (qede_alloc_fp_resc(qdev))
1414                         return -ENOMEM;
1415         }
1416
1417         /* If jumbo enabled adjust MTU */
1418         if (eth_dev->data->dev_conf.rxmode.jumbo_frame)
1419                 eth_dev->data->mtu =
1420                                 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1421                                 ETHER_HDR_LEN - ETHER_CRC_LEN;
1422
1423         /* VF's MTU has to be set using vport-start where as
1424          * PF's MTU can be updated via vport-update.
1425          */
1426         if (IS_VF(edev)) {
1427                 if (qede_start_vport(qdev, eth_dev->data->mtu))
1428                         return -1;
1429         } else {
1430                 if (qede_update_mtu(eth_dev, eth_dev->data->mtu))
1431                         return -1;
1432         }
1433
1434         qdev->mtu = eth_dev->data->mtu;
1435         qdev->new_mtu = qdev->mtu;
1436
1437         /* Enable VLAN offloads by default */
1438         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1439                         ETH_VLAN_FILTER_MASK |
1440                         ETH_VLAN_EXTEND_MASK);
1441         if (ret)
1442                 return ret;
1443
1444         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1445                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1446
1447         return 0;
1448 }
1449
1450 /* Info about HW descriptor ring limitations */
1451 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1452         .nb_max = 0x8000, /* 32K */
1453         .nb_min = 128,
1454         .nb_align = 128 /* lowest common multiple */
1455 };
1456
1457 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1458         .nb_max = 0x8000, /* 32K */
1459         .nb_min = 256,
1460         .nb_align = 256,
1461         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1462         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1463 };
1464
1465 static void
1466 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1467                   struct rte_eth_dev_info *dev_info)
1468 {
1469         struct qede_dev *qdev = eth_dev->data->dev_private;
1470         struct ecore_dev *edev = &qdev->edev;
1471         struct qed_link_output link;
1472         uint32_t speed_cap = 0;
1473
1474         PMD_INIT_FUNC_TRACE(edev);
1475
1476         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1477         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1478         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1479         dev_info->rx_desc_lim = qede_rx_desc_lim;
1480         dev_info->tx_desc_lim = qede_tx_desc_lim;
1481
1482         if (IS_PF(edev))
1483                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1484                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1485         else
1486                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1487                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1488         dev_info->max_tx_queues = dev_info->max_rx_queues;
1489
1490         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1491         dev_info->max_vfs = 0;
1492         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1493         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1494         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1495
1496         dev_info->default_txconf = (struct rte_eth_txconf) {
1497                 .txq_flags = QEDE_TXQ_FLAGS,
1498         };
1499
1500         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1501                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1502                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1503                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1504                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1505                                      DEV_RX_OFFLOAD_TCP_LRO);
1506
1507         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1508                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1509                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1510                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1511                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1512                                      DEV_TX_OFFLOAD_TCP_TSO |
1513                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1514                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1515
1516         memset(&link, 0, sizeof(struct qed_link_output));
1517         qdev->ops->common->get_link(edev, &link);
1518         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1519                 speed_cap |= ETH_LINK_SPEED_1G;
1520         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1521                 speed_cap |= ETH_LINK_SPEED_10G;
1522         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1523                 speed_cap |= ETH_LINK_SPEED_25G;
1524         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1525                 speed_cap |= ETH_LINK_SPEED_40G;
1526         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1527                 speed_cap |= ETH_LINK_SPEED_50G;
1528         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1529                 speed_cap |= ETH_LINK_SPEED_100G;
1530         dev_info->speed_capa = speed_cap;
1531 }
1532
1533 /* return 0 means link status changed, -1 means not changed */
1534 int
1535 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1536 {
1537         struct qede_dev *qdev = eth_dev->data->dev_private;
1538         struct ecore_dev *edev = &qdev->edev;
1539         uint16_t link_duplex;
1540         struct qed_link_output link;
1541         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1542
1543         memset(&link, 0, sizeof(struct qed_link_output));
1544         qdev->ops->common->get_link(edev, &link);
1545
1546         /* Link Speed */
1547         curr->link_speed = link.speed;
1548
1549         /* Link Mode */
1550         switch (link.duplex) {
1551         case QEDE_DUPLEX_HALF:
1552                 link_duplex = ETH_LINK_HALF_DUPLEX;
1553                 break;
1554         case QEDE_DUPLEX_FULL:
1555                 link_duplex = ETH_LINK_FULL_DUPLEX;
1556                 break;
1557         case QEDE_DUPLEX_UNKNOWN:
1558         default:
1559                 link_duplex = -1;
1560         }
1561         curr->link_duplex = link_duplex;
1562
1563         /* Link Status */
1564         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1565
1566         /* AN */
1567         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1568                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1569
1570         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1571                 curr->link_speed, curr->link_duplex,
1572                 curr->link_autoneg, curr->link_status);
1573
1574         /* return 0 means link status changed, -1 means not changed */
1575         return ((curr->link_status == link.link_up) ? -1 : 0);
1576 }
1577
1578 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1579 {
1580 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1581         struct qede_dev *qdev = eth_dev->data->dev_private;
1582         struct ecore_dev *edev = &qdev->edev;
1583
1584         PMD_INIT_FUNC_TRACE(edev);
1585 #endif
1586
1587         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1588
1589         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1590                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1591
1592         qed_configure_filter_rx_mode(eth_dev, type);
1593 }
1594
1595 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1596 {
1597 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1598         struct qede_dev *qdev = eth_dev->data->dev_private;
1599         struct ecore_dev *edev = &qdev->edev;
1600
1601         PMD_INIT_FUNC_TRACE(edev);
1602 #endif
1603
1604         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1605                 qed_configure_filter_rx_mode(eth_dev,
1606                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1607         else
1608                 qed_configure_filter_rx_mode(eth_dev,
1609                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1610 }
1611
1612 static void qede_poll_sp_sb_cb(void *param)
1613 {
1614         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1615         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1616         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1617         int rc;
1618
1619         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1620         qede_interrupt_action(&edev->hwfns[1]);
1621
1622         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1623                                qede_poll_sp_sb_cb,
1624                                (void *)eth_dev);
1625         if (rc != 0) {
1626                 DP_ERR(edev, "Unable to start periodic"
1627                              " timer rc %d\n", rc);
1628                 assert(false && "Unable to start periodic timer");
1629         }
1630 }
1631
1632 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1633 {
1634         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1635         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1636         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1637
1638         PMD_INIT_FUNC_TRACE(edev);
1639
1640         /* dev_stop() shall cleanup fp resources in hw but without releasing
1641          * dma memories and sw structures so that dev_start() can be called
1642          * by the app without reconfiguration. However, in dev_close() we
1643          * can release all the resources and device can be brought up newly
1644          */
1645         if (eth_dev->data->dev_started)
1646                 qede_dev_stop(eth_dev);
1647
1648         qede_stop_vport(edev);
1649         qede_fdir_dealloc_resc(eth_dev);
1650         qede_dealloc_fp_resc(eth_dev);
1651
1652         eth_dev->data->nb_rx_queues = 0;
1653         eth_dev->data->nb_tx_queues = 0;
1654
1655         qdev->ops->common->slowpath_stop(edev);
1656         qdev->ops->common->remove(edev);
1657         rte_intr_disable(&pci_dev->intr_handle);
1658         rte_intr_callback_unregister(&pci_dev->intr_handle,
1659                                      qede_interrupt_handler, (void *)eth_dev);
1660         if (ECORE_IS_CMT(edev))
1661                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1662 }
1663
1664 static int
1665 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1666 {
1667         struct qede_dev *qdev = eth_dev->data->dev_private;
1668         struct ecore_dev *edev = &qdev->edev;
1669         struct ecore_eth_stats stats;
1670         unsigned int i = 0, j = 0, qid;
1671         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1672         struct qede_tx_queue *txq;
1673
1674         ecore_get_vport_stats(edev, &stats);
1675
1676         /* RX Stats */
1677         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1678             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1679
1680         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1681             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1682
1683         eth_stats->ierrors = stats.common.rx_crc_errors +
1684             stats.common.rx_align_errors +
1685             stats.common.rx_carrier_errors +
1686             stats.common.rx_oversize_packets +
1687             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1688
1689         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1690
1691         eth_stats->imissed = stats.common.mftag_filter_discards +
1692             stats.common.mac_filter_discards +
1693             stats.common.no_buff_discards +
1694             stats.common.brb_truncates + stats.common.brb_discards;
1695
1696         /* TX stats */
1697         eth_stats->opackets = stats.common.tx_ucast_pkts +
1698             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1699
1700         eth_stats->obytes = stats.common.tx_ucast_bytes +
1701             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1702
1703         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1704
1705         /* Queue stats */
1706         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1707                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1708         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1709                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1710         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1711             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1712                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1713                        "Not all the queue stats will be displayed. Set"
1714                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1715                        " appropriately and retry.\n");
1716
1717         for_each_rss(qid) {
1718                 eth_stats->q_ipackets[i] =
1719                         *(uint64_t *)(
1720                                 ((char *)(qdev->fp_array[qid].rxq)) +
1721                                 offsetof(struct qede_rx_queue,
1722                                 rcv_pkts));
1723                 eth_stats->q_errors[i] =
1724                         *(uint64_t *)(
1725                                 ((char *)(qdev->fp_array[qid].rxq)) +
1726                                 offsetof(struct qede_rx_queue,
1727                                 rx_hw_errors)) +
1728                         *(uint64_t *)(
1729                                 ((char *)(qdev->fp_array[qid].rxq)) +
1730                                 offsetof(struct qede_rx_queue,
1731                                 rx_alloc_errors));
1732                 i++;
1733                 if (i == rxq_stat_cntrs)
1734                         break;
1735         }
1736
1737         for_each_tss(qid) {
1738                 txq = qdev->fp_array[qid].txq;
1739                 eth_stats->q_opackets[j] =
1740                         *((uint64_t *)(uintptr_t)
1741                                 (((uint64_t)(uintptr_t)(txq)) +
1742                                  offsetof(struct qede_tx_queue,
1743                                           xmit_pkts)));
1744                 j++;
1745                 if (j == txq_stat_cntrs)
1746                         break;
1747         }
1748
1749         return 0;
1750 }
1751
1752 static unsigned
1753 qede_get_xstats_count(struct qede_dev *qdev) {
1754         if (ECORE_IS_BB(&qdev->edev))
1755                 return RTE_DIM(qede_xstats_strings) +
1756                        RTE_DIM(qede_bb_xstats_strings) +
1757                        (RTE_DIM(qede_rxq_xstats_strings) *
1758                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1759                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1760         else
1761                 return RTE_DIM(qede_xstats_strings) +
1762                        RTE_DIM(qede_ah_xstats_strings) +
1763                        (RTE_DIM(qede_rxq_xstats_strings) *
1764                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1765                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1766 }
1767
1768 static int
1769 qede_get_xstats_names(struct rte_eth_dev *dev,
1770                       struct rte_eth_xstat_name *xstats_names,
1771                       __rte_unused unsigned int limit)
1772 {
1773         struct qede_dev *qdev = dev->data->dev_private;
1774         struct ecore_dev *edev = &qdev->edev;
1775         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1776         unsigned int i, qid, stat_idx = 0;
1777         unsigned int rxq_stat_cntrs;
1778
1779         if (xstats_names != NULL) {
1780                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1781                         snprintf(xstats_names[stat_idx].name,
1782                                 sizeof(xstats_names[stat_idx].name),
1783                                 "%s",
1784                                 qede_xstats_strings[i].name);
1785                         stat_idx++;
1786                 }
1787
1788                 if (ECORE_IS_BB(edev)) {
1789                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1790                                 snprintf(xstats_names[stat_idx].name,
1791                                         sizeof(xstats_names[stat_idx].name),
1792                                         "%s",
1793                                         qede_bb_xstats_strings[i].name);
1794                                 stat_idx++;
1795                         }
1796                 } else {
1797                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1798                                 snprintf(xstats_names[stat_idx].name,
1799                                         sizeof(xstats_names[stat_idx].name),
1800                                         "%s",
1801                                         qede_ah_xstats_strings[i].name);
1802                                 stat_idx++;
1803                         }
1804                 }
1805
1806                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1807                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1808                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1809                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1810                                 snprintf(xstats_names[stat_idx].name,
1811                                         sizeof(xstats_names[stat_idx].name),
1812                                         "%.4s%d%s",
1813                                         qede_rxq_xstats_strings[i].name, qid,
1814                                         qede_rxq_xstats_strings[i].name + 4);
1815                                 stat_idx++;
1816                         }
1817                 }
1818         }
1819
1820         return stat_cnt;
1821 }
1822
1823 static int
1824 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1825                 unsigned int n)
1826 {
1827         struct qede_dev *qdev = dev->data->dev_private;
1828         struct ecore_dev *edev = &qdev->edev;
1829         struct ecore_eth_stats stats;
1830         const unsigned int num = qede_get_xstats_count(qdev);
1831         unsigned int i, qid, stat_idx = 0;
1832         unsigned int rxq_stat_cntrs;
1833
1834         if (n < num)
1835                 return num;
1836
1837         ecore_get_vport_stats(edev, &stats);
1838
1839         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1840                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1841                                              qede_xstats_strings[i].offset);
1842                 xstats[stat_idx].id = stat_idx;
1843                 stat_idx++;
1844         }
1845
1846         if (ECORE_IS_BB(edev)) {
1847                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1848                         xstats[stat_idx].value =
1849                                         *(uint64_t *)(((char *)&stats) +
1850                                         qede_bb_xstats_strings[i].offset);
1851                         xstats[stat_idx].id = stat_idx;
1852                         stat_idx++;
1853                 }
1854         } else {
1855                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1856                         xstats[stat_idx].value =
1857                                         *(uint64_t *)(((char *)&stats) +
1858                                         qede_ah_xstats_strings[i].offset);
1859                         xstats[stat_idx].id = stat_idx;
1860                         stat_idx++;
1861                 }
1862         }
1863
1864         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1865                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1866         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1867                 for_each_rss(qid) {
1868                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1869                                 xstats[stat_idx].value = *(uint64_t *)(
1870                                         ((char *)(qdev->fp_array[qid].rxq)) +
1871                                          qede_rxq_xstats_strings[i].offset);
1872                                 xstats[stat_idx].id = stat_idx;
1873                                 stat_idx++;
1874                         }
1875                 }
1876         }
1877
1878         return stat_idx;
1879 }
1880
1881 static void
1882 qede_reset_xstats(struct rte_eth_dev *dev)
1883 {
1884         struct qede_dev *qdev = dev->data->dev_private;
1885         struct ecore_dev *edev = &qdev->edev;
1886
1887         ecore_reset_vport_stats(edev);
1888 }
1889
1890 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1891 {
1892         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1893         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1894         struct qed_link_params link_params;
1895         int rc;
1896
1897         DP_INFO(edev, "setting link state %d\n", link_up);
1898         memset(&link_params, 0, sizeof(link_params));
1899         link_params.link_up = link_up;
1900         rc = qdev->ops->common->set_link(edev, &link_params);
1901         if (rc != ECORE_SUCCESS)
1902                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1903
1904         return rc;
1905 }
1906
1907 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1908 {
1909         return qede_dev_set_link_state(eth_dev, true);
1910 }
1911
1912 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1913 {
1914         return qede_dev_set_link_state(eth_dev, false);
1915 }
1916
1917 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1918 {
1919         struct qede_dev *qdev = eth_dev->data->dev_private;
1920         struct ecore_dev *edev = &qdev->edev;
1921
1922         ecore_reset_vport_stats(edev);
1923 }
1924
1925 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1926 {
1927         enum qed_filter_rx_mode_type type =
1928             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1929
1930         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1931                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1932
1933         qed_configure_filter_rx_mode(eth_dev, type);
1934 }
1935
1936 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1937 {
1938         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1939                 qed_configure_filter_rx_mode(eth_dev,
1940                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1941         else
1942                 qed_configure_filter_rx_mode(eth_dev,
1943                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1944 }
1945
1946 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1947                               struct rte_eth_fc_conf *fc_conf)
1948 {
1949         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1950         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1951         struct qed_link_output current_link;
1952         struct qed_link_params params;
1953
1954         memset(&current_link, 0, sizeof(current_link));
1955         qdev->ops->common->get_link(edev, &current_link);
1956
1957         memset(&params, 0, sizeof(params));
1958         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1959         if (fc_conf->autoneg) {
1960                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1961                         DP_ERR(edev, "Autoneg not supported\n");
1962                         return -EINVAL;
1963                 }
1964                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1965         }
1966
1967         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1968         if (fc_conf->mode == RTE_FC_FULL)
1969                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1970                                         QED_LINK_PAUSE_RX_ENABLE);
1971         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1972                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1973         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1974                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1975
1976         params.link_up = true;
1977         (void)qdev->ops->common->set_link(edev, &params);
1978
1979         return 0;
1980 }
1981
1982 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1983                               struct rte_eth_fc_conf *fc_conf)
1984 {
1985         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1986         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1987         struct qed_link_output current_link;
1988
1989         memset(&current_link, 0, sizeof(current_link));
1990         qdev->ops->common->get_link(edev, &current_link);
1991
1992         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1993                 fc_conf->autoneg = true;
1994
1995         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1996                                          QED_LINK_PAUSE_TX_ENABLE))
1997                 fc_conf->mode = RTE_FC_FULL;
1998         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1999                 fc_conf->mode = RTE_FC_RX_PAUSE;
2000         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2001                 fc_conf->mode = RTE_FC_TX_PAUSE;
2002         else
2003                 fc_conf->mode = RTE_FC_NONE;
2004
2005         return 0;
2006 }
2007
2008 static const uint32_t *
2009 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2010 {
2011         static const uint32_t ptypes[] = {
2012                 RTE_PTYPE_L2_ETHER,
2013                 RTE_PTYPE_L2_ETHER_VLAN,
2014                 RTE_PTYPE_L3_IPV4,
2015                 RTE_PTYPE_L3_IPV6,
2016                 RTE_PTYPE_L4_TCP,
2017                 RTE_PTYPE_L4_UDP,
2018                 RTE_PTYPE_TUNNEL_VXLAN,
2019                 RTE_PTYPE_L4_FRAG,
2020                 RTE_PTYPE_TUNNEL_GENEVE,
2021                 /* Inner */
2022                 RTE_PTYPE_INNER_L2_ETHER,
2023                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2024                 RTE_PTYPE_INNER_L3_IPV4,
2025                 RTE_PTYPE_INNER_L3_IPV6,
2026                 RTE_PTYPE_INNER_L4_TCP,
2027                 RTE_PTYPE_INNER_L4_UDP,
2028                 RTE_PTYPE_INNER_L4_FRAG,
2029                 RTE_PTYPE_UNKNOWN
2030         };
2031
2032         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2033                 return ptypes;
2034
2035         return NULL;
2036 }
2037
2038 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2039 {
2040         *rss_caps = 0;
2041         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2042         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2043         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2044         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2045         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2046         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2047         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2048         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2049 }
2050
2051 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2052                          struct rte_eth_rss_conf *rss_conf)
2053 {
2054         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2055         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2056         struct ecore_sp_vport_update_params vport_update_params;
2057         struct ecore_rss_params rss_params;
2058         struct ecore_hwfn *p_hwfn;
2059         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2060         uint64_t hf = rss_conf->rss_hf;
2061         uint8_t len = rss_conf->rss_key_len;
2062         uint8_t idx;
2063         uint8_t i;
2064         int rc;
2065
2066         memset(&vport_update_params, 0, sizeof(vport_update_params));
2067         memset(&rss_params, 0, sizeof(rss_params));
2068
2069         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2070                 (unsigned long)hf, len, key);
2071
2072         if (hf != 0) {
2073                 /* Enabling RSS */
2074                 DP_INFO(edev, "Enabling rss\n");
2075
2076                 /* RSS caps */
2077                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2078                 rss_params.update_rss_capabilities = 1;
2079
2080                 /* RSS hash key */
2081                 if (key) {
2082                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2083                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2084                                 return -EINVAL;
2085                         }
2086                         DP_INFO(edev, "Applying user supplied hash key\n");
2087                         rss_params.update_rss_key = 1;
2088                         memcpy(&rss_params.rss_key, key, len);
2089                 }
2090                 rss_params.rss_enable = 1;
2091         }
2092
2093         rss_params.update_rss_config = 1;
2094         /* tbl_size has to be set with capabilities */
2095         rss_params.rss_table_size_log = 7;
2096         vport_update_params.vport_id = 0;
2097         /* pass the L2 handles instead of qids */
2098         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2099                 idx = qdev->rss_ind_table[i];
2100                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2101         }
2102         vport_update_params.rss_params = &rss_params;
2103
2104         for_each_hwfn(edev, i) {
2105                 p_hwfn = &edev->hwfns[i];
2106                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2107                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2108                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2109                 if (rc) {
2110                         DP_ERR(edev, "vport-update for RSS failed\n");
2111                         return rc;
2112                 }
2113         }
2114         qdev->rss_enable = rss_params.rss_enable;
2115
2116         /* Update local structure for hash query */
2117         qdev->rss_conf.rss_hf = hf;
2118         qdev->rss_conf.rss_key_len = len;
2119         if (qdev->rss_enable) {
2120                 if  (qdev->rss_conf.rss_key == NULL) {
2121                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2122                         if (qdev->rss_conf.rss_key == NULL) {
2123                                 DP_ERR(edev, "No memory to store RSS key\n");
2124                                 return -ENOMEM;
2125                         }
2126                 }
2127                 if (key && len) {
2128                         DP_INFO(edev, "Storing RSS key\n");
2129                         memcpy(qdev->rss_conf.rss_key, key, len);
2130                 }
2131         } else if (!qdev->rss_enable && len == 0) {
2132                 if (qdev->rss_conf.rss_key) {
2133                         free(qdev->rss_conf.rss_key);
2134                         qdev->rss_conf.rss_key = NULL;
2135                         DP_INFO(edev, "Free RSS key\n");
2136                 }
2137         }
2138
2139         return 0;
2140 }
2141
2142 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2143                            struct rte_eth_rss_conf *rss_conf)
2144 {
2145         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2146
2147         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2148         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2149
2150         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2151                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2152                        rss_conf->rss_key_len);
2153         return 0;
2154 }
2155
2156 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2157                                     struct ecore_rss_params *rss)
2158 {
2159         int i, fn;
2160         bool rss_mode = 1; /* enable */
2161         struct ecore_queue_cid *cid;
2162         struct ecore_rss_params *t_rss;
2163
2164         /* In regular scenario, we'd simply need to take input handlers.
2165          * But in CMT, we'd have to split the handlers according to the
2166          * engine they were configured on. We'd then have to understand
2167          * whether RSS is really required, since 2-queues on CMT doesn't
2168          * require RSS.
2169          */
2170
2171         /* CMT should be round-robin */
2172         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2173                 cid = rss->rss_ind_table[i];
2174
2175                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2176                         t_rss = &rss[0];
2177                 else
2178                         t_rss = &rss[1];
2179
2180                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2181         }
2182
2183         t_rss = &rss[1];
2184         t_rss->update_rss_ind_table = 1;
2185         t_rss->rss_table_size_log = 7;
2186         t_rss->update_rss_config = 1;
2187
2188         /* Make sure RSS is actually required */
2189         for_each_hwfn(edev, fn) {
2190                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2191                      i++) {
2192                         if (rss[fn].rss_ind_table[i] !=
2193                             rss[fn].rss_ind_table[0])
2194                                 break;
2195                 }
2196
2197                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2198                         DP_INFO(edev,
2199                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2200                         rss_mode = 0;
2201                         goto out;
2202                 }
2203         }
2204
2205 out:
2206         t_rss->rss_enable = rss_mode;
2207
2208         return rss_mode;
2209 }
2210
2211 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2212                          struct rte_eth_rss_reta_entry64 *reta_conf,
2213                          uint16_t reta_size)
2214 {
2215         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2216         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2217         struct ecore_sp_vport_update_params vport_update_params;
2218         struct ecore_rss_params *params;
2219         struct ecore_hwfn *p_hwfn;
2220         uint16_t i, idx, shift;
2221         uint8_t entry;
2222         int rc = 0;
2223
2224         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2225                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2226                        reta_size);
2227                 return -EINVAL;
2228         }
2229
2230         memset(&vport_update_params, 0, sizeof(vport_update_params));
2231         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2232                              RTE_CACHE_LINE_SIZE);
2233         if (params == NULL) {
2234                 DP_ERR(edev, "failed to allocate memory\n");
2235                 return -ENOMEM;
2236         }
2237
2238         for (i = 0; i < reta_size; i++) {
2239                 idx = i / RTE_RETA_GROUP_SIZE;
2240                 shift = i % RTE_RETA_GROUP_SIZE;
2241                 if (reta_conf[idx].mask & (1ULL << shift)) {
2242                         entry = reta_conf[idx].reta[shift];
2243                         /* Pass rxq handles to ecore */
2244                         params->rss_ind_table[i] =
2245                                         qdev->fp_array[entry].rxq->handle;
2246                         /* Update the local copy for RETA query command */
2247                         qdev->rss_ind_table[i] = entry;
2248                 }
2249         }
2250
2251         params->update_rss_ind_table = 1;
2252         params->rss_table_size_log = 7;
2253         params->update_rss_config = 1;
2254
2255         /* Fix up RETA for CMT mode device */
2256         if (ECORE_IS_CMT(edev))
2257                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2258                                                             params);
2259         vport_update_params.vport_id = 0;
2260         /* Use the current value of rss_enable */
2261         params->rss_enable = qdev->rss_enable;
2262         vport_update_params.rss_params = params;
2263
2264         for_each_hwfn(edev, i) {
2265                 p_hwfn = &edev->hwfns[i];
2266                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2267                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2268                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2269                 if (rc) {
2270                         DP_ERR(edev, "vport-update for RSS failed\n");
2271                         goto out;
2272                 }
2273         }
2274
2275 out:
2276         rte_free(params);
2277         return rc;
2278 }
2279
2280 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2281                                struct rte_eth_rss_reta_entry64 *reta_conf,
2282                                uint16_t reta_size)
2283 {
2284         struct qede_dev *qdev = eth_dev->data->dev_private;
2285         struct ecore_dev *edev = &qdev->edev;
2286         uint16_t i, idx, shift;
2287         uint8_t entry;
2288
2289         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2290                 DP_ERR(edev, "reta_size %d is not supported\n",
2291                        reta_size);
2292                 return -EINVAL;
2293         }
2294
2295         for (i = 0; i < reta_size; i++) {
2296                 idx = i / RTE_RETA_GROUP_SIZE;
2297                 shift = i % RTE_RETA_GROUP_SIZE;
2298                 if (reta_conf[idx].mask & (1ULL << shift)) {
2299                         entry = qdev->rss_ind_table[i];
2300                         reta_conf[idx].reta[shift] = entry;
2301                 }
2302         }
2303
2304         return 0;
2305 }
2306
2307
2308
2309 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2310 {
2311         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2312         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2313         struct rte_eth_dev_info dev_info = {0};
2314         struct qede_fastpath *fp;
2315         uint32_t max_rx_pkt_len;
2316         uint32_t frame_size;
2317         uint16_t rx_buf_size;
2318         uint16_t bufsz;
2319         bool restart = false;
2320         int i;
2321
2322         PMD_INIT_FUNC_TRACE(edev);
2323         if (IS_VF(edev))
2324                 return -ENOTSUP;
2325         qede_dev_info_get(dev, &dev_info);
2326         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2327         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2328         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2329                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2330                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2331                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2332                 return -EINVAL;
2333         }
2334         if (!dev->data->scattered_rx &&
2335             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2336                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2337                         dev->data->min_rx_buf_size);
2338                 return -EINVAL;
2339         }
2340         /* Temporarily replace I/O functions with dummy ones. It cannot
2341          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2342          */
2343         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2344         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2345         if (dev->data->dev_started) {
2346                 dev->data->dev_started = 0;
2347                 qede_dev_stop(dev);
2348                 restart = true;
2349         }
2350         rte_delay_ms(1000);
2351         qdev->new_mtu = mtu;
2352         /* Fix up RX buf size for all queues of the port */
2353         for_each_rss(i) {
2354                 fp = &qdev->fp_array[i];
2355                 if (fp->rxq != NULL) {
2356                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2357                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2358                         if (dev->data->scattered_rx)
2359                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2360                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2361                         else
2362                                 rx_buf_size = frame_size;
2363                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2364                         fp->rxq->rx_buf_size = rx_buf_size;
2365                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2366                 }
2367         }
2368         if (max_rx_pkt_len > ETHER_MAX_LEN)
2369                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2370         else
2371                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2372         if (!dev->data->dev_started && restart) {
2373                 qede_dev_start(dev);
2374                 dev->data->dev_started = 1;
2375         }
2376         /* update max frame size */
2377         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2378         /* Reassign back */
2379         dev->rx_pkt_burst = qede_recv_pkts;
2380         dev->tx_pkt_burst = qede_xmit_pkts;
2381
2382         return 0;
2383 }
2384
2385 static int
2386 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2387                       struct rte_eth_udp_tunnel *tunnel_udp)
2388 {
2389         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2390         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2391         struct ecore_tunnel_info tunn; /* @DPDK */
2392         uint16_t udp_port;
2393         int rc;
2394
2395         PMD_INIT_FUNC_TRACE(edev);
2396
2397         memset(&tunn, 0, sizeof(tunn));
2398
2399         switch (tunnel_udp->prot_type) {
2400         case RTE_TUNNEL_TYPE_VXLAN:
2401                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2402                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2403                                 tunnel_udp->udp_port);
2404                         return ECORE_INVAL;
2405                 }
2406                 udp_port = 0;
2407
2408                 tunn.vxlan_port.b_update_port = true;
2409                 tunn.vxlan_port.port = udp_port;
2410
2411                 rc = qede_tunnel_update(qdev, &tunn);
2412                 if (rc != ECORE_SUCCESS) {
2413                         DP_ERR(edev, "Unable to config UDP port %u\n",
2414                                tunn.vxlan_port.port);
2415                         return rc;
2416                 }
2417
2418                 qdev->vxlan.udp_port = udp_port;
2419                 /* If the request is to delete UDP port and if the number of
2420                  * VXLAN filters have reached 0 then VxLAN offload can be be
2421                  * disabled.
2422                  */
2423                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2424                         return qede_vxlan_enable(eth_dev,
2425                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2426
2427                 break;
2428
2429         case RTE_TUNNEL_TYPE_GENEVE:
2430                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2431                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2432                                 tunnel_udp->udp_port);
2433                         return ECORE_INVAL;
2434                 }
2435
2436                 udp_port = 0;
2437
2438                 tunn.geneve_port.b_update_port = true;
2439                 tunn.geneve_port.port = udp_port;
2440
2441                 rc = qede_tunnel_update(qdev, &tunn);
2442                 if (rc != ECORE_SUCCESS) {
2443                         DP_ERR(edev, "Unable to config UDP port %u\n",
2444                                tunn.vxlan_port.port);
2445                         return rc;
2446                 }
2447
2448                 qdev->vxlan.udp_port = udp_port;
2449                 /* If the request is to delete UDP port and if the number of
2450                  * GENEVE filters have reached 0 then GENEVE offload can be be
2451                  * disabled.
2452                  */
2453                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2454                         return qede_geneve_enable(eth_dev,
2455                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2456
2457                 break;
2458
2459         default:
2460                 return ECORE_INVAL;
2461         }
2462
2463         return 0;
2464
2465 }
2466 static int
2467 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2468                       struct rte_eth_udp_tunnel *tunnel_udp)
2469 {
2470         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2472         struct ecore_tunnel_info tunn; /* @DPDK */
2473         uint16_t udp_port;
2474         int rc;
2475
2476         PMD_INIT_FUNC_TRACE(edev);
2477
2478         memset(&tunn, 0, sizeof(tunn));
2479
2480         switch (tunnel_udp->prot_type) {
2481         case RTE_TUNNEL_TYPE_VXLAN:
2482                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2483                         DP_INFO(edev,
2484                                 "UDP port %u for VXLAN was already configured\n",
2485                                 tunnel_udp->udp_port);
2486                         return ECORE_SUCCESS;
2487                 }
2488
2489                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2490                  * it was not enabled while adding VXLAN filter before UDP port
2491                  * update.
2492                  */
2493                 if (!qdev->vxlan.enable) {
2494                         rc = qede_vxlan_enable(eth_dev,
2495                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2496                         if (rc != ECORE_SUCCESS) {
2497                                 DP_ERR(edev, "Failed to enable VXLAN "
2498                                         "prior to updating UDP port\n");
2499                                 return rc;
2500                         }
2501                 }
2502                 udp_port = tunnel_udp->udp_port;
2503
2504                 tunn.vxlan_port.b_update_port = true;
2505                 tunn.vxlan_port.port = udp_port;
2506
2507                 rc = qede_tunnel_update(qdev, &tunn);
2508                 if (rc != ECORE_SUCCESS) {
2509                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2510                                udp_port);
2511                         return rc;
2512                 }
2513
2514                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2515
2516                 qdev->vxlan.udp_port = udp_port;
2517                 break;
2518
2519         case RTE_TUNNEL_TYPE_GENEVE:
2520                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2521                         DP_INFO(edev,
2522                                 "UDP port %u for GENEVE was already configured\n",
2523                                 tunnel_udp->udp_port);
2524                         return ECORE_SUCCESS;
2525                 }
2526
2527                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2528                  * it was not enabled while adding GENEVE filter before UDP port
2529                  * update.
2530                  */
2531                 if (!qdev->geneve.enable) {
2532                         rc = qede_geneve_enable(eth_dev,
2533                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2534                         if (rc != ECORE_SUCCESS) {
2535                                 DP_ERR(edev, "Failed to enable GENEVE "
2536                                         "prior to updating UDP port\n");
2537                                 return rc;
2538                         }
2539                 }
2540                 udp_port = tunnel_udp->udp_port;
2541
2542                 tunn.geneve_port.b_update_port = true;
2543                 tunn.geneve_port.port = udp_port;
2544
2545                 rc = qede_tunnel_update(qdev, &tunn);
2546                 if (rc != ECORE_SUCCESS) {
2547                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2548                                udp_port);
2549                         return rc;
2550                 }
2551
2552                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2553
2554                 qdev->geneve.udp_port = udp_port;
2555                 break;
2556
2557         default:
2558                 return ECORE_INVAL;
2559         }
2560
2561         return 0;
2562 }
2563
2564 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2565                                        uint32_t *clss, char *str)
2566 {
2567         uint16_t j;
2568         *clss = MAX_ECORE_TUNN_CLSS;
2569
2570         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2571                 if (filter == qede_tunn_types[j].rte_filter_type) {
2572                         *type = qede_tunn_types[j].qede_type;
2573                         *clss = qede_tunn_types[j].qede_tunn_clss;
2574                         strcpy(str, qede_tunn_types[j].string);
2575                         return;
2576                 }
2577         }
2578 }
2579
2580 static int
2581 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2582                               const struct rte_eth_tunnel_filter_conf *conf,
2583                               uint32_t type)
2584 {
2585         /* Init commmon ucast params first */
2586         qede_set_ucast_cmn_params(ucast);
2587
2588         /* Copy out the required fields based on classification type */
2589         ucast->type = type;
2590
2591         switch (type) {
2592         case ECORE_FILTER_VNI:
2593                 ucast->vni = conf->tenant_id;
2594         break;
2595         case ECORE_FILTER_INNER_VLAN:
2596                 ucast->vlan = conf->inner_vlan;
2597         break;
2598         case ECORE_FILTER_MAC:
2599                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2600                        ETHER_ADDR_LEN);
2601         break;
2602         case ECORE_FILTER_INNER_MAC:
2603                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2604                        ETHER_ADDR_LEN);
2605         break;
2606         case ECORE_FILTER_MAC_VNI_PAIR:
2607                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2608                         ETHER_ADDR_LEN);
2609                 ucast->vni = conf->tenant_id;
2610         break;
2611         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2612                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2613                         ETHER_ADDR_LEN);
2614                 ucast->vni = conf->tenant_id;
2615         break;
2616         case ECORE_FILTER_INNER_PAIR:
2617                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2618                         ETHER_ADDR_LEN);
2619                 ucast->vlan = conf->inner_vlan;
2620         break;
2621         default:
2622                 return -EINVAL;
2623         }
2624
2625         return ECORE_SUCCESS;
2626 }
2627
2628 static int
2629 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2630                          const struct rte_eth_tunnel_filter_conf *conf,
2631                          __attribute__((unused)) enum rte_filter_op filter_op,
2632                          enum ecore_tunn_clss *clss,
2633                          bool add)
2634 {
2635         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2636         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2637         struct ecore_filter_ucast ucast = {0};
2638         enum ecore_filter_ucast_type type;
2639         uint16_t filter_type = 0;
2640         char str[80];
2641         int rc;
2642
2643         filter_type = conf->filter_type;
2644         /* Determine if the given filter classification is supported */
2645         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2646         if (*clss == MAX_ECORE_TUNN_CLSS) {
2647                 DP_ERR(edev, "Unsupported filter type\n");
2648                 return -EINVAL;
2649         }
2650         /* Init tunnel ucast params */
2651         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2652         if (rc != ECORE_SUCCESS) {
2653                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2654                 conf->filter_type);
2655                 return rc;
2656         }
2657         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2658                 str, filter_op, ucast.type);
2659
2660         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2661
2662         /* Skip MAC/VLAN if filter is based on VNI */
2663         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2664                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2665                 if ((rc == 0) && add) {
2666                         /* Enable accept anyvlan */
2667                         qede_config_accept_any_vlan(qdev, true);
2668                 }
2669         } else {
2670                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2671                 if (rc == 0)
2672                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2673                                             ECORE_SPQ_MODE_CB, NULL);
2674         }
2675
2676         return rc;
2677 }
2678
2679 static int
2680 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2681                         enum rte_filter_op filter_op,
2682                         const struct rte_eth_tunnel_filter_conf *conf)
2683 {
2684         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2685         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2686         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2687         bool add;
2688         int rc;
2689
2690         PMD_INIT_FUNC_TRACE(edev);
2691
2692         switch (filter_op) {
2693         case RTE_ETH_FILTER_ADD:
2694                 add = true;
2695                 break;
2696         case RTE_ETH_FILTER_DELETE:
2697                 add = false;
2698                 break;
2699         default:
2700                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2701                 return -EINVAL;
2702         }
2703
2704         if (IS_VF(edev))
2705                 return qede_tunn_enable(eth_dev,
2706                                         ECORE_TUNN_CLSS_MAC_VLAN,
2707                                         conf->tunnel_type, add);
2708
2709         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2710         if (rc != ECORE_SUCCESS)
2711                 return rc;
2712
2713         if (add) {
2714                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2715                         qdev->vxlan.num_filters++;
2716                         qdev->vxlan.filter_type = conf->filter_type;
2717                 } else { /* GENEVE */
2718                         qdev->geneve.num_filters++;
2719                         qdev->geneve.filter_type = conf->filter_type;
2720                 }
2721
2722                 if (!qdev->vxlan.enable || !qdev->geneve.enable)
2723                         return qede_tunn_enable(eth_dev, clss,
2724                                                 conf->tunnel_type,
2725                                                 true);
2726         } else {
2727                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2728                         qdev->vxlan.num_filters--;
2729                 else /*GENEVE*/
2730                         qdev->geneve.num_filters--;
2731
2732                 /* Disable VXLAN if VXLAN filters become 0 */
2733                 if ((qdev->vxlan.num_filters == 0) ||
2734                     (qdev->geneve.num_filters == 0))
2735                         return qede_tunn_enable(eth_dev, clss,
2736                                                 conf->tunnel_type,
2737                                                 false);
2738         }
2739
2740         return 0;
2741 }
2742
2743 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2744                          enum rte_filter_type filter_type,
2745                          enum rte_filter_op filter_op,
2746                          void *arg)
2747 {
2748         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2749         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2750         struct rte_eth_tunnel_filter_conf *filter_conf =
2751                         (struct rte_eth_tunnel_filter_conf *)arg;
2752
2753         switch (filter_type) {
2754         case RTE_ETH_FILTER_TUNNEL:
2755                 switch (filter_conf->tunnel_type) {
2756                 case RTE_TUNNEL_TYPE_VXLAN:
2757                 case RTE_TUNNEL_TYPE_GENEVE:
2758                         DP_INFO(edev,
2759                                 "Packet steering to the specified Rx queue"
2760                                 " is not supported with UDP tunneling");
2761                         return(qede_tunn_filter_config(eth_dev, filter_op,
2762                                                       filter_conf));
2763                 /* Place holders for future tunneling support */
2764                 case RTE_TUNNEL_TYPE_TEREDO:
2765                 case RTE_TUNNEL_TYPE_NVGRE:
2766                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2767                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2768                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2769                                 filter_conf->tunnel_type);
2770                         return -EINVAL;
2771                 case RTE_TUNNEL_TYPE_NONE:
2772                 default:
2773                         return 0;
2774                 }
2775                 break;
2776         case RTE_ETH_FILTER_FDIR:
2777                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2778         case RTE_ETH_FILTER_NTUPLE:
2779                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2780         case RTE_ETH_FILTER_MACVLAN:
2781         case RTE_ETH_FILTER_ETHERTYPE:
2782         case RTE_ETH_FILTER_FLEXIBLE:
2783         case RTE_ETH_FILTER_SYN:
2784         case RTE_ETH_FILTER_HASH:
2785         case RTE_ETH_FILTER_L2_TUNNEL:
2786         case RTE_ETH_FILTER_MAX:
2787         default:
2788                 DP_ERR(edev, "Unsupported filter type %d\n",
2789                         filter_type);
2790                 return -EINVAL;
2791         }
2792
2793         return 0;
2794 }
2795
2796 static const struct eth_dev_ops qede_eth_dev_ops = {
2797         .dev_configure = qede_dev_configure,
2798         .dev_infos_get = qede_dev_info_get,
2799         .rx_queue_setup = qede_rx_queue_setup,
2800         .rx_queue_release = qede_rx_queue_release,
2801         .tx_queue_setup = qede_tx_queue_setup,
2802         .tx_queue_release = qede_tx_queue_release,
2803         .dev_start = qede_dev_start,
2804         .dev_set_link_up = qede_dev_set_link_up,
2805         .dev_set_link_down = qede_dev_set_link_down,
2806         .link_update = qede_link_update,
2807         .promiscuous_enable = qede_promiscuous_enable,
2808         .promiscuous_disable = qede_promiscuous_disable,
2809         .allmulticast_enable = qede_allmulticast_enable,
2810         .allmulticast_disable = qede_allmulticast_disable,
2811         .dev_stop = qede_dev_stop,
2812         .dev_close = qede_dev_close,
2813         .stats_get = qede_get_stats,
2814         .stats_reset = qede_reset_stats,
2815         .xstats_get = qede_get_xstats,
2816         .xstats_reset = qede_reset_xstats,
2817         .xstats_get_names = qede_get_xstats_names,
2818         .mac_addr_add = qede_mac_addr_add,
2819         .mac_addr_remove = qede_mac_addr_remove,
2820         .mac_addr_set = qede_mac_addr_set,
2821         .vlan_offload_set = qede_vlan_offload_set,
2822         .vlan_filter_set = qede_vlan_filter_set,
2823         .flow_ctrl_set = qede_flow_ctrl_set,
2824         .flow_ctrl_get = qede_flow_ctrl_get,
2825         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2826         .rss_hash_update = qede_rss_hash_update,
2827         .rss_hash_conf_get = qede_rss_hash_conf_get,
2828         .reta_update  = qede_rss_reta_update,
2829         .reta_query  = qede_rss_reta_query,
2830         .mtu_set = qede_set_mtu,
2831         .filter_ctrl = qede_dev_filter_ctrl,
2832         .udp_tunnel_port_add = qede_udp_dst_port_add,
2833         .udp_tunnel_port_del = qede_udp_dst_port_del,
2834 };
2835
2836 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2837         .dev_configure = qede_dev_configure,
2838         .dev_infos_get = qede_dev_info_get,
2839         .rx_queue_setup = qede_rx_queue_setup,
2840         .rx_queue_release = qede_rx_queue_release,
2841         .tx_queue_setup = qede_tx_queue_setup,
2842         .tx_queue_release = qede_tx_queue_release,
2843         .dev_start = qede_dev_start,
2844         .dev_set_link_up = qede_dev_set_link_up,
2845         .dev_set_link_down = qede_dev_set_link_down,
2846         .link_update = qede_link_update,
2847         .promiscuous_enable = qede_promiscuous_enable,
2848         .promiscuous_disable = qede_promiscuous_disable,
2849         .allmulticast_enable = qede_allmulticast_enable,
2850         .allmulticast_disable = qede_allmulticast_disable,
2851         .dev_stop = qede_dev_stop,
2852         .dev_close = qede_dev_close,
2853         .stats_get = qede_get_stats,
2854         .stats_reset = qede_reset_stats,
2855         .xstats_get = qede_get_xstats,
2856         .xstats_reset = qede_reset_xstats,
2857         .xstats_get_names = qede_get_xstats_names,
2858         .vlan_offload_set = qede_vlan_offload_set,
2859         .vlan_filter_set = qede_vlan_filter_set,
2860         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2861         .rss_hash_update = qede_rss_hash_update,
2862         .rss_hash_conf_get = qede_rss_hash_conf_get,
2863         .reta_update  = qede_rss_reta_update,
2864         .reta_query  = qede_rss_reta_query,
2865         .mtu_set = qede_set_mtu,
2866         .udp_tunnel_port_add = qede_udp_dst_port_add,
2867         .udp_tunnel_port_del = qede_udp_dst_port_del,
2868 };
2869
2870 static void qede_update_pf_params(struct ecore_dev *edev)
2871 {
2872         struct ecore_pf_params pf_params;
2873
2874         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2875         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2876         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2877         qed_ops->common->update_pf_params(edev, &pf_params);
2878 }
2879
2880 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2881 {
2882         struct rte_pci_device *pci_dev;
2883         struct rte_pci_addr pci_addr;
2884         struct qede_dev *adapter;
2885         struct ecore_dev *edev;
2886         struct qed_dev_eth_info dev_info;
2887         struct qed_slowpath_params params;
2888         static bool do_once = true;
2889         uint8_t bulletin_change;
2890         uint8_t vf_mac[ETHER_ADDR_LEN];
2891         uint8_t is_mac_forced;
2892         bool is_mac_exist;
2893         /* Fix up ecore debug level */
2894         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2895         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2896         int rc;
2897
2898         /* Extract key data structures */
2899         adapter = eth_dev->data->dev_private;
2900         adapter->ethdev = eth_dev;
2901         edev = &adapter->edev;
2902         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2903         pci_addr = pci_dev->addr;
2904
2905         PMD_INIT_FUNC_TRACE(edev);
2906
2907         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2908                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2909                  eth_dev->data->port_id);
2910
2911         eth_dev->rx_pkt_burst = qede_recv_pkts;
2912         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2913         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2914
2915         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2916                 DP_ERR(edev, "Skipping device init from secondary process\n");
2917                 return 0;
2918         }
2919
2920         rte_eth_copy_pci_info(eth_dev, pci_dev);
2921
2922         /* @DPDK */
2923         edev->vendor_id = pci_dev->id.vendor_id;
2924         edev->device_id = pci_dev->id.device_id;
2925
2926         qed_ops = qed_get_eth_ops();
2927         if (!qed_ops) {
2928                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2929                 return -EINVAL;
2930         }
2931
2932         DP_INFO(edev, "Starting qede probe\n");
2933         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2934                                     dp_level, is_vf);
2935         if (rc != 0) {
2936                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2937                 return -ENODEV;
2938         }
2939         qede_update_pf_params(edev);
2940         rte_intr_callback_register(&pci_dev->intr_handle,
2941                                    qede_interrupt_handler, (void *)eth_dev);
2942         if (rte_intr_enable(&pci_dev->intr_handle)) {
2943                 DP_ERR(edev, "rte_intr_enable() failed\n");
2944                 return -ENODEV;
2945         }
2946
2947         /* Start the Slowpath-process */
2948         memset(&params, 0, sizeof(struct qed_slowpath_params));
2949         params.int_mode = ECORE_INT_MODE_MSIX;
2950         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2951         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2952         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2953         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2954         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2955                 QEDE_PMD_DRV_VER_STR_SIZE);
2956
2957         /* For CMT mode device do periodic polling for slowpath events.
2958          * This is required since uio device uses only one MSI-x
2959          * interrupt vector but we need one for each engine.
2960          */
2961         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2962                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2963                                        qede_poll_sp_sb_cb,
2964                                        (void *)eth_dev);
2965                 if (rc != 0) {
2966                         DP_ERR(edev, "Unable to start periodic"
2967                                      " timer rc %d\n", rc);
2968                         return -EINVAL;
2969                 }
2970         }
2971
2972         rc = qed_ops->common->slowpath_start(edev, &params);
2973         if (rc) {
2974                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2975                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2976                                      (void *)eth_dev);
2977                 return -ENODEV;
2978         }
2979
2980         rc = qed_ops->fill_dev_info(edev, &dev_info);
2981         if (rc) {
2982                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2983                 qed_ops->common->slowpath_stop(edev);
2984                 qed_ops->common->remove(edev);
2985                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2986                                      (void *)eth_dev);
2987                 return -ENODEV;
2988         }
2989
2990         qede_alloc_etherdev(adapter, &dev_info);
2991
2992         adapter->ops->common->set_name(edev, edev->name);
2993
2994         if (!is_vf)
2995                 adapter->dev_info.num_mac_filters =
2996                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2997                                             ECORE_MAC);
2998         else
2999                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3000                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3001
3002         /* Allocate memory for storing MAC addr */
3003         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3004                                         (ETHER_ADDR_LEN *
3005                                         adapter->dev_info.num_mac_filters),
3006                                         RTE_CACHE_LINE_SIZE);
3007
3008         if (eth_dev->data->mac_addrs == NULL) {
3009                 DP_ERR(edev, "Failed to allocate MAC address\n");
3010                 qed_ops->common->slowpath_stop(edev);
3011                 qed_ops->common->remove(edev);
3012                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3013                                      (void *)eth_dev);
3014                 return -ENOMEM;
3015         }
3016
3017         if (!is_vf) {
3018                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3019                                 hw_info.hw_mac_addr,
3020                                 &eth_dev->data->mac_addrs[0]);
3021                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3022                                 &adapter->primary_mac);
3023         } else {
3024                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3025                                        &bulletin_change);
3026                 if (bulletin_change) {
3027                         is_mac_exist =
3028                             ecore_vf_bulletin_get_forced_mac(
3029                                                 ECORE_LEADING_HWFN(edev),
3030                                                 vf_mac,
3031                                                 &is_mac_forced);
3032                         if (is_mac_exist && is_mac_forced) {
3033                                 DP_INFO(edev, "VF macaddr received from PF\n");
3034                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3035                                                 &eth_dev->data->mac_addrs[0]);
3036                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3037                                                 &adapter->primary_mac);
3038                         } else {
3039                                 DP_ERR(edev, "No VF macaddr assigned\n");
3040                         }
3041                 }
3042         }
3043
3044         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3045
3046         if (do_once) {
3047                 qede_print_adapter_info(adapter);
3048                 do_once = false;
3049         }
3050
3051         adapter->num_tx_queues = 0;
3052         adapter->num_rx_queues = 0;
3053         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3054         SLIST_INIT(&adapter->vlan_list_head);
3055         SLIST_INIT(&adapter->uc_list_head);
3056         adapter->mtu = ETHER_MTU;
3057         adapter->new_mtu = ETHER_MTU;
3058         if (!is_vf) {
3059                 if (qede_start_vport(adapter, adapter->mtu))
3060                         return -1;
3061         } else {
3062                 /* VF tunnel offloads is enabled by default in PF driver */
3063                 adapter->vxlan.enable = true;
3064                 adapter->vxlan.num_filters = 0;
3065                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3066                                              ETH_TUNNEL_FILTER_IVLAN;
3067                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3068                 adapter->geneve.enable = true;
3069                 adapter->vxlan.num_filters = 0;
3070                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3071                                              ETH_TUNNEL_FILTER_IVLAN;
3072                 adapter->vxlan.udp_port = QEDE_GENEVE_DEF_PORT;
3073         }
3074
3075         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3076                 adapter->primary_mac.addr_bytes[0],
3077                 adapter->primary_mac.addr_bytes[1],
3078                 adapter->primary_mac.addr_bytes[2],
3079                 adapter->primary_mac.addr_bytes[3],
3080                 adapter->primary_mac.addr_bytes[4],
3081                 adapter->primary_mac.addr_bytes[5]);
3082
3083         DP_INFO(edev, "Device initialized\n");
3084
3085         return 0;
3086 }
3087
3088 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3089 {
3090         return qede_common_dev_init(eth_dev, 1);
3091 }
3092
3093 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3094 {
3095         return qede_common_dev_init(eth_dev, 0);
3096 }
3097
3098 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3099 {
3100 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3101         struct qede_dev *qdev = eth_dev->data->dev_private;
3102         struct ecore_dev *edev = &qdev->edev;
3103
3104         PMD_INIT_FUNC_TRACE(edev);
3105 #endif
3106
3107         /* only uninitialize in the primary process */
3108         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3109                 return 0;
3110
3111         /* safe to close dev here */
3112         qede_dev_close(eth_dev);
3113
3114         eth_dev->dev_ops = NULL;
3115         eth_dev->rx_pkt_burst = NULL;
3116         eth_dev->tx_pkt_burst = NULL;
3117
3118         if (eth_dev->data->mac_addrs)
3119                 rte_free(eth_dev->data->mac_addrs);
3120
3121         eth_dev->data->mac_addrs = NULL;
3122
3123         return 0;
3124 }
3125
3126 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3127 {
3128         return qede_dev_common_uninit(eth_dev);
3129 }
3130
3131 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3132 {
3133         return qede_dev_common_uninit(eth_dev);
3134 }
3135
3136 static const struct rte_pci_id pci_id_qedevf_map[] = {
3137 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3138         {
3139                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3140         },
3141         {
3142                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3143         },
3144         {
3145                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3146         },
3147         {.vendor_id = 0,}
3148 };
3149
3150 static const struct rte_pci_id pci_id_qede_map[] = {
3151 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3152         {
3153                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3154         },
3155         {
3156                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3157         },
3158         {
3159                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3160         },
3161         {
3162                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3163         },
3164         {
3165                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3166         },
3167         {
3168                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3169         },
3170         {
3171                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3172         },
3173         {
3174                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3175         },
3176         {
3177                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3178         },
3179         {
3180                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3181         },
3182         {.vendor_id = 0,}
3183 };
3184
3185 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3186         struct rte_pci_device *pci_dev)
3187 {
3188         return rte_eth_dev_pci_generic_probe(pci_dev,
3189                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3190 }
3191
3192 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3193 {
3194         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3195 }
3196
3197 static struct rte_pci_driver rte_qedevf_pmd = {
3198         .id_table = pci_id_qedevf_map,
3199         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3200         .probe = qedevf_eth_dev_pci_probe,
3201         .remove = qedevf_eth_dev_pci_remove,
3202 };
3203
3204 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3205         struct rte_pci_device *pci_dev)
3206 {
3207         return rte_eth_dev_pci_generic_probe(pci_dev,
3208                 sizeof(struct qede_dev), qede_eth_dev_init);
3209 }
3210
3211 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3212 {
3213         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3214 }
3215
3216 static struct rte_pci_driver rte_qede_pmd = {
3217         .id_table = pci_id_qede_map,
3218         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3219         .probe = qede_eth_dev_pci_probe,
3220         .remove = qede_eth_dev_pci_remove,
3221 };
3222
3223 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3224 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3225 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3226 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3227 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3228 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3229
3230 RTE_INIT(qede_init_log);
3231 static void
3232 qede_init_log(void)
3233 {
3234         qede_logtype_init = rte_log_register("pmd.qede.init");
3235         if (qede_logtype_init >= 0)
3236                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3237         qede_logtype_driver = rte_log_register("pmd.qede.driver");
3238         if (qede_logtype_driver >= 0)
3239                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3240 }