drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(eth_dev->intr_handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->num_tc = qdev->dev_info.num_tc;
 298         qdev->ops = qed_ops;
 299 }
 300
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329
 330 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 331 {
 332         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 333         ucast->is_rx_filter = true;
 334         ucast->is_tx_filter = true;
 335         /* ucast->assert_on_error = true; - For debug */
 336 }
 337
 338 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 339                                     uint8_t clss, bool mode, bool mask)
 340 {
 341         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 342         p_tunn->vxlan.b_update_mode = mode;
 343         p_tunn->vxlan.b_mode_enabled = mask;
 344         p_tunn->b_update_rx_cls = true;
 345         p_tunn->b_update_tx_cls = true;
 346         p_tunn->vxlan.tun_cls = clss;
 347 }
 348
 349 static int
 350 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 351                   bool add)
 352 {
 353         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 354         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 355         struct qede_ucast_entry *tmp = NULL;
 356         struct qede_ucast_entry *u;
 357         struct ether_addr *mac_addr;
 358
 359         mac_addr  = (struct ether_addr *)ucast->mac;
 360         if (add) {
 361                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 362                         if ((memcmp(mac_addr, &tmp->mac,
 363                                     ETHER_ADDR_LEN) == 0) &&
 364                              ucast->vlan == tmp->vlan) {
 365                                 DP_ERR(edev, "Unicast MAC is already added"
 366                                        " with vlan = %u, vni = %u\n",
 367                                        ucast->vlan,  ucast->vni);
 368                                         return -EEXIST;
 369                         }
 370                 }
 371                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 372                                RTE_CACHE_LINE_SIZE);
 373                 if (!u) {
 374                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 375                         return -ENOMEM;
 376                 }
 377                 ether_addr_copy(mac_addr, &u->mac);
 378                 u->vlan = ucast->vlan;
 379                 u->vni = ucast->vni;
 380                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 381                 qdev->num_uc_addr++;
 382         } else {
 383                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 384                         if ((memcmp(mac_addr, &tmp->mac,
 385                                     ETHER_ADDR_LEN) == 0) &&
 386                             ucast->vlan == tmp->vlan      &&
 387                             ucast->vni == tmp->vni)
 388                         break;
 389                 }
 390                 if (tmp == NULL) {
 391                         DP_INFO(edev, "Unicast MAC is not found\n");
 392                         return -EINVAL;
 393                 }
 394                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 395                 qdev->num_uc_addr--;
 396         }
 397
 398         return 0;
 399 }
 400
 401 static int
 402 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 403                   bool add)
 404 {
 405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 407         struct ether_addr *mac_addr;
 408         struct qede_mcast_entry *tmp = NULL;
 409         struct qede_mcast_entry *m;
 410
 411         mac_addr  = (struct ether_addr *)mcast->mac;
 412         if (add) {
 413                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 414                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 415                                 DP_ERR(edev,
 416                                         "Multicast MAC is already added\n");
 417                                 return -EEXIST;
 418                         }
 419                 }
 420                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 421                         RTE_CACHE_LINE_SIZE);
 422                 if (!m) {
 423                         DP_ERR(edev,
 424                                 "Did not allocate memory for mcast\n");
 425                         return -ENOMEM;
 426                 }
 427                 ether_addr_copy(mac_addr, &m->mac);
 428                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 429                 qdev->num_mc_addr++;
 430         } else {
 431                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 432                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 433                                 break;
 434                 }
 435                 if (tmp == NULL) {
 436                         DP_INFO(edev, "Multicast mac is not found\n");
 437                         return -EINVAL;
 438                 }
 439                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 440                              qede_mcast_entry, list);
 441                 qdev->num_mc_addr--;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static enum _ecore_status_t
 448 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 449                  bool add)
 450 {
 451         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 452         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 453         enum _ecore_status_t rc;
 454         struct ecore_filter_mcast mcast;
 455         struct qede_mcast_entry *tmp;
 456         uint16_t j = 0;
 457
 458         /* Multicast */
 459         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 460                 if (add) {
 461                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 462                                 DP_ERR(edev,
 463                                        "Mcast filter table limit exceeded, "
 464                                        "Please enable mcast promisc mode\n");
 465                                 return -ECORE_INVAL;
 466                         }
 467                 }
 468                 rc = qede_mcast_filter(eth_dev, ucast, add);
 469                 if (rc == 0) {
 470                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 471                         memset(&mcast, 0, sizeof(mcast));
 472                         mcast.num_mc_addrs = qdev->num_mc_addr;
 473                         mcast.opcode = ECORE_FILTER_ADD;
 474                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 475                                 ether_addr_copy(&tmp->mac,
 476                                         (struct ether_addr *)&mcast.mac[j]);
 477                                 j++;
 478                         }
 479                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 480                                                     ECORE_SPQ_MODE_CB, NULL);
 481                 }
 482                 if (rc != ECORE_SUCCESS) {
 483                         DP_ERR(edev, "Failed to add multicast filter"
 484                                " rc = %d, op = %d\n", rc, add);
 485                 }
 486         } else { /* Unicast */
 487                 if (add) {
 488                         if (qdev->num_uc_addr >=
 489                             qdev->dev_info.num_mac_filters) {
 490                                 DP_ERR(edev,
 491                                        "Ucast filter table limit exceeded,"
 492                                        " Please enable promisc mode\n");
 493                                 return -ECORE_INVAL;
 494                         }
 495                 }
 496                 rc = qede_ucast_filter(eth_dev, ucast, add);
 497                 if (rc == 0)
 498                         rc = ecore_filter_ucast_cmd(edev, ucast,
 499                                                     ECORE_SPQ_MODE_CB, NULL);
 500                 if (rc != ECORE_SUCCESS) {
 501                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 502                                rc, add);
 503                 }
 504         }
 505
 506         return rc;
 507 }
 508
 509 static void
 510 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 511                   uint32_t index, __rte_unused uint32_t pool)
 512 {
 513         struct ecore_filter_ucast ucast;
 514
 515         qede_set_ucast_cmn_params(&ucast);
 516         ucast.type = ECORE_FILTER_MAC;
 517         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 518         (void)qede_mac_int_ops(eth_dev, &ucast, 1);
 519 }
 520
 521 static void
 522 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 523 {
 524         struct qede_dev *qdev = eth_dev->data->dev_private;
 525         struct ecore_dev *edev = &qdev->edev;
 526         struct ether_addr mac_addr;
 527         struct ecore_filter_ucast ucast;
 528         int rc;
 529
 530         PMD_INIT_FUNC_TRACE(edev);
 531
 532         if (index >= qdev->dev_info.num_mac_filters) {
 533                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 534                        index, qdev->dev_info.num_mac_filters);
 535                 return;
 536         }
 537
 538         qede_set_ucast_cmn_params(&ucast);
 539         ucast.opcode = ECORE_FILTER_REMOVE;
 540         ucast.type = ECORE_FILTER_MAC;
 541
 542         /* Use the index maintained by rte */
 543         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 544                         (struct ether_addr *)&ucast.mac);
 545
 546         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 547 }
 548
 549 static void
 550 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 551 {
 552         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 553         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 554
 555         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 556                                                mac_addr->addr_bytes)) {
 557                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 558                 ether_addr_copy(&qdev->primary_mac,
 559                                 &eth_dev->data->mac_addrs[0]);
 560                 return;
 561         }
 562
 563         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 564 }
 565
 566 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 567 {
 568         struct ecore_dev *edev = &qdev->edev;
 569         struct qed_update_vport_params params = {
 570                 .vport_id = 0,
 571                 .accept_any_vlan = action,
 572                 .update_accept_any_vlan_flg = 1,
 573         };
 574         int rc;
 575
 576         /* Proceed only if action actually needs to be performed */
 577         if (qdev->accept_any_vlan == action)
 578                 return;
 579
 580         rc = qdev->ops->vport_update(edev, &params);
 581         if (rc) {
 582                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 583                        action ? "enable" : "disable");
 584         } else {
 585                 DP_INFO(edev, "%s accept-any-vlan\n",
 586                         action ? "enabled" : "disabled");
 587                 qdev->accept_any_vlan = action;
 588         }
 589 }
 590
 591 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 592 {
 593         struct qed_update_vport_params vport_update_params;
 594         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 595         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 596         int rc;
 597
 598         memset(&vport_update_params, 0, sizeof(vport_update_params));
 599         vport_update_params.vport_id = 0;
 600         vport_update_params.update_inner_vlan_removal_flg = 1;
 601         vport_update_params.inner_vlan_removal_flg = set_stripping;
 602         rc = qdev->ops->vport_update(edev, &vport_update_params);
 603         if (rc) {
 604                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 605                 return rc;
 606         }
 607         qdev->vlan_strip_flg = set_stripping;
 608
 609         return 0;
 610 }
 611
 612 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 613 {
 614         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 615         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 616         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 617
 618         if (mask & ETH_VLAN_STRIP_MASK) {
 619                 if (rxmode->hw_vlan_strip)
 620                         (void)qede_vlan_stripping(eth_dev, 1);
 621                 else
 622                         (void)qede_vlan_stripping(eth_dev, 0);
 623         }
 624
 625         if (mask & ETH_VLAN_FILTER_MASK) {
 626                 /* VLAN filtering kicks in when a VLAN is added */
 627                 if (rxmode->hw_vlan_filter) {
 628                         qede_vlan_filter_set(eth_dev, 0, 1);
 629                 } else {
 630                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 631                                 DP_ERR(edev,
 632                                   " Please remove existing VLAN filters"
 633                                   " before disabling VLAN filtering\n");
 634                                 /* Signal app that VLAN filtering is still
 635                                  * enabled
 636                                  */
 637                                 rxmode->hw_vlan_filter = true;
 638                         } else {
 639                                 qede_vlan_filter_set(eth_dev, 0, 0);
 640                         }
 641                 }
 642         }
 643
 644         if (mask & ETH_VLAN_EXTEND_MASK)
 645                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 646                         " and classification is based on outer tag only\n");
 647
 648         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 649                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 650 }
 651
 652 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 653                                 uint16_t vlan_id, int on)
 654 {
 655         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 656         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 657         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 658         struct qede_vlan_entry *tmp = NULL;
 659         struct qede_vlan_entry *vlan;
 660         struct ecore_filter_ucast ucast;
 661         int rc;
 662
 663         if (on) {
 664                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 665                         DP_ERR(edev, "Reached max VLAN filter limit"
 666                                       " enabling accept_any_vlan\n");
 667                         qede_config_accept_any_vlan(qdev, true);
 668                         return 0;
 669                 }
 670
 671                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 672                         if (tmp->vid == vlan_id) {
 673                                 DP_ERR(edev, "VLAN %u already configured\n",
 674                                        vlan_id);
 675                                 return -EEXIST;
 676                         }
 677                 }
 678
 679                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 680                                   RTE_CACHE_LINE_SIZE);
 681
 682                 if (!vlan) {
 683                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 684                         return -ENOMEM;
 685                 }
 686
 687                 qede_set_ucast_cmn_params(&ucast);
 688                 ucast.opcode = ECORE_FILTER_ADD;
 689                 ucast.type = ECORE_FILTER_VLAN;
 690                 ucast.vlan = vlan_id;
 691                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 692                                             NULL);
 693                 if (rc != 0) {
 694                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 695                                rc);
 696                         rte_free(vlan);
 697                 } else {
 698                         vlan->vid = vlan_id;
 699                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 700                         qdev->configured_vlans++;
 701                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 702                                 vlan_id, qdev->configured_vlans);
 703                 }
 704         } else {
 705                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 706                         if (tmp->vid == vlan_id)
 707                                 break;
 708                 }
 709
 710                 if (!tmp) {
 711                         if (qdev->configured_vlans == 0) {
 712                                 DP_INFO(edev,
 713                                         "No VLAN filters configured yet\n");
 714                                 return 0;
 715                         }
 716
 717                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 718                         return -EINVAL;
 719                 }
 720
 721                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 722
 723                 qede_set_ucast_cmn_params(&ucast);
 724                 ucast.opcode = ECORE_FILTER_REMOVE;
 725                 ucast.type = ECORE_FILTER_VLAN;
 726                 ucast.vlan = vlan_id;
 727                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 728                                             NULL);
 729                 if (rc != 0) {
 730                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 731                                vlan_id, rc);
 732                 } else {
 733                         qdev->configured_vlans--;
 734                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 735                                 vlan_id, qdev->configured_vlans);
 736                 }
 737         }
 738
 739         return rc;
 740 }
 741
 742 static int qede_init_vport(struct qede_dev *qdev)
 743 {
 744         struct ecore_dev *edev = &qdev->edev;
 745         struct qed_start_vport_params start = {0};
 746         int rc;
 747
 748         start.remove_inner_vlan = 1;
 749         start.enable_lro = qdev->enable_lro;
 750         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 751         start.vport_id = 0;
 752         start.drop_ttl0 = false;
 753         start.clear_stats = 1;
 754         start.handle_ptp_pkts = 0;
 755
 756         rc = qdev->ops->vport_start(edev, &start);
 757         if (rc) {
 758                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 759                 return rc;
 760         }
 761
 762         DP_INFO(edev,
 763                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 764                 start.vport_id, ETHER_MTU);
 765
 766         return 0;
 767 }
 768
 769 static void qede_prandom_bytes(uint32_t *buff)
 770 {
 771         uint8_t i;
 772
 773         srand((unsigned int)time(NULL));
 774         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 775                 buff[i] = rand();
 776 }
 777
 778 int qede_config_rss(struct rte_eth_dev *eth_dev)
 779 {
 780         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 781         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 782         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 783         struct rte_eth_rss_reta_entry64 reta_conf[2];
 784         struct rte_eth_rss_conf rss_conf;
 785         uint32_t i, id, pos, q;
 786
 787         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 788         if (!rss_conf.rss_key) {
 789                 DP_INFO(edev, "Applying driver default key\n");
 790                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 791                 qede_prandom_bytes(&def_rss_key[0]);
 792                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 793         }
 794
 795         /* Configure RSS hash */
 796         if (qede_rss_hash_update(eth_dev, &rss_conf))
 797                 return -EINVAL;
 798
 799         /* Configure default RETA */
 800         memset(reta_conf, 0, sizeof(reta_conf));
 801         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 802                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 803
 804         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 805                 id = i / RTE_RETA_GROUP_SIZE;
 806                 pos = i % RTE_RETA_GROUP_SIZE;
 807                 q = i % QEDE_RSS_COUNT(qdev);
 808                 reta_conf[id].reta[pos] = q;
 809         }
 810         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 811                                  ECORE_RSS_IND_TABLE_SIZE))
 812                 return -EINVAL;
 813
 814         return 0;
 815 }
 816
 817 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 818 {
 819         struct qede_dev *qdev = eth_dev->data->dev_private;
 820         struct ecore_dev *edev = &qdev->edev;
 821         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 822         int rc, i, j;
 823
 824         PMD_INIT_FUNC_TRACE(edev);
 825
 826         /* Check requirements for 100G mode */
 827         if (edev->num_hwfns > 1) {
 828                 if (eth_dev->data->nb_rx_queues < 2 ||
 829                     eth_dev->data->nb_tx_queues < 2) {
 830                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
 831                         return -EINVAL;
 832                 }
 833
 834                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 835                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 836                         DP_ERR(edev,
 837                                   "100G mode needs even no. of RX/TX queues\n");
 838                         return -EINVAL;
 839                 }
 840         }
 841
 842         /* Sanity checks and throw warnings */
 843         if (rxmode->enable_scatter == 1)
 844                 eth_dev->data->scattered_rx = 1;
 845
 846         if (!rxmode->hw_strip_crc)
 847                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 848
 849         if (!rxmode->hw_ip_checksum)
 850                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 851                               "in hw\n");
 852
 853         if (rxmode->enable_lro) {
 854                 qdev->enable_lro = true;
 855                 /* Enable scatter mode for LRO */
 856                 if (!rxmode->enable_scatter)
 857                         eth_dev->data->scattered_rx = 1;
 858         }
 859
 860         /* Check for the port restart case */
 861         if (qdev->state != QEDE_DEV_INIT) {
 862                 rc = qdev->ops->vport_stop(edev, 0);
 863                 if (rc != 0)
 864                         return rc;
 865                 qede_dealloc_fp_resc(eth_dev);
 866         }
 867
 868         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 869         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 870         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 871
 872         /* Fastpath status block should be initialized before sending
 873          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 874          */
 875         rc = qede_alloc_fp_resc(qdev);
 876         if (rc != 0)
 877                 return rc;
 878
 879         /* Issue VPORT-START with default config values to allow
 880          * other port configurations early on.
 881          */
 882         rc = qede_init_vport(qdev);
 883         if (rc != 0)
 884                 return rc;
 885
 886         if (!(rxmode->mq_mode == ETH_MQ_RX_RSS ||
 887             rxmode->mq_mode == ETH_MQ_RX_NONE)) {
 888                 DP_ERR(edev, "Unsupported RSS mode\n");
 889                 qdev->ops->vport_stop(edev, 0);
 890                 qede_dealloc_fp_resc(eth_dev);
 891                 return -EINVAL;
 892         }
 893
 894         /* Flow director mode check */
 895         rc = qede_check_fdir_support(eth_dev);
 896         if (rc) {
 897                 qdev->ops->vport_stop(edev, 0);
 898                 qede_dealloc_fp_resc(eth_dev);
 899                 return -EINVAL;
 900         }
 901         SLIST_INIT(&qdev->fdir_info.fdir_list_head);
 902
 903         SLIST_INIT(&qdev->vlan_list_head);
 904
 905         /* Enable VLAN offloads by default */
 906         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
 907                                        ETH_VLAN_FILTER_MASK |
 908                                        ETH_VLAN_EXTEND_MASK);
 909
 910         qdev->state = QEDE_DEV_CONFIG;
 911
 912         DP_INFO(edev, "Allocated RSS=%d TSS=%d (with CoS=%d)\n",
 913                 (int)QEDE_RSS_COUNT(qdev), (int)QEDE_TSS_COUNT(qdev),
 914                 qdev->num_tc);
 915
 916         return 0;
 917 }
 918
 919 /* Info about HW descriptor ring limitations */
 920 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 921         .nb_max = NUM_RX_BDS_MAX,
 922         .nb_min = 128,
 923         .nb_align = 128 /* lowest common multiple */
 924 };
 925
 926 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 927         .nb_max = NUM_TX_BDS_MAX,
 928         .nb_min = 256,
 929         .nb_align = 256,
 930         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
 931         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
 932 };
 933
 934 static void
 935 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 936                   struct rte_eth_dev_info *dev_info)
 937 {
 938         struct qede_dev *qdev = eth_dev->data->dev_private;
 939         struct ecore_dev *edev = &qdev->edev;
 940         struct qed_link_output link;
 941         uint32_t speed_cap = 0;
 942
 943         PMD_INIT_FUNC_TRACE(edev);
 944
 945         dev_info->pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
 946         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
 947         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 948         dev_info->rx_desc_lim = qede_rx_desc_lim;
 949         dev_info->tx_desc_lim = qede_tx_desc_lim;
 950
 951         if (IS_PF(edev))
 952                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 953                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
 954         else
 955                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
 956                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
 957         dev_info->max_tx_queues = dev_info->max_rx_queues;
 958
 959         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
 960         dev_info->max_vfs = 0;
 961         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 962         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 963         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 964
 965         dev_info->default_txconf = (struct rte_eth_txconf) {
 966                 .txq_flags = QEDE_TXQ_FLAGS,
 967         };
 968
 969         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
 970                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
 971                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
 972                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
 973                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
 974                                      DEV_RX_OFFLOAD_TCP_LRO);
 975
 976         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 977                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
 978                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
 979                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
 980                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
 981                                      DEV_TX_OFFLOAD_TCP_TSO |
 982                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
 983
 984         memset(&link, 0, sizeof(struct qed_link_output));
 985         qdev->ops->common->get_link(edev, &link);
 986         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
 987                 speed_cap |= ETH_LINK_SPEED_1G;
 988         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
 989                 speed_cap |= ETH_LINK_SPEED_10G;
 990         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
 991                 speed_cap |= ETH_LINK_SPEED_25G;
 992         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
 993                 speed_cap |= ETH_LINK_SPEED_40G;
 994         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
 995                 speed_cap |= ETH_LINK_SPEED_50G;
 996         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
 997                 speed_cap |= ETH_LINK_SPEED_100G;
 998         dev_info->speed_capa = speed_cap;
 999 }
1000
1001 /* return 0 means link status changed, -1 means not changed */
1002 static int
1003 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1004 {
1005         struct qede_dev *qdev = eth_dev->data->dev_private;
1006         struct ecore_dev *edev = &qdev->edev;
1007         uint16_t link_duplex;
1008         struct qed_link_output link;
1009         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1010
1011         memset(&link, 0, sizeof(struct qed_link_output));
1012         qdev->ops->common->get_link(edev, &link);
1013
1014         /* Link Speed */
1015         curr->link_speed = link.speed;
1016
1017         /* Link Mode */
1018         switch (link.duplex) {
1019         case QEDE_DUPLEX_HALF:
1020                 link_duplex = ETH_LINK_HALF_DUPLEX;
1021                 break;
1022         case QEDE_DUPLEX_FULL:
1023                 link_duplex = ETH_LINK_FULL_DUPLEX;
1024                 break;
1025         case QEDE_DUPLEX_UNKNOWN:
1026         default:
1027                 link_duplex = -1;
1028         }
1029         curr->link_duplex = link_duplex;
1030
1031         /* Link Status */
1032         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1033
1034         /* AN */
1035         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1036                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1037
1038         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1039                 curr->link_speed, curr->link_duplex,
1040                 curr->link_autoneg, curr->link_status);
1041
1042         /* return 0 means link status changed, -1 means not changed */
1043         return ((curr->link_status == link.link_up) ? -1 : 0);
1044 }
1045
1046 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1047 {
1048         struct qede_dev *qdev = eth_dev->data->dev_private;
1049         struct ecore_dev *edev = &qdev->edev;
1050
1051         PMD_INIT_FUNC_TRACE(edev);
1052
1053         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1054
1055         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1056                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1057
1058         qed_configure_filter_rx_mode(eth_dev, type);
1059 }
1060
1061 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1062 {
1063         struct qede_dev *qdev = eth_dev->data->dev_private;
1064         struct ecore_dev *edev = &qdev->edev;
1065
1066         PMD_INIT_FUNC_TRACE(edev);
1067
1068         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1069                 qed_configure_filter_rx_mode(eth_dev,
1070                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1071         else
1072                 qed_configure_filter_rx_mode(eth_dev,
1073                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1074 }
1075
1076 static void qede_poll_sp_sb_cb(void *param)
1077 {
1078         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1079         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1080         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1081         int rc;
1082
1083         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1084         qede_interrupt_action(&edev->hwfns[1]);
1085
1086         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1087                                qede_poll_sp_sb_cb,
1088                                (void *)eth_dev);
1089         if (rc != 0) {
1090                 DP_ERR(edev, "Unable to start periodic"
1091                              " timer rc %d\n", rc);
1092                 assert(false && "Unable to start periodic timer");
1093         }
1094 }
1095
1096 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1097 {
1098         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1099         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1100         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1101         int rc;
1102
1103         PMD_INIT_FUNC_TRACE(edev);
1104
1105         qede_fdir_dealloc_resc(eth_dev);
1106
1107         /* dev_stop() shall cleanup fp resources in hw but without releasing
1108          * dma memories and sw structures so that dev_start() can be called
1109          * by the app without reconfiguration. However, in dev_close() we
1110          * can release all the resources and device can be brought up newly
1111          */
1112         if (qdev->state != QEDE_DEV_STOP)
1113                 qede_dev_stop(eth_dev);
1114         else
1115                 DP_INFO(edev, "Device is already stopped\n");
1116
1117         rc = qdev->ops->vport_stop(edev, 0);
1118         if (rc != 0)
1119                 DP_ERR(edev, "Failed to stop VPORT\n");
1120
1121         qede_dealloc_fp_resc(eth_dev);
1122
1123         qdev->ops->common->slowpath_stop(edev);
1124
1125         qdev->ops->common->remove(edev);
1126
1127         rte_intr_disable(&pci_dev->intr_handle);
1128
1129         rte_intr_callback_unregister(&pci_dev->intr_handle,
1130                                      qede_interrupt_handler, (void *)eth_dev);
1131
1132         if (edev->num_hwfns > 1)
1133                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1134
1135         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
1136 }
1137
1138 static void
1139 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1140 {
1141         struct qede_dev *qdev = eth_dev->data->dev_private;
1142         struct ecore_dev *edev = &qdev->edev;
1143         struct ecore_eth_stats stats;
1144         unsigned int i = 0, j = 0, qid;
1145         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1146         struct qede_tx_queue *txq;
1147
1148         qdev->ops->get_vport_stats(edev, &stats);
1149
1150         /* RX Stats */
1151         eth_stats->ipackets = stats.rx_ucast_pkts +
1152             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1153
1154         eth_stats->ibytes = stats.rx_ucast_bytes +
1155             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1156
1157         eth_stats->ierrors = stats.rx_crc_errors +
1158             stats.rx_align_errors +
1159             stats.rx_carrier_errors +
1160             stats.rx_oversize_packets +
1161             stats.rx_jabbers + stats.rx_undersize_packets;
1162
1163         eth_stats->rx_nombuf = stats.no_buff_discards;
1164
1165         eth_stats->imissed = stats.mftag_filter_discards +
1166             stats.mac_filter_discards +
1167             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1168
1169         /* TX stats */
1170         eth_stats->opackets = stats.tx_ucast_pkts +
1171             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1172
1173         eth_stats->obytes = stats.tx_ucast_bytes +
1174             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1175
1176         eth_stats->oerrors = stats.tx_err_drop_pkts;
1177
1178         /* Queue stats */
1179         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1180                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1181         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1182                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1183         if ((rxq_stat_cntrs != QEDE_RSS_COUNT(qdev)) ||
1184             (txq_stat_cntrs != QEDE_TSS_COUNT(qdev)))
1185                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1186                        "Not all the queue stats will be displayed. Set"
1187                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1188                        " appropriately and retry.\n");
1189
1190         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1191                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1192                         eth_stats->q_ipackets[i] =
1193                                 *(uint64_t *)(
1194                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1195                                         offsetof(struct qede_rx_queue,
1196                                         rcv_pkts));
1197                         eth_stats->q_errors[i] =
1198                                 *(uint64_t *)(
1199                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1200                                         offsetof(struct qede_rx_queue,
1201                                         rx_hw_errors)) +
1202                                 *(uint64_t *)(
1203                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1204                                         offsetof(struct qede_rx_queue,
1205                                         rx_alloc_errors));
1206                         i++;
1207                 }
1208                 if (i == rxq_stat_cntrs)
1209                         break;
1210         }
1211
1212         for (qid = 0; qid < QEDE_QUEUE_CNT(qdev); qid++) {
1213                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_TX) {
1214                         txq = qdev->fp_array[(qid)].txqs[0];
1215                         eth_stats->q_opackets[j] =
1216                                 *((uint64_t *)(uintptr_t)
1217                                         (((uint64_t)(uintptr_t)(txq)) +
1218                                          offsetof(struct qede_tx_queue,
1219                                                   xmit_pkts)));
1220                         j++;
1221                 }
1222                 if (j == txq_stat_cntrs)
1223                         break;
1224         }
1225 }
1226
1227 static unsigned
1228 qede_get_xstats_count(struct qede_dev *qdev) {
1229         return RTE_DIM(qede_xstats_strings) +
1230                 (RTE_DIM(qede_rxq_xstats_strings) *
1231                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1232                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1233 }
1234
1235 static int
1236 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
1237                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
1238 {
1239         struct qede_dev *qdev = dev->data->dev_private;
1240         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1241         unsigned int i, qid, stat_idx = 0;
1242         unsigned int rxq_stat_cntrs;
1243
1244         if (xstats_names != NULL) {
1245                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1246                         snprintf(xstats_names[stat_idx].name,
1247                                 sizeof(xstats_names[stat_idx].name),
1248                                 "%s",
1249                                 qede_xstats_strings[i].name);
1250                         stat_idx++;
1251                 }
1252
1253                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1254                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1255                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1256                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1257                                 snprintf(xstats_names[stat_idx].name,
1258                                         sizeof(xstats_names[stat_idx].name),
1259                                         "%.4s%d%s",
1260                                         qede_rxq_xstats_strings[i].name, qid,
1261                                         qede_rxq_xstats_strings[i].name + 4);
1262                                 stat_idx++;
1263                         }
1264                 }
1265         }
1266
1267         return stat_cnt;
1268 }
1269
1270 static int
1271 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1272                 unsigned int n)
1273 {
1274         struct qede_dev *qdev = dev->data->dev_private;
1275         struct ecore_dev *edev = &qdev->edev;
1276         struct ecore_eth_stats stats;
1277         const unsigned int num = qede_get_xstats_count(qdev);
1278         unsigned int i, qid, stat_idx = 0;
1279         unsigned int rxq_stat_cntrs;
1280
1281         if (n < num)
1282                 return num;
1283
1284         qdev->ops->get_vport_stats(edev, &stats);
1285
1286         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1287                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1288                                              qede_xstats_strings[i].offset);
1289                 xstats[stat_idx].id = stat_idx;
1290                 stat_idx++;
1291         }
1292
1293         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1294                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1295         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1296                 if (qdev->fp_array[qid].type & QEDE_FASTPATH_RX) {
1297                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1298                                 xstats[stat_idx].value = *(uint64_t *)(
1299                                         ((char *)(qdev->fp_array[(qid)].rxq)) +
1300                                          qede_rxq_xstats_strings[i].offset);
1301                                 xstats[stat_idx].id = stat_idx;
1302                                 stat_idx++;
1303                         }
1304                 }
1305         }
1306
1307         return stat_idx;
1308 }
1309
1310 static void
1311 qede_reset_xstats(struct rte_eth_dev *dev)
1312 {
1313         struct qede_dev *qdev = dev->data->dev_private;
1314         struct ecore_dev *edev = &qdev->edev;
1315
1316         ecore_reset_vport_stats(edev);
1317 }
1318
1319 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1320 {
1321         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1322         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1323         struct qed_link_params link_params;
1324         int rc;
1325
1326         DP_INFO(edev, "setting link state %d\n", link_up);
1327         memset(&link_params, 0, sizeof(link_params));
1328         link_params.link_up = link_up;
1329         rc = qdev->ops->common->set_link(edev, &link_params);
1330         if (rc != ECORE_SUCCESS)
1331                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1332
1333         return rc;
1334 }
1335
1336 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1337 {
1338         return qede_dev_set_link_state(eth_dev, true);
1339 }
1340
1341 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1342 {
1343         return qede_dev_set_link_state(eth_dev, false);
1344 }
1345
1346 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1347 {
1348         struct qede_dev *qdev = eth_dev->data->dev_private;
1349         struct ecore_dev *edev = &qdev->edev;
1350
1351         ecore_reset_vport_stats(edev);
1352 }
1353
1354 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1355 {
1356         enum qed_filter_rx_mode_type type =
1357             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1358
1359         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1360                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1361
1362         qed_configure_filter_rx_mode(eth_dev, type);
1363 }
1364
1365 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1366 {
1367         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1368                 qed_configure_filter_rx_mode(eth_dev,
1369                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1370         else
1371                 qed_configure_filter_rx_mode(eth_dev,
1372                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1373 }
1374
1375 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1376                               struct rte_eth_fc_conf *fc_conf)
1377 {
1378         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1379         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1380         struct qed_link_output current_link;
1381         struct qed_link_params params;
1382
1383         memset(&current_link, 0, sizeof(current_link));
1384         qdev->ops->common->get_link(edev, &current_link);
1385
1386         memset(&params, 0, sizeof(params));
1387         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1388         if (fc_conf->autoneg) {
1389                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1390                         DP_ERR(edev, "Autoneg not supported\n");
1391                         return -EINVAL;
1392                 }
1393                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1394         }
1395
1396         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1397         if (fc_conf->mode == RTE_FC_FULL)
1398                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1399                                         QED_LINK_PAUSE_RX_ENABLE);
1400         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1401                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1402         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1403                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1404
1405         params.link_up = true;
1406         (void)qdev->ops->common->set_link(edev, &params);
1407
1408         return 0;
1409 }
1410
1411 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1412                               struct rte_eth_fc_conf *fc_conf)
1413 {
1414         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1415         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1416         struct qed_link_output current_link;
1417
1418         memset(&current_link, 0, sizeof(current_link));
1419         qdev->ops->common->get_link(edev, &current_link);
1420
1421         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1422                 fc_conf->autoneg = true;
1423
1424         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1425                                          QED_LINK_PAUSE_TX_ENABLE))
1426                 fc_conf->mode = RTE_FC_FULL;
1427         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1428                 fc_conf->mode = RTE_FC_RX_PAUSE;
1429         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1430                 fc_conf->mode = RTE_FC_TX_PAUSE;
1431         else
1432                 fc_conf->mode = RTE_FC_NONE;
1433
1434         return 0;
1435 }
1436
1437 static const uint32_t *
1438 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1439 {
1440         static const uint32_t ptypes[] = {
1441                 RTE_PTYPE_L3_IPV4,
1442                 RTE_PTYPE_L3_IPV6,
1443                 RTE_PTYPE_UNKNOWN
1444         };
1445
1446         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1447                 return ptypes;
1448
1449         return NULL;
1450 }
1451
1452 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1453 {
1454         *rss_caps = 0;
1455         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1456         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1457         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1458         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1459         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1460         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1461         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1462         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1463 }
1464
1465 static int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1466                                 struct rte_eth_rss_conf *rss_conf)
1467 {
1468         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1469         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1470         struct ecore_sp_vport_update_params vport_update_params;
1471         struct ecore_rss_params rss_params;
1472         struct ecore_hwfn *p_hwfn;
1473         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1474         uint64_t hf = rss_conf->rss_hf;
1475         uint8_t len = rss_conf->rss_key_len;
1476         uint8_t idx;
1477         uint8_t i;
1478         int rc;
1479
1480         memset(&vport_update_params, 0, sizeof(vport_update_params));
1481         memset(&rss_params, 0, sizeof(rss_params));
1482
1483         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1484                 (unsigned long)hf, len, key);
1485
1486         if (hf != 0) {
1487                 /* Enabling RSS */
1488                 DP_INFO(edev, "Enabling rss\n");
1489
1490                 /* RSS caps */
1491                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1492                 rss_params.update_rss_capabilities = 1;
1493
1494                 /* RSS hash key */
1495                 if (key) {
1496                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1497                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1498                                 return -EINVAL;
1499                         }
1500                         DP_INFO(edev, "Applying user supplied hash key\n");
1501                         rss_params.update_rss_key = 1;
1502                         memcpy(&rss_params.rss_key, key, len);
1503                 }
1504                 rss_params.rss_enable = 1;
1505         }
1506
1507         rss_params.update_rss_config = 1;
1508         /* tbl_size has to be set with capabilities */
1509         rss_params.rss_table_size_log = 7;
1510         vport_update_params.vport_id = 0;
1511         /* pass the L2 handles instead of qids */
1512         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1513                 idx = qdev->rss_ind_table[i];
1514                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1515         }
1516         vport_update_params.rss_params = &rss_params;
1517
1518         for_each_hwfn(edev, i) {
1519                 p_hwfn = &edev->hwfns[i];
1520                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1521                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1522                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1523                 if (rc) {
1524                         DP_ERR(edev, "vport-update for RSS failed\n");
1525                         return rc;
1526                 }
1527         }
1528         qdev->rss_enable = rss_params.rss_enable;
1529
1530         /* Update local structure for hash query */
1531         qdev->rss_conf.rss_hf = hf;
1532         qdev->rss_conf.rss_key_len = len;
1533         if (qdev->rss_enable) {
1534                 if  (qdev->rss_conf.rss_key == NULL) {
1535                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1536                         if (qdev->rss_conf.rss_key == NULL) {
1537                                 DP_ERR(edev, "No memory to store RSS key\n");
1538                                 return -ENOMEM;
1539                         }
1540                 }
1541                 if (key && len) {
1542                         DP_INFO(edev, "Storing RSS key\n");
1543                         memcpy(qdev->rss_conf.rss_key, key, len);
1544                 }
1545         } else if (!qdev->rss_enable && len == 0) {
1546                 if (qdev->rss_conf.rss_key) {
1547                         free(qdev->rss_conf.rss_key);
1548                         qdev->rss_conf.rss_key = NULL;
1549                         DP_INFO(edev, "Free RSS key\n");
1550                 }
1551         }
1552
1553         return 0;
1554 }
1555
1556 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1557                            struct rte_eth_rss_conf *rss_conf)
1558 {
1559         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1560
1561         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1562         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1563
1564         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1565                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1566                        rss_conf->rss_key_len);
1567         return 0;
1568 }
1569
1570 static int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1571                                 struct rte_eth_rss_reta_entry64 *reta_conf,
1572                                 uint16_t reta_size)
1573 {
1574         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1575         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1576         struct ecore_sp_vport_update_params vport_update_params;
1577         struct ecore_rss_params params;
1578         struct ecore_hwfn *p_hwfn;
1579         uint16_t i, idx, shift;
1580         uint8_t entry;
1581         int rc;
1582
1583         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1584                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1585                        reta_size);
1586                 return -EINVAL;
1587         }
1588
1589         memset(&vport_update_params, 0, sizeof(vport_update_params));
1590         memset(&params, 0, sizeof(params));
1591
1592         for (i = 0; i < reta_size; i++) {
1593                 idx = i / RTE_RETA_GROUP_SIZE;
1594                 shift = i % RTE_RETA_GROUP_SIZE;
1595                 if (reta_conf[idx].mask & (1ULL << shift)) {
1596                         entry = reta_conf[idx].reta[shift];
1597                         /* Pass rxq handles to ecore */
1598                         params.rss_ind_table[i] =
1599                                         qdev->fp_array[entry].rxq->handle;
1600                         /* Update the local copy for RETA query command */
1601                         qdev->rss_ind_table[i] = entry;
1602                 }
1603         }
1604
1605         /* Fix up RETA for CMT mode device */
1606         if (edev->num_hwfns > 1)
1607                 qdev->rss_enable = qed_update_rss_parm_cmt(edev,
1608                                         params.rss_ind_table[0]);
1609         params.update_rss_ind_table = 1;
1610         params.rss_table_size_log = 7;
1611         params.update_rss_config = 1;
1612         vport_update_params.vport_id = 0;
1613         /* Use the current value of rss_enable */
1614         params.rss_enable = qdev->rss_enable;
1615         vport_update_params.rss_params = &params;
1616
1617         for_each_hwfn(edev, i) {
1618                 p_hwfn = &edev->hwfns[i];
1619                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1620                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1621                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1622                 if (rc) {
1623                         DP_ERR(edev, "vport-update for RSS failed\n");
1624                         return rc;
1625                 }
1626         }
1627
1628         return 0;
1629 }
1630
1631 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1632                                struct rte_eth_rss_reta_entry64 *reta_conf,
1633                                uint16_t reta_size)
1634 {
1635         struct qede_dev *qdev = eth_dev->data->dev_private;
1636         struct ecore_dev *edev = &qdev->edev;
1637         uint16_t i, idx, shift;
1638         uint8_t entry;
1639
1640         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1641                 DP_ERR(edev, "reta_size %d is not supported\n",
1642                        reta_size);
1643                 return -EINVAL;
1644         }
1645
1646         for (i = 0; i < reta_size; i++) {
1647                 idx = i / RTE_RETA_GROUP_SIZE;
1648                 shift = i % RTE_RETA_GROUP_SIZE;
1649                 if (reta_conf[idx].mask & (1ULL << shift)) {
1650                         entry = qdev->rss_ind_table[i];
1651                         reta_conf[idx].reta[shift] = entry;
1652                 }
1653         }
1654
1655         return 0;
1656 }
1657
1658 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1659 {
1660         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1661         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1662         struct rte_eth_dev_info dev_info = {0};
1663         struct qede_fastpath *fp;
1664         uint32_t frame_size;
1665         uint16_t rx_buf_size;
1666         uint16_t bufsz;
1667         int i;
1668
1669         PMD_INIT_FUNC_TRACE(edev);
1670         qede_dev_info_get(dev, &dev_info);
1671         frame_size = mtu + QEDE_ETH_OVERHEAD;
1672         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1673                 DP_ERR(edev, "MTU %u out of range\n", mtu);
1674                 return -EINVAL;
1675         }
1676         if (!dev->data->scattered_rx &&
1677             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
1678                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
1679                         dev->data->min_rx_buf_size);
1680                 return -EINVAL;
1681         }
1682         /* Temporarily replace I/O functions with dummy ones. It cannot
1683          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
1684          */
1685         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
1686         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
1687         qede_dev_stop(dev);
1688         rte_delay_ms(1000);
1689         qdev->mtu = mtu;
1690         /* Fix up RX buf size for all queues of the port */
1691         for_each_queue(i) {
1692                 fp = &qdev->fp_array[i];
1693                 if (fp->type & QEDE_FASTPATH_RX) {
1694                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
1695                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
1696                         if (dev->data->scattered_rx)
1697                                 rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
1698                         else
1699                                 rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
1700                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
1701                         fp->rxq->rx_buf_size = rx_buf_size;
1702                         DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
1703                 }
1704         }
1705         qede_dev_start(dev);
1706         if (frame_size > ETHER_MAX_LEN)
1707                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1708         else
1709                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1710         /* update max frame size */
1711         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1712         /* Reassign back */
1713         dev->rx_pkt_burst = qede_recv_pkts;
1714         dev->tx_pkt_burst = qede_xmit_pkts;
1715
1716         return 0;
1717 }
1718
1719 static int
1720 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
1721                        struct rte_eth_udp_tunnel *tunnel_udp,
1722                        bool add)
1723 {
1724         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1725         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1726         struct ecore_tunnel_info tunn; /* @DPDK */
1727         struct ecore_hwfn *p_hwfn;
1728         int rc, i;
1729
1730         PMD_INIT_FUNC_TRACE(edev);
1731
1732         memset(&tunn, 0, sizeof(tunn));
1733         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
1734                 tunn.vxlan_port.b_update_port = true;
1735                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
1736                                                   QEDE_VXLAN_DEF_PORT;
1737                 for_each_hwfn(edev, i) {
1738                         p_hwfn = &edev->hwfns[i];
1739                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1740                                                 ECORE_SPQ_MODE_CB, NULL);
1741                         if (rc != ECORE_SUCCESS) {
1742                                 DP_ERR(edev, "Unable to config UDP port %u\n",
1743                                        tunn.vxlan_port.port);
1744                                 return rc;
1745                         }
1746                 }
1747         }
1748
1749         return 0;
1750 }
1751
1752 int
1753 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
1754                       struct rte_eth_udp_tunnel *tunnel_udp)
1755 {
1756         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
1757 }
1758
1759 int
1760 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
1761                       struct rte_eth_udp_tunnel *tunnel_udp)
1762 {
1763         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
1764 }
1765
1766 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
1767                                        uint32_t *clss, char *str)
1768 {
1769         uint16_t j;
1770         *clss = MAX_ECORE_TUNN_CLSS;
1771
1772         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
1773                 if (filter == qede_tunn_types[j].rte_filter_type) {
1774                         *type = qede_tunn_types[j].qede_type;
1775                         *clss = qede_tunn_types[j].qede_tunn_clss;
1776                         strcpy(str, qede_tunn_types[j].string);
1777                         return;
1778                 }
1779         }
1780 }
1781
1782 static int
1783 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
1784                               const struct rte_eth_tunnel_filter_conf *conf,
1785                               uint32_t type)
1786 {
1787         /* Init commmon ucast params first */
1788         qede_set_ucast_cmn_params(ucast);
1789
1790         /* Copy out the required fields based on classification type */
1791         ucast->type = type;
1792
1793         switch (type) {
1794         case ECORE_FILTER_VNI:
1795                 ucast->vni = conf->tenant_id;
1796         break;
1797         case ECORE_FILTER_INNER_VLAN:
1798                 ucast->vlan = conf->inner_vlan;
1799         break;
1800         case ECORE_FILTER_MAC:
1801                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1802                        ETHER_ADDR_LEN);
1803         break;
1804         case ECORE_FILTER_INNER_MAC:
1805                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1806                        ETHER_ADDR_LEN);
1807         break;
1808         case ECORE_FILTER_MAC_VNI_PAIR:
1809                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
1810                         ETHER_ADDR_LEN);
1811                 ucast->vni = conf->tenant_id;
1812         break;
1813         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
1814                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1815                         ETHER_ADDR_LEN);
1816                 ucast->vni = conf->tenant_id;
1817         break;
1818         case ECORE_FILTER_INNER_PAIR:
1819                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
1820                         ETHER_ADDR_LEN);
1821                 ucast->vlan = conf->inner_vlan;
1822         break;
1823         default:
1824                 return -EINVAL;
1825         }
1826
1827         return ECORE_SUCCESS;
1828 }
1829
1830 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
1831                                   enum rte_filter_op filter_op,
1832                                   const struct rte_eth_tunnel_filter_conf *conf)
1833 {
1834         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1835         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1836         struct ecore_tunnel_info tunn;
1837         struct ecore_hwfn *p_hwfn;
1838         enum ecore_filter_ucast_type type;
1839         enum ecore_tunn_clss clss;
1840         struct ecore_filter_ucast ucast;
1841         char str[80];
1842         uint16_t filter_type;
1843         int rc, i;
1844
1845         filter_type = conf->filter_type | qdev->vxlan_filter_type;
1846         /* First determine if the given filter classification is supported */
1847         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
1848         if (clss == MAX_ECORE_TUNN_CLSS) {
1849                 DP_ERR(edev, "Wrong filter type\n");
1850                 return -EINVAL;
1851         }
1852         /* Init tunnel ucast params */
1853         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
1854         if (rc != ECORE_SUCCESS) {
1855                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
1856                                 conf->filter_type);
1857                 return rc;
1858         }
1859         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
1860                 str, filter_op, ucast.type);
1861         switch (filter_op) {
1862         case RTE_ETH_FILTER_ADD:
1863                 ucast.opcode = ECORE_FILTER_ADD;
1864
1865                 /* Skip MAC/VLAN if filter is based on VNI */
1866                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1867                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
1868                         if (rc == 0) {
1869                                 /* Enable accept anyvlan */
1870                                 qede_config_accept_any_vlan(qdev, true);
1871                         }
1872                 } else {
1873                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
1874                         if (rc == 0)
1875                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1876                                                     ECORE_SPQ_MODE_CB, NULL);
1877                 }
1878
1879                 if (rc != ECORE_SUCCESS)
1880                         return rc;
1881
1882                 qdev->vxlan_filter_type = filter_type;
1883
1884                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
1885                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
1886                 for_each_hwfn(edev, i) {
1887                         p_hwfn = &edev->hwfns[i];
1888                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
1889                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
1890                         if (rc != ECORE_SUCCESS) {
1891                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
1892                                        tunn.vxlan.tun_cls);
1893                         }
1894                 }
1895                 qdev->num_tunn_filters++; /* Filter added successfully */
1896         break;
1897         case RTE_ETH_FILTER_DELETE:
1898                 ucast.opcode = ECORE_FILTER_REMOVE;
1899
1900                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
1901                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
1902                 } else {
1903                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
1904                         if (rc == 0)
1905                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
1906                                                     ECORE_SPQ_MODE_CB, NULL);
1907                 }
1908                 if (rc != ECORE_SUCCESS)
1909                         return rc;
1910
1911                 qdev->vxlan_filter_type = filter_type;
1912                 qdev->num_tunn_filters--;
1913
1914                 /* Disable VXLAN if VXLAN filters become 0 */
1915                 if (qdev->num_tunn_filters == 0) {
1916                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
1917
1918                         /* Use 0 as tunnel mode */
1919                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
1920                         for_each_hwfn(edev, i) {
1921                                 p_hwfn = &edev->hwfns[i];
1922                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
1923                                         ECORE_SPQ_MODE_CB, NULL);
1924                                 if (rc != ECORE_SUCCESS) {
1925                                         DP_ERR(edev,
1926                                                 "Failed to update tunn_clss %u\n",
1927                                                 tunn.vxlan.tun_cls);
1928                                         break;
1929                                 }
1930                         }
1931                 }
1932         break;
1933         default:
1934                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
1935                 return -EINVAL;
1936         }
1937         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
1938
1939         return 0;
1940 }
1941
1942 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
1943                          enum rte_filter_type filter_type,
1944                          enum rte_filter_op filter_op,
1945                          void *arg)
1946 {
1947         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1948         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1949         struct rte_eth_tunnel_filter_conf *filter_conf =
1950                         (struct rte_eth_tunnel_filter_conf *)arg;
1951
1952         switch (filter_type) {
1953         case RTE_ETH_FILTER_TUNNEL:
1954                 switch (filter_conf->tunnel_type) {
1955                 case RTE_TUNNEL_TYPE_VXLAN:
1956                         DP_INFO(edev,
1957                                 "Packet steering to the specified Rx queue"
1958                                 " is not supported with VXLAN tunneling");
1959                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
1960                                                       filter_conf));
1961                 /* Place holders for future tunneling support */
1962                 case RTE_TUNNEL_TYPE_GENEVE:
1963                 case RTE_TUNNEL_TYPE_TEREDO:
1964                 case RTE_TUNNEL_TYPE_NVGRE:
1965                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
1966                 case RTE_L2_TUNNEL_TYPE_E_TAG:
1967                         DP_ERR(edev, "Unsupported tunnel type %d\n",
1968                                 filter_conf->tunnel_type);
1969                         return -EINVAL;
1970                 case RTE_TUNNEL_TYPE_NONE:
1971                 default:
1972                         return 0;
1973                 }
1974                 break;
1975         case RTE_ETH_FILTER_FDIR:
1976                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
1977         case RTE_ETH_FILTER_NTUPLE:
1978                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
1979         case RTE_ETH_FILTER_MACVLAN:
1980         case RTE_ETH_FILTER_ETHERTYPE:
1981         case RTE_ETH_FILTER_FLEXIBLE:
1982         case RTE_ETH_FILTER_SYN:
1983         case RTE_ETH_FILTER_HASH:
1984         case RTE_ETH_FILTER_L2_TUNNEL:
1985         case RTE_ETH_FILTER_MAX:
1986         default:
1987                 DP_ERR(edev, "Unsupported filter type %d\n",
1988                         filter_type);
1989                 return -EINVAL;
1990         }
1991
1992         return 0;
1993 }
1994
1995 static const struct eth_dev_ops qede_eth_dev_ops = {
1996         .dev_configure = qede_dev_configure,
1997         .dev_infos_get = qede_dev_info_get,
1998         .rx_queue_setup = qede_rx_queue_setup,
1999         .rx_queue_release = qede_rx_queue_release,
2000         .tx_queue_setup = qede_tx_queue_setup,
2001         .tx_queue_release = qede_tx_queue_release,
2002         .dev_start = qede_dev_start,
2003         .dev_set_link_up = qede_dev_set_link_up,
2004         .dev_set_link_down = qede_dev_set_link_down,
2005         .link_update = qede_link_update,
2006         .promiscuous_enable = qede_promiscuous_enable,
2007         .promiscuous_disable = qede_promiscuous_disable,
2008         .allmulticast_enable = qede_allmulticast_enable,
2009         .allmulticast_disable = qede_allmulticast_disable,
2010         .dev_stop = qede_dev_stop,
2011         .dev_close = qede_dev_close,
2012         .stats_get = qede_get_stats,
2013         .stats_reset = qede_reset_stats,
2014         .xstats_get = qede_get_xstats,
2015         .xstats_reset = qede_reset_xstats,
2016         .xstats_get_names = qede_get_xstats_names,
2017         .mac_addr_add = qede_mac_addr_add,
2018         .mac_addr_remove = qede_mac_addr_remove,
2019         .mac_addr_set = qede_mac_addr_set,
2020         .vlan_offload_set = qede_vlan_offload_set,
2021         .vlan_filter_set = qede_vlan_filter_set,
2022         .flow_ctrl_set = qede_flow_ctrl_set,
2023         .flow_ctrl_get = qede_flow_ctrl_get,
2024         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2025         .rss_hash_update = qede_rss_hash_update,
2026         .rss_hash_conf_get = qede_rss_hash_conf_get,
2027         .reta_update  = qede_rss_reta_update,
2028         .reta_query  = qede_rss_reta_query,
2029         .mtu_set = qede_set_mtu,
2030         .filter_ctrl = qede_dev_filter_ctrl,
2031         .udp_tunnel_port_add = qede_udp_dst_port_add,
2032         .udp_tunnel_port_del = qede_udp_dst_port_del,
2033 };
2034
2035 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2036         .dev_configure = qede_dev_configure,
2037         .dev_infos_get = qede_dev_info_get,
2038         .rx_queue_setup = qede_rx_queue_setup,
2039         .rx_queue_release = qede_rx_queue_release,
2040         .tx_queue_setup = qede_tx_queue_setup,
2041         .tx_queue_release = qede_tx_queue_release,
2042         .dev_start = qede_dev_start,
2043         .dev_set_link_up = qede_dev_set_link_up,
2044         .dev_set_link_down = qede_dev_set_link_down,
2045         .link_update = qede_link_update,
2046         .promiscuous_enable = qede_promiscuous_enable,
2047         .promiscuous_disable = qede_promiscuous_disable,
2048         .allmulticast_enable = qede_allmulticast_enable,
2049         .allmulticast_disable = qede_allmulticast_disable,
2050         .dev_stop = qede_dev_stop,
2051         .dev_close = qede_dev_close,
2052         .stats_get = qede_get_stats,
2053         .stats_reset = qede_reset_stats,
2054         .xstats_get = qede_get_xstats,
2055         .xstats_reset = qede_reset_xstats,
2056         .xstats_get_names = qede_get_xstats_names,
2057         .vlan_offload_set = qede_vlan_offload_set,
2058         .vlan_filter_set = qede_vlan_filter_set,
2059         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2060         .rss_hash_update = qede_rss_hash_update,
2061         .rss_hash_conf_get = qede_rss_hash_conf_get,
2062         .reta_update  = qede_rss_reta_update,
2063         .reta_query  = qede_rss_reta_query,
2064         .mtu_set = qede_set_mtu,
2065 };
2066
2067 static void qede_update_pf_params(struct ecore_dev *edev)
2068 {
2069         struct ecore_pf_params pf_params;
2070
2071         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2072         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2073         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2074         qed_ops->common->update_pf_params(edev, &pf_params);
2075 }
2076
2077 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2078 {
2079         struct rte_pci_device *pci_dev;
2080         struct rte_pci_addr pci_addr;
2081         struct qede_dev *adapter;
2082         struct ecore_dev *edev;
2083         struct qed_dev_eth_info dev_info;
2084         struct qed_slowpath_params params;
2085         static bool do_once = true;
2086         uint8_t bulletin_change;
2087         uint8_t vf_mac[ETHER_ADDR_LEN];
2088         uint8_t is_mac_forced;
2089         bool is_mac_exist;
2090         /* Fix up ecore debug level */
2091         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2092         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2093         uint32_t max_mac_addrs;
2094         int rc;
2095
2096         /* Extract key data structures */
2097         adapter = eth_dev->data->dev_private;
2098         edev = &adapter->edev;
2099         pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
2100         pci_addr = pci_dev->addr;
2101
2102         PMD_INIT_FUNC_TRACE(edev);
2103
2104         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2105                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2106                  eth_dev->data->port_id);
2107
2108         eth_dev->rx_pkt_burst = qede_recv_pkts;
2109         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2110         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2111
2112         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2113                 DP_NOTICE(edev, false,
2114                           "Skipping device init from secondary process\n");
2115                 return 0;
2116         }
2117
2118         rte_eth_copy_pci_info(eth_dev, pci_dev);
2119
2120         /* @DPDK */
2121         edev->vendor_id = pci_dev->id.vendor_id;
2122         edev->device_id = pci_dev->id.device_id;
2123
2124         qed_ops = qed_get_eth_ops();
2125         if (!qed_ops) {
2126                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2127                 return -EINVAL;
2128         }
2129
2130         DP_INFO(edev, "Starting qede probe\n");
2131
2132         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
2133                                     dp_module, dp_level, is_vf);
2134
2135         if (rc != 0) {
2136                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2137                 return -ENODEV;
2138         }
2139
2140         qede_update_pf_params(edev);
2141
2142         rte_intr_callback_register(&pci_dev->intr_handle,
2143                                    qede_interrupt_handler, (void *)eth_dev);
2144
2145         if (rte_intr_enable(&pci_dev->intr_handle)) {
2146                 DP_ERR(edev, "rte_intr_enable() failed\n");
2147                 return -ENODEV;
2148         }
2149
2150         /* Start the Slowpath-process */
2151         memset(&params, 0, sizeof(struct qed_slowpath_params));
2152         params.int_mode = ECORE_INT_MODE_MSIX;
2153         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2154         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2155         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2156         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2157         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2158                 QEDE_PMD_DRV_VER_STR_SIZE);
2159
2160         /* For CMT mode device do periodic polling for slowpath events.
2161          * This is required since uio device uses only one MSI-x
2162          * interrupt vector but we need one for each engine.
2163          */
2164         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2165                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2166                                        qede_poll_sp_sb_cb,
2167                                        (void *)eth_dev);
2168                 if (rc != 0) {
2169                         DP_ERR(edev, "Unable to start periodic"
2170                                      " timer rc %d\n", rc);
2171                         return -EINVAL;
2172                 }
2173         }
2174
2175         rc = qed_ops->common->slowpath_start(edev, &params);
2176         if (rc) {
2177                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2178                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2179                                      (void *)eth_dev);
2180                 return -ENODEV;
2181         }
2182
2183         rc = qed_ops->fill_dev_info(edev, &dev_info);
2184         if (rc) {
2185                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2186                 qed_ops->common->slowpath_stop(edev);
2187                 qed_ops->common->remove(edev);
2188                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2189                                      (void *)eth_dev);
2190                 return -ENODEV;
2191         }
2192
2193         qede_alloc_etherdev(adapter, &dev_info);
2194
2195         adapter->ops->common->set_name(edev, edev->name);
2196
2197         if (!is_vf)
2198                 adapter->dev_info.num_mac_filters =
2199                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2200                                             ECORE_MAC);
2201         else
2202                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2203                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2204
2205         /* Allocate memory for storing MAC addr */
2206         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2207                                         (ETHER_ADDR_LEN *
2208                                         adapter->dev_info.num_mac_filters),
2209                                         RTE_CACHE_LINE_SIZE);
2210
2211         if (eth_dev->data->mac_addrs == NULL) {
2212                 DP_ERR(edev, "Failed to allocate MAC address\n");
2213                 qed_ops->common->slowpath_stop(edev);
2214                 qed_ops->common->remove(edev);
2215                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2216                                      (void *)eth_dev);
2217                 return -ENOMEM;
2218         }
2219
2220         if (!is_vf) {
2221                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2222                                 hw_info.hw_mac_addr,
2223                                 &eth_dev->data->mac_addrs[0]);
2224                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2225                                 &adapter->primary_mac);
2226         } else {
2227                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2228                                        &bulletin_change);
2229                 if (bulletin_change) {
2230                         is_mac_exist =
2231                             ecore_vf_bulletin_get_forced_mac(
2232                                                 ECORE_LEADING_HWFN(edev),
2233                                                 vf_mac,
2234                                                 &is_mac_forced);
2235                         if (is_mac_exist && is_mac_forced) {
2236                                 DP_INFO(edev, "VF macaddr received from PF\n");
2237                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2238                                                 &eth_dev->data->mac_addrs[0]);
2239                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2240                                                 &adapter->primary_mac);
2241                         } else {
2242                                 DP_NOTICE(edev, false,
2243                                           "No VF macaddr assigned\n");
2244                         }
2245                 }
2246         }
2247
2248         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2249
2250         if (do_once) {
2251                 qede_print_adapter_info(adapter);
2252                 do_once = false;
2253         }
2254
2255         adapter->state = QEDE_DEV_INIT;
2256
2257         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2258                   adapter->primary_mac.addr_bytes[0],
2259                   adapter->primary_mac.addr_bytes[1],
2260                   adapter->primary_mac.addr_bytes[2],
2261                   adapter->primary_mac.addr_bytes[3],
2262                   adapter->primary_mac.addr_bytes[4],
2263                   adapter->primary_mac.addr_bytes[5]);
2264
2265         return rc;
2266 }
2267
2268 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2269 {
2270         return qede_common_dev_init(eth_dev, 1);
2271 }
2272
2273 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2274 {
2275         return qede_common_dev_init(eth_dev, 0);
2276 }
2277
2278 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2279 {
2280         /* only uninitialize in the primary process */
2281         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2282                 return 0;
2283
2284         /* safe to close dev here */
2285         qede_dev_close(eth_dev);
2286
2287         eth_dev->dev_ops = NULL;
2288         eth_dev->rx_pkt_burst = NULL;
2289         eth_dev->tx_pkt_burst = NULL;
2290
2291         if (eth_dev->data->mac_addrs)
2292                 rte_free(eth_dev->data->mac_addrs);
2293
2294         eth_dev->data->mac_addrs = NULL;
2295
2296         return 0;
2297 }
2298
2299 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2300 {
2301         return qede_dev_common_uninit(eth_dev);
2302 }
2303
2304 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2305 {
2306         return qede_dev_common_uninit(eth_dev);
2307 }
2308
2309 static const struct rte_pci_id pci_id_qedevf_map[] = {
2310 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2311         {
2312                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2313         },
2314         {
2315                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2316         },
2317         {
2318                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2319         },
2320         {.vendor_id = 0,}
2321 };
2322
2323 static const struct rte_pci_id pci_id_qede_map[] = {
2324 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2325         {
2326                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2327         },
2328         {
2329                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2330         },
2331         {
2332                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2333         },
2334         {
2335                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2336         },
2337         {
2338                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2339         },
2340         {
2341                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2342         },
2343         {
2344                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2345         },
2346         {
2347                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2348         },
2349         {
2350                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2351         },
2352         {
2353                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2354         },
2355         {.vendor_id = 0,}
2356 };
2357
2358 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2359         struct rte_pci_device *pci_dev)
2360 {
2361         return rte_eth_dev_pci_generic_probe(pci_dev,
2362                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2363 }
2364
2365 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2366 {
2367         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2368 }
2369
2370 static struct rte_pci_driver rte_qedevf_pmd = {
2371         .id_table = pci_id_qedevf_map,
2372         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2373         .probe = qedevf_eth_dev_pci_probe,
2374         .remove = qedevf_eth_dev_pci_remove,
2375 };
2376
2377 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2378         struct rte_pci_device *pci_dev)
2379 {
2380         return rte_eth_dev_pci_generic_probe(pci_dev,
2381                 sizeof(struct qede_dev), qede_eth_dev_init);
2382 }
2383
2384 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2385 {
2386         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2387 }
2388
2389 static struct rte_pci_driver rte_qede_pmd = {
2390         .id_table = pci_id_qede_map,
2391         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2392         .probe = qede_eth_dev_pci_probe,
2393         .remove = qede_eth_dev_pci_remove,
2394 };
2395
2396 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2397 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2398 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio");
2399 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2400 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2401 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio");