drivers/net/qede/qede_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  */
   6
   7 #include "qede_ethdev.h"
   8 #include <rte_string_fns.h>
   9 #include <rte_alarm.h>
  10 #include <rte_version.h>
  11 #include <rte_kvargs.h>
  12
  13 /* Globals */
  14 int qede_logtype_init;
  15 int qede_logtype_driver;
  16
  17 static const struct qed_eth_ops *qed_ops;
  18 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev);
  19 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev);
  20
  21 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  22
  23 struct rte_qede_xstats_name_off {
  24         char name[RTE_ETH_XSTATS_NAME_SIZE];
  25         uint64_t offset;
  26 };
  27
  28 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  29         {"rx_unicast_bytes",
  30                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
  31         {"rx_multicast_bytes",
  32                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
  33         {"rx_broadcast_bytes",
  34                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
  35         {"rx_unicast_packets",
  36                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
  37         {"rx_multicast_packets",
  38                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
  39         {"rx_broadcast_packets",
  40                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
  41
  42         {"tx_unicast_bytes",
  43                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
  44         {"tx_multicast_bytes",
  45                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
  46         {"tx_broadcast_bytes",
  47                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
  48         {"tx_unicast_packets",
  49                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
  50         {"tx_multicast_packets",
  51                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
  52         {"tx_broadcast_packets",
  53                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
  54
  55         {"rx_64_byte_packets",
  56                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
  57         {"rx_65_to_127_byte_packets",
  58                 offsetof(struct ecore_eth_stats_common,
  59                          rx_65_to_127_byte_packets)},
  60         {"rx_128_to_255_byte_packets",
  61                 offsetof(struct ecore_eth_stats_common,
  62                          rx_128_to_255_byte_packets)},
  63         {"rx_256_to_511_byte_packets",
  64                 offsetof(struct ecore_eth_stats_common,
  65                          rx_256_to_511_byte_packets)},
  66         {"rx_512_to_1023_byte_packets",
  67                 offsetof(struct ecore_eth_stats_common,
  68                          rx_512_to_1023_byte_packets)},
  69         {"rx_1024_to_1518_byte_packets",
  70                 offsetof(struct ecore_eth_stats_common,
  71                          rx_1024_to_1518_byte_packets)},
  72         {"tx_64_byte_packets",
  73                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
  74         {"tx_65_to_127_byte_packets",
  75                 offsetof(struct ecore_eth_stats_common,
  76                          tx_65_to_127_byte_packets)},
  77         {"tx_128_to_255_byte_packets",
  78                 offsetof(struct ecore_eth_stats_common,
  79                          tx_128_to_255_byte_packets)},
  80         {"tx_256_to_511_byte_packets",
  81                 offsetof(struct ecore_eth_stats_common,
  82                          tx_256_to_511_byte_packets)},
  83         {"tx_512_to_1023_byte_packets",
  84                 offsetof(struct ecore_eth_stats_common,
  85                          tx_512_to_1023_byte_packets)},
  86         {"tx_1024_to_1518_byte_packets",
  87                 offsetof(struct ecore_eth_stats_common,
  88                          tx_1024_to_1518_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames",
  95                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
  96         {"tx_pause_frames",
  97                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
  98         {"rx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 100         {"tx_priority_flow_control_frames",
 101                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 102
 103         {"rx_crc_errors",
 104                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 105         {"rx_align_errors",
 106                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 107         {"rx_carrier_errors",
 108                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 109         {"rx_oversize_packet_errors",
 110                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 111         {"rx_jabber_errors",
 112                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 113         {"rx_undersize_packet_errors",
 114                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 115         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 116         {"rx_host_buffer_not_available",
 117                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 118         /* Number of packets discarded because they are bigger than MTU */
 119         {"rx_packet_too_big_discards",
 120                 offsetof(struct ecore_eth_stats_common,
 121                          packet_too_big_discard)},
 122         {"rx_ttl_zero_discards",
 123                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 124         {"rx_multi_function_tag_filter_discards",
 125                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 126         {"rx_mac_filter_discards",
 127                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 128         {"rx_hw_buffer_truncates",
 129                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 130         {"rx_hw_buffer_discards",
 131                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 132         {"tx_error_drop_packets",
 133                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 134
 135         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 136         {"rx_mac_unicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 138         {"rx_mac_multicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 140         {"rx_mac_broadcast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 142         {"rx_mac_frames_ok",
 143                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 144         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 145         {"tx_mac_unicast_packets",
 146                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 147         {"tx_mac_multicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 149         {"tx_mac_broadcast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 151
 152         {"lro_coalesced_packets",
 153                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 154         {"lro_coalesced_events",
 155                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 156         {"lro_aborts_num",
 157                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 158         {"lro_not_coalesced_packets",
 159                 offsetof(struct ecore_eth_stats_common,
 160                          tpa_not_coalesced_pkts)},
 161         {"lro_coalesced_bytes",
 162                 offsetof(struct ecore_eth_stats_common,
 163                          tpa_coalesced_bytes)},
 164 };
 165
 166 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 167         {"rx_1519_to_1522_byte_packets",
 168                 offsetof(struct ecore_eth_stats, bb) +
 169                 offsetof(struct ecore_eth_stats_bb,
 170                          rx_1519_to_1522_byte_packets)},
 171         {"rx_1519_to_2047_byte_packets",
 172                 offsetof(struct ecore_eth_stats, bb) +
 173                 offsetof(struct ecore_eth_stats_bb,
 174                          rx_1519_to_2047_byte_packets)},
 175         {"rx_2048_to_4095_byte_packets",
 176                 offsetof(struct ecore_eth_stats, bb) +
 177                 offsetof(struct ecore_eth_stats_bb,
 178                          rx_2048_to_4095_byte_packets)},
 179         {"rx_4096_to_9216_byte_packets",
 180                 offsetof(struct ecore_eth_stats, bb) +
 181                 offsetof(struct ecore_eth_stats_bb,
 182                          rx_4096_to_9216_byte_packets)},
 183         {"rx_9217_to_16383_byte_packets",
 184                 offsetof(struct ecore_eth_stats, bb) +
 185                 offsetof(struct ecore_eth_stats_bb,
 186                          rx_9217_to_16383_byte_packets)},
 187
 188         {"tx_1519_to_2047_byte_packets",
 189                 offsetof(struct ecore_eth_stats, bb) +
 190                 offsetof(struct ecore_eth_stats_bb,
 191                          tx_1519_to_2047_byte_packets)},
 192         {"tx_2048_to_4095_byte_packets",
 193                 offsetof(struct ecore_eth_stats, bb) +
 194                 offsetof(struct ecore_eth_stats_bb,
 195                          tx_2048_to_4095_byte_packets)},
 196         {"tx_4096_to_9216_byte_packets",
 197                 offsetof(struct ecore_eth_stats, bb) +
 198                 offsetof(struct ecore_eth_stats_bb,
 199                          tx_4096_to_9216_byte_packets)},
 200         {"tx_9217_to_16383_byte_packets",
 201                 offsetof(struct ecore_eth_stats, bb) +
 202                 offsetof(struct ecore_eth_stats_bb,
 203                          tx_9217_to_16383_byte_packets)},
 204
 205         {"tx_lpi_entry_count",
 206                 offsetof(struct ecore_eth_stats, bb) +
 207                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 208         {"tx_total_collisions",
 209                 offsetof(struct ecore_eth_stats, bb) +
 210                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 211 };
 212
 213 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 214         {"rx_1519_to_max_byte_packets",
 215                 offsetof(struct ecore_eth_stats, ah) +
 216                 offsetof(struct ecore_eth_stats_ah,
 217                          rx_1519_to_max_byte_packets)},
 218         {"tx_1519_to_max_byte_packets",
 219                 offsetof(struct ecore_eth_stats, ah) +
 220                 offsetof(struct ecore_eth_stats_ah,
 221                          tx_1519_to_max_byte_packets)},
 222 };
 223
 224 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 225         {"rx_q_segments",
 226                 offsetof(struct qede_rx_queue, rx_segs)},
 227         {"rx_q_hw_errors",
 228                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 229         {"rx_q_allocation_errors",
 230                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 231 };
 232
 233 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 234 {
 235         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 236 }
 237
 238 static void
 239 qede_interrupt_handler_intx(void *param)
 240 {
 241         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 242         struct qede_dev *qdev = eth_dev->data->dev_private;
 243         struct ecore_dev *edev = &qdev->edev;
 244         u64 status;
 245
 246         /* Check if our device actually raised an interrupt */
 247         status = ecore_int_igu_read_sisr_reg(ECORE_LEADING_HWFN(edev));
 248         if (status & 0x1) {
 249                 qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 250
 251                 if (rte_intr_enable(eth_dev->intr_handle))
 252                         DP_ERR(edev, "rte_intr_enable failed\n");
 253         }
 254 }
 255
 256 static void
 257 qede_interrupt_handler(void *param)
 258 {
 259         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 260         struct qede_dev *qdev = eth_dev->data->dev_private;
 261         struct ecore_dev *edev = &qdev->edev;
 262
 263         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 264         if (rte_intr_enable(eth_dev->intr_handle))
 265                 DP_ERR(edev, "rte_intr_enable failed\n");
 266 }
 267
 268 static void
 269 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 270 {
 271         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 272         qdev->ops = qed_ops;
 273 }
 274
 275 static void qede_print_adapter_info(struct qede_dev *qdev)
 276 {
 277         struct ecore_dev *edev = &qdev->edev;
 278         struct qed_dev_info *info = &qdev->dev_info.common;
 279         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 280         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 281
 282         DP_INFO(edev, "*********************************\n");
 283         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 284         DP_INFO(edev, " Chip details : %s %c%d\n",
 285                   ECORE_IS_BB(edev) ? "BB" : "AH",
 286                   'A' + edev->chip_rev,
 287                   (int)edev->chip_metal);
 288         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 289                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 290         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 291                  ver_str, QEDE_PMD_VERSION);
 292         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 293         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 294
 295         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 296                  "%d.%d.%d.%d",
 297                 (info->mfw_rev >> 24) & 0xff,
 298                 (info->mfw_rev >> 16) & 0xff,
 299                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 300         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 301         DP_INFO(edev, " Firmware file : %s\n", qede_fw_file);
 302         DP_INFO(edev, "*********************************\n");
 303 }
 304
 305 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 306 {
 307         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 308         unsigned int i = 0, j = 0, qid;
 309         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 310         struct qede_tx_queue *txq;
 311
 312         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 313
 314         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 315                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 316         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 317                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 318
 319         for_each_rss(qid) {
 320                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 321                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 322                             sizeof(uint64_t));
 323                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 324                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 325                             sizeof(uint64_t));
 326                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 327                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 328                             sizeof(uint64_t));
 329
 330                 if (xstats)
 331                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 332                                 OSAL_MEMSET((((char *)
 333                                               (qdev->fp_array[qid].rxq)) +
 334                                              qede_rxq_xstats_strings[j].offset),
 335                                             0,
 336                                             sizeof(uint64_t));
 337
 338                 i++;
 339                 if (i == rxq_stat_cntrs)
 340                         break;
 341         }
 342
 343         i = 0;
 344
 345         for_each_tss(qid) {
 346                 txq = qdev->fp_array[qid].txq;
 347
 348                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 349                                 (((uint64_t)(uintptr_t)(txq)) +
 350                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 351                             sizeof(uint64_t));
 352
 353                 i++;
 354                 if (i == txq_stat_cntrs)
 355                         break;
 356         }
 357 }
 358
 359 static int
 360 qede_stop_vport(struct ecore_dev *edev)
 361 {
 362         struct ecore_hwfn *p_hwfn;
 363         uint8_t vport_id;
 364         int rc;
 365         int i;
 366
 367         vport_id = 0;
 368         for_each_hwfn(edev, i) {
 369                 p_hwfn = &edev->hwfns[i];
 370                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 371                                          vport_id);
 372                 if (rc != ECORE_SUCCESS) {
 373                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 374                         return rc;
 375                 }
 376         }
 377
 378         DP_INFO(edev, "vport stopped\n");
 379
 380         return 0;
 381 }
 382
 383 static int
 384 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 385 {
 386         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 387         struct ecore_sp_vport_start_params params;
 388         struct ecore_hwfn *p_hwfn;
 389         int rc;
 390         int i;
 391
 392         if (qdev->vport_started)
 393                 qede_stop_vport(edev);
 394
 395         memset(&params, 0, sizeof(params));
 396         params.vport_id = 0;
 397         params.mtu = mtu;
 398         /* @DPDK - Disable FW placement */
 399         params.zero_placement_offset = 1;
 400         for_each_hwfn(edev, i) {
 401                 p_hwfn = &edev->hwfns[i];
 402                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 403                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 404                 rc = ecore_sp_vport_start(p_hwfn, &params);
 405                 if (rc != ECORE_SUCCESS) {
 406                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 407                         return rc;
 408                 }
 409         }
 410         ecore_reset_vport_stats(edev);
 411         qdev->vport_started = true;
 412         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 413
 414         return 0;
 415 }
 416
 417 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 418 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 419
 420 /* Activate or deactivate vport via vport-update */
 421 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 422 {
 423         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 424         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 425         struct ecore_sp_vport_update_params params;
 426         struct ecore_hwfn *p_hwfn;
 427         uint8_t i;
 428         int rc = -1;
 429
 430         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 431         params.vport_id = 0;
 432         params.update_vport_active_rx_flg = 1;
 433         params.update_vport_active_tx_flg = 1;
 434         params.vport_active_rx_flg = flg;
 435         params.vport_active_tx_flg = flg;
 436         if (~qdev->enable_tx_switching & flg) {
 437                 params.update_tx_switching_flg = 1;
 438                 params.tx_switching_flg = !flg;
 439         }
 440         for_each_hwfn(edev, i) {
 441                 p_hwfn = &edev->hwfns[i];
 442                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 443                 rc = ecore_sp_vport_update(p_hwfn, &params,
 444                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 445                 if (rc != ECORE_SUCCESS) {
 446                         DP_ERR(edev, "Failed to update vport\n");
 447                         break;
 448                 }
 449         }
 450         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 451
 452         return rc;
 453 }
 454
 455 static void
 456 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 457                            uint16_t mtu, bool enable)
 458 {
 459         /* Enable LRO in split mode */
 460         sge_tpa_params->tpa_ipv4_en_flg = enable;
 461         sge_tpa_params->tpa_ipv6_en_flg = enable;
 462         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 463         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 464         /* set if tpa enable changes */
 465         sge_tpa_params->update_tpa_en_flg = 1;
 466         /* set if tpa parameters should be handled */
 467         sge_tpa_params->update_tpa_param_flg = enable;
 468
 469         sge_tpa_params->max_buffers_per_cqe = 20;
 470         /* Enable TPA in split mode. In this mode each TPA segment
 471          * starts on the new BD, so there is one BD per segment.
 472          */
 473         sge_tpa_params->tpa_pkt_split_flg = 1;
 474         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 475         sge_tpa_params->tpa_gro_consistent_flg = 0;
 476         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 477         sge_tpa_params->tpa_max_size = 0x7FFF;
 478         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 479         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 480 }
 481
 482 /* Enable/disable LRO via vport-update */
 483 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 484 {
 485         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 486         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 487         struct ecore_sp_vport_update_params params;
 488         struct ecore_sge_tpa_params tpa_params;
 489         struct ecore_hwfn *p_hwfn;
 490         int rc;
 491         int i;
 492
 493         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 494         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 495         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 496         params.vport_id = 0;
 497         params.sge_tpa_params = &tpa_params;
 498         for_each_hwfn(edev, i) {
 499                 p_hwfn = &edev->hwfns[i];
 500                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 501                 rc = ecore_sp_vport_update(p_hwfn, &params,
 502                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 503                 if (rc != ECORE_SUCCESS) {
 504                         DP_ERR(edev, "Failed to update LRO\n");
 505                         return -1;
 506                 }
 507         }
 508         qdev->enable_lro = flg;
 509         eth_dev->data->lro = flg;
 510
 511         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 512
 513         return 0;
 514 }
 515
 516 static int
 517 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 518                              enum qed_filter_rx_mode_type type)
 519 {
 520         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 521         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 522         struct ecore_filter_accept_flags flags;
 523
 524         memset(&flags, 0, sizeof(flags));
 525
 526         flags.update_rx_mode_config = 1;
 527         flags.update_tx_mode_config = 1;
 528         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 529                 ECORE_ACCEPT_MCAST_MATCHED |
 530                 ECORE_ACCEPT_BCAST;
 531
 532         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 533                 ECORE_ACCEPT_MCAST_MATCHED |
 534                 ECORE_ACCEPT_BCAST;
 535
 536         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 537                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 538                 if (IS_VF(edev)) {
 539                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 540                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 541                 }
 542         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 543                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 544         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 545                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 546                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 547                         ECORE_ACCEPT_MCAST_UNMATCHED;
 548         }
 549
 550         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 551                         ECORE_SPQ_MODE_CB, NULL);
 552 }
 553
 554 int
 555 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 556                   bool add)
 557 {
 558         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 559         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 560         struct qede_ucast_entry *tmp = NULL;
 561         struct qede_ucast_entry *u;
 562         struct rte_ether_addr *mac_addr;
 563
 564         mac_addr  = (struct rte_ether_addr *)ucast->mac;
 565         if (add) {
 566                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 567                         if ((memcmp(mac_addr, &tmp->mac,
 568                                     RTE_ETHER_ADDR_LEN) == 0) &&
 569                              ucast->vni == tmp->vni &&
 570                              ucast->vlan == tmp->vlan) {
 571                                 DP_INFO(edev, "Unicast MAC is already added"
 572                                         " with vlan = %u, vni = %u\n",
 573                                         ucast->vlan,  ucast->vni);
 574                                         return 0;
 575                         }
 576                 }
 577                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 578                                RTE_CACHE_LINE_SIZE);
 579                 if (!u) {
 580                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 581                         return -ENOMEM;
 582                 }
 583                 rte_ether_addr_copy(mac_addr, &u->mac);
 584                 u->vlan = ucast->vlan;
 585                 u->vni = ucast->vni;
 586                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 587                 qdev->num_uc_addr++;
 588         } else {
 589                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 590                         if ((memcmp(mac_addr, &tmp->mac,
 591                                     RTE_ETHER_ADDR_LEN) == 0) &&
 592                             ucast->vlan == tmp->vlan      &&
 593                             ucast->vni == tmp->vni)
 594                         break;
 595                 }
 596                 if (tmp == NULL) {
 597                         DP_INFO(edev, "Unicast MAC is not found\n");
 598                         return -EINVAL;
 599                 }
 600                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 601                 qdev->num_uc_addr--;
 602         }
 603
 604         return 0;
 605 }
 606
 607 static int
 608 qede_add_mcast_filters(struct rte_eth_dev *eth_dev,
 609                 struct rte_ether_addr *mc_addrs,
 610                 uint32_t mc_addrs_num)
 611 {
 612         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 613         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 614         struct ecore_filter_mcast mcast;
 615         struct qede_mcast_entry *m = NULL;
 616         uint8_t i;
 617         int rc;
 618
 619         for (i = 0; i < mc_addrs_num; i++) {
 620                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 621                                RTE_CACHE_LINE_SIZE);
 622                 if (!m) {
 623                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 624                         return -ENOMEM;
 625                 }
 626                 rte_ether_addr_copy(&mc_addrs[i], &m->mac);
 627                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 628         }
 629         memset(&mcast, 0, sizeof(mcast));
 630         mcast.num_mc_addrs = mc_addrs_num;
 631         mcast.opcode = ECORE_FILTER_ADD;
 632         for (i = 0; i < mc_addrs_num; i++)
 633                 rte_ether_addr_copy(&mc_addrs[i], (struct rte_ether_addr *)
 634                                                         &mcast.mac[i]);
 635         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 636         if (rc != ECORE_SUCCESS) {
 637                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 638                 return -1;
 639         }
 640
 641         return 0;
 642 }
 643
 644 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 645 {
 646         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 647         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 648         struct qede_mcast_entry *tmp = NULL;
 649         struct ecore_filter_mcast mcast;
 650         int j;
 651         int rc;
 652
 653         memset(&mcast, 0, sizeof(mcast));
 654         mcast.num_mc_addrs = qdev->num_mc_addr;
 655         mcast.opcode = ECORE_FILTER_REMOVE;
 656         j = 0;
 657         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 658                 rte_ether_addr_copy(&tmp->mac,
 659                                 (struct rte_ether_addr *)&mcast.mac[j]);
 660                 j++;
 661         }
 662         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 663         if (rc != ECORE_SUCCESS) {
 664                 DP_ERR(edev, "Failed to delete multicast filter\n");
 665                 return -1;
 666         }
 667         /* Init the list */
 668         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 669                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 670                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 671         }
 672         SLIST_INIT(&qdev->mc_list_head);
 673
 674         return 0;
 675 }
 676
 677 enum _ecore_status_t
 678 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 679                  bool add)
 680 {
 681         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 682         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 683         enum _ecore_status_t rc = ECORE_INVAL;
 684
 685         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 686                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 687                               " Please enable promisc mode\n");
 688                         return ECORE_INVAL;
 689         }
 690
 691         rc = qede_ucast_filter(eth_dev, ucast, add);
 692         if (rc == 0)
 693                 rc = ecore_filter_ucast_cmd(edev, ucast,
 694                                             ECORE_SPQ_MODE_CB, NULL);
 695         /* Indicate error only for add filter operation.
 696          * Delete filter operations are not severe.
 697          */
 698         if ((rc != ECORE_SUCCESS) && add)
 699                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 700                        rc, add);
 701
 702         return rc;
 703 }
 704
 705 static int
 706 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr,
 707                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 708 {
 709         struct ecore_filter_ucast ucast;
 710         int re;
 711
 712         if (!rte_is_valid_assigned_ether_addr(mac_addr))
 713                 return -EINVAL;
 714
 715         qede_set_ucast_cmn_params(&ucast);
 716         ucast.opcode = ECORE_FILTER_ADD;
 717         ucast.type = ECORE_FILTER_MAC;
 718         rte_ether_addr_copy(mac_addr, (struct rte_ether_addr *)&ucast.mac);
 719         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 720         return re;
 721 }
 722
 723 static void
 724 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 725 {
 726         struct qede_dev *qdev = eth_dev->data->dev_private;
 727         struct ecore_dev *edev = &qdev->edev;
 728         struct ecore_filter_ucast ucast;
 729
 730         PMD_INIT_FUNC_TRACE(edev);
 731
 732         if (index >= qdev->dev_info.num_mac_filters) {
 733                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 734                        index, qdev->dev_info.num_mac_filters);
 735                 return;
 736         }
 737
 738         if (!rte_is_valid_assigned_ether_addr(&eth_dev->data->mac_addrs[index]))
 739                 return;
 740
 741         qede_set_ucast_cmn_params(&ucast);
 742         ucast.opcode = ECORE_FILTER_REMOVE;
 743         ucast.type = ECORE_FILTER_MAC;
 744
 745         /* Use the index maintained by rte */
 746         rte_ether_addr_copy(&eth_dev->data->mac_addrs[index],
 747                         (struct rte_ether_addr *)&ucast.mac);
 748
 749         qede_mac_int_ops(eth_dev, &ucast, false);
 750 }
 751
 752 static int
 753 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct rte_ether_addr *mac_addr)
 754 {
 755         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 756         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 757
 758         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 759                                                mac_addr->addr_bytes)) {
 760                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 761                 return -EPERM;
 762         }
 763
 764         qede_mac_addr_remove(eth_dev, 0);
 765
 766         return qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 767 }
 768
 769 void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 770 {
 771         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 772         struct ecore_sp_vport_update_params params;
 773         struct ecore_hwfn *p_hwfn;
 774         uint8_t i;
 775         int rc;
 776
 777         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 778         params.vport_id = 0;
 779         params.update_accept_any_vlan_flg = 1;
 780         params.accept_any_vlan = flg;
 781         for_each_hwfn(edev, i) {
 782                 p_hwfn = &edev->hwfns[i];
 783                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 784                 rc = ecore_sp_vport_update(p_hwfn, &params,
 785                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 786                 if (rc != ECORE_SUCCESS) {
 787                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 788                         return;
 789                 }
 790         }
 791
 792         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 793 }
 794
 795 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 796 {
 797         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 798         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 799         struct ecore_sp_vport_update_params params;
 800         struct ecore_hwfn *p_hwfn;
 801         uint8_t i;
 802         int rc;
 803
 804         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 805         params.vport_id = 0;
 806         params.update_inner_vlan_removal_flg = 1;
 807         params.inner_vlan_removal_flg = flg;
 808         for_each_hwfn(edev, i) {
 809                 p_hwfn = &edev->hwfns[i];
 810                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 811                 rc = ecore_sp_vport_update(p_hwfn, &params,
 812                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 813                 if (rc != ECORE_SUCCESS) {
 814                         DP_ERR(edev, "Failed to update vport\n");
 815                         return -1;
 816                 }
 817         }
 818
 819         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 820         return 0;
 821 }
 822
 823 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 824                                 uint16_t vlan_id, int on)
 825 {
 826         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 827         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 828         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 829         struct qede_vlan_entry *tmp = NULL;
 830         struct qede_vlan_entry *vlan;
 831         struct ecore_filter_ucast ucast;
 832         int rc;
 833
 834         if (on) {
 835                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 836                         DP_ERR(edev, "Reached max VLAN filter limit"
 837                                       " enabling accept_any_vlan\n");
 838                         qede_config_accept_any_vlan(qdev, true);
 839                         return 0;
 840                 }
 841
 842                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 843                         if (tmp->vid == vlan_id) {
 844                                 DP_INFO(edev, "VLAN %u already configured\n",
 845                                         vlan_id);
 846                                 return 0;
 847                         }
 848                 }
 849
 850                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 851                                   RTE_CACHE_LINE_SIZE);
 852
 853                 if (!vlan) {
 854                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 855                         return -ENOMEM;
 856                 }
 857
 858                 qede_set_ucast_cmn_params(&ucast);
 859                 ucast.opcode = ECORE_FILTER_ADD;
 860                 ucast.type = ECORE_FILTER_VLAN;
 861                 ucast.vlan = vlan_id;
 862                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 863                                             NULL);
 864                 if (rc != 0) {
 865                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 866                                rc);
 867                         rte_free(vlan);
 868                 } else {
 869                         vlan->vid = vlan_id;
 870                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 871                         qdev->configured_vlans++;
 872                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 873                                 vlan_id, qdev->configured_vlans);
 874                 }
 875         } else {
 876                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 877                         if (tmp->vid == vlan_id)
 878                                 break;
 879                 }
 880
 881                 if (!tmp) {
 882                         if (qdev->configured_vlans == 0) {
 883                                 DP_INFO(edev,
 884                                         "No VLAN filters configured yet\n");
 885                                 return 0;
 886                         }
 887
 888                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 889                         return -EINVAL;
 890                 }
 891
 892                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 893
 894                 qede_set_ucast_cmn_params(&ucast);
 895                 ucast.opcode = ECORE_FILTER_REMOVE;
 896                 ucast.type = ECORE_FILTER_VLAN;
 897                 ucast.vlan = vlan_id;
 898                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 899                                             NULL);
 900                 if (rc != 0) {
 901                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 902                                vlan_id, rc);
 903                 } else {
 904                         qdev->configured_vlans--;
 905                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 906                                 vlan_id, qdev->configured_vlans);
 907                 }
 908         }
 909
 910         return rc;
 911 }
 912
 913 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 914 {
 915         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 916         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 917         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
 918
 919         if (mask & ETH_VLAN_STRIP_MASK) {
 920                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
 921                         (void)qede_vlan_stripping(eth_dev, 1);
 922                 else
 923                         (void)qede_vlan_stripping(eth_dev, 0);
 924         }
 925
 926         if (mask & ETH_VLAN_FILTER_MASK) {
 927                 /* VLAN filtering kicks in when a VLAN is added */
 928                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
 929                         qede_vlan_filter_set(eth_dev, 0, 1);
 930                 } else {
 931                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 932                                 DP_ERR(edev,
 933                                   " Please remove existing VLAN filters"
 934                                   " before disabling VLAN filtering\n");
 935                                 /* Signal app that VLAN filtering is still
 936                                  * enabled
 937                                  */
 938                                 eth_dev->data->dev_conf.rxmode.offloads |=
 939                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
 940                         } else {
 941                                 qede_vlan_filter_set(eth_dev, 0, 0);
 942                         }
 943                 }
 944         }
 945
 946         if (mask & ETH_VLAN_EXTEND_MASK)
 947                 DP_ERR(edev, "Extend VLAN not supported\n");
 948
 949         qdev->vlan_offload_mask = mask;
 950
 951         DP_INFO(edev, "VLAN offload mask %d\n", mask);
 952
 953         return 0;
 954 }
 955
 956 static void qede_prandom_bytes(uint32_t *buff)
 957 {
 958         uint8_t i;
 959
 960         srand((unsigned int)time(NULL));
 961         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 962                 buff[i] = rand();
 963 }
 964
 965 int qede_config_rss(struct rte_eth_dev *eth_dev)
 966 {
 967         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 968         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 969         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 970         struct rte_eth_rss_reta_entry64 reta_conf[2];
 971         struct rte_eth_rss_conf rss_conf;
 972         uint32_t i, id, pos, q;
 973
 974         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 975         if (!rss_conf.rss_key) {
 976                 DP_INFO(edev, "Applying driver default key\n");
 977                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 978                 qede_prandom_bytes(&def_rss_key[0]);
 979                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 980         }
 981
 982         /* Configure RSS hash */
 983         if (qede_rss_hash_update(eth_dev, &rss_conf))
 984                 return -EINVAL;
 985
 986         /* Configure default RETA */
 987         memset(reta_conf, 0, sizeof(reta_conf));
 988         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 989                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 990
 991         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 992                 id = i / RTE_RETA_GROUP_SIZE;
 993                 pos = i % RTE_RETA_GROUP_SIZE;
 994                 q = i % QEDE_RSS_COUNT(qdev);
 995                 reta_conf[id].reta[pos] = q;
 996         }
 997         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
 998                                  ECORE_RSS_IND_TABLE_SIZE))
 999                 return -EINVAL;
1000
1001         return 0;
1002 }
1003
1004 static void qede_fastpath_start(struct ecore_dev *edev)
1005 {
1006         struct ecore_hwfn *p_hwfn;
1007         int i;
1008
1009         for_each_hwfn(edev, i) {
1010                 p_hwfn = &edev->hwfns[i];
1011                 ecore_hw_start_fastpath(p_hwfn);
1012         }
1013 }
1014
1015 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1016 {
1017         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1018         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1019         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1020
1021         PMD_INIT_FUNC_TRACE(edev);
1022
1023         /* Update MTU only if it has changed */
1024         if (eth_dev->data->mtu != qdev->mtu) {
1025                 if (qede_update_mtu(eth_dev, qdev->mtu))
1026                         goto err;
1027         }
1028
1029         /* Configure TPA parameters */
1030         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1031                 if (qede_enable_tpa(eth_dev, true))
1032                         return -EINVAL;
1033                 /* Enable scatter mode for LRO */
1034                 if (!eth_dev->data->scattered_rx)
1035                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1036         }
1037
1038         /* Start queues */
1039         if (qede_start_queues(eth_dev))
1040                 goto err;
1041
1042         if (IS_PF(edev))
1043                 qede_reset_queue_stats(qdev, true);
1044
1045         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1046          * enabling RSS. Hence RSS configuration is deferred upto this point.
1047          * Also, we would like to retain similar behavior in PF case, so we
1048          * don't do PF/VF specific check here.
1049          */
1050         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1051                 if (qede_config_rss(eth_dev))
1052                         goto err;
1053
1054         /* Enable vport*/
1055         if (qede_activate_vport(eth_dev, true))
1056                 goto err;
1057
1058         /* Update link status */
1059         qede_link_update(eth_dev, 0);
1060
1061         /* Start/resume traffic */
1062         qede_fastpath_start(edev);
1063
1064         DP_INFO(edev, "Device started\n");
1065
1066         return 0;
1067 err:
1068         DP_ERR(edev, "Device start fails\n");
1069         return -1; /* common error code is < 0 */
1070 }
1071
1072 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1073 {
1074         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1075         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1076
1077         PMD_INIT_FUNC_TRACE(edev);
1078
1079         /* Disable vport */
1080         if (qede_activate_vport(eth_dev, false))
1081                 return;
1082
1083         if (qdev->enable_lro)
1084                 qede_enable_tpa(eth_dev, false);
1085
1086         /* Stop queues */
1087         qede_stop_queues(eth_dev);
1088
1089         /* Disable traffic */
1090         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1091
1092         DP_INFO(edev, "Device is stopped\n");
1093 }
1094
1095 static const char * const valid_args[] = {
1096         QEDE_NPAR_TX_SWITCHING,
1097         QEDE_VF_TX_SWITCHING,
1098         NULL,
1099 };
1100
1101 static int qede_args_check(const char *key, const char *val, void *opaque)
1102 {
1103         unsigned long tmp;
1104         int ret = 0;
1105         struct rte_eth_dev *eth_dev = opaque;
1106         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1107         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1108
1109         errno = 0;
1110         tmp = strtoul(val, NULL, 0);
1111         if (errno) {
1112                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1113                 return errno;
1114         }
1115
1116         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1117             ((strcmp(QEDE_VF_TX_SWITCHING, key) == 0) && IS_VF(edev))) {
1118                 qdev->enable_tx_switching = !!tmp;
1119                 DP_INFO(edev, "Disabling %s tx-switching\n",
1120                         strcmp(QEDE_NPAR_TX_SWITCHING, key) ?
1121                         "VF" : "NPAR");
1122         }
1123
1124         return ret;
1125 }
1126
1127 static int qede_args(struct rte_eth_dev *eth_dev)
1128 {
1129         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1130         struct rte_kvargs *kvlist;
1131         struct rte_devargs *devargs;
1132         int ret;
1133         int i;
1134
1135         devargs = pci_dev->device.devargs;
1136         if (!devargs)
1137                 return 0; /* return success */
1138
1139         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1140         if (kvlist == NULL)
1141                 return -EINVAL;
1142
1143          /* Process parameters. */
1144         for (i = 0; (valid_args[i] != NULL); ++i) {
1145                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1146                         ret = rte_kvargs_process(kvlist, valid_args[i],
1147                                                  qede_args_check, eth_dev);
1148                         if (ret != ECORE_SUCCESS) {
1149                                 rte_kvargs_free(kvlist);
1150                                 return ret;
1151                         }
1152                 }
1153         }
1154         rte_kvargs_free(kvlist);
1155
1156         return 0;
1157 }
1158
1159 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1160 {
1161         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1162         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1163         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1164         int ret;
1165
1166         PMD_INIT_FUNC_TRACE(edev);
1167
1168         /* Check requirements for 100G mode */
1169         if (ECORE_IS_CMT(edev)) {
1170                 if (eth_dev->data->nb_rx_queues < 2 ||
1171                     eth_dev->data->nb_tx_queues < 2) {
1172                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1173                         return -EINVAL;
1174                 }
1175
1176                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1177                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1178                         DP_ERR(edev,
1179                                "100G mode needs even no. of RX/TX queues\n");
1180                         return -EINVAL;
1181                 }
1182         }
1183
1184         /* We need to have min 1 RX queue.There is no min check in
1185          * rte_eth_dev_configure(), so we are checking it here.
1186          */
1187         if (eth_dev->data->nb_rx_queues == 0) {
1188                 DP_ERR(edev, "Minimum one RX queue is required\n");
1189                 return -EINVAL;
1190         }
1191
1192         /* Enable Tx switching by default */
1193         qdev->enable_tx_switching = 1;
1194
1195         /* Parse devargs and fix up rxmode */
1196         if (qede_args(eth_dev))
1197                 DP_NOTICE(edev, false,
1198                           "Invalid devargs supplied, requested change will not take effect\n");
1199
1200         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1201               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1202                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1203                 return -ENOTSUP;
1204         }
1205         /* Flow director mode check */
1206         if (qede_check_fdir_support(eth_dev))
1207                 return -ENOTSUP;
1208
1209         qede_dealloc_fp_resc(eth_dev);
1210         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1211         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1212         if (qede_alloc_fp_resc(qdev))
1213                 return -ENOMEM;
1214
1215         /* If jumbo enabled adjust MTU */
1216         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1217                 eth_dev->data->mtu =
1218                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1219                         RTE_ETHER_HDR_LEN - QEDE_ETH_OVERHEAD;
1220
1221         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1222                 eth_dev->data->scattered_rx = 1;
1223
1224         if (qede_start_vport(qdev, eth_dev->data->mtu))
1225                 return -1;
1226
1227         qdev->mtu = eth_dev->data->mtu;
1228
1229         /* Enable VLAN offloads by default */
1230         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1231                                              ETH_VLAN_FILTER_MASK);
1232         if (ret)
1233                 return ret;
1234
1235         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1236                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1237
1238         return 0;
1239 }
1240
1241 /* Info about HW descriptor ring limitations */
1242 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1243         .nb_max = 0x8000, /* 32K */
1244         .nb_min = 128,
1245         .nb_align = 128 /* lowest common multiple */
1246 };
1247
1248 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1249         .nb_max = 0x8000, /* 32K */
1250         .nb_min = 256,
1251         .nb_align = 256,
1252         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1253         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1254 };
1255
1256 static void
1257 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1258                   struct rte_eth_dev_info *dev_info)
1259 {
1260         struct qede_dev *qdev = eth_dev->data->dev_private;
1261         struct ecore_dev *edev = &qdev->edev;
1262         struct qed_link_output link;
1263         uint32_t speed_cap = 0;
1264
1265         PMD_INIT_FUNC_TRACE(edev);
1266
1267         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1268         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1269         dev_info->rx_desc_lim = qede_rx_desc_lim;
1270         dev_info->tx_desc_lim = qede_tx_desc_lim;
1271
1272         if (IS_PF(edev))
1273                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1274                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1275         else
1276                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1277                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1278         dev_info->max_tx_queues = dev_info->max_rx_queues;
1279
1280         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1281         dev_info->max_vfs = 0;
1282         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1283         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1284         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1285         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1286                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1287                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1288                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1289                                      DEV_RX_OFFLOAD_TCP_LRO     |
1290                                      DEV_RX_OFFLOAD_KEEP_CRC    |
1291                                      DEV_RX_OFFLOAD_SCATTER     |
1292                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1293                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1294                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1295         dev_info->rx_queue_offload_capa = 0;
1296
1297         /* TX offloads are on a per-packet basis, so it is applicable
1298          * to both at port and queue levels.
1299          */
1300         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1301                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1302                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1303                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1304                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1305                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1306                                      DEV_TX_OFFLOAD_TCP_TSO     |
1307                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1308                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1309         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1310
1311         dev_info->default_txconf = (struct rte_eth_txconf) {
1312                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1313         };
1314
1315         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1316                 /* Packets are always dropped if no descriptors are available */
1317                 .rx_drop_en = 1,
1318                 .offloads = 0,
1319         };
1320
1321         memset(&link, 0, sizeof(struct qed_link_output));
1322         qdev->ops->common->get_link(edev, &link);
1323         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1324                 speed_cap |= ETH_LINK_SPEED_1G;
1325         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1326                 speed_cap |= ETH_LINK_SPEED_10G;
1327         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1328                 speed_cap |= ETH_LINK_SPEED_25G;
1329         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1330                 speed_cap |= ETH_LINK_SPEED_40G;
1331         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1332                 speed_cap |= ETH_LINK_SPEED_50G;
1333         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1334                 speed_cap |= ETH_LINK_SPEED_100G;
1335         dev_info->speed_capa = speed_cap;
1336 }
1337
1338 /* return 0 means link status changed, -1 means not changed */
1339 int
1340 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1341 {
1342         struct qede_dev *qdev = eth_dev->data->dev_private;
1343         struct ecore_dev *edev = &qdev->edev;
1344         struct qed_link_output q_link;
1345         struct rte_eth_link link;
1346         uint16_t link_duplex;
1347
1348         memset(&q_link, 0, sizeof(q_link));
1349         memset(&link, 0, sizeof(link));
1350
1351         qdev->ops->common->get_link(edev, &q_link);
1352
1353         /* Link Speed */
1354         link.link_speed = q_link.speed;
1355
1356         /* Link Mode */
1357         switch (q_link.duplex) {
1358         case QEDE_DUPLEX_HALF:
1359                 link_duplex = ETH_LINK_HALF_DUPLEX;
1360                 break;
1361         case QEDE_DUPLEX_FULL:
1362                 link_duplex = ETH_LINK_FULL_DUPLEX;
1363                 break;
1364         case QEDE_DUPLEX_UNKNOWN:
1365         default:
1366                 link_duplex = -1;
1367         }
1368         link.link_duplex = link_duplex;
1369
1370         /* Link Status */
1371         link.link_status = q_link.link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
1372
1373         /* AN */
1374         link.link_autoneg = (q_link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1375                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1376
1377         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1378                 link.link_speed, link.link_duplex,
1379                 link.link_autoneg, link.link_status);
1380
1381         return rte_eth_linkstatus_set(eth_dev, &link);
1382 }
1383
1384 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1385 {
1386         struct qede_dev *qdev = eth_dev->data->dev_private;
1387         struct ecore_dev *edev = &qdev->edev;
1388         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1389
1390         PMD_INIT_FUNC_TRACE(edev);
1391
1392         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1393                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1394
1395         qed_configure_filter_rx_mode(eth_dev, type);
1396 }
1397
1398 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1399 {
1400         struct qede_dev *qdev = eth_dev->data->dev_private;
1401         struct ecore_dev *edev = &qdev->edev;
1402
1403         PMD_INIT_FUNC_TRACE(edev);
1404
1405         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1406                 qed_configure_filter_rx_mode(eth_dev,
1407                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1408         else
1409                 qed_configure_filter_rx_mode(eth_dev,
1410                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1411 }
1412
1413 static void qede_poll_sp_sb_cb(void *param)
1414 {
1415         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1416         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1417         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1418         int rc;
1419
1420         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1421         qede_interrupt_action(&edev->hwfns[1]);
1422
1423         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1424                                qede_poll_sp_sb_cb,
1425                                (void *)eth_dev);
1426         if (rc != 0) {
1427                 DP_ERR(edev, "Unable to start periodic"
1428                              " timer rc %d\n", rc);
1429         }
1430 }
1431
1432 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1433 {
1434         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1435         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1436         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1437
1438         PMD_INIT_FUNC_TRACE(edev);
1439
1440         /* dev_stop() shall cleanup fp resources in hw but without releasing
1441          * dma memories and sw structures so that dev_start() can be called
1442          * by the app without reconfiguration. However, in dev_close() we
1443          * can release all the resources and device can be brought up newly
1444          */
1445         if (eth_dev->data->dev_started)
1446                 qede_dev_stop(eth_dev);
1447
1448         qede_stop_vport(edev);
1449         qdev->vport_started = false;
1450         qede_fdir_dealloc_resc(eth_dev);
1451         qede_dealloc_fp_resc(eth_dev);
1452
1453         eth_dev->data->nb_rx_queues = 0;
1454         eth_dev->data->nb_tx_queues = 0;
1455
1456         /* Bring the link down */
1457         qede_dev_set_link_state(eth_dev, false);
1458         qdev->ops->common->slowpath_stop(edev);
1459         qdev->ops->common->remove(edev);
1460         rte_intr_disable(&pci_dev->intr_handle);
1461
1462         switch (pci_dev->intr_handle.type) {
1463         case RTE_INTR_HANDLE_UIO_INTX:
1464         case RTE_INTR_HANDLE_VFIO_LEGACY:
1465                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1466                                              qede_interrupt_handler_intx,
1467                                              (void *)eth_dev);
1468                 break;
1469         default:
1470                 rte_intr_callback_unregister(&pci_dev->intr_handle,
1471                                            qede_interrupt_handler,
1472                                            (void *)eth_dev);
1473         }
1474
1475         if (ECORE_IS_CMT(edev))
1476                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1477 }
1478
1479 static int
1480 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1481 {
1482         struct qede_dev *qdev = eth_dev->data->dev_private;
1483         struct ecore_dev *edev = &qdev->edev;
1484         struct ecore_eth_stats stats;
1485         unsigned int i = 0, j = 0, qid;
1486         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1487         struct qede_tx_queue *txq;
1488
1489         ecore_get_vport_stats(edev, &stats);
1490
1491         /* RX Stats */
1492         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1493             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1494
1495         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1496             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1497
1498         eth_stats->ierrors = stats.common.rx_crc_errors +
1499             stats.common.rx_align_errors +
1500             stats.common.rx_carrier_errors +
1501             stats.common.rx_oversize_packets +
1502             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1503
1504         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1505
1506         eth_stats->imissed = stats.common.mftag_filter_discards +
1507             stats.common.mac_filter_discards +
1508             stats.common.no_buff_discards +
1509             stats.common.brb_truncates + stats.common.brb_discards;
1510
1511         /* TX stats */
1512         eth_stats->opackets = stats.common.tx_ucast_pkts +
1513             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1514
1515         eth_stats->obytes = stats.common.tx_ucast_bytes +
1516             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1517
1518         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1519
1520         /* Queue stats */
1521         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1522                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1523         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1524                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1525         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1526             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1527                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1528                        "Not all the queue stats will be displayed. Set"
1529                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1530                        " appropriately and retry.\n");
1531
1532         for_each_rss(qid) {
1533                 eth_stats->q_ipackets[i] =
1534                         *(uint64_t *)(
1535                                 ((char *)(qdev->fp_array[qid].rxq)) +
1536                                 offsetof(struct qede_rx_queue,
1537                                 rcv_pkts));
1538                 eth_stats->q_errors[i] =
1539                         *(uint64_t *)(
1540                                 ((char *)(qdev->fp_array[qid].rxq)) +
1541                                 offsetof(struct qede_rx_queue,
1542                                 rx_hw_errors)) +
1543                         *(uint64_t *)(
1544                                 ((char *)(qdev->fp_array[qid].rxq)) +
1545                                 offsetof(struct qede_rx_queue,
1546                                 rx_alloc_errors));
1547                 i++;
1548                 if (i == rxq_stat_cntrs)
1549                         break;
1550         }
1551
1552         for_each_tss(qid) {
1553                 txq = qdev->fp_array[qid].txq;
1554                 eth_stats->q_opackets[j] =
1555                         *((uint64_t *)(uintptr_t)
1556                                 (((uint64_t)(uintptr_t)(txq)) +
1557                                  offsetof(struct qede_tx_queue,
1558                                           xmit_pkts)));
1559                 j++;
1560                 if (j == txq_stat_cntrs)
1561                         break;
1562         }
1563
1564         return 0;
1565 }
1566
1567 static unsigned
1568 qede_get_xstats_count(struct qede_dev *qdev) {
1569         if (ECORE_IS_BB(&qdev->edev))
1570                 return RTE_DIM(qede_xstats_strings) +
1571                        RTE_DIM(qede_bb_xstats_strings) +
1572                        (RTE_DIM(qede_rxq_xstats_strings) *
1573                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1574                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1575         else
1576                 return RTE_DIM(qede_xstats_strings) +
1577                        RTE_DIM(qede_ah_xstats_strings) +
1578                        (RTE_DIM(qede_rxq_xstats_strings) *
1579                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1580                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1581 }
1582
1583 static int
1584 qede_get_xstats_names(struct rte_eth_dev *dev,
1585                       struct rte_eth_xstat_name *xstats_names,
1586                       __rte_unused unsigned int limit)
1587 {
1588         struct qede_dev *qdev = dev->data->dev_private;
1589         struct ecore_dev *edev = &qdev->edev;
1590         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1591         unsigned int i, qid, stat_idx = 0;
1592         unsigned int rxq_stat_cntrs;
1593
1594         if (xstats_names != NULL) {
1595                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1596                         strlcpy(xstats_names[stat_idx].name,
1597                                 qede_xstats_strings[i].name,
1598                                 sizeof(xstats_names[stat_idx].name));
1599                         stat_idx++;
1600                 }
1601
1602                 if (ECORE_IS_BB(edev)) {
1603                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1604                                 strlcpy(xstats_names[stat_idx].name,
1605                                         qede_bb_xstats_strings[i].name,
1606                                         sizeof(xstats_names[stat_idx].name));
1607                                 stat_idx++;
1608                         }
1609                 } else {
1610                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1611                                 strlcpy(xstats_names[stat_idx].name,
1612                                         qede_ah_xstats_strings[i].name,
1613                                         sizeof(xstats_names[stat_idx].name));
1614                                 stat_idx++;
1615                         }
1616                 }
1617
1618                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1619                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1620                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1621                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1622                                 snprintf(xstats_names[stat_idx].name,
1623                                         sizeof(xstats_names[stat_idx].name),
1624                                         "%.4s%d%s",
1625                                         qede_rxq_xstats_strings[i].name, qid,
1626                                         qede_rxq_xstats_strings[i].name + 4);
1627                                 stat_idx++;
1628                         }
1629                 }
1630         }
1631
1632         return stat_cnt;
1633 }
1634
1635 static int
1636 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1637                 unsigned int n)
1638 {
1639         struct qede_dev *qdev = dev->data->dev_private;
1640         struct ecore_dev *edev = &qdev->edev;
1641         struct ecore_eth_stats stats;
1642         const unsigned int num = qede_get_xstats_count(qdev);
1643         unsigned int i, qid, stat_idx = 0;
1644         unsigned int rxq_stat_cntrs;
1645
1646         if (n < num)
1647                 return num;
1648
1649         ecore_get_vport_stats(edev, &stats);
1650
1651         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1652                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1653                                              qede_xstats_strings[i].offset);
1654                 xstats[stat_idx].id = stat_idx;
1655                 stat_idx++;
1656         }
1657
1658         if (ECORE_IS_BB(edev)) {
1659                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1660                         xstats[stat_idx].value =
1661                                         *(uint64_t *)(((char *)&stats) +
1662                                         qede_bb_xstats_strings[i].offset);
1663                         xstats[stat_idx].id = stat_idx;
1664                         stat_idx++;
1665                 }
1666         } else {
1667                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1668                         xstats[stat_idx].value =
1669                                         *(uint64_t *)(((char *)&stats) +
1670                                         qede_ah_xstats_strings[i].offset);
1671                         xstats[stat_idx].id = stat_idx;
1672                         stat_idx++;
1673                 }
1674         }
1675
1676         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1677                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1678         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1679                 for_each_rss(qid) {
1680                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1681                                 xstats[stat_idx].value = *(uint64_t *)(
1682                                         ((char *)(qdev->fp_array[qid].rxq)) +
1683                                          qede_rxq_xstats_strings[i].offset);
1684                                 xstats[stat_idx].id = stat_idx;
1685                                 stat_idx++;
1686                         }
1687                 }
1688         }
1689
1690         return stat_idx;
1691 }
1692
1693 static void
1694 qede_reset_xstats(struct rte_eth_dev *dev)
1695 {
1696         struct qede_dev *qdev = dev->data->dev_private;
1697         struct ecore_dev *edev = &qdev->edev;
1698
1699         ecore_reset_vport_stats(edev);
1700         qede_reset_queue_stats(qdev, true);
1701 }
1702
1703 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1704 {
1705         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1706         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1707         struct qed_link_params link_params;
1708         int rc;
1709
1710         DP_INFO(edev, "setting link state %d\n", link_up);
1711         memset(&link_params, 0, sizeof(link_params));
1712         link_params.link_up = link_up;
1713         rc = qdev->ops->common->set_link(edev, &link_params);
1714         if (rc != ECORE_SUCCESS)
1715                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1716
1717         return rc;
1718 }
1719
1720 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1721 {
1722         return qede_dev_set_link_state(eth_dev, true);
1723 }
1724
1725 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1726 {
1727         return qede_dev_set_link_state(eth_dev, false);
1728 }
1729
1730 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1731 {
1732         struct qede_dev *qdev = eth_dev->data->dev_private;
1733         struct ecore_dev *edev = &qdev->edev;
1734
1735         ecore_reset_vport_stats(edev);
1736         qede_reset_queue_stats(qdev, false);
1737 }
1738
1739 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1740 {
1741         enum qed_filter_rx_mode_type type =
1742             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1743
1744         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1745                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1746
1747         qed_configure_filter_rx_mode(eth_dev, type);
1748 }
1749
1750 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1751 {
1752         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1753                 qed_configure_filter_rx_mode(eth_dev,
1754                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1755         else
1756                 qed_configure_filter_rx_mode(eth_dev,
1757                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1758 }
1759
1760 static int
1761 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev,
1762                 struct rte_ether_addr *mc_addrs,
1763                 uint32_t mc_addrs_num)
1764 {
1765         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1766         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1767         uint8_t i;
1768
1769         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
1770                 DP_ERR(edev, "Reached max multicast filters limit,"
1771                              "Please enable multicast promisc mode\n");
1772                 return -ENOSPC;
1773         }
1774
1775         for (i = 0; i < mc_addrs_num; i++) {
1776                 if (!rte_is_multicast_ether_addr(&mc_addrs[i])) {
1777                         DP_ERR(edev, "Not a valid multicast MAC\n");
1778                         return -EINVAL;
1779                 }
1780         }
1781
1782         /* Flush all existing entries */
1783         if (qede_del_mcast_filters(eth_dev))
1784                 return -1;
1785
1786         /* Set new mcast list */
1787         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
1788 }
1789
1790 /* Update MTU via vport-update without doing port restart.
1791  * The vport must be deactivated before calling this API.
1792  */
1793 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
1794 {
1795         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1796         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1797         struct ecore_hwfn *p_hwfn;
1798         int rc;
1799         int i;
1800
1801         if (IS_PF(edev)) {
1802                 struct ecore_sp_vport_update_params params;
1803
1804                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1805                 params.vport_id = 0;
1806                 params.mtu = mtu;
1807                 params.vport_id = 0;
1808                 for_each_hwfn(edev, i) {
1809                         p_hwfn = &edev->hwfns[i];
1810                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1811                         rc = ecore_sp_vport_update(p_hwfn, &params,
1812                                         ECORE_SPQ_MODE_EBLOCK, NULL);
1813                         if (rc != ECORE_SUCCESS)
1814                                 goto err;
1815                 }
1816         } else {
1817                 for_each_hwfn(edev, i) {
1818                         p_hwfn = &edev->hwfns[i];
1819                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
1820                         if (rc == ECORE_INVAL) {
1821                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
1822                                 /* Recreate vport */
1823                                 rc = qede_start_vport(qdev, mtu);
1824                                 if (rc != ECORE_SUCCESS)
1825                                         goto err;
1826
1827                                 /* Restore config lost due to vport stop */
1828                                 if (eth_dev->data->promiscuous)
1829                                         qede_promiscuous_enable(eth_dev);
1830                                 else
1831                                         qede_promiscuous_disable(eth_dev);
1832
1833                                 if (eth_dev->data->all_multicast)
1834                                         qede_allmulticast_enable(eth_dev);
1835                                 else
1836                                         qede_allmulticast_disable(eth_dev);
1837
1838                                 qede_vlan_offload_set(eth_dev,
1839                                                       qdev->vlan_offload_mask);
1840                         } else if (rc != ECORE_SUCCESS) {
1841                                 goto err;
1842                         }
1843                 }
1844         }
1845         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
1846
1847         return 0;
1848
1849 err:
1850         DP_ERR(edev, "Failed to update MTU\n");
1851         return -1;
1852 }
1853
1854 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1855                               struct rte_eth_fc_conf *fc_conf)
1856 {
1857         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1858         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1859         struct qed_link_output current_link;
1860         struct qed_link_params params;
1861
1862         memset(&current_link, 0, sizeof(current_link));
1863         qdev->ops->common->get_link(edev, &current_link);
1864
1865         memset(&params, 0, sizeof(params));
1866         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1867         if (fc_conf->autoneg) {
1868                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1869                         DP_ERR(edev, "Autoneg not supported\n");
1870                         return -EINVAL;
1871                 }
1872                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1873         }
1874
1875         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1876         if (fc_conf->mode == RTE_FC_FULL)
1877                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1878                                         QED_LINK_PAUSE_RX_ENABLE);
1879         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1880                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1881         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1882                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1883
1884         params.link_up = true;
1885         (void)qdev->ops->common->set_link(edev, &params);
1886
1887         return 0;
1888 }
1889
1890 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1891                               struct rte_eth_fc_conf *fc_conf)
1892 {
1893         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1894         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1895         struct qed_link_output current_link;
1896
1897         memset(&current_link, 0, sizeof(current_link));
1898         qdev->ops->common->get_link(edev, &current_link);
1899
1900         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1901                 fc_conf->autoneg = true;
1902
1903         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1904                                          QED_LINK_PAUSE_TX_ENABLE))
1905                 fc_conf->mode = RTE_FC_FULL;
1906         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1907                 fc_conf->mode = RTE_FC_RX_PAUSE;
1908         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1909                 fc_conf->mode = RTE_FC_TX_PAUSE;
1910         else
1911                 fc_conf->mode = RTE_FC_NONE;
1912
1913         return 0;
1914 }
1915
1916 static const uint32_t *
1917 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1918 {
1919         static const uint32_t ptypes[] = {
1920                 RTE_PTYPE_L2_ETHER,
1921                 RTE_PTYPE_L2_ETHER_VLAN,
1922                 RTE_PTYPE_L3_IPV4,
1923                 RTE_PTYPE_L3_IPV6,
1924                 RTE_PTYPE_L4_TCP,
1925                 RTE_PTYPE_L4_UDP,
1926                 RTE_PTYPE_TUNNEL_VXLAN,
1927                 RTE_PTYPE_L4_FRAG,
1928                 RTE_PTYPE_TUNNEL_GENEVE,
1929                 RTE_PTYPE_TUNNEL_GRE,
1930                 /* Inner */
1931                 RTE_PTYPE_INNER_L2_ETHER,
1932                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1933                 RTE_PTYPE_INNER_L3_IPV4,
1934                 RTE_PTYPE_INNER_L3_IPV6,
1935                 RTE_PTYPE_INNER_L4_TCP,
1936                 RTE_PTYPE_INNER_L4_UDP,
1937                 RTE_PTYPE_INNER_L4_FRAG,
1938                 RTE_PTYPE_UNKNOWN
1939         };
1940
1941         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1942                 return ptypes;
1943
1944         return NULL;
1945 }
1946
1947 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1948 {
1949         *rss_caps = 0;
1950         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1951         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1952         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1953         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1954         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1955         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1956         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1957         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1958 }
1959
1960 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1961                          struct rte_eth_rss_conf *rss_conf)
1962 {
1963         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1964         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1965         struct ecore_sp_vport_update_params vport_update_params;
1966         struct ecore_rss_params rss_params;
1967         struct ecore_hwfn *p_hwfn;
1968         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1969         uint64_t hf = rss_conf->rss_hf;
1970         uint8_t len = rss_conf->rss_key_len;
1971         uint8_t idx;
1972         uint8_t i;
1973         int rc;
1974
1975         memset(&vport_update_params, 0, sizeof(vport_update_params));
1976         memset(&rss_params, 0, sizeof(rss_params));
1977
1978         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1979                 (unsigned long)hf, len, key);
1980
1981         if (hf != 0) {
1982                 /* Enabling RSS */
1983                 DP_INFO(edev, "Enabling rss\n");
1984
1985                 /* RSS caps */
1986                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1987                 rss_params.update_rss_capabilities = 1;
1988
1989                 /* RSS hash key */
1990                 if (key) {
1991                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1992                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1993                                 return -EINVAL;
1994                         }
1995                         DP_INFO(edev, "Applying user supplied hash key\n");
1996                         rss_params.update_rss_key = 1;
1997                         memcpy(&rss_params.rss_key, key, len);
1998                 }
1999                 rss_params.rss_enable = 1;
2000         }
2001
2002         rss_params.update_rss_config = 1;
2003         /* tbl_size has to be set with capabilities */
2004         rss_params.rss_table_size_log = 7;
2005         vport_update_params.vport_id = 0;
2006         /* pass the L2 handles instead of qids */
2007         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2008                 idx = i % QEDE_RSS_COUNT(qdev);
2009                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2010         }
2011         vport_update_params.rss_params = &rss_params;
2012
2013         for_each_hwfn(edev, i) {
2014                 p_hwfn = &edev->hwfns[i];
2015                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2016                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2017                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2018                 if (rc) {
2019                         DP_ERR(edev, "vport-update for RSS failed\n");
2020                         return rc;
2021                 }
2022         }
2023         qdev->rss_enable = rss_params.rss_enable;
2024
2025         /* Update local structure for hash query */
2026         qdev->rss_conf.rss_hf = hf;
2027         qdev->rss_conf.rss_key_len = len;
2028         if (qdev->rss_enable) {
2029                 if  (qdev->rss_conf.rss_key == NULL) {
2030                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2031                         if (qdev->rss_conf.rss_key == NULL) {
2032                                 DP_ERR(edev, "No memory to store RSS key\n");
2033                                 return -ENOMEM;
2034                         }
2035                 }
2036                 if (key && len) {
2037                         DP_INFO(edev, "Storing RSS key\n");
2038                         memcpy(qdev->rss_conf.rss_key, key, len);
2039                 }
2040         } else if (!qdev->rss_enable && len == 0) {
2041                 if (qdev->rss_conf.rss_key) {
2042                         free(qdev->rss_conf.rss_key);
2043                         qdev->rss_conf.rss_key = NULL;
2044                         DP_INFO(edev, "Free RSS key\n");
2045                 }
2046         }
2047
2048         return 0;
2049 }
2050
2051 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2052                            struct rte_eth_rss_conf *rss_conf)
2053 {
2054         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2055
2056         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2057         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2058
2059         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2060                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2061                        rss_conf->rss_key_len);
2062         return 0;
2063 }
2064
2065 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2066                                     struct ecore_rss_params *rss)
2067 {
2068         int i, fn;
2069         bool rss_mode = 1; /* enable */
2070         struct ecore_queue_cid *cid;
2071         struct ecore_rss_params *t_rss;
2072
2073         /* In regular scenario, we'd simply need to take input handlers.
2074          * But in CMT, we'd have to split the handlers according to the
2075          * engine they were configured on. We'd then have to understand
2076          * whether RSS is really required, since 2-queues on CMT doesn't
2077          * require RSS.
2078          */
2079
2080         /* CMT should be round-robin */
2081         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2082                 cid = rss->rss_ind_table[i];
2083
2084                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2085                         t_rss = &rss[0];
2086                 else
2087                         t_rss = &rss[1];
2088
2089                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2090         }
2091
2092         t_rss = &rss[1];
2093         t_rss->update_rss_ind_table = 1;
2094         t_rss->rss_table_size_log = 7;
2095         t_rss->update_rss_config = 1;
2096
2097         /* Make sure RSS is actually required */
2098         for_each_hwfn(edev, fn) {
2099                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2100                      i++) {
2101                         if (rss[fn].rss_ind_table[i] !=
2102                             rss[fn].rss_ind_table[0])
2103                                 break;
2104                 }
2105
2106                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2107                         DP_INFO(edev,
2108                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2109                         rss_mode = 0;
2110                         goto out;
2111                 }
2112         }
2113
2114 out:
2115         t_rss->rss_enable = rss_mode;
2116
2117         return rss_mode;
2118 }
2119
2120 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2121                          struct rte_eth_rss_reta_entry64 *reta_conf,
2122                          uint16_t reta_size)
2123 {
2124         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2125         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2126         struct ecore_sp_vport_update_params vport_update_params;
2127         struct ecore_rss_params *params;
2128         struct ecore_hwfn *p_hwfn;
2129         uint16_t i, idx, shift;
2130         uint8_t entry;
2131         int rc = 0;
2132
2133         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2134                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2135                        reta_size);
2136                 return -EINVAL;
2137         }
2138
2139         memset(&vport_update_params, 0, sizeof(vport_update_params));
2140         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2141                              RTE_CACHE_LINE_SIZE);
2142         if (params == NULL) {
2143                 DP_ERR(edev, "failed to allocate memory\n");
2144                 return -ENOMEM;
2145         }
2146
2147         for (i = 0; i < reta_size; i++) {
2148                 idx = i / RTE_RETA_GROUP_SIZE;
2149                 shift = i % RTE_RETA_GROUP_SIZE;
2150                 if (reta_conf[idx].mask & (1ULL << shift)) {
2151                         entry = reta_conf[idx].reta[shift];
2152                         /* Pass rxq handles to ecore */
2153                         params->rss_ind_table[i] =
2154                                         qdev->fp_array[entry].rxq->handle;
2155                         /* Update the local copy for RETA query command */
2156                         qdev->rss_ind_table[i] = entry;
2157                 }
2158         }
2159
2160         params->update_rss_ind_table = 1;
2161         params->rss_table_size_log = 7;
2162         params->update_rss_config = 1;
2163
2164         /* Fix up RETA for CMT mode device */
2165         if (ECORE_IS_CMT(edev))
2166                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2167                                                             params);
2168         vport_update_params.vport_id = 0;
2169         /* Use the current value of rss_enable */
2170         params->rss_enable = qdev->rss_enable;
2171         vport_update_params.rss_params = params;
2172
2173         for_each_hwfn(edev, i) {
2174                 p_hwfn = &edev->hwfns[i];
2175                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2176                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2177                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2178                 if (rc) {
2179                         DP_ERR(edev, "vport-update for RSS failed\n");
2180                         goto out;
2181                 }
2182         }
2183
2184 out:
2185         rte_free(params);
2186         return rc;
2187 }
2188
2189 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2190                                struct rte_eth_rss_reta_entry64 *reta_conf,
2191                                uint16_t reta_size)
2192 {
2193         struct qede_dev *qdev = eth_dev->data->dev_private;
2194         struct ecore_dev *edev = &qdev->edev;
2195         uint16_t i, idx, shift;
2196         uint8_t entry;
2197
2198         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2199                 DP_ERR(edev, "reta_size %d is not supported\n",
2200                        reta_size);
2201                 return -EINVAL;
2202         }
2203
2204         for (i = 0; i < reta_size; i++) {
2205                 idx = i / RTE_RETA_GROUP_SIZE;
2206                 shift = i % RTE_RETA_GROUP_SIZE;
2207                 if (reta_conf[idx].mask & (1ULL << shift)) {
2208                         entry = qdev->rss_ind_table[i];
2209                         reta_conf[idx].reta[shift] = entry;
2210                 }
2211         }
2212
2213         return 0;
2214 }
2215
2216
2217
2218 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2219 {
2220         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2221         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2222         struct rte_eth_dev_info dev_info = {0};
2223         struct qede_fastpath *fp;
2224         uint32_t max_rx_pkt_len;
2225         uint32_t frame_size;
2226         uint16_t bufsz;
2227         bool restart = false;
2228         int i, rc;
2229
2230         PMD_INIT_FUNC_TRACE(edev);
2231         qede_dev_info_get(dev, &dev_info);
2232         max_rx_pkt_len = mtu + QEDE_MAX_ETHER_HDR_LEN;
2233         frame_size = max_rx_pkt_len;
2234         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen) {
2235                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2236                        mtu, dev_info.max_rx_pktlen - RTE_ETHER_HDR_LEN -
2237                        QEDE_ETH_OVERHEAD);
2238                 return -EINVAL;
2239         }
2240         if (!dev->data->scattered_rx &&
2241             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2242                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2243                         dev->data->min_rx_buf_size);
2244                 return -EINVAL;
2245         }
2246         /* Temporarily replace I/O functions with dummy ones. It cannot
2247          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2248          */
2249         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2250         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2251         if (dev->data->dev_started) {
2252                 dev->data->dev_started = 0;
2253                 qede_dev_stop(dev);
2254                 restart = true;
2255         }
2256         rte_delay_ms(1000);
2257         qdev->mtu = mtu;
2258
2259         /* Fix up RX buf size for all queues of the port */
2260         for_each_rss(i) {
2261                 fp = &qdev->fp_array[i];
2262                 if (fp->rxq != NULL) {
2263                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2264                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2265                         /* cache align the mbuf size to simplfy rx_buf_size
2266                          * calculation
2267                          */
2268                         bufsz = QEDE_FLOOR_TO_CACHE_LINE_SIZE(bufsz);
2269                         rc = qede_calc_rx_buf_size(dev, bufsz, frame_size);
2270                         if (rc < 0)
2271                                 return rc;
2272
2273                         fp->rxq->rx_buf_size = rc;
2274                 }
2275         }
2276         if (max_rx_pkt_len > RTE_ETHER_MAX_LEN)
2277                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
2278         else
2279                 dev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2280
2281         if (!dev->data->dev_started && restart) {
2282                 qede_dev_start(dev);
2283                 dev->data->dev_started = 1;
2284         }
2285
2286         /* update max frame size */
2287         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2288         /* Reassign back */
2289         dev->rx_pkt_burst = qede_recv_pkts;
2290         dev->tx_pkt_burst = qede_xmit_pkts;
2291
2292         return 0;
2293 }
2294
2295 static int
2296 qede_dev_reset(struct rte_eth_dev *dev)
2297 {
2298         int ret;
2299
2300         ret = qede_eth_dev_uninit(dev);
2301         if (ret)
2302                 return ret;
2303
2304         return qede_eth_dev_init(dev);
2305 }
2306
2307 static const struct eth_dev_ops qede_eth_dev_ops = {
2308         .dev_configure = qede_dev_configure,
2309         .dev_infos_get = qede_dev_info_get,
2310         .rx_queue_setup = qede_rx_queue_setup,
2311         .rx_queue_release = qede_rx_queue_release,
2312         .rx_descriptor_status = qede_rx_descriptor_status,
2313         .tx_queue_setup = qede_tx_queue_setup,
2314         .tx_queue_release = qede_tx_queue_release,
2315         .dev_start = qede_dev_start,
2316         .dev_reset = qede_dev_reset,
2317         .dev_set_link_up = qede_dev_set_link_up,
2318         .dev_set_link_down = qede_dev_set_link_down,
2319         .link_update = qede_link_update,
2320         .promiscuous_enable = qede_promiscuous_enable,
2321         .promiscuous_disable = qede_promiscuous_disable,
2322         .allmulticast_enable = qede_allmulticast_enable,
2323         .allmulticast_disable = qede_allmulticast_disable,
2324         .set_mc_addr_list = qede_set_mc_addr_list,
2325         .dev_stop = qede_dev_stop,
2326         .dev_close = qede_dev_close,
2327         .stats_get = qede_get_stats,
2328         .stats_reset = qede_reset_stats,
2329         .xstats_get = qede_get_xstats,
2330         .xstats_reset = qede_reset_xstats,
2331         .xstats_get_names = qede_get_xstats_names,
2332         .mac_addr_add = qede_mac_addr_add,
2333         .mac_addr_remove = qede_mac_addr_remove,
2334         .mac_addr_set = qede_mac_addr_set,
2335         .vlan_offload_set = qede_vlan_offload_set,
2336         .vlan_filter_set = qede_vlan_filter_set,
2337         .flow_ctrl_set = qede_flow_ctrl_set,
2338         .flow_ctrl_get = qede_flow_ctrl_get,
2339         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2340         .rss_hash_update = qede_rss_hash_update,
2341         .rss_hash_conf_get = qede_rss_hash_conf_get,
2342         .reta_update  = qede_rss_reta_update,
2343         .reta_query  = qede_rss_reta_query,
2344         .mtu_set = qede_set_mtu,
2345         .filter_ctrl = qede_dev_filter_ctrl,
2346         .udp_tunnel_port_add = qede_udp_dst_port_add,
2347         .udp_tunnel_port_del = qede_udp_dst_port_del,
2348 };
2349
2350 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2351         .dev_configure = qede_dev_configure,
2352         .dev_infos_get = qede_dev_info_get,
2353         .rx_queue_setup = qede_rx_queue_setup,
2354         .rx_queue_release = qede_rx_queue_release,
2355         .rx_descriptor_status = qede_rx_descriptor_status,
2356         .tx_queue_setup = qede_tx_queue_setup,
2357         .tx_queue_release = qede_tx_queue_release,
2358         .dev_start = qede_dev_start,
2359         .dev_reset = qede_dev_reset,
2360         .dev_set_link_up = qede_dev_set_link_up,
2361         .dev_set_link_down = qede_dev_set_link_down,
2362         .link_update = qede_link_update,
2363         .promiscuous_enable = qede_promiscuous_enable,
2364         .promiscuous_disable = qede_promiscuous_disable,
2365         .allmulticast_enable = qede_allmulticast_enable,
2366         .allmulticast_disable = qede_allmulticast_disable,
2367         .set_mc_addr_list = qede_set_mc_addr_list,
2368         .dev_stop = qede_dev_stop,
2369         .dev_close = qede_dev_close,
2370         .stats_get = qede_get_stats,
2371         .stats_reset = qede_reset_stats,
2372         .xstats_get = qede_get_xstats,
2373         .xstats_reset = qede_reset_xstats,
2374         .xstats_get_names = qede_get_xstats_names,
2375         .vlan_offload_set = qede_vlan_offload_set,
2376         .vlan_filter_set = qede_vlan_filter_set,
2377         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2378         .rss_hash_update = qede_rss_hash_update,
2379         .rss_hash_conf_get = qede_rss_hash_conf_get,
2380         .reta_update  = qede_rss_reta_update,
2381         .reta_query  = qede_rss_reta_query,
2382         .mtu_set = qede_set_mtu,
2383         .udp_tunnel_port_add = qede_udp_dst_port_add,
2384         .udp_tunnel_port_del = qede_udp_dst_port_del,
2385         .mac_addr_add = qede_mac_addr_add,
2386         .mac_addr_remove = qede_mac_addr_remove,
2387         .mac_addr_set = qede_mac_addr_set,
2388 };
2389
2390 static void qede_update_pf_params(struct ecore_dev *edev)
2391 {
2392         struct ecore_pf_params pf_params;
2393
2394         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2395         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2396         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2397         qed_ops->common->update_pf_params(edev, &pf_params);
2398 }
2399
2400 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2401 {
2402         struct rte_pci_device *pci_dev;
2403         struct rte_pci_addr pci_addr;
2404         struct qede_dev *adapter;
2405         struct ecore_dev *edev;
2406         struct qed_dev_eth_info dev_info;
2407         struct qed_slowpath_params params;
2408         static bool do_once = true;
2409         uint8_t bulletin_change;
2410         uint8_t vf_mac[RTE_ETHER_ADDR_LEN];
2411         uint8_t is_mac_forced;
2412         bool is_mac_exist;
2413         /* Fix up ecore debug level */
2414         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2415         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2416         uint32_t int_mode;
2417         int rc;
2418
2419         /* Extract key data structures */
2420         adapter = eth_dev->data->dev_private;
2421         adapter->ethdev = eth_dev;
2422         edev = &adapter->edev;
2423         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2424         pci_addr = pci_dev->addr;
2425
2426         PMD_INIT_FUNC_TRACE(edev);
2427
2428         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2429                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2430                  eth_dev->data->port_id);
2431
2432         eth_dev->rx_pkt_burst = qede_recv_pkts;
2433         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2434         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2435
2436         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2437                 DP_ERR(edev, "Skipping device init from secondary process\n");
2438                 return 0;
2439         }
2440
2441         rte_eth_copy_pci_info(eth_dev, pci_dev);
2442
2443         /* @DPDK */
2444         edev->vendor_id = pci_dev->id.vendor_id;
2445         edev->device_id = pci_dev->id.device_id;
2446
2447         qed_ops = qed_get_eth_ops();
2448         if (!qed_ops) {
2449                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2450                 return -EINVAL;
2451         }
2452
2453         DP_INFO(edev, "Starting qede probe\n");
2454         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2455                                     dp_level, is_vf);
2456         if (rc != 0) {
2457                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2458                 return -ENODEV;
2459         }
2460         qede_update_pf_params(edev);
2461
2462         switch (pci_dev->intr_handle.type) {
2463         case RTE_INTR_HANDLE_UIO_INTX:
2464         case RTE_INTR_HANDLE_VFIO_LEGACY:
2465                 int_mode = ECORE_INT_MODE_INTA;
2466                 rte_intr_callback_register(&pci_dev->intr_handle,
2467                                            qede_interrupt_handler_intx,
2468                                            (void *)eth_dev);
2469                 break;
2470         default:
2471                 int_mode = ECORE_INT_MODE_MSIX;
2472                 rte_intr_callback_register(&pci_dev->intr_handle,
2473                                            qede_interrupt_handler,
2474                                            (void *)eth_dev);
2475         }
2476
2477         if (rte_intr_enable(&pci_dev->intr_handle)) {
2478                 DP_ERR(edev, "rte_intr_enable() failed\n");
2479                 return -ENODEV;
2480         }
2481
2482         /* Start the Slowpath-process */
2483         memset(&params, 0, sizeof(struct qed_slowpath_params));
2484
2485         params.int_mode = int_mode;
2486         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2487         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2488         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2489         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2490         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2491                 QEDE_PMD_DRV_VER_STR_SIZE);
2492
2493         /* For CMT mode device do periodic polling for slowpath events.
2494          * This is required since uio device uses only one MSI-x
2495          * interrupt vector but we need one for each engine.
2496          */
2497         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2498                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
2499                                        qede_poll_sp_sb_cb,
2500                                        (void *)eth_dev);
2501                 if (rc != 0) {
2502                         DP_ERR(edev, "Unable to start periodic"
2503                                      " timer rc %d\n", rc);
2504                         return -EINVAL;
2505                 }
2506         }
2507
2508         rc = qed_ops->common->slowpath_start(edev, &params);
2509         if (rc) {
2510                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2511                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2512                                      (void *)eth_dev);
2513                 return -ENODEV;
2514         }
2515
2516         rc = qed_ops->fill_dev_info(edev, &dev_info);
2517         if (rc) {
2518                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2519                 qed_ops->common->slowpath_stop(edev);
2520                 qed_ops->common->remove(edev);
2521                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2522                                      (void *)eth_dev);
2523                 return -ENODEV;
2524         }
2525
2526         qede_alloc_etherdev(adapter, &dev_info);
2527
2528         adapter->ops->common->set_name(edev, edev->name);
2529
2530         if (!is_vf)
2531                 adapter->dev_info.num_mac_filters =
2532                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2533                                             ECORE_MAC);
2534         else
2535                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2536                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2537
2538         /* Allocate memory for storing MAC addr */
2539         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2540                                         (RTE_ETHER_ADDR_LEN *
2541                                         adapter->dev_info.num_mac_filters),
2542                                         RTE_CACHE_LINE_SIZE);
2543
2544         if (eth_dev->data->mac_addrs == NULL) {
2545                 DP_ERR(edev, "Failed to allocate MAC address\n");
2546                 qed_ops->common->slowpath_stop(edev);
2547                 qed_ops->common->remove(edev);
2548                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2549                                      (void *)eth_dev);
2550                 return -ENOMEM;
2551         }
2552
2553         if (!is_vf) {
2554                 rte_ether_addr_copy((struct rte_ether_addr *)edev->hwfns[0].
2555                                 hw_info.hw_mac_addr,
2556                                 &eth_dev->data->mac_addrs[0]);
2557                 rte_ether_addr_copy(&eth_dev->data->mac_addrs[0],
2558                                 &adapter->primary_mac);
2559         } else {
2560                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2561                                        &bulletin_change);
2562                 if (bulletin_change) {
2563                         is_mac_exist =
2564                             ecore_vf_bulletin_get_forced_mac(
2565                                                 ECORE_LEADING_HWFN(edev),
2566                                                 vf_mac,
2567                                                 &is_mac_forced);
2568                         if (is_mac_exist) {
2569                                 DP_INFO(edev, "VF macaddr received from PF\n");
2570                                 rte_ether_addr_copy(
2571                                         (struct rte_ether_addr *)&vf_mac,
2572                                         &eth_dev->data->mac_addrs[0]);
2573                                 rte_ether_addr_copy(
2574                                         &eth_dev->data->mac_addrs[0],
2575                                         &adapter->primary_mac);
2576                         } else {
2577                                 DP_ERR(edev, "No VF macaddr assigned\n");
2578                         }
2579                 }
2580         }
2581
2582         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2583
2584         if (do_once) {
2585                 qede_print_adapter_info(adapter);
2586                 do_once = false;
2587         }
2588
2589         /* Bring-up the link */
2590         qede_dev_set_link_state(eth_dev, true);
2591
2592         adapter->num_tx_queues = 0;
2593         adapter->num_rx_queues = 0;
2594         SLIST_INIT(&adapter->arfs_info.arfs_list_head);
2595         SLIST_INIT(&adapter->vlan_list_head);
2596         SLIST_INIT(&adapter->uc_list_head);
2597         SLIST_INIT(&adapter->mc_list_head);
2598         adapter->mtu = RTE_ETHER_MTU;
2599         adapter->vport_started = false;
2600
2601         /* VF tunnel offloads is enabled by default in PF driver */
2602         adapter->vxlan.num_filters = 0;
2603         adapter->geneve.num_filters = 0;
2604         adapter->ipgre.num_filters = 0;
2605         if (is_vf) {
2606                 adapter->vxlan.enable = true;
2607                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
2608                                              ETH_TUNNEL_FILTER_IVLAN;
2609                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
2610                 adapter->geneve.enable = true;
2611                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
2612                                               ETH_TUNNEL_FILTER_IVLAN;
2613                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
2614                 adapter->ipgre.enable = true;
2615                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
2616                                              ETH_TUNNEL_FILTER_IVLAN;
2617         } else {
2618                 adapter->vxlan.enable = false;
2619                 adapter->geneve.enable = false;
2620                 adapter->ipgre.enable = false;
2621         }
2622
2623         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2624                 adapter->primary_mac.addr_bytes[0],
2625                 adapter->primary_mac.addr_bytes[1],
2626                 adapter->primary_mac.addr_bytes[2],
2627                 adapter->primary_mac.addr_bytes[3],
2628                 adapter->primary_mac.addr_bytes[4],
2629                 adapter->primary_mac.addr_bytes[5]);
2630
2631         DP_INFO(edev, "Device initialized\n");
2632
2633         return 0;
2634 }
2635
2636 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2637 {
2638         return qede_common_dev_init(eth_dev, 1);
2639 }
2640
2641 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2642 {
2643         return qede_common_dev_init(eth_dev, 0);
2644 }
2645
2646 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2647 {
2648         struct qede_dev *qdev = eth_dev->data->dev_private;
2649         struct ecore_dev *edev = &qdev->edev;
2650
2651         PMD_INIT_FUNC_TRACE(edev);
2652
2653         /* only uninitialize in the primary process */
2654         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2655                 return 0;
2656
2657         /* safe to close dev here */
2658         qede_dev_close(eth_dev);
2659
2660         eth_dev->dev_ops = NULL;
2661         eth_dev->rx_pkt_burst = NULL;
2662         eth_dev->tx_pkt_burst = NULL;
2663
2664         return 0;
2665 }
2666
2667 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2668 {
2669         return qede_dev_common_uninit(eth_dev);
2670 }
2671
2672 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2673 {
2674         return qede_dev_common_uninit(eth_dev);
2675 }
2676
2677 static const struct rte_pci_id pci_id_qedevf_map[] = {
2678 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2679         {
2680                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2681         },
2682         {
2683                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2684         },
2685         {
2686                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2687         },
2688         {.vendor_id = 0,}
2689 };
2690
2691 static const struct rte_pci_id pci_id_qede_map[] = {
2692 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2693         {
2694                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2695         },
2696         {
2697                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2698         },
2699         {
2700                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2701         },
2702         {
2703                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2704         },
2705         {
2706                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2707         },
2708         {
2709                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2710         },
2711         {
2712                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2713         },
2714         {
2715                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2716         },
2717         {
2718                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2719         },
2720         {
2721                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2722         },
2723         {.vendor_id = 0,}
2724 };
2725
2726 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2727         struct rte_pci_device *pci_dev)
2728 {
2729         return rte_eth_dev_pci_generic_probe(pci_dev,
2730                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2731 }
2732
2733 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2734 {
2735         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2736 }
2737
2738 static struct rte_pci_driver rte_qedevf_pmd = {
2739         .id_table = pci_id_qedevf_map,
2740         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2741         .probe = qedevf_eth_dev_pci_probe,
2742         .remove = qedevf_eth_dev_pci_remove,
2743 };
2744
2745 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2746         struct rte_pci_device *pci_dev)
2747 {
2748         return rte_eth_dev_pci_generic_probe(pci_dev,
2749                 sizeof(struct qede_dev), qede_eth_dev_init);
2750 }
2751
2752 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2753 {
2754         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2755 }
2756
2757 static struct rte_pci_driver rte_qede_pmd = {
2758         .id_table = pci_id_qede_map,
2759         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2760         .probe = qede_eth_dev_pci_probe,
2761         .remove = qede_eth_dev_pci_remove,
2762 };
2763
2764 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2765 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2766 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2767 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2768 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2769 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
2770
2771 RTE_INIT(qede_init_log)
2772 {
2773         qede_logtype_init = rte_log_register("pmd.net.qede.init");
2774         if (qede_logtype_init >= 0)
2775                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
2776         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
2777         if (qede_logtype_driver >= 0)
2778                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
2779 }