drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 - 2018 Cavium Inc.
   3  * All rights reserved.
   4  * www.cavium.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 #define QEDE_SP_TIMER_PERIOD    10000 /* 100ms */
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 #define QEDE_NPAR_TX_SWITCHING          "npar_tx_switching"
 503 #define QEDE_VF_TX_SWITCHING            "vf_tx_switching"
 504
 505 /* Activate or deactivate vport via vport-update */
 506 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 507 {
 508         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 509         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 510         struct ecore_sp_vport_update_params params;
 511         struct ecore_hwfn *p_hwfn;
 512         uint8_t i;
 513         int rc = -1;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         params.vport_id = 0;
 517         params.update_vport_active_rx_flg = 1;
 518         params.update_vport_active_tx_flg = 1;
 519         params.vport_active_rx_flg = flg;
 520         params.vport_active_tx_flg = flg;
 521         if (!qdev->enable_tx_switching) {
 522                 if ((QEDE_NPAR_TX_SWITCHING != NULL) ||
 523                     ((QEDE_VF_TX_SWITCHING != NULL) && IS_VF(edev))) {
 524                         params.update_tx_switching_flg = 1;
 525                         params.tx_switching_flg = !flg;
 526                         DP_INFO(edev, "%s tx-switching is disabled\n",
 527                                 QEDE_NPAR_TX_SWITCHING ? "NPAR" : "VF");
 528                 }
 529         }
 530         for_each_hwfn(edev, i) {
 531                 p_hwfn = &edev->hwfns[i];
 532                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 533                 rc = ecore_sp_vport_update(p_hwfn, &params,
 534                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 535                 if (rc != ECORE_SUCCESS) {
 536                         DP_ERR(edev, "Failed to update vport\n");
 537                         break;
 538                 }
 539         }
 540         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 541
 542         return rc;
 543 }
 544
 545 static void
 546 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 547                            uint16_t mtu, bool enable)
 548 {
 549         /* Enable LRO in split mode */
 550         sge_tpa_params->tpa_ipv4_en_flg = enable;
 551         sge_tpa_params->tpa_ipv6_en_flg = enable;
 552         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 553         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 554         /* set if tpa enable changes */
 555         sge_tpa_params->update_tpa_en_flg = 1;
 556         /* set if tpa parameters should be handled */
 557         sge_tpa_params->update_tpa_param_flg = enable;
 558
 559         sge_tpa_params->max_buffers_per_cqe = 20;
 560         /* Enable TPA in split mode. In this mode each TPA segment
 561          * starts on the new BD, so there is one BD per segment.
 562          */
 563         sge_tpa_params->tpa_pkt_split_flg = 1;
 564         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 565         sge_tpa_params->tpa_gro_consistent_flg = 0;
 566         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 567         sge_tpa_params->tpa_max_size = 0x7FFF;
 568         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 569         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 570 }
 571
 572 /* Enable/disable LRO via vport-update */
 573 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 574 {
 575         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 576         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 577         struct ecore_sp_vport_update_params params;
 578         struct ecore_sge_tpa_params tpa_params;
 579         struct ecore_hwfn *p_hwfn;
 580         int rc;
 581         int i;
 582
 583         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 584         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 585         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 586         params.vport_id = 0;
 587         params.sge_tpa_params = &tpa_params;
 588         for_each_hwfn(edev, i) {
 589                 p_hwfn = &edev->hwfns[i];
 590                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 591                 rc = ecore_sp_vport_update(p_hwfn, &params,
 592                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 593                 if (rc != ECORE_SUCCESS) {
 594                         DP_ERR(edev, "Failed to update LRO\n");
 595                         return -1;
 596                 }
 597         }
 598         qdev->enable_lro = flg;
 599         eth_dev->data->lro = flg;
 600
 601         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 602
 603         return 0;
 604 }
 605
 606 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 607 {
 608         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 609         ucast->is_rx_filter = true;
 610         ucast->is_tx_filter = true;
 611         /* ucast->assert_on_error = true; - For debug */
 612 }
 613
 614 static int
 615 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 616                              enum qed_filter_rx_mode_type type)
 617 {
 618         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 619         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 620         struct ecore_filter_accept_flags flags;
 621
 622         memset(&flags, 0, sizeof(flags));
 623
 624         flags.update_rx_mode_config = 1;
 625         flags.update_tx_mode_config = 1;
 626         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 627                 ECORE_ACCEPT_MCAST_MATCHED |
 628                 ECORE_ACCEPT_BCAST;
 629
 630         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 631                 ECORE_ACCEPT_MCAST_MATCHED |
 632                 ECORE_ACCEPT_BCAST;
 633
 634         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 635                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 636                 if (IS_VF(edev)) {
 637                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 638                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 639                 }
 640         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 641                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 642         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 643                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 644                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 645                         ECORE_ACCEPT_MCAST_UNMATCHED;
 646         }
 647
 648         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 649                         ECORE_SPQ_MODE_CB, NULL);
 650 }
 651
 652 static int
 653 qede_tunnel_update(struct qede_dev *qdev,
 654                    struct ecore_tunnel_info *tunn_info)
 655 {
 656         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 657         enum _ecore_status_t rc = ECORE_INVAL;
 658         struct ecore_hwfn *p_hwfn;
 659         struct ecore_ptt *p_ptt;
 660         int i;
 661
 662         for_each_hwfn(edev, i) {
 663                 p_hwfn = &edev->hwfns[i];
 664                 if (IS_PF(edev)) {
 665                         p_ptt = ecore_ptt_acquire(p_hwfn);
 666                         if (!p_ptt) {
 667                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 668                                 return -EAGAIN;
 669                         }
 670                 } else {
 671                         p_ptt = NULL;
 672                 }
 673
 674                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 675                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 676                 if (IS_PF(edev))
 677                         ecore_ptt_release(p_hwfn, p_ptt);
 678
 679                 if (rc != ECORE_SUCCESS)
 680                         break;
 681         }
 682
 683         return rc;
 684 }
 685
 686 static int
 687 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 688                   bool enable)
 689 {
 690         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 691         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 692         enum _ecore_status_t rc = ECORE_INVAL;
 693         struct ecore_tunnel_info tunn;
 694
 695         if (qdev->vxlan.enable == enable)
 696                 return ECORE_SUCCESS;
 697
 698         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 699         tunn.vxlan.b_update_mode = true;
 700         tunn.vxlan.b_mode_enabled = enable;
 701         tunn.b_update_rx_cls = true;
 702         tunn.b_update_tx_cls = true;
 703         tunn.vxlan.tun_cls = clss;
 704
 705         tunn.vxlan_port.b_update_port = true;
 706         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 707
 708         rc = qede_tunnel_update(qdev, &tunn);
 709         if (rc == ECORE_SUCCESS) {
 710                 qdev->vxlan.enable = enable;
 711                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 712                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 713                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 714         } else {
 715                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 716                        tunn.vxlan.tun_cls);
 717         }
 718
 719         return rc;
 720 }
 721
 722 static int
 723 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 724                   bool enable)
 725 {
 726         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 727         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 728         enum _ecore_status_t rc = ECORE_INVAL;
 729         struct ecore_tunnel_info tunn;
 730
 731         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 732         tunn.l2_geneve.b_update_mode = true;
 733         tunn.l2_geneve.b_mode_enabled = enable;
 734         tunn.ip_geneve.b_update_mode = true;
 735         tunn.ip_geneve.b_mode_enabled = enable;
 736         tunn.l2_geneve.tun_cls = clss;
 737         tunn.ip_geneve.tun_cls = clss;
 738         tunn.b_update_rx_cls = true;
 739         tunn.b_update_tx_cls = true;
 740
 741         tunn.geneve_port.b_update_port = true;
 742         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 743
 744         rc = qede_tunnel_update(qdev, &tunn);
 745         if (rc == ECORE_SUCCESS) {
 746                 qdev->geneve.enable = enable;
 747                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 748                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 749                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 750         } else {
 751                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 752                        clss);
 753         }
 754
 755         return rc;
 756 }
 757
 758 static int
 759 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 760                   bool enable)
 761 {
 762         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 763         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 764         enum _ecore_status_t rc = ECORE_INVAL;
 765         struct ecore_tunnel_info tunn;
 766
 767         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 768         tunn.ip_gre.b_update_mode = true;
 769         tunn.ip_gre.b_mode_enabled = enable;
 770         tunn.ip_gre.tun_cls = clss;
 771         tunn.ip_gre.tun_cls = clss;
 772         tunn.b_update_rx_cls = true;
 773         tunn.b_update_tx_cls = true;
 774
 775         rc = qede_tunnel_update(qdev, &tunn);
 776         if (rc == ECORE_SUCCESS) {
 777                 qdev->ipgre.enable = enable;
 778                 DP_INFO(edev, "IPGRE is %s\n",
 779                         enable ? "enabled" : "disabled");
 780         } else {
 781                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 782                        clss);
 783         }
 784
 785         return rc;
 786 }
 787
 788 static int
 789 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 790                  enum rte_eth_tunnel_type tunn_type, bool enable)
 791 {
 792         int rc = -EINVAL;
 793
 794         switch (tunn_type) {
 795         case RTE_TUNNEL_TYPE_VXLAN:
 796                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 797                 break;
 798         case RTE_TUNNEL_TYPE_GENEVE:
 799                 rc = qede_geneve_enable(eth_dev, clss, enable);
 800                 break;
 801         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 802                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 803                 break;
 804         default:
 805                 rc = -EINVAL;
 806                 break;
 807         }
 808
 809         return rc;
 810 }
 811
 812 static int
 813 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 814                   bool add)
 815 {
 816         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 817         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 818         struct qede_ucast_entry *tmp = NULL;
 819         struct qede_ucast_entry *u;
 820         struct ether_addr *mac_addr;
 821
 822         mac_addr  = (struct ether_addr *)ucast->mac;
 823         if (add) {
 824                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 825                         if ((memcmp(mac_addr, &tmp->mac,
 826                                     ETHER_ADDR_LEN) == 0) &&
 827                              ucast->vni == tmp->vni &&
 828                              ucast->vlan == tmp->vlan) {
 829                                 DP_INFO(edev, "Unicast MAC is already added"
 830                                         " with vlan = %u, vni = %u\n",
 831                                         ucast->vlan,  ucast->vni);
 832                                         return 0;
 833                         }
 834                 }
 835                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 836                                RTE_CACHE_LINE_SIZE);
 837                 if (!u) {
 838                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 839                         return -ENOMEM;
 840                 }
 841                 ether_addr_copy(mac_addr, &u->mac);
 842                 u->vlan = ucast->vlan;
 843                 u->vni = ucast->vni;
 844                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 845                 qdev->num_uc_addr++;
 846         } else {
 847                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 848                         if ((memcmp(mac_addr, &tmp->mac,
 849                                     ETHER_ADDR_LEN) == 0) &&
 850                             ucast->vlan == tmp->vlan      &&
 851                             ucast->vni == tmp->vni)
 852                         break;
 853                 }
 854                 if (tmp == NULL) {
 855                         DP_INFO(edev, "Unicast MAC is not found\n");
 856                         return -EINVAL;
 857                 }
 858                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 859                 qdev->num_uc_addr--;
 860         }
 861
 862         return 0;
 863 }
 864
 865 static int
 866 qede_add_mcast_filters(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
 867                        uint32_t mc_addrs_num)
 868 {
 869         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 870         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 871         struct ecore_filter_mcast mcast;
 872         struct qede_mcast_entry *m = NULL;
 873         uint8_t i;
 874         int rc;
 875
 876         for (i = 0; i < mc_addrs_num; i++) {
 877                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 878                                RTE_CACHE_LINE_SIZE);
 879                 if (!m) {
 880                         DP_ERR(edev, "Did not allocate memory for mcast\n");
 881                         return -ENOMEM;
 882                 }
 883                 ether_addr_copy(&mc_addrs[i], &m->mac);
 884                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 885         }
 886         memset(&mcast, 0, sizeof(mcast));
 887         mcast.num_mc_addrs = mc_addrs_num;
 888         mcast.opcode = ECORE_FILTER_ADD;
 889         for (i = 0; i < mc_addrs_num; i++)
 890                 ether_addr_copy(&mc_addrs[i], (struct ether_addr *)
 891                                                         &mcast.mac[i]);
 892         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 893         if (rc != ECORE_SUCCESS) {
 894                 DP_ERR(edev, "Failed to add multicast filter (rc = %d\n)", rc);
 895                 return -1;
 896         }
 897
 898         return 0;
 899 }
 900
 901 static int qede_del_mcast_filters(struct rte_eth_dev *eth_dev)
 902 {
 903         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 904         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 905         struct qede_mcast_entry *tmp = NULL;
 906         struct ecore_filter_mcast mcast;
 907         int j;
 908         int rc;
 909
 910         memset(&mcast, 0, sizeof(mcast));
 911         mcast.num_mc_addrs = qdev->num_mc_addr;
 912         mcast.opcode = ECORE_FILTER_REMOVE;
 913         j = 0;
 914         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 915                 ether_addr_copy(&tmp->mac, (struct ether_addr *)&mcast.mac[j]);
 916                 j++;
 917         }
 918         rc = ecore_filter_mcast_cmd(edev, &mcast, ECORE_SPQ_MODE_CB, NULL);
 919         if (rc != ECORE_SUCCESS) {
 920                 DP_ERR(edev, "Failed to delete multicast filter\n");
 921                 return -1;
 922         }
 923         /* Init the list */
 924         while (!SLIST_EMPTY(&qdev->mc_list_head)) {
 925                 tmp = SLIST_FIRST(&qdev->mc_list_head);
 926                 SLIST_REMOVE_HEAD(&qdev->mc_list_head, list);
 927         }
 928         SLIST_INIT(&qdev->mc_list_head);
 929
 930         return 0;
 931 }
 932
 933 static enum _ecore_status_t
 934 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 935                  bool add)
 936 {
 937         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 938         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 939         enum _ecore_status_t rc = ECORE_INVAL;
 940
 941         if (add && (qdev->num_uc_addr >= qdev->dev_info.num_mac_filters)) {
 942                 DP_ERR(edev, "Ucast filter table limit exceeded,"
 943                               " Please enable promisc mode\n");
 944                         return ECORE_INVAL;
 945         }
 946
 947         rc = qede_ucast_filter(eth_dev, ucast, add);
 948         if (rc == 0)
 949                 rc = ecore_filter_ucast_cmd(edev, ucast,
 950                                             ECORE_SPQ_MODE_CB, NULL);
 951         if (rc != ECORE_SUCCESS)
 952                 DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 953                        rc, add);
 954
 955         return rc;
 956 }
 957
 958 static int
 959 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 960                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 961 {
 962         struct ecore_filter_ucast ucast;
 963         int re;
 964
 965         qede_set_ucast_cmn_params(&ucast);
 966         ucast.type = ECORE_FILTER_MAC;
 967         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 968         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 969         return re;
 970 }
 971
 972 static void
 973 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 974 {
 975         struct qede_dev *qdev = eth_dev->data->dev_private;
 976         struct ecore_dev *edev = &qdev->edev;
 977         struct ecore_filter_ucast ucast;
 978
 979         PMD_INIT_FUNC_TRACE(edev);
 980
 981         if (index >= qdev->dev_info.num_mac_filters) {
 982                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 983                        index, qdev->dev_info.num_mac_filters);
 984                 return;
 985         }
 986
 987         qede_set_ucast_cmn_params(&ucast);
 988         ucast.opcode = ECORE_FILTER_REMOVE;
 989         ucast.type = ECORE_FILTER_MAC;
 990
 991         /* Use the index maintained by rte */
 992         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 993                         (struct ether_addr *)&ucast.mac);
 994
 995         qede_mac_int_ops(eth_dev, &ucast, false);
 996 }
 997
 998 static int
 999 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1000 {
1001         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1002         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1003
1004         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1005                                                mac_addr->addr_bytes)) {
1006                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1007                 return -EPERM;
1008         }
1009
1010         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1011         return 0;
1012 }
1013
1014 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1015 {
1016         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1017         struct ecore_sp_vport_update_params params;
1018         struct ecore_hwfn *p_hwfn;
1019         uint8_t i;
1020         int rc;
1021
1022         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1023         params.vport_id = 0;
1024         params.update_accept_any_vlan_flg = 1;
1025         params.accept_any_vlan = flg;
1026         for_each_hwfn(edev, i) {
1027                 p_hwfn = &edev->hwfns[i];
1028                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1029                 rc = ecore_sp_vport_update(p_hwfn, &params,
1030                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1031                 if (rc != ECORE_SUCCESS) {
1032                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1033                         return;
1034                 }
1035         }
1036
1037         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1038 }
1039
1040 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1041 {
1042         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1043         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1044         struct ecore_sp_vport_update_params params;
1045         struct ecore_hwfn *p_hwfn;
1046         uint8_t i;
1047         int rc;
1048
1049         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1050         params.vport_id = 0;
1051         params.update_inner_vlan_removal_flg = 1;
1052         params.inner_vlan_removal_flg = flg;
1053         for_each_hwfn(edev, i) {
1054                 p_hwfn = &edev->hwfns[i];
1055                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1056                 rc = ecore_sp_vport_update(p_hwfn, &params,
1057                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1058                 if (rc != ECORE_SUCCESS) {
1059                         DP_ERR(edev, "Failed to update vport\n");
1060                         return -1;
1061                 }
1062         }
1063
1064         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1065         return 0;
1066 }
1067
1068 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1069                                 uint16_t vlan_id, int on)
1070 {
1071         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1072         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1073         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1074         struct qede_vlan_entry *tmp = NULL;
1075         struct qede_vlan_entry *vlan;
1076         struct ecore_filter_ucast ucast;
1077         int rc;
1078
1079         if (on) {
1080                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1081                         DP_ERR(edev, "Reached max VLAN filter limit"
1082                                       " enabling accept_any_vlan\n");
1083                         qede_config_accept_any_vlan(qdev, true);
1084                         return 0;
1085                 }
1086
1087                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1088                         if (tmp->vid == vlan_id) {
1089                                 DP_INFO(edev, "VLAN %u already configured\n",
1090                                         vlan_id);
1091                                 return 0;
1092                         }
1093                 }
1094
1095                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1096                                   RTE_CACHE_LINE_SIZE);
1097
1098                 if (!vlan) {
1099                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1100                         return -ENOMEM;
1101                 }
1102
1103                 qede_set_ucast_cmn_params(&ucast);
1104                 ucast.opcode = ECORE_FILTER_ADD;
1105                 ucast.type = ECORE_FILTER_VLAN;
1106                 ucast.vlan = vlan_id;
1107                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1108                                             NULL);
1109                 if (rc != 0) {
1110                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1111                                rc);
1112                         rte_free(vlan);
1113                 } else {
1114                         vlan->vid = vlan_id;
1115                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1116                         qdev->configured_vlans++;
1117                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1118                                 vlan_id, qdev->configured_vlans);
1119                 }
1120         } else {
1121                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1122                         if (tmp->vid == vlan_id)
1123                                 break;
1124                 }
1125
1126                 if (!tmp) {
1127                         if (qdev->configured_vlans == 0) {
1128                                 DP_INFO(edev,
1129                                         "No VLAN filters configured yet\n");
1130                                 return 0;
1131                         }
1132
1133                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1134                         return -EINVAL;
1135                 }
1136
1137                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1138
1139                 qede_set_ucast_cmn_params(&ucast);
1140                 ucast.opcode = ECORE_FILTER_REMOVE;
1141                 ucast.type = ECORE_FILTER_VLAN;
1142                 ucast.vlan = vlan_id;
1143                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1144                                             NULL);
1145                 if (rc != 0) {
1146                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1147                                vlan_id, rc);
1148                 } else {
1149                         qdev->configured_vlans--;
1150                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1151                                 vlan_id, qdev->configured_vlans);
1152                 }
1153         }
1154
1155         return rc;
1156 }
1157
1158 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1159 {
1160         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1161         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1162         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1163
1164         if (mask & ETH_VLAN_STRIP_MASK) {
1165                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1166                         (void)qede_vlan_stripping(eth_dev, 1);
1167                 else
1168                         (void)qede_vlan_stripping(eth_dev, 0);
1169         }
1170
1171         if (mask & ETH_VLAN_FILTER_MASK) {
1172                 /* VLAN filtering kicks in when a VLAN is added */
1173                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1174                         qede_vlan_filter_set(eth_dev, 0, 1);
1175                 } else {
1176                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1177                                 DP_ERR(edev,
1178                                   " Please remove existing VLAN filters"
1179                                   " before disabling VLAN filtering\n");
1180                                 /* Signal app that VLAN filtering is still
1181                                  * enabled
1182                                  */
1183                                 eth_dev->data->dev_conf.rxmode.offloads |=
1184                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1185                         } else {
1186                                 qede_vlan_filter_set(eth_dev, 0, 0);
1187                         }
1188                 }
1189         }
1190
1191         if (mask & ETH_VLAN_EXTEND_MASK)
1192                 DP_ERR(edev, "Extend VLAN not supported\n");
1193
1194         qdev->vlan_offload_mask = mask;
1195
1196         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1197
1198         return 0;
1199 }
1200
1201 static void qede_prandom_bytes(uint32_t *buff)
1202 {
1203         uint8_t i;
1204
1205         srand((unsigned int)time(NULL));
1206         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1207                 buff[i] = rand();
1208 }
1209
1210 int qede_config_rss(struct rte_eth_dev *eth_dev)
1211 {
1212         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1213         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1214         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1215         struct rte_eth_rss_reta_entry64 reta_conf[2];
1216         struct rte_eth_rss_conf rss_conf;
1217         uint32_t i, id, pos, q;
1218
1219         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1220         if (!rss_conf.rss_key) {
1221                 DP_INFO(edev, "Applying driver default key\n");
1222                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1223                 qede_prandom_bytes(&def_rss_key[0]);
1224                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1225         }
1226
1227         /* Configure RSS hash */
1228         if (qede_rss_hash_update(eth_dev, &rss_conf))
1229                 return -EINVAL;
1230
1231         /* Configure default RETA */
1232         memset(reta_conf, 0, sizeof(reta_conf));
1233         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1234                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1235
1236         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1237                 id = i / RTE_RETA_GROUP_SIZE;
1238                 pos = i % RTE_RETA_GROUP_SIZE;
1239                 q = i % QEDE_RSS_COUNT(qdev);
1240                 reta_conf[id].reta[pos] = q;
1241         }
1242         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1243                                  ECORE_RSS_IND_TABLE_SIZE))
1244                 return -EINVAL;
1245
1246         return 0;
1247 }
1248
1249 static void qede_fastpath_start(struct ecore_dev *edev)
1250 {
1251         struct ecore_hwfn *p_hwfn;
1252         int i;
1253
1254         for_each_hwfn(edev, i) {
1255                 p_hwfn = &edev->hwfns[i];
1256                 ecore_hw_start_fastpath(p_hwfn);
1257         }
1258 }
1259
1260 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1261 {
1262         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1263         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1264         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1265
1266         PMD_INIT_FUNC_TRACE(edev);
1267
1268         /* Update MTU only if it has changed */
1269         if (eth_dev->data->mtu != qdev->mtu) {
1270                 if (qede_update_mtu(eth_dev, qdev->mtu))
1271                         goto err;
1272         }
1273
1274         /* Configure TPA parameters */
1275         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1276                 if (qede_enable_tpa(eth_dev, true))
1277                         return -EINVAL;
1278                 /* Enable scatter mode for LRO */
1279                 if (!eth_dev->data->scattered_rx)
1280                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1281         }
1282
1283         /* Start queues */
1284         if (qede_start_queues(eth_dev))
1285                 goto err;
1286
1287         if (IS_PF(edev))
1288                 qede_reset_queue_stats(qdev, true);
1289
1290         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1291          * enabling RSS. Hence RSS configuration is deferred upto this point.
1292          * Also, we would like to retain similar behavior in PF case, so we
1293          * don't do PF/VF specific check here.
1294          */
1295         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1296                 if (qede_config_rss(eth_dev))
1297                         goto err;
1298
1299         /* Enable vport*/
1300         if (qede_activate_vport(eth_dev, true))
1301                 goto err;
1302
1303         /* Update link status */
1304         qede_link_update(eth_dev, 0);
1305
1306         /* Start/resume traffic */
1307         qede_fastpath_start(edev);
1308
1309         DP_INFO(edev, "Device started\n");
1310
1311         return 0;
1312 err:
1313         DP_ERR(edev, "Device start fails\n");
1314         return -1; /* common error code is < 0 */
1315 }
1316
1317 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1318 {
1319         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1320         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1321
1322         PMD_INIT_FUNC_TRACE(edev);
1323
1324         /* Disable vport */
1325         if (qede_activate_vport(eth_dev, false))
1326                 return;
1327
1328         if (qdev->enable_lro)
1329                 qede_enable_tpa(eth_dev, false);
1330
1331         /* Stop queues */
1332         qede_stop_queues(eth_dev);
1333
1334         /* Disable traffic */
1335         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1336
1337         if (IS_PF(edev))
1338                 qede_mac_addr_remove(eth_dev, 0);
1339
1340         DP_INFO(edev, "Device is stopped\n");
1341 }
1342
1343 const char *valid_args[] = {
1344         QEDE_NPAR_TX_SWITCHING,
1345         QEDE_VF_TX_SWITCHING,
1346         NULL,
1347 };
1348
1349 static int qede_args_check(const char *key, const char *val, void *opaque)
1350 {
1351         unsigned long tmp;
1352         int ret = 0;
1353         struct rte_eth_dev *eth_dev = opaque;
1354         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1355         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1356
1357         errno = 0;
1358         tmp = strtoul(val, NULL, 0);
1359         if (errno) {
1360                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1361                 return errno;
1362         }
1363
1364         if ((strcmp(QEDE_NPAR_TX_SWITCHING, key) == 0) ||
1365             (strcmp(QEDE_VF_TX_SWITCHING, key) == 0))
1366                 qdev->enable_tx_switching = !!tmp;
1367
1368         return ret;
1369 }
1370
1371 static int qede_args(struct rte_eth_dev *eth_dev)
1372 {
1373         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1374         struct rte_kvargs *kvlist;
1375         struct rte_devargs *devargs;
1376         int ret;
1377         int i;
1378
1379         devargs = pci_dev->device.devargs;
1380         if (!devargs)
1381                 return 0; /* return success */
1382
1383         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1384         if (kvlist == NULL)
1385                 return -EINVAL;
1386
1387          /* Process parameters. */
1388         for (i = 0; (valid_args[i] != NULL); ++i) {
1389                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1390                         ret = rte_kvargs_process(kvlist, valid_args[i],
1391                                                  qede_args_check, eth_dev);
1392                         if (ret != ECORE_SUCCESS) {
1393                                 rte_kvargs_free(kvlist);
1394                                 return ret;
1395                         }
1396                 }
1397         }
1398         rte_kvargs_free(kvlist);
1399
1400         return 0;
1401 }
1402
1403 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1404 {
1405         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1407         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1408         int ret;
1409
1410         PMD_INIT_FUNC_TRACE(edev);
1411
1412         /* Check requirements for 100G mode */
1413         if (ECORE_IS_CMT(edev)) {
1414                 if (eth_dev->data->nb_rx_queues < 2 ||
1415                     eth_dev->data->nb_tx_queues < 2) {
1416                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1417                         return -EINVAL;
1418                 }
1419
1420                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1421                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1422                         DP_ERR(edev,
1423                                "100G mode needs even no. of RX/TX queues\n");
1424                         return -EINVAL;
1425                 }
1426         }
1427
1428         /* We need to have min 1 RX queue.There is no min check in
1429          * rte_eth_dev_configure(), so we are checking it here.
1430          */
1431         if (eth_dev->data->nb_rx_queues == 0) {
1432                 DP_ERR(edev, "Minimum one RX queue is required\n");
1433                 return -EINVAL;
1434         }
1435
1436         /* Enable Tx switching by default */
1437         qdev->enable_tx_switching = 1;
1438
1439         /* Parse devargs and fix up rxmode */
1440         if (qede_args(eth_dev))
1441                 return -ENOTSUP;
1442
1443         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1444               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1445                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1446                 return -ENOTSUP;
1447         }
1448         /* Flow director mode check */
1449         if (qede_check_fdir_support(eth_dev))
1450                 return -ENOTSUP;
1451
1452         qede_dealloc_fp_resc(eth_dev);
1453         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1454         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1455         if (qede_alloc_fp_resc(qdev))
1456                 return -ENOMEM;
1457
1458         /* If jumbo enabled adjust MTU */
1459         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1460                 eth_dev->data->mtu =
1461                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1462                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1463
1464         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1465                 eth_dev->data->scattered_rx = 1;
1466
1467         if (qede_start_vport(qdev, eth_dev->data->mtu))
1468                 return -1;
1469
1470         qdev->mtu = eth_dev->data->mtu;
1471
1472         /* Enable VLAN offloads by default */
1473         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1474                                              ETH_VLAN_FILTER_MASK |
1475                                              ETH_VLAN_EXTEND_MASK);
1476         if (ret)
1477                 return ret;
1478
1479         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1480                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1481
1482         return 0;
1483 }
1484
1485 /* Info about HW descriptor ring limitations */
1486 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1487         .nb_max = 0x8000, /* 32K */
1488         .nb_min = 128,
1489         .nb_align = 128 /* lowest common multiple */
1490 };
1491
1492 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1493         .nb_max = 0x8000, /* 32K */
1494         .nb_min = 256,
1495         .nb_align = 256,
1496         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1497         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1498 };
1499
1500 static void
1501 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1502                   struct rte_eth_dev_info *dev_info)
1503 {
1504         struct qede_dev *qdev = eth_dev->data->dev_private;
1505         struct ecore_dev *edev = &qdev->edev;
1506         struct qed_link_output link;
1507         uint32_t speed_cap = 0;
1508
1509         PMD_INIT_FUNC_TRACE(edev);
1510
1511         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1512         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1513         dev_info->rx_desc_lim = qede_rx_desc_lim;
1514         dev_info->tx_desc_lim = qede_tx_desc_lim;
1515
1516         if (IS_PF(edev))
1517                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1518                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1519         else
1520                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1521                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1522         dev_info->max_tx_queues = dev_info->max_rx_queues;
1523
1524         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1525         dev_info->max_vfs = 0;
1526         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1527         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1528         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1529         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1530                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1531                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1532                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1533                                      DEV_RX_OFFLOAD_TCP_LRO     |
1534                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1535                                      DEV_RX_OFFLOAD_SCATTER     |
1536                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1537                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1538                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1539         dev_info->rx_queue_offload_capa = 0;
1540
1541         /* TX offloads are on a per-packet basis, so it is applicable
1542          * to both at port and queue levels.
1543          */
1544         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1545                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1546                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1547                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1548                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1549                                      DEV_TX_OFFLOAD_QINQ_INSERT |
1550                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1551                                      DEV_TX_OFFLOAD_TCP_TSO     |
1552                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1553                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1554         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1555
1556         dev_info->default_txconf = (struct rte_eth_txconf) {
1557                 .offloads = DEV_TX_OFFLOAD_MULTI_SEGS,
1558         };
1559
1560         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1561                 /* Packets are always dropped if no descriptors are available */
1562                 .rx_drop_en = 1,
1563                 /* The below RX offloads are always enabled */
1564                 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP  |
1565                              DEV_RX_OFFLOAD_IPV4_CKSUM |
1566                              DEV_RX_OFFLOAD_TCP_CKSUM  |
1567                              DEV_RX_OFFLOAD_UDP_CKSUM),
1568         };
1569
1570         memset(&link, 0, sizeof(struct qed_link_output));
1571         qdev->ops->common->get_link(edev, &link);
1572         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1573                 speed_cap |= ETH_LINK_SPEED_1G;
1574         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1575                 speed_cap |= ETH_LINK_SPEED_10G;
1576         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1577                 speed_cap |= ETH_LINK_SPEED_25G;
1578         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1579                 speed_cap |= ETH_LINK_SPEED_40G;
1580         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1581                 speed_cap |= ETH_LINK_SPEED_50G;
1582         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1583                 speed_cap |= ETH_LINK_SPEED_100G;
1584         dev_info->speed_capa = speed_cap;
1585 }
1586
1587 /* return 0 means link status changed, -1 means not changed */
1588 int
1589 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1590 {
1591         struct qede_dev *qdev = eth_dev->data->dev_private;
1592         struct ecore_dev *edev = &qdev->edev;
1593         uint16_t link_duplex;
1594         struct qed_link_output link;
1595         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1596
1597         memset(&link, 0, sizeof(struct qed_link_output));
1598         qdev->ops->common->get_link(edev, &link);
1599
1600         /* Link Speed */
1601         curr->link_speed = link.speed;
1602
1603         /* Link Mode */
1604         switch (link.duplex) {
1605         case QEDE_DUPLEX_HALF:
1606                 link_duplex = ETH_LINK_HALF_DUPLEX;
1607                 break;
1608         case QEDE_DUPLEX_FULL:
1609                 link_duplex = ETH_LINK_FULL_DUPLEX;
1610                 break;
1611         case QEDE_DUPLEX_UNKNOWN:
1612         default:
1613                 link_duplex = -1;
1614         }
1615         curr->link_duplex = link_duplex;
1616
1617         /* Link Status */
1618         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1619
1620         /* AN */
1621         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1622                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1623
1624         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1625                 curr->link_speed, curr->link_duplex,
1626                 curr->link_autoneg, curr->link_status);
1627
1628         /* return 0 means link status changed, -1 means not changed */
1629         return ((curr->link_status == link.link_up) ? -1 : 0);
1630 }
1631
1632 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1633 {
1634 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1635         struct qede_dev *qdev = eth_dev->data->dev_private;
1636         struct ecore_dev *edev = &qdev->edev;
1637
1638         PMD_INIT_FUNC_TRACE(edev);
1639 #endif
1640
1641         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1642
1643         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1644                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1645
1646         qed_configure_filter_rx_mode(eth_dev, type);
1647 }
1648
1649 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1650 {
1651 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1652         struct qede_dev *qdev = eth_dev->data->dev_private;
1653         struct ecore_dev *edev = &qdev->edev;
1654
1655         PMD_INIT_FUNC_TRACE(edev);
1656 #endif
1657
1658         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1659                 qed_configure_filter_rx_mode(eth_dev,
1660                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1661         else
1662                 qed_configure_filter_rx_mode(eth_dev,
1663                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1664 }
1665
1666 static void qede_poll_sp_sb_cb(void *param)
1667 {
1668         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1669         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1670         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1671         int rc;
1672
1673         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1674         qede_interrupt_action(&edev->hwfns[1]);
1675
1676         rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
1677                                qede_poll_sp_sb_cb,
1678                                (void *)eth_dev);
1679         if (rc != 0) {
1680                 DP_ERR(edev, "Unable to start periodic"
1681                              " timer rc %d\n", rc);
1682                 assert(false && "Unable to start periodic timer");
1683         }
1684 }
1685
1686 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1687 {
1688         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1689         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1690         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1691
1692         PMD_INIT_FUNC_TRACE(edev);
1693
1694         /* dev_stop() shall cleanup fp resources in hw but without releasing
1695          * dma memories and sw structures so that dev_start() can be called
1696          * by the app without reconfiguration. However, in dev_close() we
1697          * can release all the resources and device can be brought up newly
1698          */
1699         if (eth_dev->data->dev_started)
1700                 qede_dev_stop(eth_dev);
1701
1702         qede_stop_vport(edev);
1703         qdev->vport_started = false;
1704         qede_fdir_dealloc_resc(eth_dev);
1705         qede_dealloc_fp_resc(eth_dev);
1706
1707         eth_dev->data->nb_rx_queues = 0;
1708         eth_dev->data->nb_tx_queues = 0;
1709
1710         /* Bring the link down */
1711         qede_dev_set_link_state(eth_dev, false);
1712         qdev->ops->common->slowpath_stop(edev);
1713         qdev->ops->common->remove(edev);
1714         rte_intr_disable(&pci_dev->intr_handle);
1715         rte_intr_callback_unregister(&pci_dev->intr_handle,
1716                                      qede_interrupt_handler, (void *)eth_dev);
1717         if (ECORE_IS_CMT(edev))
1718                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1719 }
1720
1721 static int
1722 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1723 {
1724         struct qede_dev *qdev = eth_dev->data->dev_private;
1725         struct ecore_dev *edev = &qdev->edev;
1726         struct ecore_eth_stats stats;
1727         unsigned int i = 0, j = 0, qid;
1728         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1729         struct qede_tx_queue *txq;
1730
1731         ecore_get_vport_stats(edev, &stats);
1732
1733         /* RX Stats */
1734         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1735             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1736
1737         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1738             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1739
1740         eth_stats->ierrors = stats.common.rx_crc_errors +
1741             stats.common.rx_align_errors +
1742             stats.common.rx_carrier_errors +
1743             stats.common.rx_oversize_packets +
1744             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1745
1746         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1747
1748         eth_stats->imissed = stats.common.mftag_filter_discards +
1749             stats.common.mac_filter_discards +
1750             stats.common.no_buff_discards +
1751             stats.common.brb_truncates + stats.common.brb_discards;
1752
1753         /* TX stats */
1754         eth_stats->opackets = stats.common.tx_ucast_pkts +
1755             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1756
1757         eth_stats->obytes = stats.common.tx_ucast_bytes +
1758             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1759
1760         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1761
1762         /* Queue stats */
1763         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1764                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1765         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1766                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1767         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1768             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1769                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1770                        "Not all the queue stats will be displayed. Set"
1771                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1772                        " appropriately and retry.\n");
1773
1774         for_each_rss(qid) {
1775                 eth_stats->q_ipackets[i] =
1776                         *(uint64_t *)(
1777                                 ((char *)(qdev->fp_array[qid].rxq)) +
1778                                 offsetof(struct qede_rx_queue,
1779                                 rcv_pkts));
1780                 eth_stats->q_errors[i] =
1781                         *(uint64_t *)(
1782                                 ((char *)(qdev->fp_array[qid].rxq)) +
1783                                 offsetof(struct qede_rx_queue,
1784                                 rx_hw_errors)) +
1785                         *(uint64_t *)(
1786                                 ((char *)(qdev->fp_array[qid].rxq)) +
1787                                 offsetof(struct qede_rx_queue,
1788                                 rx_alloc_errors));
1789                 i++;
1790                 if (i == rxq_stat_cntrs)
1791                         break;
1792         }
1793
1794         for_each_tss(qid) {
1795                 txq = qdev->fp_array[qid].txq;
1796                 eth_stats->q_opackets[j] =
1797                         *((uint64_t *)(uintptr_t)
1798                                 (((uint64_t)(uintptr_t)(txq)) +
1799                                  offsetof(struct qede_tx_queue,
1800                                           xmit_pkts)));
1801                 j++;
1802                 if (j == txq_stat_cntrs)
1803                         break;
1804         }
1805
1806         return 0;
1807 }
1808
1809 static unsigned
1810 qede_get_xstats_count(struct qede_dev *qdev) {
1811         if (ECORE_IS_BB(&qdev->edev))
1812                 return RTE_DIM(qede_xstats_strings) +
1813                        RTE_DIM(qede_bb_xstats_strings) +
1814                        (RTE_DIM(qede_rxq_xstats_strings) *
1815                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1816                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1817         else
1818                 return RTE_DIM(qede_xstats_strings) +
1819                        RTE_DIM(qede_ah_xstats_strings) +
1820                        (RTE_DIM(qede_rxq_xstats_strings) *
1821                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1822                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1823 }
1824
1825 static int
1826 qede_get_xstats_names(struct rte_eth_dev *dev,
1827                       struct rte_eth_xstat_name *xstats_names,
1828                       __rte_unused unsigned int limit)
1829 {
1830         struct qede_dev *qdev = dev->data->dev_private;
1831         struct ecore_dev *edev = &qdev->edev;
1832         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1833         unsigned int i, qid, stat_idx = 0;
1834         unsigned int rxq_stat_cntrs;
1835
1836         if (xstats_names != NULL) {
1837                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1838                         snprintf(xstats_names[stat_idx].name,
1839                                 sizeof(xstats_names[stat_idx].name),
1840                                 "%s",
1841                                 qede_xstats_strings[i].name);
1842                         stat_idx++;
1843                 }
1844
1845                 if (ECORE_IS_BB(edev)) {
1846                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1847                                 snprintf(xstats_names[stat_idx].name,
1848                                         sizeof(xstats_names[stat_idx].name),
1849                                         "%s",
1850                                         qede_bb_xstats_strings[i].name);
1851                                 stat_idx++;
1852                         }
1853                 } else {
1854                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1855                                 snprintf(xstats_names[stat_idx].name,
1856                                         sizeof(xstats_names[stat_idx].name),
1857                                         "%s",
1858                                         qede_ah_xstats_strings[i].name);
1859                                 stat_idx++;
1860                         }
1861                 }
1862
1863                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1864                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1865                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1866                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1867                                 snprintf(xstats_names[stat_idx].name,
1868                                         sizeof(xstats_names[stat_idx].name),
1869                                         "%.4s%d%s",
1870                                         qede_rxq_xstats_strings[i].name, qid,
1871                                         qede_rxq_xstats_strings[i].name + 4);
1872                                 stat_idx++;
1873                         }
1874                 }
1875         }
1876
1877         return stat_cnt;
1878 }
1879
1880 static int
1881 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1882                 unsigned int n)
1883 {
1884         struct qede_dev *qdev = dev->data->dev_private;
1885         struct ecore_dev *edev = &qdev->edev;
1886         struct ecore_eth_stats stats;
1887         const unsigned int num = qede_get_xstats_count(qdev);
1888         unsigned int i, qid, stat_idx = 0;
1889         unsigned int rxq_stat_cntrs;
1890
1891         if (n < num)
1892                 return num;
1893
1894         ecore_get_vport_stats(edev, &stats);
1895
1896         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1897                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1898                                              qede_xstats_strings[i].offset);
1899                 xstats[stat_idx].id = stat_idx;
1900                 stat_idx++;
1901         }
1902
1903         if (ECORE_IS_BB(edev)) {
1904                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1905                         xstats[stat_idx].value =
1906                                         *(uint64_t *)(((char *)&stats) +
1907                                         qede_bb_xstats_strings[i].offset);
1908                         xstats[stat_idx].id = stat_idx;
1909                         stat_idx++;
1910                 }
1911         } else {
1912                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1913                         xstats[stat_idx].value =
1914                                         *(uint64_t *)(((char *)&stats) +
1915                                         qede_ah_xstats_strings[i].offset);
1916                         xstats[stat_idx].id = stat_idx;
1917                         stat_idx++;
1918                 }
1919         }
1920
1921         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1922                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1923         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1924                 for_each_rss(qid) {
1925                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1926                                 xstats[stat_idx].value = *(uint64_t *)(
1927                                         ((char *)(qdev->fp_array[qid].rxq)) +
1928                                          qede_rxq_xstats_strings[i].offset);
1929                                 xstats[stat_idx].id = stat_idx;
1930                                 stat_idx++;
1931                         }
1932                 }
1933         }
1934
1935         return stat_idx;
1936 }
1937
1938 static void
1939 qede_reset_xstats(struct rte_eth_dev *dev)
1940 {
1941         struct qede_dev *qdev = dev->data->dev_private;
1942         struct ecore_dev *edev = &qdev->edev;
1943
1944         ecore_reset_vport_stats(edev);
1945         qede_reset_queue_stats(qdev, true);
1946 }
1947
1948 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1949 {
1950         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1951         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1952         struct qed_link_params link_params;
1953         int rc;
1954
1955         DP_INFO(edev, "setting link state %d\n", link_up);
1956         memset(&link_params, 0, sizeof(link_params));
1957         link_params.link_up = link_up;
1958         rc = qdev->ops->common->set_link(edev, &link_params);
1959         if (rc != ECORE_SUCCESS)
1960                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1961
1962         return rc;
1963 }
1964
1965 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1966 {
1967         return qede_dev_set_link_state(eth_dev, true);
1968 }
1969
1970 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1971 {
1972         return qede_dev_set_link_state(eth_dev, false);
1973 }
1974
1975 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1976 {
1977         struct qede_dev *qdev = eth_dev->data->dev_private;
1978         struct ecore_dev *edev = &qdev->edev;
1979
1980         ecore_reset_vport_stats(edev);
1981         qede_reset_queue_stats(qdev, false);
1982 }
1983
1984 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1985 {
1986         enum qed_filter_rx_mode_type type =
1987             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1988
1989         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1990                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1991
1992         qed_configure_filter_rx_mode(eth_dev, type);
1993 }
1994
1995 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1996 {
1997         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1998                 qed_configure_filter_rx_mode(eth_dev,
1999                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2000         else
2001                 qed_configure_filter_rx_mode(eth_dev,
2002                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2003 }
2004
2005 static int
2006 qede_set_mc_addr_list(struct rte_eth_dev *eth_dev, struct ether_addr *mc_addrs,
2007                       uint32_t mc_addrs_num)
2008 {
2009         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2010         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2011         uint8_t i;
2012
2013         if (mc_addrs_num > ECORE_MAX_MC_ADDRS) {
2014                 DP_ERR(edev, "Reached max multicast filters limit,"
2015                              "Please enable multicast promisc mode\n");
2016                 return -ENOSPC;
2017         }
2018
2019         for (i = 0; i < mc_addrs_num; i++) {
2020                 if (!is_multicast_ether_addr(&mc_addrs[i])) {
2021                         DP_ERR(edev, "Not a valid multicast MAC\n");
2022                         return -EINVAL;
2023                 }
2024         }
2025
2026         /* Flush all existing entries */
2027         if (qede_del_mcast_filters(eth_dev))
2028                 return -1;
2029
2030         /* Set new mcast list */
2031         return qede_add_mcast_filters(eth_dev, mc_addrs, mc_addrs_num);
2032 }
2033
2034 /* Update MTU via vport-update without doing port restart.
2035  * The vport must be deactivated before calling this API.
2036  */
2037 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
2038 {
2039         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2040         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2041         struct ecore_hwfn *p_hwfn;
2042         int rc;
2043         int i;
2044
2045         if (IS_PF(edev)) {
2046                 struct ecore_sp_vport_update_params params;
2047
2048                 memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
2049                 params.vport_id = 0;
2050                 params.mtu = mtu;
2051                 params.vport_id = 0;
2052                 for_each_hwfn(edev, i) {
2053                         p_hwfn = &edev->hwfns[i];
2054                         params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2055                         rc = ecore_sp_vport_update(p_hwfn, &params,
2056                                         ECORE_SPQ_MODE_EBLOCK, NULL);
2057                         if (rc != ECORE_SUCCESS)
2058                                 goto err;
2059                 }
2060         } else {
2061                 for_each_hwfn(edev, i) {
2062                         p_hwfn = &edev->hwfns[i];
2063                         rc = ecore_vf_pf_update_mtu(p_hwfn, mtu);
2064                         if (rc == ECORE_INVAL) {
2065                                 DP_INFO(edev, "VF MTU Update TLV not supported\n");
2066                                 /* Recreate vport */
2067                                 rc = qede_start_vport(qdev, mtu);
2068                                 if (rc != ECORE_SUCCESS)
2069                                         goto err;
2070
2071                                 /* Restore config lost due to vport stop */
2072                                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
2073
2074                                 if (eth_dev->data->promiscuous)
2075                                         qede_promiscuous_enable(eth_dev);
2076                                 else
2077                                         qede_promiscuous_disable(eth_dev);
2078
2079                                 if (eth_dev->data->all_multicast)
2080                                         qede_allmulticast_enable(eth_dev);
2081                                 else
2082                                         qede_allmulticast_disable(eth_dev);
2083
2084                                 qede_vlan_offload_set(eth_dev,
2085                                                       qdev->vlan_offload_mask);
2086                         } else if (rc != ECORE_SUCCESS) {
2087                                 goto err;
2088                         }
2089                 }
2090         }
2091         DP_INFO(edev, "%s MTU updated to %u\n", IS_PF(edev) ? "PF" : "VF", mtu);
2092
2093         return 0;
2094
2095 err:
2096         DP_ERR(edev, "Failed to update MTU\n");
2097         return -1;
2098 }
2099
2100 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2101                               struct rte_eth_fc_conf *fc_conf)
2102 {
2103         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2104         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2105         struct qed_link_output current_link;
2106         struct qed_link_params params;
2107
2108         memset(&current_link, 0, sizeof(current_link));
2109         qdev->ops->common->get_link(edev, &current_link);
2110
2111         memset(&params, 0, sizeof(params));
2112         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2113         if (fc_conf->autoneg) {
2114                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2115                         DP_ERR(edev, "Autoneg not supported\n");
2116                         return -EINVAL;
2117                 }
2118                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2119         }
2120
2121         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2122         if (fc_conf->mode == RTE_FC_FULL)
2123                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2124                                         QED_LINK_PAUSE_RX_ENABLE);
2125         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2126                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2127         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2128                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2129
2130         params.link_up = true;
2131         (void)qdev->ops->common->set_link(edev, &params);
2132
2133         return 0;
2134 }
2135
2136 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2137                               struct rte_eth_fc_conf *fc_conf)
2138 {
2139         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2140         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2141         struct qed_link_output current_link;
2142
2143         memset(&current_link, 0, sizeof(current_link));
2144         qdev->ops->common->get_link(edev, &current_link);
2145
2146         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2147                 fc_conf->autoneg = true;
2148
2149         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2150                                          QED_LINK_PAUSE_TX_ENABLE))
2151                 fc_conf->mode = RTE_FC_FULL;
2152         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2153                 fc_conf->mode = RTE_FC_RX_PAUSE;
2154         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2155                 fc_conf->mode = RTE_FC_TX_PAUSE;
2156         else
2157                 fc_conf->mode = RTE_FC_NONE;
2158
2159         return 0;
2160 }
2161
2162 static const uint32_t *
2163 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2164 {
2165         static const uint32_t ptypes[] = {
2166                 RTE_PTYPE_L2_ETHER,
2167                 RTE_PTYPE_L2_ETHER_VLAN,
2168                 RTE_PTYPE_L3_IPV4,
2169                 RTE_PTYPE_L3_IPV6,
2170                 RTE_PTYPE_L4_TCP,
2171                 RTE_PTYPE_L4_UDP,
2172                 RTE_PTYPE_TUNNEL_VXLAN,
2173                 RTE_PTYPE_L4_FRAG,
2174                 RTE_PTYPE_TUNNEL_GENEVE,
2175                 RTE_PTYPE_TUNNEL_GRE,
2176                 /* Inner */
2177                 RTE_PTYPE_INNER_L2_ETHER,
2178                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2179                 RTE_PTYPE_INNER_L3_IPV4,
2180                 RTE_PTYPE_INNER_L3_IPV6,
2181                 RTE_PTYPE_INNER_L4_TCP,
2182                 RTE_PTYPE_INNER_L4_UDP,
2183                 RTE_PTYPE_INNER_L4_FRAG,
2184                 RTE_PTYPE_UNKNOWN
2185         };
2186
2187         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2188                 return ptypes;
2189
2190         return NULL;
2191 }
2192
2193 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2194 {
2195         *rss_caps = 0;
2196         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2197         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2198         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2199         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2200         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2201         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2202         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2203         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2204 }
2205
2206 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2207                          struct rte_eth_rss_conf *rss_conf)
2208 {
2209         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2210         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2211         struct ecore_sp_vport_update_params vport_update_params;
2212         struct ecore_rss_params rss_params;
2213         struct ecore_hwfn *p_hwfn;
2214         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2215         uint64_t hf = rss_conf->rss_hf;
2216         uint8_t len = rss_conf->rss_key_len;
2217         uint8_t idx;
2218         uint8_t i;
2219         int rc;
2220
2221         memset(&vport_update_params, 0, sizeof(vport_update_params));
2222         memset(&rss_params, 0, sizeof(rss_params));
2223
2224         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2225                 (unsigned long)hf, len, key);
2226
2227         if (hf != 0) {
2228                 /* Enabling RSS */
2229                 DP_INFO(edev, "Enabling rss\n");
2230
2231                 /* RSS caps */
2232                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2233                 rss_params.update_rss_capabilities = 1;
2234
2235                 /* RSS hash key */
2236                 if (key) {
2237                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2238                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2239                                 return -EINVAL;
2240                         }
2241                         DP_INFO(edev, "Applying user supplied hash key\n");
2242                         rss_params.update_rss_key = 1;
2243                         memcpy(&rss_params.rss_key, key, len);
2244                 }
2245                 rss_params.rss_enable = 1;
2246         }
2247
2248         rss_params.update_rss_config = 1;
2249         /* tbl_size has to be set with capabilities */
2250         rss_params.rss_table_size_log = 7;
2251         vport_update_params.vport_id = 0;
2252         /* pass the L2 handles instead of qids */
2253         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2254                 idx = qdev->rss_ind_table[i];
2255                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2256         }
2257         vport_update_params.rss_params = &rss_params;
2258
2259         for_each_hwfn(edev, i) {
2260                 p_hwfn = &edev->hwfns[i];
2261                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2262                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2263                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2264                 if (rc) {
2265                         DP_ERR(edev, "vport-update for RSS failed\n");
2266                         return rc;
2267                 }
2268         }
2269         qdev->rss_enable = rss_params.rss_enable;
2270
2271         /* Update local structure for hash query */
2272         qdev->rss_conf.rss_hf = hf;
2273         qdev->rss_conf.rss_key_len = len;
2274         if (qdev->rss_enable) {
2275                 if  (qdev->rss_conf.rss_key == NULL) {
2276                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2277                         if (qdev->rss_conf.rss_key == NULL) {
2278                                 DP_ERR(edev, "No memory to store RSS key\n");
2279                                 return -ENOMEM;
2280                         }
2281                 }
2282                 if (key && len) {
2283                         DP_INFO(edev, "Storing RSS key\n");
2284                         memcpy(qdev->rss_conf.rss_key, key, len);
2285                 }
2286         } else if (!qdev->rss_enable && len == 0) {
2287                 if (qdev->rss_conf.rss_key) {
2288                         free(qdev->rss_conf.rss_key);
2289                         qdev->rss_conf.rss_key = NULL;
2290                         DP_INFO(edev, "Free RSS key\n");
2291                 }
2292         }
2293
2294         return 0;
2295 }
2296
2297 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2298                            struct rte_eth_rss_conf *rss_conf)
2299 {
2300         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2301
2302         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2303         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2304
2305         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2306                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2307                        rss_conf->rss_key_len);
2308         return 0;
2309 }
2310
2311 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2312                                     struct ecore_rss_params *rss)
2313 {
2314         int i, fn;
2315         bool rss_mode = 1; /* enable */
2316         struct ecore_queue_cid *cid;
2317         struct ecore_rss_params *t_rss;
2318
2319         /* In regular scenario, we'd simply need to take input handlers.
2320          * But in CMT, we'd have to split the handlers according to the
2321          * engine they were configured on. We'd then have to understand
2322          * whether RSS is really required, since 2-queues on CMT doesn't
2323          * require RSS.
2324          */
2325
2326         /* CMT should be round-robin */
2327         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2328                 cid = rss->rss_ind_table[i];
2329
2330                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2331                         t_rss = &rss[0];
2332                 else
2333                         t_rss = &rss[1];
2334
2335                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2336         }
2337
2338         t_rss = &rss[1];
2339         t_rss->update_rss_ind_table = 1;
2340         t_rss->rss_table_size_log = 7;
2341         t_rss->update_rss_config = 1;
2342
2343         /* Make sure RSS is actually required */
2344         for_each_hwfn(edev, fn) {
2345                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2346                      i++) {
2347                         if (rss[fn].rss_ind_table[i] !=
2348                             rss[fn].rss_ind_table[0])
2349                                 break;
2350                 }
2351
2352                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2353                         DP_INFO(edev,
2354                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2355                         rss_mode = 0;
2356                         goto out;
2357                 }
2358         }
2359
2360 out:
2361         t_rss->rss_enable = rss_mode;
2362
2363         return rss_mode;
2364 }
2365
2366 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2367                          struct rte_eth_rss_reta_entry64 *reta_conf,
2368                          uint16_t reta_size)
2369 {
2370         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2371         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2372         struct ecore_sp_vport_update_params vport_update_params;
2373         struct ecore_rss_params *params;
2374         struct ecore_hwfn *p_hwfn;
2375         uint16_t i, idx, shift;
2376         uint8_t entry;
2377         int rc = 0;
2378
2379         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2380                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2381                        reta_size);
2382                 return -EINVAL;
2383         }
2384
2385         memset(&vport_update_params, 0, sizeof(vport_update_params));
2386         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2387                              RTE_CACHE_LINE_SIZE);
2388         if (params == NULL) {
2389                 DP_ERR(edev, "failed to allocate memory\n");
2390                 return -ENOMEM;
2391         }
2392
2393         for (i = 0; i < reta_size; i++) {
2394                 idx = i / RTE_RETA_GROUP_SIZE;
2395                 shift = i % RTE_RETA_GROUP_SIZE;
2396                 if (reta_conf[idx].mask & (1ULL << shift)) {
2397                         entry = reta_conf[idx].reta[shift];
2398                         /* Pass rxq handles to ecore */
2399                         params->rss_ind_table[i] =
2400                                         qdev->fp_array[entry].rxq->handle;
2401                         /* Update the local copy for RETA query command */
2402                         qdev->rss_ind_table[i] = entry;
2403                 }
2404         }
2405
2406         params->update_rss_ind_table = 1;
2407         params->rss_table_size_log = 7;
2408         params->update_rss_config = 1;
2409
2410         /* Fix up RETA for CMT mode device */
2411         if (ECORE_IS_CMT(edev))
2412                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2413                                                             params);
2414         vport_update_params.vport_id = 0;
2415         /* Use the current value of rss_enable */
2416         params->rss_enable = qdev->rss_enable;
2417         vport_update_params.rss_params = params;
2418
2419         for_each_hwfn(edev, i) {
2420                 p_hwfn = &edev->hwfns[i];
2421                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2422                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2423                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2424                 if (rc) {
2425                         DP_ERR(edev, "vport-update for RSS failed\n");
2426                         goto out;
2427                 }
2428         }
2429
2430 out:
2431         rte_free(params);
2432         return rc;
2433 }
2434
2435 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2436                                struct rte_eth_rss_reta_entry64 *reta_conf,
2437                                uint16_t reta_size)
2438 {
2439         struct qede_dev *qdev = eth_dev->data->dev_private;
2440         struct ecore_dev *edev = &qdev->edev;
2441         uint16_t i, idx, shift;
2442         uint8_t entry;
2443
2444         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2445                 DP_ERR(edev, "reta_size %d is not supported\n",
2446                        reta_size);
2447                 return -EINVAL;
2448         }
2449
2450         for (i = 0; i < reta_size; i++) {
2451                 idx = i / RTE_RETA_GROUP_SIZE;
2452                 shift = i % RTE_RETA_GROUP_SIZE;
2453                 if (reta_conf[idx].mask & (1ULL << shift)) {
2454                         entry = qdev->rss_ind_table[i];
2455                         reta_conf[idx].reta[shift] = entry;
2456                 }
2457         }
2458
2459         return 0;
2460 }
2461
2462
2463
2464 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2465 {
2466         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2467         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2468         struct rte_eth_dev_info dev_info = {0};
2469         struct qede_fastpath *fp;
2470         uint32_t max_rx_pkt_len;
2471         uint32_t frame_size;
2472         uint16_t rx_buf_size;
2473         uint16_t bufsz;
2474         bool restart = false;
2475         int i;
2476
2477         PMD_INIT_FUNC_TRACE(edev);
2478         qede_dev_info_get(dev, &dev_info);
2479         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2480         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2481         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2482                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2483                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2484                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2485                 return -EINVAL;
2486         }
2487         if (!dev->data->scattered_rx &&
2488             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2489                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2490                         dev->data->min_rx_buf_size);
2491                 return -EINVAL;
2492         }
2493         /* Temporarily replace I/O functions with dummy ones. It cannot
2494          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2495          */
2496         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2497         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2498         if (dev->data->dev_started) {
2499                 dev->data->dev_started = 0;
2500                 qede_dev_stop(dev);
2501                 restart = true;
2502         } else {
2503                 if (IS_PF(edev))
2504                         qede_mac_addr_remove(dev, 0);
2505         }
2506         rte_delay_ms(1000);
2507         qdev->mtu = mtu;
2508
2509         /* Fix up RX buf size for all queues of the port */
2510         for_each_rss(i) {
2511                 fp = &qdev->fp_array[i];
2512                 if (fp->rxq != NULL) {
2513                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2514                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2515                         if (dev->data->scattered_rx)
2516                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2517                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2518                         else
2519                                 rx_buf_size = frame_size;
2520                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2521                         fp->rxq->rx_buf_size = rx_buf_size;
2522                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2523                 }
2524         }
2525         if (max_rx_pkt_len > ETHER_MAX_LEN)
2526                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2527         else
2528                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2529
2530         if (!dev->data->dev_started && restart) {
2531                 qede_dev_start(dev);
2532                 dev->data->dev_started = 1;
2533         }
2534
2535         /* update max frame size */
2536         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2537         /* Reassign back */
2538         dev->rx_pkt_burst = qede_recv_pkts;
2539         dev->tx_pkt_burst = qede_xmit_pkts;
2540
2541         return 0;
2542 }
2543
2544 static int
2545 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2546                       struct rte_eth_udp_tunnel *tunnel_udp)
2547 {
2548         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2549         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2550         struct ecore_tunnel_info tunn; /* @DPDK */
2551         uint16_t udp_port;
2552         int rc;
2553
2554         PMD_INIT_FUNC_TRACE(edev);
2555
2556         memset(&tunn, 0, sizeof(tunn));
2557
2558         switch (tunnel_udp->prot_type) {
2559         case RTE_TUNNEL_TYPE_VXLAN:
2560                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2561                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2562                                 tunnel_udp->udp_port);
2563                         return ECORE_INVAL;
2564                 }
2565                 udp_port = 0;
2566
2567                 tunn.vxlan_port.b_update_port = true;
2568                 tunn.vxlan_port.port = udp_port;
2569
2570                 rc = qede_tunnel_update(qdev, &tunn);
2571                 if (rc != ECORE_SUCCESS) {
2572                         DP_ERR(edev, "Unable to config UDP port %u\n",
2573                                tunn.vxlan_port.port);
2574                         return rc;
2575                 }
2576
2577                 qdev->vxlan.udp_port = udp_port;
2578                 /* If the request is to delete UDP port and if the number of
2579                  * VXLAN filters have reached 0 then VxLAN offload can be be
2580                  * disabled.
2581                  */
2582                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2583                         return qede_vxlan_enable(eth_dev,
2584                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2585
2586                 break;
2587         case RTE_TUNNEL_TYPE_GENEVE:
2588                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2589                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2590                                 tunnel_udp->udp_port);
2591                         return ECORE_INVAL;
2592                 }
2593
2594                 udp_port = 0;
2595
2596                 tunn.geneve_port.b_update_port = true;
2597                 tunn.geneve_port.port = udp_port;
2598
2599                 rc = qede_tunnel_update(qdev, &tunn);
2600                 if (rc != ECORE_SUCCESS) {
2601                         DP_ERR(edev, "Unable to config UDP port %u\n",
2602                                tunn.vxlan_port.port);
2603                         return rc;
2604                 }
2605
2606                 qdev->vxlan.udp_port = udp_port;
2607                 /* If the request is to delete UDP port and if the number of
2608                  * GENEVE filters have reached 0 then GENEVE offload can be be
2609                  * disabled.
2610                  */
2611                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2612                         return qede_geneve_enable(eth_dev,
2613                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2614
2615                 break;
2616
2617         default:
2618                 return ECORE_INVAL;
2619         }
2620
2621         return 0;
2622
2623 }
2624 static int
2625 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2626                       struct rte_eth_udp_tunnel *tunnel_udp)
2627 {
2628         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2629         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2630         struct ecore_tunnel_info tunn; /* @DPDK */
2631         uint16_t udp_port;
2632         int rc;
2633
2634         PMD_INIT_FUNC_TRACE(edev);
2635
2636         memset(&tunn, 0, sizeof(tunn));
2637
2638         switch (tunnel_udp->prot_type) {
2639         case RTE_TUNNEL_TYPE_VXLAN:
2640                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2641                         DP_INFO(edev,
2642                                 "UDP port %u for VXLAN was already configured\n",
2643                                 tunnel_udp->udp_port);
2644                         return ECORE_SUCCESS;
2645                 }
2646
2647                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2648                  * it was not enabled while adding VXLAN filter before UDP port
2649                  * update.
2650                  */
2651                 if (!qdev->vxlan.enable) {
2652                         rc = qede_vxlan_enable(eth_dev,
2653                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2654                         if (rc != ECORE_SUCCESS) {
2655                                 DP_ERR(edev, "Failed to enable VXLAN "
2656                                         "prior to updating UDP port\n");
2657                                 return rc;
2658                         }
2659                 }
2660                 udp_port = tunnel_udp->udp_port;
2661
2662                 tunn.vxlan_port.b_update_port = true;
2663                 tunn.vxlan_port.port = udp_port;
2664
2665                 rc = qede_tunnel_update(qdev, &tunn);
2666                 if (rc != ECORE_SUCCESS) {
2667                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2668                                udp_port);
2669                         return rc;
2670                 }
2671
2672                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2673
2674                 qdev->vxlan.udp_port = udp_port;
2675                 break;
2676         case RTE_TUNNEL_TYPE_GENEVE:
2677                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2678                         DP_INFO(edev,
2679                                 "UDP port %u for GENEVE was already configured\n",
2680                                 tunnel_udp->udp_port);
2681                         return ECORE_SUCCESS;
2682                 }
2683
2684                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2685                  * it was not enabled while adding GENEVE filter before UDP port
2686                  * update.
2687                  */
2688                 if (!qdev->geneve.enable) {
2689                         rc = qede_geneve_enable(eth_dev,
2690                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2691                         if (rc != ECORE_SUCCESS) {
2692                                 DP_ERR(edev, "Failed to enable GENEVE "
2693                                         "prior to updating UDP port\n");
2694                                 return rc;
2695                         }
2696                 }
2697                 udp_port = tunnel_udp->udp_port;
2698
2699                 tunn.geneve_port.b_update_port = true;
2700                 tunn.geneve_port.port = udp_port;
2701
2702                 rc = qede_tunnel_update(qdev, &tunn);
2703                 if (rc != ECORE_SUCCESS) {
2704                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2705                                udp_port);
2706                         return rc;
2707                 }
2708
2709                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2710
2711                 qdev->geneve.udp_port = udp_port;
2712                 break;
2713         default:
2714                 return ECORE_INVAL;
2715         }
2716
2717         return 0;
2718 }
2719
2720 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2721                                        uint32_t *clss, char *str)
2722 {
2723         uint16_t j;
2724         *clss = MAX_ECORE_TUNN_CLSS;
2725
2726         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2727                 if (filter == qede_tunn_types[j].rte_filter_type) {
2728                         *type = qede_tunn_types[j].qede_type;
2729                         *clss = qede_tunn_types[j].qede_tunn_clss;
2730                         strcpy(str, qede_tunn_types[j].string);
2731                         return;
2732                 }
2733         }
2734 }
2735
2736 static int
2737 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2738                               const struct rte_eth_tunnel_filter_conf *conf,
2739                               uint32_t type)
2740 {
2741         /* Init commmon ucast params first */
2742         qede_set_ucast_cmn_params(ucast);
2743
2744         /* Copy out the required fields based on classification type */
2745         ucast->type = type;
2746
2747         switch (type) {
2748         case ECORE_FILTER_VNI:
2749                 ucast->vni = conf->tenant_id;
2750         break;
2751         case ECORE_FILTER_INNER_VLAN:
2752                 ucast->vlan = conf->inner_vlan;
2753         break;
2754         case ECORE_FILTER_MAC:
2755                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2756                        ETHER_ADDR_LEN);
2757         break;
2758         case ECORE_FILTER_INNER_MAC:
2759                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2760                        ETHER_ADDR_LEN);
2761         break;
2762         case ECORE_FILTER_MAC_VNI_PAIR:
2763                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2764                         ETHER_ADDR_LEN);
2765                 ucast->vni = conf->tenant_id;
2766         break;
2767         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2768                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2769                         ETHER_ADDR_LEN);
2770                 ucast->vni = conf->tenant_id;
2771         break;
2772         case ECORE_FILTER_INNER_PAIR:
2773                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2774                         ETHER_ADDR_LEN);
2775                 ucast->vlan = conf->inner_vlan;
2776         break;
2777         default:
2778                 return -EINVAL;
2779         }
2780
2781         return ECORE_SUCCESS;
2782 }
2783
2784 static int
2785 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2786                          const struct rte_eth_tunnel_filter_conf *conf,
2787                          __attribute__((unused)) enum rte_filter_op filter_op,
2788                          enum ecore_tunn_clss *clss,
2789                          bool add)
2790 {
2791         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2792         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2793         struct ecore_filter_ucast ucast = {0};
2794         enum ecore_filter_ucast_type type;
2795         uint16_t filter_type = 0;
2796         char str[80];
2797         int rc;
2798
2799         filter_type = conf->filter_type;
2800         /* Determine if the given filter classification is supported */
2801         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2802         if (*clss == MAX_ECORE_TUNN_CLSS) {
2803                 DP_ERR(edev, "Unsupported filter type\n");
2804                 return -EINVAL;
2805         }
2806         /* Init tunnel ucast params */
2807         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2808         if (rc != ECORE_SUCCESS) {
2809                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2810                 conf->filter_type);
2811                 return rc;
2812         }
2813         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2814                 str, filter_op, ucast.type);
2815
2816         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2817
2818         /* Skip MAC/VLAN if filter is based on VNI */
2819         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2820                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2821                 if ((rc == 0) && add) {
2822                         /* Enable accept anyvlan */
2823                         qede_config_accept_any_vlan(qdev, true);
2824                 }
2825         } else {
2826                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2827                 if (rc == 0)
2828                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2829                                             ECORE_SPQ_MODE_CB, NULL);
2830         }
2831
2832         return rc;
2833 }
2834
2835 static int
2836 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2837                         enum rte_filter_op filter_op,
2838                         const struct rte_eth_tunnel_filter_conf *conf)
2839 {
2840         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2841         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2842         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2843         bool add;
2844         int rc;
2845
2846         PMD_INIT_FUNC_TRACE(edev);
2847
2848         switch (filter_op) {
2849         case RTE_ETH_FILTER_ADD:
2850                 add = true;
2851                 break;
2852         case RTE_ETH_FILTER_DELETE:
2853                 add = false;
2854                 break;
2855         default:
2856                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2857                 return -EINVAL;
2858         }
2859
2860         if (IS_VF(edev))
2861                 return qede_tunn_enable(eth_dev,
2862                                         ECORE_TUNN_CLSS_MAC_VLAN,
2863                                         conf->tunnel_type, add);
2864
2865         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2866         if (rc != ECORE_SUCCESS)
2867                 return rc;
2868
2869         if (add) {
2870                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2871                         qdev->vxlan.num_filters++;
2872                         qdev->vxlan.filter_type = conf->filter_type;
2873                 } else { /* GENEVE */
2874                         qdev->geneve.num_filters++;
2875                         qdev->geneve.filter_type = conf->filter_type;
2876                 }
2877
2878                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2879                     !qdev->ipgre.enable)
2880                         return qede_tunn_enable(eth_dev, clss,
2881                                                 conf->tunnel_type,
2882                                                 true);
2883         } else {
2884                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2885                         qdev->vxlan.num_filters--;
2886                 else /*GENEVE*/
2887                         qdev->geneve.num_filters--;
2888
2889                 /* Disable VXLAN if VXLAN filters become 0 */
2890                 if ((qdev->vxlan.num_filters == 0) ||
2891                     (qdev->geneve.num_filters == 0))
2892                         return qede_tunn_enable(eth_dev, clss,
2893                                                 conf->tunnel_type,
2894                                                 false);
2895         }
2896
2897         return 0;
2898 }
2899
2900 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2901                          enum rte_filter_type filter_type,
2902                          enum rte_filter_op filter_op,
2903                          void *arg)
2904 {
2905         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2906         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2907         struct rte_eth_tunnel_filter_conf *filter_conf =
2908                         (struct rte_eth_tunnel_filter_conf *)arg;
2909
2910         switch (filter_type) {
2911         case RTE_ETH_FILTER_TUNNEL:
2912                 switch (filter_conf->tunnel_type) {
2913                 case RTE_TUNNEL_TYPE_VXLAN:
2914                 case RTE_TUNNEL_TYPE_GENEVE:
2915                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2916                         DP_INFO(edev,
2917                                 "Packet steering to the specified Rx queue"
2918                                 " is not supported with UDP tunneling");
2919                         return(qede_tunn_filter_config(eth_dev, filter_op,
2920                                                       filter_conf));
2921                 case RTE_TUNNEL_TYPE_TEREDO:
2922                 case RTE_TUNNEL_TYPE_NVGRE:
2923                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2924                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2925                                 filter_conf->tunnel_type);
2926                         return -EINVAL;
2927                 case RTE_TUNNEL_TYPE_NONE:
2928                 default:
2929                         return 0;
2930                 }
2931                 break;
2932         case RTE_ETH_FILTER_FDIR:
2933                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2934         case RTE_ETH_FILTER_NTUPLE:
2935                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2936         case RTE_ETH_FILTER_MACVLAN:
2937         case RTE_ETH_FILTER_ETHERTYPE:
2938         case RTE_ETH_FILTER_FLEXIBLE:
2939         case RTE_ETH_FILTER_SYN:
2940         case RTE_ETH_FILTER_HASH:
2941         case RTE_ETH_FILTER_L2_TUNNEL:
2942         case RTE_ETH_FILTER_MAX:
2943         default:
2944                 DP_ERR(edev, "Unsupported filter type %d\n",
2945                         filter_type);
2946                 return -EINVAL;
2947         }
2948
2949         return 0;
2950 }
2951
2952 static const struct eth_dev_ops qede_eth_dev_ops = {
2953         .dev_configure = qede_dev_configure,
2954         .dev_infos_get = qede_dev_info_get,
2955         .rx_queue_setup = qede_rx_queue_setup,
2956         .rx_queue_release = qede_rx_queue_release,
2957         .tx_queue_setup = qede_tx_queue_setup,
2958         .tx_queue_release = qede_tx_queue_release,
2959         .dev_start = qede_dev_start,
2960         .dev_set_link_up = qede_dev_set_link_up,
2961         .dev_set_link_down = qede_dev_set_link_down,
2962         .link_update = qede_link_update,
2963         .promiscuous_enable = qede_promiscuous_enable,
2964         .promiscuous_disable = qede_promiscuous_disable,
2965         .allmulticast_enable = qede_allmulticast_enable,
2966         .allmulticast_disable = qede_allmulticast_disable,
2967         .set_mc_addr_list = qede_set_mc_addr_list,
2968         .dev_stop = qede_dev_stop,
2969         .dev_close = qede_dev_close,
2970         .stats_get = qede_get_stats,
2971         .stats_reset = qede_reset_stats,
2972         .xstats_get = qede_get_xstats,
2973         .xstats_reset = qede_reset_xstats,
2974         .xstats_get_names = qede_get_xstats_names,
2975         .mac_addr_add = qede_mac_addr_add,
2976         .mac_addr_remove = qede_mac_addr_remove,
2977         .mac_addr_set = qede_mac_addr_set,
2978         .vlan_offload_set = qede_vlan_offload_set,
2979         .vlan_filter_set = qede_vlan_filter_set,
2980         .flow_ctrl_set = qede_flow_ctrl_set,
2981         .flow_ctrl_get = qede_flow_ctrl_get,
2982         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2983         .rss_hash_update = qede_rss_hash_update,
2984         .rss_hash_conf_get = qede_rss_hash_conf_get,
2985         .reta_update  = qede_rss_reta_update,
2986         .reta_query  = qede_rss_reta_query,
2987         .mtu_set = qede_set_mtu,
2988         .filter_ctrl = qede_dev_filter_ctrl,
2989         .udp_tunnel_port_add = qede_udp_dst_port_add,
2990         .udp_tunnel_port_del = qede_udp_dst_port_del,
2991 };
2992
2993 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2994         .dev_configure = qede_dev_configure,
2995         .dev_infos_get = qede_dev_info_get,
2996         .rx_queue_setup = qede_rx_queue_setup,
2997         .rx_queue_release = qede_rx_queue_release,
2998         .tx_queue_setup = qede_tx_queue_setup,
2999         .tx_queue_release = qede_tx_queue_release,
3000         .dev_start = qede_dev_start,
3001         .dev_set_link_up = qede_dev_set_link_up,
3002         .dev_set_link_down = qede_dev_set_link_down,
3003         .link_update = qede_link_update,
3004         .promiscuous_enable = qede_promiscuous_enable,
3005         .promiscuous_disable = qede_promiscuous_disable,
3006         .allmulticast_enable = qede_allmulticast_enable,
3007         .allmulticast_disable = qede_allmulticast_disable,
3008         .set_mc_addr_list = qede_set_mc_addr_list,
3009         .dev_stop = qede_dev_stop,
3010         .dev_close = qede_dev_close,
3011         .stats_get = qede_get_stats,
3012         .stats_reset = qede_reset_stats,
3013         .xstats_get = qede_get_xstats,
3014         .xstats_reset = qede_reset_xstats,
3015         .xstats_get_names = qede_get_xstats_names,
3016         .vlan_offload_set = qede_vlan_offload_set,
3017         .vlan_filter_set = qede_vlan_filter_set,
3018         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
3019         .rss_hash_update = qede_rss_hash_update,
3020         .rss_hash_conf_get = qede_rss_hash_conf_get,
3021         .reta_update  = qede_rss_reta_update,
3022         .reta_query  = qede_rss_reta_query,
3023         .mtu_set = qede_set_mtu,
3024         .udp_tunnel_port_add = qede_udp_dst_port_add,
3025         .udp_tunnel_port_del = qede_udp_dst_port_del,
3026 };
3027
3028 static void qede_update_pf_params(struct ecore_dev *edev)
3029 {
3030         struct ecore_pf_params pf_params;
3031
3032         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
3033         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
3034         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
3035         qed_ops->common->update_pf_params(edev, &pf_params);
3036 }
3037
3038 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
3039 {
3040         struct rte_pci_device *pci_dev;
3041         struct rte_pci_addr pci_addr;
3042         struct qede_dev *adapter;
3043         struct ecore_dev *edev;
3044         struct qed_dev_eth_info dev_info;
3045         struct qed_slowpath_params params;
3046         static bool do_once = true;
3047         uint8_t bulletin_change;
3048         uint8_t vf_mac[ETHER_ADDR_LEN];
3049         uint8_t is_mac_forced;
3050         bool is_mac_exist;
3051         /* Fix up ecore debug level */
3052         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3053         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3054         int rc;
3055
3056         /* Extract key data structures */
3057         adapter = eth_dev->data->dev_private;
3058         adapter->ethdev = eth_dev;
3059         edev = &adapter->edev;
3060         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3061         pci_addr = pci_dev->addr;
3062
3063         PMD_INIT_FUNC_TRACE(edev);
3064
3065         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3066                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3067                  eth_dev->data->port_id);
3068
3069         eth_dev->rx_pkt_burst = qede_recv_pkts;
3070         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3071         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3072
3073         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3074                 DP_ERR(edev, "Skipping device init from secondary process\n");
3075                 return 0;
3076         }
3077
3078         rte_eth_copy_pci_info(eth_dev, pci_dev);
3079
3080         /* @DPDK */
3081         edev->vendor_id = pci_dev->id.vendor_id;
3082         edev->device_id = pci_dev->id.device_id;
3083
3084         qed_ops = qed_get_eth_ops();
3085         if (!qed_ops) {
3086                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3087                 return -EINVAL;
3088         }
3089
3090         DP_INFO(edev, "Starting qede probe\n");
3091         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3092                                     dp_level, is_vf);
3093         if (rc != 0) {
3094                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3095                 return -ENODEV;
3096         }
3097         qede_update_pf_params(edev);
3098         rte_intr_callback_register(&pci_dev->intr_handle,
3099                                    qede_interrupt_handler, (void *)eth_dev);
3100         if (rte_intr_enable(&pci_dev->intr_handle)) {
3101                 DP_ERR(edev, "rte_intr_enable() failed\n");
3102                 return -ENODEV;
3103         }
3104
3105         /* Start the Slowpath-process */
3106         memset(&params, 0, sizeof(struct qed_slowpath_params));
3107         params.int_mode = ECORE_INT_MODE_MSIX;
3108         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3109         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3110         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3111         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3112         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3113                 QEDE_PMD_DRV_VER_STR_SIZE);
3114
3115         /* For CMT mode device do periodic polling for slowpath events.
3116          * This is required since uio device uses only one MSI-x
3117          * interrupt vector but we need one for each engine.
3118          */
3119         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3120                 rc = rte_eal_alarm_set(QEDE_SP_TIMER_PERIOD,
3121                                        qede_poll_sp_sb_cb,
3122                                        (void *)eth_dev);
3123                 if (rc != 0) {
3124                         DP_ERR(edev, "Unable to start periodic"
3125                                      " timer rc %d\n", rc);
3126                         return -EINVAL;
3127                 }
3128         }
3129
3130         rc = qed_ops->common->slowpath_start(edev, &params);
3131         if (rc) {
3132                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3133                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3134                                      (void *)eth_dev);
3135                 return -ENODEV;
3136         }
3137
3138         rc = qed_ops->fill_dev_info(edev, &dev_info);
3139         if (rc) {
3140                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3141                 qed_ops->common->slowpath_stop(edev);
3142                 qed_ops->common->remove(edev);
3143                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3144                                      (void *)eth_dev);
3145                 return -ENODEV;
3146         }
3147
3148         qede_alloc_etherdev(adapter, &dev_info);
3149
3150         adapter->ops->common->set_name(edev, edev->name);
3151
3152         if (!is_vf)
3153                 adapter->dev_info.num_mac_filters =
3154                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3155                                             ECORE_MAC);
3156         else
3157                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3158                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3159
3160         /* Allocate memory for storing MAC addr */
3161         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3162                                         (ETHER_ADDR_LEN *
3163                                         adapter->dev_info.num_mac_filters),
3164                                         RTE_CACHE_LINE_SIZE);
3165
3166         if (eth_dev->data->mac_addrs == NULL) {
3167                 DP_ERR(edev, "Failed to allocate MAC address\n");
3168                 qed_ops->common->slowpath_stop(edev);
3169                 qed_ops->common->remove(edev);
3170                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3171                                      (void *)eth_dev);
3172                 return -ENOMEM;
3173         }
3174
3175         if (!is_vf) {
3176                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3177                                 hw_info.hw_mac_addr,
3178                                 &eth_dev->data->mac_addrs[0]);
3179                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3180                                 &adapter->primary_mac);
3181         } else {
3182                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3183                                        &bulletin_change);
3184                 if (bulletin_change) {
3185                         is_mac_exist =
3186                             ecore_vf_bulletin_get_forced_mac(
3187                                                 ECORE_LEADING_HWFN(edev),
3188                                                 vf_mac,
3189                                                 &is_mac_forced);
3190                         if (is_mac_exist && is_mac_forced) {
3191                                 DP_INFO(edev, "VF macaddr received from PF\n");
3192                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3193                                                 &eth_dev->data->mac_addrs[0]);
3194                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3195                                                 &adapter->primary_mac);
3196                         } else {
3197                                 DP_ERR(edev, "No VF macaddr assigned\n");
3198                         }
3199                 }
3200         }
3201
3202         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3203
3204         if (do_once) {
3205                 qede_print_adapter_info(adapter);
3206                 do_once = false;
3207         }
3208
3209         /* Bring-up the link */
3210         qede_dev_set_link_state(eth_dev, true);
3211
3212         adapter->num_tx_queues = 0;
3213         adapter->num_rx_queues = 0;
3214         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3215         SLIST_INIT(&adapter->vlan_list_head);
3216         SLIST_INIT(&adapter->uc_list_head);
3217         SLIST_INIT(&adapter->mc_list_head);
3218         adapter->mtu = ETHER_MTU;
3219         adapter->vport_started = false;
3220
3221         /* VF tunnel offloads is enabled by default in PF driver */
3222         adapter->vxlan.num_filters = 0;
3223         adapter->geneve.num_filters = 0;
3224         adapter->ipgre.num_filters = 0;
3225         if (is_vf) {
3226                 adapter->vxlan.enable = true;
3227                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3228                                              ETH_TUNNEL_FILTER_IVLAN;
3229                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3230                 adapter->geneve.enable = true;
3231                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3232                                               ETH_TUNNEL_FILTER_IVLAN;
3233                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3234                 adapter->ipgre.enable = true;
3235                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3236                                              ETH_TUNNEL_FILTER_IVLAN;
3237         } else {
3238                 adapter->vxlan.enable = false;
3239                 adapter->geneve.enable = false;
3240                 adapter->ipgre.enable = false;
3241         }
3242
3243         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3244                 adapter->primary_mac.addr_bytes[0],
3245                 adapter->primary_mac.addr_bytes[1],
3246                 adapter->primary_mac.addr_bytes[2],
3247                 adapter->primary_mac.addr_bytes[3],
3248                 adapter->primary_mac.addr_bytes[4],
3249                 adapter->primary_mac.addr_bytes[5]);
3250
3251         DP_INFO(edev, "Device initialized\n");
3252
3253         return 0;
3254 }
3255
3256 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3257 {
3258         return qede_common_dev_init(eth_dev, 1);
3259 }
3260
3261 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3262 {
3263         return qede_common_dev_init(eth_dev, 0);
3264 }
3265
3266 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3267 {
3268 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3269         struct qede_dev *qdev = eth_dev->data->dev_private;
3270         struct ecore_dev *edev = &qdev->edev;
3271
3272         PMD_INIT_FUNC_TRACE(edev);
3273 #endif
3274
3275         /* only uninitialize in the primary process */
3276         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3277                 return 0;
3278
3279         /* safe to close dev here */
3280         qede_dev_close(eth_dev);
3281
3282         eth_dev->dev_ops = NULL;
3283         eth_dev->rx_pkt_burst = NULL;
3284         eth_dev->tx_pkt_burst = NULL;
3285
3286         if (eth_dev->data->mac_addrs)
3287                 rte_free(eth_dev->data->mac_addrs);
3288
3289         eth_dev->data->mac_addrs = NULL;
3290
3291         return 0;
3292 }
3293
3294 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3295 {
3296         return qede_dev_common_uninit(eth_dev);
3297 }
3298
3299 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3300 {
3301         return qede_dev_common_uninit(eth_dev);
3302 }
3303
3304 static const struct rte_pci_id pci_id_qedevf_map[] = {
3305 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3306         {
3307                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3308         },
3309         {
3310                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3311         },
3312         {
3313                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3314         },
3315         {.vendor_id = 0,}
3316 };
3317
3318 static const struct rte_pci_id pci_id_qede_map[] = {
3319 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3320         {
3321                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3322         },
3323         {
3324                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3325         },
3326         {
3327                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3328         },
3329         {
3330                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3331         },
3332         {
3333                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3334         },
3335         {
3336                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3337         },
3338         {
3339                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3340         },
3341         {
3342                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3343         },
3344         {
3345                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3346         },
3347         {
3348                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3349         },
3350         {.vendor_id = 0,}
3351 };
3352
3353 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3354         struct rte_pci_device *pci_dev)
3355 {
3356         return rte_eth_dev_pci_generic_probe(pci_dev,
3357                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3358 }
3359
3360 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3361 {
3362         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3363 }
3364
3365 static struct rte_pci_driver rte_qedevf_pmd = {
3366         .id_table = pci_id_qedevf_map,
3367         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3368         .probe = qedevf_eth_dev_pci_probe,
3369         .remove = qedevf_eth_dev_pci_remove,
3370 };
3371
3372 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3373         struct rte_pci_device *pci_dev)
3374 {
3375         return rte_eth_dev_pci_generic_probe(pci_dev,
3376                 sizeof(struct qede_dev), qede_eth_dev_init);
3377 }
3378
3379 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3380 {
3381         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3382 }
3383
3384 static struct rte_pci_driver rte_qede_pmd = {
3385         .id_table = pci_id_qede_map,
3386         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3387         .probe = qede_eth_dev_pci_probe,
3388         .remove = qede_eth_dev_pci_remove,
3389 };
3390
3391 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3392 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3393 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3394 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3395 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3396 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3397
3398 RTE_INIT(qede_init_log);
3399 static void
3400 qede_init_log(void)
3401 {
3402         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3403         if (qede_logtype_init >= 0)
3404                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3405         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3406         if (qede_logtype_driver >= 0)
3407                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3408 }