drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11
  12 /* Globals */
  13 static const struct qed_eth_ops *qed_ops;
  14 static const char *drivername = "qede pmd";
  15 static int64_t timer_period = 1;
  16
  17 struct rte_qede_xstats_name_off {
  18         char name[RTE_ETH_XSTATS_NAME_SIZE];
  19         uint64_t offset;
  20 };
  21
  22 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
  23         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
  24         {"rx_multicast_bytes",
  25                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
  26         {"rx_broadcast_bytes",
  27                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
  28         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
  29         {"rx_multicast_packets",
  30                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
  31         {"rx_broadcast_packets",
  32                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
  33
  34         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
  35         {"tx_multicast_bytes",
  36                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
  37         {"tx_broadcast_bytes",
  38                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
  39         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
  40         {"tx_multicast_packets",
  41                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
  42         {"tx_broadcast_packets",
  43                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
  44
  45         {"rx_64_byte_packets",
  46                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
  47         {"rx_65_to_127_byte_packets",
  48                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
  49         {"rx_128_to_255_byte_packets",
  50                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
  51         {"rx_256_to_511_byte_packets",
  52                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
  53         {"rx_512_to_1023_byte_packets",
  54                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
  55         {"rx_1024_to_1518_byte_packets",
  56                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
  57         {"rx_1519_to_1522_byte_packets",
  58                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
  59         {"rx_1519_to_2047_byte_packets",
  60                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
  61         {"rx_2048_to_4095_byte_packets",
  62                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
  63         {"rx_4096_to_9216_byte_packets",
  64                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
  65         {"rx_9217_to_16383_byte_packets",
  66                 offsetof(struct ecore_eth_stats,
  67                          rx_9217_to_16383_byte_packets)},
  68         {"tx_64_byte_packets",
  69                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
  70         {"tx_65_to_127_byte_packets",
  71                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
  72         {"tx_128_to_255_byte_packets",
  73                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
  74         {"tx_256_to_511_byte_packets",
  75                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
  76         {"tx_512_to_1023_byte_packets",
  77                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
  78         {"tx_1024_to_1518_byte_packets",
  79                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
  80         {"trx_1519_to_1522_byte_packets",
  81                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
  82         {"tx_2048_to_4095_byte_packets",
  83                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
  84         {"tx_4096_to_9216_byte_packets",
  85                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
  86         {"tx_9217_to_16383_byte_packets",
  87                 offsetof(struct ecore_eth_stats,
  88                          tx_9217_to_16383_byte_packets)},
  89
  90         {"rx_mac_crtl_frames",
  91                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
  92         {"tx_mac_control_frames",
  93                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
  94         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
  95         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
  96         {"rx_priority_flow_control_frames",
  97                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
  98         {"tx_priority_flow_control_frames",
  99                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 100
 101         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 102         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 103         {"rx_carrier_errors",
 104                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 105         {"rx_oversize_packet_errors",
 106                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 107         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 108         {"rx_undersize_packet_errors",
 109                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 110         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 111         {"rx_host_buffer_not_available",
 112                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 113         /* Number of packets discarded because they are bigger than MTU */
 114         {"rx_packet_too_big_discards",
 115                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 116         {"rx_ttl_zero_discards",
 117                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 118         {"rx_multi_function_tag_filter_discards",
 119                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 120         {"rx_mac_filter_discards",
 121                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 122         {"rx_hw_buffer_truncates",
 123                 offsetof(struct ecore_eth_stats, brb_truncates)},
 124         {"rx_hw_buffer_discards",
 125                 offsetof(struct ecore_eth_stats, brb_discards)},
 126         {"tx_lpi_entry_count",
 127                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 128         {"tx_total_collisions",
 129                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 130         {"tx_error_drop_packets",
 131                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 132
 133         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 134         {"rx_mac_unicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 136         {"rx_mac_multicast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 138         {"rx_mac_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 140         {"rx_mac_frames_ok",
 141                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 142         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 143         {"tx_mac_unicast_packets",
 144                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 145         {"tx_mac_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 147         {"tx_mac_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 149
 150         {"lro_coalesced_packets",
 151                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 152         {"lro_coalesced_events",
 153                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 154         {"lro_aborts_num",
 155                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 156         {"lro_not_coalesced_packets",
 157                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 158         {"lro_coalesced_bytes",
 159                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 160 };
 161
 162 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 163 {
 164         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 165 }
 166
 167 static void
 168 qede_interrupt_handler(__rte_unused struct rte_intr_handle *handle, void *param)
 169 {
 170         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 171         struct qede_dev *qdev = eth_dev->data->dev_private;
 172         struct ecore_dev *edev = &qdev->edev;
 173
 174         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 175         if (rte_intr_enable(&eth_dev->pci_dev->intr_handle))
 176                 DP_ERR(edev, "rte_intr_enable failed\n");
 177 }
 178
 179 static void
 180 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 181 {
 182         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 183         qdev->num_tc = qdev->dev_info.num_tc;
 184         qdev->ops = qed_ops;
 185 }
 186
 187 static void qede_print_adapter_info(struct qede_dev *qdev)
 188 {
 189         struct ecore_dev *edev = &qdev->edev;
 190         struct qed_dev_info *info = &qdev->dev_info.common;
 191         static char ver_str[QED_DRV_VER_STR_SIZE];
 192
 193         DP_INFO(edev, "*********************************\n");
 194         DP_INFO(edev, " Chip details : %s%d\n",
 195                 ECORE_IS_BB(edev) ? "BB" : "AH",
 196                 CHIP_REV_IS_A0(edev) ? 0 : 1);
 197
 198         sprintf(ver_str, "%s %s_%d.%d.%d.%d", QEDE_PMD_VER_PREFIX,
 199                 edev->ver_str, QEDE_PMD_VERSION_MAJOR, QEDE_PMD_VERSION_MINOR,
 200                 QEDE_PMD_VERSION_REVISION, QEDE_PMD_VERSION_PATCH);
 201         strcpy(qdev->drv_ver, ver_str);
 202         DP_INFO(edev, " Driver version : %s\n", ver_str);
 203
 204         sprintf(ver_str, "%d.%d.%d.%d", info->fw_major, info->fw_minor,
 205                 info->fw_rev, info->fw_eng);
 206         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 207
 208         sprintf(ver_str, "%d.%d.%d.%d",
 209                 (info->mfw_rev >> 24) & 0xff,
 210                 (info->mfw_rev >> 16) & 0xff,
 211                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 212         DP_INFO(edev, " Management firmware version : %s\n", ver_str);
 213
 214         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 215
 216         DP_INFO(edev, "*********************************\n");
 217 }
 218
 219 static int
 220 qede_set_ucast_rx_mac(struct qede_dev *qdev,
 221                       enum qed_filter_xcast_params_type opcode,
 222                       uint8_t mac[ETHER_ADDR_LEN])
 223 {
 224         struct ecore_dev *edev = &qdev->edev;
 225         struct qed_filter_params filter_cmd;
 226
 227         memset(&filter_cmd, 0, sizeof(filter_cmd));
 228         filter_cmd.type = QED_FILTER_TYPE_UCAST;
 229         filter_cmd.filter.ucast.type = opcode;
 230         filter_cmd.filter.ucast.mac_valid = 1;
 231         rte_memcpy(&filter_cmd.filter.ucast.mac[0], &mac[0], ETHER_ADDR_LEN);
 232         return qdev->ops->filter_config(edev, &filter_cmd);
 233 }
 234
 235 static void
 236 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 237                   uint32_t index, __rte_unused uint32_t pool)
 238 {
 239         struct qede_dev *qdev = eth_dev->data->dev_private;
 240         struct ecore_dev *edev = &qdev->edev;
 241         int rc;
 242
 243         PMD_INIT_FUNC_TRACE(edev);
 244
 245         if (index >= qdev->dev_info.num_mac_addrs) {
 246                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 247                        index, qdev->dev_info.num_mac_addrs);
 248                 return;
 249         }
 250
 251         /* Adding macaddr even though promiscuous mode is set */
 252         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
 253                 DP_INFO(edev, "Port is in promisc mode, yet adding it\n");
 254
 255         /* Add MAC filters according to the unicast secondary macs */
 256         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD,
 257                                    mac_addr->addr_bytes);
 258         if (rc)
 259                 DP_ERR(edev, "Unable to add macaddr rc=%d\n", rc);
 260 }
 261
 262 static void
 263 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 264 {
 265         struct qede_dev *qdev = eth_dev->data->dev_private;
 266         struct ecore_dev *edev = &qdev->edev;
 267         struct ether_addr mac_addr;
 268         int rc;
 269
 270         PMD_INIT_FUNC_TRACE(edev);
 271
 272         if (index >= qdev->dev_info.num_mac_addrs) {
 273                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 274                        index, qdev->dev_info.num_mac_addrs);
 275                 return;
 276         }
 277
 278         /* Use the index maintained by rte */
 279         ether_addr_copy(&eth_dev->data->mac_addrs[index], &mac_addr);
 280         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL,
 281                                    mac_addr.addr_bytes);
 282         if (rc)
 283                 DP_ERR(edev, "Unable to remove macaddr rc=%d\n", rc);
 284 }
 285
 286 static void
 287 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 288 {
 289         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 290         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 291         int rc;
 292
 293         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 294                                                mac_addr->addr_bytes)) {
 295                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 296                 ether_addr_copy(&qdev->primary_mac,
 297                                 &eth_dev->data->mac_addrs[0]);
 298                 return;
 299         }
 300
 301         /* First remove the primary mac */
 302         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_DEL,
 303                                    qdev->primary_mac.addr_bytes);
 304
 305         if (rc) {
 306                 DP_ERR(edev, "Unable to remove current macaddr"
 307                              " Reverting to previous default mac\n");
 308                 ether_addr_copy(&qdev->primary_mac,
 309                                 &eth_dev->data->mac_addrs[0]);
 310                 return;
 311         }
 312
 313         /* Add new MAC */
 314         rc = qede_set_ucast_rx_mac(qdev, QED_FILTER_XCAST_TYPE_ADD,
 315                                    mac_addr->addr_bytes);
 316
 317         if (rc)
 318                 DP_ERR(edev, "Unable to add new default mac\n");
 319         else
 320                 ether_addr_copy(mac_addr, &qdev->primary_mac);
 321 }
 322
 323
 324
 325
 326 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool action)
 327 {
 328         struct ecore_dev *edev = &qdev->edev;
 329         struct qed_update_vport_params params = {
 330                 .vport_id = 0,
 331                 .accept_any_vlan = action,
 332                 .update_accept_any_vlan_flg = 1,
 333         };
 334         int rc;
 335
 336         /* Proceed only if action actually needs to be performed */
 337         if (qdev->accept_any_vlan == action)
 338                 return;
 339
 340         rc = qdev->ops->vport_update(edev, &params);
 341         if (rc) {
 342                 DP_ERR(edev, "Failed to %s accept-any-vlan\n",
 343                        action ? "enable" : "disable");
 344         } else {
 345                 DP_INFO(edev, "%s accept-any-vlan\n",
 346                         action ? "enabled" : "disabled");
 347                 qdev->accept_any_vlan = action;
 348         }
 349 }
 350
 351 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool set_stripping)
 352 {
 353         struct qed_update_vport_params vport_update_params;
 354         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 355         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 356         int rc;
 357
 358         memset(&vport_update_params, 0, sizeof(vport_update_params));
 359         vport_update_params.vport_id = 0;
 360         vport_update_params.update_inner_vlan_removal_flg = 1;
 361         vport_update_params.inner_vlan_removal_flg = set_stripping;
 362         rc = qdev->ops->vport_update(edev, &vport_update_params);
 363         if (rc) {
 364                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 365                 return rc;
 366         }
 367
 368         return 0;
 369 }
 370
 371 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 372 {
 373         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 374         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 375
 376         if (mask & ETH_VLAN_STRIP_MASK) {
 377                 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip)
 378                         (void)qede_vlan_stripping(eth_dev, 1);
 379                 else
 380                         (void)qede_vlan_stripping(eth_dev, 0);
 381         }
 382
 383         DP_INFO(edev, "vlan offload mask %d vlan-strip %d\n",
 384                 mask, eth_dev->data->dev_conf.rxmode.hw_vlan_strip);
 385 }
 386
 387 static int qede_set_ucast_rx_vlan(struct qede_dev *qdev,
 388                                   enum qed_filter_xcast_params_type opcode,
 389                                   uint16_t vid)
 390 {
 391         struct qed_filter_params filter_cmd;
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393
 394         memset(&filter_cmd, 0, sizeof(filter_cmd));
 395         filter_cmd.type = QED_FILTER_TYPE_UCAST;
 396         filter_cmd.filter.ucast.type = opcode;
 397         filter_cmd.filter.ucast.vlan_valid = 1;
 398         filter_cmd.filter.ucast.vlan = vid;
 399
 400         return qdev->ops->filter_config(edev, &filter_cmd);
 401 }
 402
 403 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 404                                 uint16_t vlan_id, int on)
 405 {
 406         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 407         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 408         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 409         struct qede_vlan_entry *tmp = NULL;
 410         struct qede_vlan_entry *vlan;
 411         int rc;
 412
 413         if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 414                 DP_NOTICE(edev, false, "Reached max VLAN filter limit"
 415                                      " enabling accept_any_vlan\n");
 416                 qede_config_accept_any_vlan(qdev, true);
 417                 return 0;
 418         }
 419
 420         if (on) {
 421                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 422                         if (tmp->vid == vlan_id) {
 423                                 DP_ERR(edev, "VLAN %u already configured\n",
 424                                        vlan_id);
 425                                 return -EEXIST;
 426                         }
 427                 }
 428
 429                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 430                                   RTE_CACHE_LINE_SIZE);
 431
 432                 if (!vlan) {
 433                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 434                         return -ENOMEM;
 435                 }
 436
 437                 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_ADD,
 438                                             vlan_id);
 439                 if (rc) {
 440                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 441                                rc);
 442                         rte_free(vlan);
 443                 } else {
 444                         vlan->vid = vlan_id;
 445                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 446                         qdev->configured_vlans++;
 447                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 448                                 vlan_id, qdev->configured_vlans);
 449                 }
 450         } else {
 451                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 452                         if (tmp->vid == vlan_id)
 453                                 break;
 454                 }
 455
 456                 if (!tmp) {
 457                         if (qdev->configured_vlans == 0) {
 458                                 DP_INFO(edev,
 459                                         "No VLAN filters configured yet\n");
 460                                 return 0;
 461                         }
 462
 463                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 464                         return -EINVAL;
 465                 }
 466
 467                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 468
 469                 rc = qede_set_ucast_rx_vlan(qdev, QED_FILTER_XCAST_TYPE_DEL,
 470                                             vlan_id);
 471                 if (rc) {
 472                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 473                                vlan_id, rc);
 474                 } else {
 475                         qdev->configured_vlans--;
 476                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 477                                 vlan_id, qdev->configured_vlans);
 478                 }
 479         }
 480
 481         return rc;
 482 }
 483
 484 static int qede_init_vport(struct qede_dev *qdev)
 485 {
 486         struct ecore_dev *edev = &qdev->edev;
 487         struct qed_start_vport_params start = {0};
 488         int rc;
 489
 490         start.remove_inner_vlan = 1;
 491         start.gro_enable = 0;
 492         start.mtu = ETHER_MTU + QEDE_ETH_OVERHEAD;
 493         start.vport_id = 0;
 494         start.drop_ttl0 = false;
 495         start.clear_stats = 1;
 496         start.handle_ptp_pkts = 0;
 497
 498         rc = qdev->ops->vport_start(edev, &start);
 499         if (rc) {
 500                 DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 501                 return rc;
 502         }
 503
 504         DP_INFO(edev,
 505                 "Start vport ramrod passed, vport_id = %d, MTU = %u\n",
 506                 start.vport_id, ETHER_MTU);
 507
 508         return 0;
 509 }
 510
 511 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
 512 {
 513         struct qede_dev *qdev = eth_dev->data->dev_private;
 514         struct ecore_dev *edev = &qdev->edev;
 515         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 516         int rc;
 517
 518         PMD_INIT_FUNC_TRACE(edev);
 519
 520         /* Check requirements for 100G mode */
 521         if (edev->num_hwfns > 1) {
 522                 if (eth_dev->data->nb_rx_queues < 2 ||
 523                     eth_dev->data->nb_tx_queues < 2) {
 524                         DP_NOTICE(edev, false,
 525                                   "100G mode needs min. 2 RX/TX queues\n");
 526                         return -EINVAL;
 527                 }
 528
 529                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
 530                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
 531                         DP_NOTICE(edev, false,
 532                                   "100G mode needs even no. of RX/TX queues\n");
 533                         return -EINVAL;
 534                 }
 535         }
 536
 537         qdev->fp_num_tx = eth_dev->data->nb_tx_queues;
 538         qdev->fp_num_rx = eth_dev->data->nb_rx_queues;
 539         qdev->num_queues = qdev->fp_num_tx + qdev->fp_num_rx;
 540
 541         /* Sanity checks and throw warnings */
 542         if (rxmode->enable_scatter == 1) {
 543                 DP_ERR(edev, "RX scatter packets is not supported\n");
 544                 return -EINVAL;
 545         }
 546
 547         if (rxmode->enable_lro == 1) {
 548                 DP_INFO(edev, "LRO is not supported\n");
 549                 return -EINVAL;
 550         }
 551
 552         if (!rxmode->hw_strip_crc)
 553                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
 554
 555         if (!rxmode->hw_ip_checksum)
 556                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
 557                               "in hw\n");
 558
 559         SLIST_INIT(&qdev->vlan_list_head);
 560
 561         /* Check for the port restart case */
 562         if (qdev->state != QEDE_DEV_INIT) {
 563                 rc = qdev->ops->vport_stop(edev, 0);
 564                 if (rc != 0)
 565                         return rc;
 566                 qede_dealloc_fp_resc(eth_dev);
 567         }
 568
 569         /* Fastpath status block should be initialized before sending
 570          * VPORT-START in the case of VF. Anyway, do it for both VF/PF.
 571          */
 572         rc = qede_alloc_fp_resc(qdev);
 573         if (rc != 0)
 574                 return rc;
 575
 576         /* Issue VPORT-START with default config values to allow
 577          * other port configurations early on.
 578          */
 579         rc = qede_init_vport(qdev);
 580         if (rc != 0)
 581                 return rc;
 582
 583         /* Add primary mac for PF */
 584         if (IS_PF(edev))
 585                 qede_mac_addr_set(eth_dev, &qdev->primary_mac);
 586
 587         qdev->state = QEDE_DEV_CONFIG;
 588
 589         return 0;
 590 }
 591
 592 /* Info about HW descriptor ring limitations */
 593 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
 594         .nb_max = NUM_RX_BDS_MAX,
 595         .nb_min = 128,
 596         .nb_align = 128 /* lowest common multiple */
 597 };
 598
 599 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
 600         .nb_max = NUM_TX_BDS_MAX,
 601         .nb_min = 256,
 602         .nb_align = 256
 603 };
 604
 605 static void
 606 qede_dev_info_get(struct rte_eth_dev *eth_dev,
 607                   struct rte_eth_dev_info *dev_info)
 608 {
 609         struct qede_dev *qdev = eth_dev->data->dev_private;
 610         struct ecore_dev *edev = &qdev->edev;
 611
 612         PMD_INIT_FUNC_TRACE(edev);
 613
 614         dev_info->min_rx_bufsize = (uint32_t)(ETHER_MIN_MTU +
 615                                               QEDE_ETH_OVERHEAD);
 616         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
 617         dev_info->rx_desc_lim = qede_rx_desc_lim;
 618         dev_info->tx_desc_lim = qede_tx_desc_lim;
 619         dev_info->max_rx_queues = (uint16_t)QEDE_MAX_RSS_CNT(qdev);
 620         dev_info->max_tx_queues = dev_info->max_rx_queues;
 621         dev_info->max_mac_addrs = qdev->dev_info.num_mac_addrs;
 622         if (IS_VF(edev))
 623                 dev_info->max_vfs = 0;
 624         else
 625                 dev_info->max_vfs = (uint16_t)NUM_OF_VFS(&qdev->edev);
 626         dev_info->driver_name = qdev->drv_ver;
 627         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
 628         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
 629
 630         dev_info->default_txconf = (struct rte_eth_txconf) {
 631                 .txq_flags = QEDE_TXQ_FLAGS,
 632         };
 633
 634         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP |
 635                                      DEV_RX_OFFLOAD_IPV4_CKSUM |
 636                                      DEV_RX_OFFLOAD_UDP_CKSUM |
 637                                      DEV_RX_OFFLOAD_TCP_CKSUM);
 638         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
 639                                      DEV_TX_OFFLOAD_IPV4_CKSUM |
 640                                      DEV_TX_OFFLOAD_UDP_CKSUM |
 641                                      DEV_TX_OFFLOAD_TCP_CKSUM);
 642
 643         dev_info->speed_capa = ETH_LINK_SPEED_25G | ETH_LINK_SPEED_40G |
 644                                ETH_LINK_SPEED_100G;
 645 }
 646
 647 /* return 0 means link status changed, -1 means not changed */
 648 static int
 649 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
 650 {
 651         struct qede_dev *qdev = eth_dev->data->dev_private;
 652         struct ecore_dev *edev = &qdev->edev;
 653         uint16_t link_duplex;
 654         struct qed_link_output link;
 655         struct rte_eth_link *curr = &eth_dev->data->dev_link;
 656
 657         memset(&link, 0, sizeof(struct qed_link_output));
 658         qdev->ops->common->get_link(edev, &link);
 659
 660         /* Link Speed */
 661         curr->link_speed = link.speed;
 662
 663         /* Link Mode */
 664         switch (link.duplex) {
 665         case QEDE_DUPLEX_HALF:
 666                 link_duplex = ETH_LINK_HALF_DUPLEX;
 667                 break;
 668         case QEDE_DUPLEX_FULL:
 669                 link_duplex = ETH_LINK_FULL_DUPLEX;
 670                 break;
 671         case QEDE_DUPLEX_UNKNOWN:
 672         default:
 673                 link_duplex = -1;
 674         }
 675         curr->link_duplex = link_duplex;
 676
 677         /* Link Status */
 678         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
 679
 680         /* AN */
 681         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
 682                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
 683
 684         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
 685                 curr->link_speed, curr->link_duplex,
 686                 curr->link_autoneg, curr->link_status);
 687
 688         /* return 0 means link status changed, -1 means not changed */
 689         return ((curr->link_status == link.link_up) ? -1 : 0);
 690 }
 691
 692 static void
 693 qede_rx_mode_setting(struct rte_eth_dev *eth_dev,
 694                      enum qed_filter_rx_mode_type accept_flags)
 695 {
 696         struct qede_dev *qdev = eth_dev->data->dev_private;
 697         struct ecore_dev *edev = &qdev->edev;
 698         struct qed_filter_params rx_mode;
 699
 700         DP_INFO(edev, "%s mode %u\n", __func__, accept_flags);
 701
 702         memset(&rx_mode, 0, sizeof(struct qed_filter_params));
 703         rx_mode.type = QED_FILTER_TYPE_RX_MODE;
 704         rx_mode.filter.accept_flags = accept_flags;
 705         qdev->ops->filter_config(edev, &rx_mode);
 706 }
 707
 708 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
 709 {
 710         struct qede_dev *qdev = eth_dev->data->dev_private;
 711         struct ecore_dev *edev = &qdev->edev;
 712
 713         PMD_INIT_FUNC_TRACE(edev);
 714
 715         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
 716
 717         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 718                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
 719
 720         qede_rx_mode_setting(eth_dev, type);
 721 }
 722
 723 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
 724 {
 725         struct qede_dev *qdev = eth_dev->data->dev_private;
 726         struct ecore_dev *edev = &qdev->edev;
 727
 728         PMD_INIT_FUNC_TRACE(edev);
 729
 730         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
 731                 qede_rx_mode_setting(eth_dev,
 732                                      QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
 733         else
 734                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR);
 735 }
 736
 737 static void qede_poll_sp_sb_cb(void *param)
 738 {
 739         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 740         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 741         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 742         int rc;
 743
 744         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 745         qede_interrupt_action(&edev->hwfns[1]);
 746
 747         rc = rte_eal_alarm_set(timer_period * US_PER_S,
 748                                qede_poll_sp_sb_cb,
 749                                (void *)eth_dev);
 750         if (rc != 0) {
 751                 DP_ERR(edev, "Unable to start periodic"
 752                              " timer rc %d\n", rc);
 753                 assert(false && "Unable to start periodic timer");
 754         }
 755 }
 756
 757 static void qede_dev_close(struct rte_eth_dev *eth_dev)
 758 {
 759         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 760         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 761         int rc;
 762
 763         PMD_INIT_FUNC_TRACE(edev);
 764
 765         /* dev_stop() shall cleanup fp resources in hw but without releasing
 766          * dma memories and sw structures so that dev_start() can be called
 767          * by the app without reconfiguration. However, in dev_close() we
 768          * can release all the resources and device can be brought up newly
 769          */
 770         if (qdev->state != QEDE_DEV_STOP)
 771                 qede_dev_stop(eth_dev);
 772         else
 773                 DP_INFO(edev, "Device is already stopped\n");
 774
 775         rc = qdev->ops->vport_stop(edev, 0);
 776         if (rc != 0)
 777                 DP_ERR(edev, "Failed to stop VPORT\n");
 778
 779         qede_dealloc_fp_resc(eth_dev);
 780
 781         qdev->ops->common->slowpath_stop(edev);
 782
 783         qdev->ops->common->remove(edev);
 784
 785         rte_intr_disable(&eth_dev->pci_dev->intr_handle);
 786
 787         rte_intr_callback_unregister(&eth_dev->pci_dev->intr_handle,
 788                                      qede_interrupt_handler, (void *)eth_dev);
 789
 790         if (edev->num_hwfns > 1)
 791                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
 792
 793         qdev->state = QEDE_DEV_INIT; /* Go back to init state */
 794 }
 795
 796 static void
 797 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
 798 {
 799         struct qede_dev *qdev = eth_dev->data->dev_private;
 800         struct ecore_dev *edev = &qdev->edev;
 801         struct ecore_eth_stats stats;
 802
 803         qdev->ops->get_vport_stats(edev, &stats);
 804
 805         /* RX Stats */
 806         eth_stats->ipackets = stats.rx_ucast_pkts +
 807             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
 808
 809         eth_stats->ibytes = stats.rx_ucast_bytes +
 810             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
 811
 812         eth_stats->ierrors = stats.rx_crc_errors +
 813             stats.rx_align_errors +
 814             stats.rx_carrier_errors +
 815             stats.rx_oversize_packets +
 816             stats.rx_jabbers + stats.rx_undersize_packets;
 817
 818         eth_stats->rx_nombuf = stats.no_buff_discards;
 819
 820         eth_stats->imissed = stats.mftag_filter_discards +
 821             stats.mac_filter_discards +
 822             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
 823
 824         /* TX stats */
 825         eth_stats->opackets = stats.tx_ucast_pkts +
 826             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
 827
 828         eth_stats->obytes = stats.tx_ucast_bytes +
 829             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
 830
 831         eth_stats->oerrors = stats.tx_err_drop_pkts;
 832 }
 833
 834 static int
 835 qede_get_xstats_names(__rte_unused struct rte_eth_dev *dev,
 836                       struct rte_eth_xstat_name *xstats_names, unsigned limit)
 837 {
 838         unsigned int i, stat_cnt = RTE_DIM(qede_xstats_strings);
 839
 840         if (xstats_names != NULL)
 841                 for (i = 0; i < stat_cnt; i++)
 842                         snprintf(xstats_names[i].name,
 843                                 sizeof(xstats_names[i].name),
 844                                 "%s",
 845                                 qede_xstats_strings[i].name);
 846
 847         return stat_cnt;
 848 }
 849
 850 static int
 851 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
 852                 unsigned int n)
 853 {
 854         struct qede_dev *qdev = dev->data->dev_private;
 855         struct ecore_dev *edev = &qdev->edev;
 856         struct ecore_eth_stats stats;
 857         unsigned int num = RTE_DIM(qede_xstats_strings);
 858
 859         if (n < num)
 860                 return num;
 861
 862         qdev->ops->get_vport_stats(edev, &stats);
 863
 864         for (num = 0; num < n; num++)
 865                 xstats[num].value = *(u64 *)(((char *)&stats) +
 866                                              qede_xstats_strings[num].offset);
 867
 868         return num;
 869 }
 870
 871 static void
 872 qede_reset_xstats(struct rte_eth_dev *dev)
 873 {
 874         struct qede_dev *qdev = dev->data->dev_private;
 875         struct ecore_dev *edev = &qdev->edev;
 876
 877         ecore_reset_vport_stats(edev);
 878 }
 879
 880 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
 881 {
 882         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 883         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 884         struct qed_link_params link_params;
 885         int rc;
 886
 887         DP_INFO(edev, "setting link state %d\n", link_up);
 888         memset(&link_params, 0, sizeof(link_params));
 889         link_params.link_up = link_up;
 890         rc = qdev->ops->common->set_link(edev, &link_params);
 891         if (rc != ECORE_SUCCESS)
 892                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
 893
 894         return rc;
 895 }
 896
 897 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
 898 {
 899         return qede_dev_set_link_state(eth_dev, true);
 900 }
 901
 902 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
 903 {
 904         return qede_dev_set_link_state(eth_dev, false);
 905 }
 906
 907 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
 908 {
 909         struct qede_dev *qdev = eth_dev->data->dev_private;
 910         struct ecore_dev *edev = &qdev->edev;
 911
 912         ecore_reset_vport_stats(edev);
 913 }
 914
 915 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
 916 {
 917         enum qed_filter_rx_mode_type type =
 918             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
 919
 920         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
 921                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
 922
 923         qede_rx_mode_setting(eth_dev, type);
 924 }
 925
 926 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
 927 {
 928         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
 929                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_PROMISC);
 930         else
 931                 qede_rx_mode_setting(eth_dev, QED_FILTER_RX_MODE_TYPE_REGULAR);
 932 }
 933
 934 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
 935                               struct rte_eth_fc_conf *fc_conf)
 936 {
 937         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 938         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 939         struct qed_link_output current_link;
 940         struct qed_link_params params;
 941
 942         memset(&current_link, 0, sizeof(current_link));
 943         qdev->ops->common->get_link(edev, &current_link);
 944
 945         memset(&params, 0, sizeof(params));
 946         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
 947         if (fc_conf->autoneg) {
 948                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
 949                         DP_ERR(edev, "Autoneg not supported\n");
 950                         return -EINVAL;
 951                 }
 952                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
 953         }
 954
 955         /* Pause is assumed to be supported (SUPPORTED_Pause) */
 956         if (fc_conf->mode == RTE_FC_FULL)
 957                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
 958                                         QED_LINK_PAUSE_RX_ENABLE);
 959         if (fc_conf->mode == RTE_FC_TX_PAUSE)
 960                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
 961         if (fc_conf->mode == RTE_FC_RX_PAUSE)
 962                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
 963
 964         params.link_up = true;
 965         (void)qdev->ops->common->set_link(edev, &params);
 966
 967         return 0;
 968 }
 969
 970 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
 971                               struct rte_eth_fc_conf *fc_conf)
 972 {
 973         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 974         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 975         struct qed_link_output current_link;
 976
 977         memset(&current_link, 0, sizeof(current_link));
 978         qdev->ops->common->get_link(edev, &current_link);
 979
 980         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
 981                 fc_conf->autoneg = true;
 982
 983         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
 984                                          QED_LINK_PAUSE_TX_ENABLE))
 985                 fc_conf->mode = RTE_FC_FULL;
 986         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
 987                 fc_conf->mode = RTE_FC_RX_PAUSE;
 988         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
 989                 fc_conf->mode = RTE_FC_TX_PAUSE;
 990         else
 991                 fc_conf->mode = RTE_FC_NONE;
 992
 993         return 0;
 994 }
 995
 996 static const uint32_t *
 997 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
 998 {
 999         static const uint32_t ptypes[] = {
1000                 RTE_PTYPE_L3_IPV4,
1001                 RTE_PTYPE_L3_IPV6,
1002                 RTE_PTYPE_UNKNOWN
1003         };
1004
1005         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1006                 return ptypes;
1007
1008         return NULL;
1009 }
1010
1011 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1012                          struct rte_eth_rss_conf *rss_conf)
1013 {
1014         struct qed_update_vport_params vport_update_params;
1015         struct qede_dev *qdev = eth_dev->data->dev_private;
1016         struct ecore_dev *edev = &qdev->edev;
1017         uint8_t rss_caps;
1018         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1019         uint64_t hf = rss_conf->rss_hf;
1020         int i;
1021
1022         if (hf == 0)
1023                 DP_ERR(edev, "hash function 0 will disable RSS\n");
1024
1025         rss_caps = 0;
1026         rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1027         rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1028         rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1029         rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1030         rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1031         rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1032
1033         /* If the mapping doesn't fit any supported, return */
1034         if (rss_caps == 0 && hf != 0)
1035                 return -EINVAL;
1036
1037         memset(&vport_update_params, 0, sizeof(vport_update_params));
1038
1039         if (key != NULL)
1040                 memcpy(qdev->rss_params.rss_key, rss_conf->rss_key,
1041                        rss_conf->rss_key_len);
1042
1043         qdev->rss_params.rss_caps = rss_caps;
1044         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1045                sizeof(vport_update_params.rss_params));
1046         vport_update_params.update_rss_flg = 1;
1047         vport_update_params.vport_id = 0;
1048
1049         return qdev->ops->vport_update(edev, &vport_update_params);
1050 }
1051
1052 int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1053                            struct rte_eth_rss_conf *rss_conf)
1054 {
1055         struct qede_dev *qdev = eth_dev->data->dev_private;
1056         uint64_t hf;
1057
1058         if (rss_conf->rss_key_len < sizeof(qdev->rss_params.rss_key))
1059                 return -EINVAL;
1060
1061         if (rss_conf->rss_key)
1062                 memcpy(rss_conf->rss_key, qdev->rss_params.rss_key,
1063                        sizeof(qdev->rss_params.rss_key));
1064
1065         hf = 0;
1066         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4)     ?
1067                         ETH_RSS_IPV4 : 0;
1068         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1069                         ETH_RSS_IPV6 : 0;
1070         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6)     ?
1071                         ETH_RSS_IPV6_EX : 0;
1072         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV4_TCP) ?
1073                         ETH_RSS_NONFRAG_IPV4_TCP : 0;
1074         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1075                         ETH_RSS_NONFRAG_IPV6_TCP : 0;
1076         hf |= (qdev->rss_params.rss_caps & ECORE_RSS_IPV6_TCP) ?
1077                         ETH_RSS_IPV6_TCP_EX : 0;
1078
1079         rss_conf->rss_hf = hf;
1080
1081         return 0;
1082 }
1083
1084 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1085                          struct rte_eth_rss_reta_entry64 *reta_conf,
1086                          uint16_t reta_size)
1087 {
1088         struct qed_update_vport_params vport_update_params;
1089         struct qede_dev *qdev = eth_dev->data->dev_private;
1090         struct ecore_dev *edev = &qdev->edev;
1091         uint16_t i, idx, shift;
1092
1093         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1094                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1095                        reta_size);
1096                 return -EINVAL;
1097         }
1098
1099         memset(&vport_update_params, 0, sizeof(vport_update_params));
1100         memcpy(&vport_update_params.rss_params, &qdev->rss_params,
1101                sizeof(vport_update_params.rss_params));
1102
1103         for (i = 0; i < reta_size; i++) {
1104                 idx = i / RTE_RETA_GROUP_SIZE;
1105                 shift = i % RTE_RETA_GROUP_SIZE;
1106                 if (reta_conf[idx].mask & (1ULL << shift)) {
1107                         uint8_t entry = reta_conf[idx].reta[shift];
1108                         qdev->rss_params.rss_ind_table[i] = entry;
1109                 }
1110         }
1111
1112         vport_update_params.update_rss_flg = 1;
1113         vport_update_params.vport_id = 0;
1114
1115         return qdev->ops->vport_update(edev, &vport_update_params);
1116 }
1117
1118 int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1119                         struct rte_eth_rss_reta_entry64 *reta_conf,
1120                         uint16_t reta_size)
1121 {
1122         struct qede_dev *qdev = eth_dev->data->dev_private;
1123         uint16_t i, idx, shift;
1124
1125         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1126                 struct ecore_dev *edev = &qdev->edev;
1127                 DP_ERR(edev, "reta_size %d is not supported\n",
1128                        reta_size);
1129         }
1130
1131         for (i = 0; i < reta_size; i++) {
1132                 idx = i / RTE_RETA_GROUP_SIZE;
1133                 shift = i % RTE_RETA_GROUP_SIZE;
1134                 if (reta_conf[idx].mask & (1ULL << shift)) {
1135                         uint8_t entry = qdev->rss_params.rss_ind_table[i];
1136                         reta_conf[idx].reta[shift] = entry;
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1144 {
1145         uint32_t frame_size;
1146         struct qede_dev *qdev = dev->data->dev_private;
1147         struct rte_eth_dev_info dev_info = {0};
1148
1149         qede_dev_info_get(dev, &dev_info);
1150
1151         /* VLAN_TAG = 4 */
1152         frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 4;
1153
1154         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen))
1155                 return -EINVAL;
1156
1157         if (!dev->data->scattered_rx &&
1158             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)
1159                 return -EINVAL;
1160
1161         if (frame_size > ETHER_MAX_LEN)
1162                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
1163         else
1164                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
1165
1166         /* update max frame size */
1167         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
1168         qdev->mtu = mtu;
1169         qede_dev_stop(dev);
1170         qede_dev_start(dev);
1171
1172         return 0;
1173 }
1174
1175 static const struct eth_dev_ops qede_eth_dev_ops = {
1176         .dev_configure = qede_dev_configure,
1177         .dev_infos_get = qede_dev_info_get,
1178         .rx_queue_setup = qede_rx_queue_setup,
1179         .rx_queue_release = qede_rx_queue_release,
1180         .tx_queue_setup = qede_tx_queue_setup,
1181         .tx_queue_release = qede_tx_queue_release,
1182         .dev_start = qede_dev_start,
1183         .dev_set_link_up = qede_dev_set_link_up,
1184         .dev_set_link_down = qede_dev_set_link_down,
1185         .link_update = qede_link_update,
1186         .promiscuous_enable = qede_promiscuous_enable,
1187         .promiscuous_disable = qede_promiscuous_disable,
1188         .allmulticast_enable = qede_allmulticast_enable,
1189         .allmulticast_disable = qede_allmulticast_disable,
1190         .dev_stop = qede_dev_stop,
1191         .dev_close = qede_dev_close,
1192         .stats_get = qede_get_stats,
1193         .stats_reset = qede_reset_stats,
1194         .xstats_get = qede_get_xstats,
1195         .xstats_reset = qede_reset_xstats,
1196         .xstats_get_names = qede_get_xstats_names,
1197         .mac_addr_add = qede_mac_addr_add,
1198         .mac_addr_remove = qede_mac_addr_remove,
1199         .mac_addr_set = qede_mac_addr_set,
1200         .vlan_offload_set = qede_vlan_offload_set,
1201         .vlan_filter_set = qede_vlan_filter_set,
1202         .flow_ctrl_set = qede_flow_ctrl_set,
1203         .flow_ctrl_get = qede_flow_ctrl_get,
1204         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1205         .rss_hash_update = qede_rss_hash_update,
1206         .rss_hash_conf_get = qede_rss_hash_conf_get,
1207         .reta_update  = qede_rss_reta_update,
1208         .reta_query  = qede_rss_reta_query,
1209         .mtu_set = qede_set_mtu,
1210 };
1211
1212 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
1213         .dev_configure = qede_dev_configure,
1214         .dev_infos_get = qede_dev_info_get,
1215         .rx_queue_setup = qede_rx_queue_setup,
1216         .rx_queue_release = qede_rx_queue_release,
1217         .tx_queue_setup = qede_tx_queue_setup,
1218         .tx_queue_release = qede_tx_queue_release,
1219         .dev_start = qede_dev_start,
1220         .dev_set_link_up = qede_dev_set_link_up,
1221         .dev_set_link_down = qede_dev_set_link_down,
1222         .link_update = qede_link_update,
1223         .promiscuous_enable = qede_promiscuous_enable,
1224         .promiscuous_disable = qede_promiscuous_disable,
1225         .allmulticast_enable = qede_allmulticast_enable,
1226         .allmulticast_disable = qede_allmulticast_disable,
1227         .dev_stop = qede_dev_stop,
1228         .dev_close = qede_dev_close,
1229         .stats_get = qede_get_stats,
1230         .stats_reset = qede_reset_stats,
1231         .xstats_get = qede_get_xstats,
1232         .xstats_reset = qede_reset_xstats,
1233         .xstats_get_names = qede_get_xstats_names,
1234         .vlan_offload_set = qede_vlan_offload_set,
1235         .vlan_filter_set = qede_vlan_filter_set,
1236         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
1237         .rss_hash_update = qede_rss_hash_update,
1238         .rss_hash_conf_get = qede_rss_hash_conf_get,
1239         .reta_update  = qede_rss_reta_update,
1240         .reta_query  = qede_rss_reta_query,
1241         .mtu_set = qede_set_mtu,
1242 };
1243
1244 static void qede_update_pf_params(struct ecore_dev *edev)
1245 {
1246         struct ecore_pf_params pf_params;
1247         /* 32 rx + 32 tx */
1248         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
1249         pf_params.eth_pf_params.num_cons = 64;
1250         qed_ops->common->update_pf_params(edev, &pf_params);
1251 }
1252
1253 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
1254 {
1255         struct rte_pci_device *pci_dev;
1256         struct rte_pci_addr pci_addr;
1257         struct qede_dev *adapter;
1258         struct ecore_dev *edev;
1259         struct qed_dev_eth_info dev_info;
1260         struct qed_slowpath_params params;
1261         static bool do_once = true;
1262         uint8_t bulletin_change;
1263         uint8_t vf_mac[ETHER_ADDR_LEN];
1264         uint8_t is_mac_forced;
1265         bool is_mac_exist;
1266         /* Fix up ecore debug level */
1267         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
1268         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
1269         uint32_t max_mac_addrs;
1270         int rc;
1271
1272         /* Extract key data structures */
1273         adapter = eth_dev->data->dev_private;
1274         edev = &adapter->edev;
1275         pci_addr = eth_dev->pci_dev->addr;
1276
1277         PMD_INIT_FUNC_TRACE(edev);
1278
1279         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
1280                  pci_addr.bus, pci_addr.devid, pci_addr.function,
1281                  eth_dev->data->port_id);
1282
1283         eth_dev->rx_pkt_burst = qede_recv_pkts;
1284         eth_dev->tx_pkt_burst = qede_xmit_pkts;
1285
1286         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
1287                 DP_NOTICE(edev, false,
1288                           "Skipping device init from secondary process\n");
1289                 return 0;
1290         }
1291
1292         pci_dev = eth_dev->pci_dev;
1293
1294         rte_eth_copy_pci_info(eth_dev, pci_dev);
1295
1296         qed_ops = qed_get_eth_ops();
1297         if (!qed_ops) {
1298                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
1299                 return -EINVAL;
1300         }
1301
1302         DP_INFO(edev, "Starting qede probe\n");
1303
1304         rc = qed_ops->common->probe(edev, pci_dev, QED_PROTOCOL_ETH,
1305                                     dp_module, dp_level, is_vf);
1306
1307         if (rc != 0) {
1308                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
1309                 return -ENODEV;
1310         }
1311
1312         qede_update_pf_params(edev);
1313
1314         rte_intr_callback_register(&eth_dev->pci_dev->intr_handle,
1315                                    qede_interrupt_handler, (void *)eth_dev);
1316
1317         if (rte_intr_enable(&eth_dev->pci_dev->intr_handle)) {
1318                 DP_ERR(edev, "rte_intr_enable() failed\n");
1319                 return -ENODEV;
1320         }
1321
1322         /* Start the Slowpath-process */
1323         memset(&params, 0, sizeof(struct qed_slowpath_params));
1324         params.int_mode = ECORE_INT_MODE_MSIX;
1325         params.drv_major = QEDE_MAJOR_VERSION;
1326         params.drv_minor = QEDE_MINOR_VERSION;
1327         params.drv_rev = QEDE_REVISION_VERSION;
1328         params.drv_eng = QEDE_ENGINEERING_VERSION;
1329         strncpy((char *)params.name, "qede LAN", QED_DRV_VER_STR_SIZE);
1330
1331         /* For CMT mode device do periodic polling for slowpath events.
1332          * This is required since uio device uses only one MSI-x
1333          * interrupt vector but we need one for each engine.
1334          */
1335         if (edev->num_hwfns > 1) {
1336                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
1337                                        qede_poll_sp_sb_cb,
1338                                        (void *)eth_dev);
1339                 if (rc != 0) {
1340                         DP_ERR(edev, "Unable to start periodic"
1341                                      " timer rc %d\n", rc);
1342                         return -EINVAL;
1343                 }
1344         }
1345
1346         rc = qed_ops->common->slowpath_start(edev, &params);
1347         if (rc) {
1348                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
1349                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1350                                      (void *)eth_dev);
1351                 return -ENODEV;
1352         }
1353
1354         rc = qed_ops->fill_dev_info(edev, &dev_info);
1355         if (rc) {
1356                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
1357                 qed_ops->common->slowpath_stop(edev);
1358                 qed_ops->common->remove(edev);
1359                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1360                                      (void *)eth_dev);
1361                 return -ENODEV;
1362         }
1363
1364         qede_alloc_etherdev(adapter, &dev_info);
1365
1366         adapter->ops->common->set_id(edev, edev->name, QEDE_DRV_MODULE_VERSION);
1367
1368         if (!is_vf)
1369                 adapter->dev_info.num_mac_addrs =
1370                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
1371                                             ECORE_MAC);
1372         else
1373                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
1374                                              &adapter->dev_info.num_mac_addrs);
1375
1376         /* Allocate memory for storing MAC addr */
1377         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
1378                                         (ETHER_ADDR_LEN *
1379                                         adapter->dev_info.num_mac_addrs),
1380                                         RTE_CACHE_LINE_SIZE);
1381
1382         if (eth_dev->data->mac_addrs == NULL) {
1383                 DP_ERR(edev, "Failed to allocate MAC address\n");
1384                 qed_ops->common->slowpath_stop(edev);
1385                 qed_ops->common->remove(edev);
1386                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
1387                                      (void *)eth_dev);
1388                 return -ENOMEM;
1389         }
1390
1391         if (!is_vf) {
1392                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
1393                                 hw_info.hw_mac_addr,
1394                                 &eth_dev->data->mac_addrs[0]);
1395                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1396                                 &adapter->primary_mac);
1397         } else {
1398                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
1399                                        &bulletin_change);
1400                 if (bulletin_change) {
1401                         is_mac_exist =
1402                             ecore_vf_bulletin_get_forced_mac(
1403                                                 ECORE_LEADING_HWFN(edev),
1404                                                 vf_mac,
1405                                                 &is_mac_forced);
1406                         if (is_mac_exist && is_mac_forced) {
1407                                 DP_INFO(edev, "VF macaddr received from PF\n");
1408                                 ether_addr_copy((struct ether_addr *)&vf_mac,
1409                                                 &eth_dev->data->mac_addrs[0]);
1410                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
1411                                                 &adapter->primary_mac);
1412                         } else {
1413                                 DP_NOTICE(edev, false,
1414                                           "No VF macaddr assigned\n");
1415                         }
1416                 }
1417         }
1418
1419         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
1420
1421         if (do_once) {
1422                 qede_print_adapter_info(adapter);
1423                 do_once = false;
1424         }
1425
1426         adapter->state = QEDE_DEV_INIT;
1427
1428         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
1429                   adapter->primary_mac.addr_bytes[0],
1430                   adapter->primary_mac.addr_bytes[1],
1431                   adapter->primary_mac.addr_bytes[2],
1432                   adapter->primary_mac.addr_bytes[3],
1433                   adapter->primary_mac.addr_bytes[4],
1434                   adapter->primary_mac.addr_bytes[5]);
1435
1436         return rc;
1437 }
1438
1439 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
1440 {
1441         return qede_common_dev_init(eth_dev, 1);
1442 }
1443
1444 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
1445 {
1446         return qede_common_dev_init(eth_dev, 0);
1447 }
1448
1449 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
1450 {
1451         /* only uninitialize in the primary process */
1452         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1453                 return 0;
1454
1455         /* safe to close dev here */
1456         qede_dev_close(eth_dev);
1457
1458         eth_dev->dev_ops = NULL;
1459         eth_dev->rx_pkt_burst = NULL;
1460         eth_dev->tx_pkt_burst = NULL;
1461
1462         if (eth_dev->data->mac_addrs)
1463                 rte_free(eth_dev->data->mac_addrs);
1464
1465         eth_dev->data->mac_addrs = NULL;
1466
1467         return 0;
1468 }
1469
1470 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1471 {
1472         return qede_dev_common_uninit(eth_dev);
1473 }
1474
1475 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
1476 {
1477         return qede_dev_common_uninit(eth_dev);
1478 }
1479
1480 static struct rte_pci_id pci_id_qedevf_map[] = {
1481 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1482         {
1483                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_VF)
1484         },
1485         {
1486                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_IOV)
1487         },
1488         {.vendor_id = 0,}
1489 };
1490
1491 static struct rte_pci_id pci_id_qede_map[] = {
1492 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
1493         {
1494                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980E)
1495         },
1496         {
1497                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_NX2_57980S)
1498         },
1499         {
1500                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_40)
1501         },
1502         {
1503                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_25)
1504         },
1505         {
1506                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_57980S_100)
1507         },
1508         {.vendor_id = 0,}
1509 };
1510
1511 static struct eth_driver rte_qedevf_pmd = {
1512         .pci_drv = {
1513                     .id_table = pci_id_qedevf_map,
1514                     .drv_flags =
1515                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1516                     .probe = rte_eth_dev_pci_probe,
1517                     .remove = rte_eth_dev_pci_remove,
1518                    },
1519         .eth_dev_init = qedevf_eth_dev_init,
1520         .eth_dev_uninit = qedevf_eth_dev_uninit,
1521         .dev_private_size = sizeof(struct qede_dev),
1522 };
1523
1524 static struct eth_driver rte_qede_pmd = {
1525         .pci_drv = {
1526                     .id_table = pci_id_qede_map,
1527                     .drv_flags =
1528                     RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
1529                     .probe = rte_eth_dev_pci_probe,
1530                     .remove = rte_eth_dev_pci_remove,
1531                    },
1532         .eth_dev_init = qede_eth_dev_init,
1533         .eth_dev_uninit = qede_eth_dev_uninit,
1534         .dev_private_size = sizeof(struct qede_dev),
1535 };
1536
1537 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd.pci_drv);
1538 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
1539 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd.pci_drv);
1540 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);