drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes",
 129                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 130         {"rx_multicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 132         {"rx_broadcast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 134         {"rx_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 136         {"rx_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 138         {"rx_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 140
 141         {"tx_unicast_bytes",
 142                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 143         {"tx_multicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 145         {"tx_broadcast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 147         {"tx_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 149         {"tx_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 151         {"tx_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 153
 154         {"rx_64_byte_packets",
 155                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 156         {"rx_65_to_127_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          rx_65_to_127_byte_packets)},
 159         {"rx_128_to_255_byte_packets",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          rx_128_to_255_byte_packets)},
 162         {"rx_256_to_511_byte_packets",
 163                 offsetof(struct ecore_eth_stats_common,
 164                          rx_256_to_511_byte_packets)},
 165         {"rx_512_to_1023_byte_packets",
 166                 offsetof(struct ecore_eth_stats_common,
 167                          rx_512_to_1023_byte_packets)},
 168         {"rx_1024_to_1518_byte_packets",
 169                 offsetof(struct ecore_eth_stats_common,
 170                          rx_1024_to_1518_byte_packets)},
 171         {"tx_64_byte_packets",
 172                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 173         {"tx_65_to_127_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common,
 175                          tx_65_to_127_byte_packets)},
 176         {"tx_128_to_255_byte_packets",
 177                 offsetof(struct ecore_eth_stats_common,
 178                          tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats_common,
 181                          tx_256_to_511_byte_packets)},
 182         {"tx_512_to_1023_byte_packets",
 183                 offsetof(struct ecore_eth_stats_common,
 184                          tx_512_to_1023_byte_packets)},
 185         {"tx_1024_to_1518_byte_packets",
 186                 offsetof(struct ecore_eth_stats_common,
 187                          tx_1024_to_1518_byte_packets)},
 188
 189         {"rx_mac_crtl_frames",
 190                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 191         {"tx_mac_control_frames",
 192                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 193         {"rx_pause_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 195         {"tx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 197         {"rx_priority_flow_control_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 199         {"tx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 201
 202         {"rx_crc_errors",
 203                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 204         {"rx_align_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 206         {"rx_carrier_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 208         {"rx_oversize_packet_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 210         {"rx_jabber_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 212         {"rx_undersize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 214         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 215         {"rx_host_buffer_not_available",
 216                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 217         /* Number of packets discarded because they are bigger than MTU */
 218         {"rx_packet_too_big_discards",
 219                 offsetof(struct ecore_eth_stats_common,
 220                          packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 231         {"tx_error_drop_packets",
 232                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 233
 234         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 235         {"rx_mac_unicast_packets",
 236                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 237         {"rx_mac_multicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 239         {"rx_mac_broadcast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 241         {"rx_mac_frames_ok",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 243         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 244         {"tx_mac_unicast_packets",
 245                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 246         {"tx_mac_multicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 248         {"tx_mac_broadcast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 250
 251         {"lro_coalesced_packets",
 252                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 253         {"lro_coalesced_events",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 255         {"lro_aborts_num",
 256                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 257         {"lro_not_coalesced_packets",
 258                 offsetof(struct ecore_eth_stats_common,
 259                          tpa_not_coalesced_pkts)},
 260         {"lro_coalesced_bytes",
 261                 offsetof(struct ecore_eth_stats_common,
 262                          tpa_coalesced_bytes)},
 263 };
 264
 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 266         {"rx_1519_to_1522_byte_packets",
 267                 offsetof(struct ecore_eth_stats, bb) +
 268                 offsetof(struct ecore_eth_stats_bb,
 269                          rx_1519_to_1522_byte_packets)},
 270         {"rx_1519_to_2047_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_2047_byte_packets)},
 274         {"rx_2048_to_4095_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_2048_to_4095_byte_packets)},
 278         {"rx_4096_to_9216_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_4096_to_9216_byte_packets)},
 282         {"rx_9217_to_16383_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_9217_to_16383_byte_packets)},
 286
 287         {"tx_1519_to_2047_byte_packets",
 288                 offsetof(struct ecore_eth_stats, bb) +
 289                 offsetof(struct ecore_eth_stats_bb,
 290                          tx_1519_to_2047_byte_packets)},
 291         {"tx_2048_to_4095_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_2048_to_4095_byte_packets)},
 295         {"tx_4096_to_9216_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_4096_to_9216_byte_packets)},
 299         {"tx_9217_to_16383_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_9217_to_16383_byte_packets)},
 303
 304         {"tx_lpi_entry_count",
 305                 offsetof(struct ecore_eth_stats, bb) +
 306                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 307         {"tx_total_collisions",
 308                 offsetof(struct ecore_eth_stats, bb) +
 309                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 310 };
 311
 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 313         {"rx_1519_to_max_byte_packets",
 314                 offsetof(struct ecore_eth_stats, ah) +
 315                 offsetof(struct ecore_eth_stats_ah,
 316                          rx_1519_to_max_byte_packets)},
 317         {"tx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          tx_1519_to_max_byte_packets)},
 321 };
 322
 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 324         {"rx_q_segments",
 325                 offsetof(struct qede_rx_queue, rx_segs)},
 326         {"rx_q_hw_errors",
 327                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 328         {"rx_q_allocation_errors",
 329                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 330 };
 331
 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 333 {
 334         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 335 }
 336
 337 static void
 338 qede_interrupt_handler(void *param)
 339 {
 340         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 341         struct qede_dev *qdev = eth_dev->data->dev_private;
 342         struct ecore_dev *edev = &qdev->edev;
 343
 344         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 345         if (rte_intr_enable(eth_dev->intr_handle))
 346                 DP_ERR(edev, "rte_intr_enable failed\n");
 347 }
 348
 349 static void
 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 351 {
 352         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 353         qdev->ops = qed_ops;
 354 }
 355
 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 357 static void qede_print_adapter_info(struct qede_dev *qdev)
 358 {
 359         struct ecore_dev *edev = &qdev->edev;
 360         struct qed_dev_info *info = &qdev->dev_info.common;
 361         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 362         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 363
 364         DP_INFO(edev, "*********************************\n");
 365         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 366         DP_INFO(edev, " Chip details : %s %c%d\n",
 367                   ECORE_IS_BB(edev) ? "BB" : "AH",
 368                   'A' + edev->chip_rev,
 369                   (int)edev->chip_metal);
 370         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 371                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 372         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 373                  ver_str, QEDE_PMD_VERSION);
 374         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 375         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 376
 377         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 378                  "%d.%d.%d.%d",
 379                 (info->mfw_rev >> 24) & 0xff,
 380                 (info->mfw_rev >> 16) & 0xff,
 381                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 382         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 383         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 384         DP_INFO(edev, "*********************************\n");
 385 }
 386 #endif
 387
 388 static int
 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 390 {
 391         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 392         struct ecore_sp_vport_start_params params;
 393         struct ecore_hwfn *p_hwfn;
 394         int rc;
 395         int i;
 396
 397         memset(&params, 0, sizeof(params));
 398         params.vport_id = 0;
 399         params.mtu = mtu;
 400         /* @DPDK - Disable FW placement */
 401         params.zero_placement_offset = 1;
 402         for_each_hwfn(edev, i) {
 403                 p_hwfn = &edev->hwfns[i];
 404                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 405                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 406                 rc = ecore_sp_vport_start(p_hwfn, &params);
 407                 if (rc != ECORE_SUCCESS) {
 408                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 409                         return rc;
 410                 }
 411         }
 412         ecore_reset_vport_stats(edev);
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 static int
 419 qede_stop_vport(struct ecore_dev *edev)
 420 {
 421         struct ecore_hwfn *p_hwfn;
 422         uint8_t vport_id;
 423         int rc;
 424         int i;
 425
 426         vport_id = 0;
 427         for_each_hwfn(edev, i) {
 428                 p_hwfn = &edev->hwfns[i];
 429                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 430                                          vport_id);
 431                 if (rc != ECORE_SUCCESS) {
 432                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 433                         return rc;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Activate or deactivate vport via vport-update */
 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_hwfn *p_hwfn;
 447         uint8_t i;
 448         int rc = -1;
 449
 450         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 451         params.vport_id = 0;
 452         params.update_vport_active_rx_flg = 1;
 453         params.update_vport_active_tx_flg = 1;
 454         params.vport_active_rx_flg = flg;
 455         params.vport_active_tx_flg = flg;
 456         for_each_hwfn(edev, i) {
 457                 p_hwfn = &edev->hwfns[i];
 458                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 459                 rc = ecore_sp_vport_update(p_hwfn, &params,
 460                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 461                 if (rc != ECORE_SUCCESS) {
 462                         DP_ERR(edev, "Failed to update vport\n");
 463                         break;
 464                 }
 465         }
 466         DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
 467         return rc;
 468 }
 469
 470 static void
 471 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 472                            uint16_t mtu, bool enable)
 473 {
 474         /* Enable LRO in split mode */
 475         sge_tpa_params->tpa_ipv4_en_flg = enable;
 476         sge_tpa_params->tpa_ipv6_en_flg = enable;
 477         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 478         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 479         /* set if tpa enable changes */
 480         sge_tpa_params->update_tpa_en_flg = 1;
 481         /* set if tpa parameters should be handled */
 482         sge_tpa_params->update_tpa_param_flg = enable;
 483
 484         sge_tpa_params->max_buffers_per_cqe = 20;
 485         /* Enable TPA in split mode. In this mode each TPA segment
 486          * starts on the new BD, so there is one BD per segment.
 487          */
 488         sge_tpa_params->tpa_pkt_split_flg = 1;
 489         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 490         sge_tpa_params->tpa_gro_consistent_flg = 0;
 491         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 492         sge_tpa_params->tpa_max_size = 0x7FFF;
 493         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 494         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 495 }
 496
 497 /* Enable/disable LRO via vport-update */
 498 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 499 {
 500         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 501         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 502         struct ecore_sp_vport_update_params params;
 503         struct ecore_sge_tpa_params tpa_params;
 504         struct ecore_hwfn *p_hwfn;
 505         int rc;
 506         int i;
 507
 508         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 509         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 510         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 511         params.vport_id = 0;
 512         params.sge_tpa_params = &tpa_params;
 513         for_each_hwfn(edev, i) {
 514                 p_hwfn = &edev->hwfns[i];
 515                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 516                 rc = ecore_sp_vport_update(p_hwfn, &params,
 517                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 518                 if (rc != ECORE_SUCCESS) {
 519                         DP_ERR(edev, "Failed to update LRO\n");
 520                         return -1;
 521                 }
 522         }
 523         qdev->enable_lro = flg;
 524         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 525
 526         return 0;
 527 }
 528
 529 /* Update MTU via vport-update without doing port restart.
 530  * The vport must be deactivated before calling this API.
 531  */
 532 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 533 {
 534         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 535         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 536         struct ecore_sp_vport_update_params params;
 537         struct ecore_hwfn *p_hwfn;
 538         int rc;
 539         int i;
 540
 541         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 542         params.vport_id = 0;
 543         params.mtu = mtu;
 544         params.vport_id = 0;
 545         for_each_hwfn(edev, i) {
 546                 p_hwfn = &edev->hwfns[i];
 547                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 548                 rc = ecore_sp_vport_update(p_hwfn, &params,
 549                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 550                 if (rc != ECORE_SUCCESS) {
 551                         DP_ERR(edev, "Failed to update MTU\n");
 552                         return -1;
 553                 }
 554         }
 555         DP_INFO(edev, "MTU updated to %u\n", mtu);
 556
 557         return 0;
 558 }
 559
 560 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 561 {
 562         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 563         ucast->is_rx_filter = true;
 564         ucast->is_tx_filter = true;
 565         /* ucast->assert_on_error = true; - For debug */
 566 }
 567
 568 static int
 569 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 570                              enum qed_filter_rx_mode_type type)
 571 {
 572         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 573         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 574         struct ecore_filter_accept_flags flags;
 575
 576         memset(&flags, 0, sizeof(flags));
 577
 578         flags.update_rx_mode_config = 1;
 579         flags.update_tx_mode_config = 1;
 580         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 581                 ECORE_ACCEPT_MCAST_MATCHED |
 582                 ECORE_ACCEPT_BCAST;
 583
 584         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 585                 ECORE_ACCEPT_MCAST_MATCHED |
 586                 ECORE_ACCEPT_BCAST;
 587
 588         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 589                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 590                 if (IS_VF(edev)) {
 591                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 592                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 593                 }
 594         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 595                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 596         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 597                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 598                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 599                         ECORE_ACCEPT_MCAST_UNMATCHED;
 600         }
 601
 602         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 603                         ECORE_SPQ_MODE_CB, NULL);
 604 }
 605
 606 static int
 607 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 608                   bool enable, bool mask)
 609 {
 610         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 611         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 612         enum _ecore_status_t rc = ECORE_INVAL;
 613         struct ecore_ptt *p_ptt;
 614         struct ecore_tunnel_info tunn;
 615         struct ecore_hwfn *p_hwfn;
 616         int i;
 617
 618         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 619         tunn.vxlan.b_update_mode = enable;
 620         tunn.vxlan.b_mode_enabled = mask;
 621         tunn.b_update_rx_cls = true;
 622         tunn.b_update_tx_cls = true;
 623         tunn.vxlan.tun_cls = clss;
 624
 625         for_each_hwfn(edev, i) {
 626                 p_hwfn = &edev->hwfns[i];
 627                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 628                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 629                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
 630                 if (rc != ECORE_SUCCESS) {
 631                         DP_ERR(edev, "Failed to update tunn_clss %u\n",
 632                                         tunn.vxlan.tun_cls);
 633                         break;
 634                 }
 635         }
 636
 637         if (rc == ECORE_SUCCESS) {
 638                 qdev->vxlan.enable = enable;
 639                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 640                 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
 641         }
 642
 643         return rc;
 644 }
 645
 646 static int
 647 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 648                   bool add)
 649 {
 650         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 651         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 652         struct qede_ucast_entry *tmp = NULL;
 653         struct qede_ucast_entry *u;
 654         struct ether_addr *mac_addr;
 655
 656         mac_addr  = (struct ether_addr *)ucast->mac;
 657         if (add) {
 658                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 659                         if ((memcmp(mac_addr, &tmp->mac,
 660                                     ETHER_ADDR_LEN) == 0) &&
 661                              ucast->vni == tmp->vni &&
 662                              ucast->vlan == tmp->vlan) {
 663                                 DP_ERR(edev, "Unicast MAC is already added"
 664                                        " with vlan = %u, vni = %u\n",
 665                                        ucast->vlan,  ucast->vni);
 666                                         return -EEXIST;
 667                         }
 668                 }
 669                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 670                                RTE_CACHE_LINE_SIZE);
 671                 if (!u) {
 672                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 673                         return -ENOMEM;
 674                 }
 675                 ether_addr_copy(mac_addr, &u->mac);
 676                 u->vlan = ucast->vlan;
 677                 u->vni = ucast->vni;
 678                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 679                 qdev->num_uc_addr++;
 680         } else {
 681                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 682                         if ((memcmp(mac_addr, &tmp->mac,
 683                                     ETHER_ADDR_LEN) == 0) &&
 684                             ucast->vlan == tmp->vlan      &&
 685                             ucast->vni == tmp->vni)
 686                         break;
 687                 }
 688                 if (tmp == NULL) {
 689                         DP_INFO(edev, "Unicast MAC is not found\n");
 690                         return -EINVAL;
 691                 }
 692                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 693                 qdev->num_uc_addr--;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int
 700 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 701                   bool add)
 702 {
 703         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 704         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 705         struct ether_addr *mac_addr;
 706         struct qede_mcast_entry *tmp = NULL;
 707         struct qede_mcast_entry *m;
 708
 709         mac_addr  = (struct ether_addr *)mcast->mac;
 710         if (add) {
 711                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 712                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 713                                 DP_ERR(edev,
 714                                         "Multicast MAC is already added\n");
 715                                 return -EEXIST;
 716                         }
 717                 }
 718                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 719                         RTE_CACHE_LINE_SIZE);
 720                 if (!m) {
 721                         DP_ERR(edev,
 722                                 "Did not allocate memory for mcast\n");
 723                         return -ENOMEM;
 724                 }
 725                 ether_addr_copy(mac_addr, &m->mac);
 726                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 727                 qdev->num_mc_addr++;
 728         } else {
 729                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 730                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 731                                 break;
 732                 }
 733                 if (tmp == NULL) {
 734                         DP_INFO(edev, "Multicast mac is not found\n");
 735                         return -EINVAL;
 736                 }
 737                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 738                              qede_mcast_entry, list);
 739                 qdev->num_mc_addr--;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static enum _ecore_status_t
 746 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 747                  bool add)
 748 {
 749         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 750         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 751         enum _ecore_status_t rc;
 752         struct ecore_filter_mcast mcast;
 753         struct qede_mcast_entry *tmp;
 754         uint16_t j = 0;
 755
 756         /* Multicast */
 757         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 758                 if (add) {
 759                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 760                                 DP_ERR(edev,
 761                                        "Mcast filter table limit exceeded, "
 762                                        "Please enable mcast promisc mode\n");
 763                                 return -ECORE_INVAL;
 764                         }
 765                 }
 766                 rc = qede_mcast_filter(eth_dev, ucast, add);
 767                 if (rc == 0) {
 768                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 769                         memset(&mcast, 0, sizeof(mcast));
 770                         mcast.num_mc_addrs = qdev->num_mc_addr;
 771                         mcast.opcode = ECORE_FILTER_ADD;
 772                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 773                                 ether_addr_copy(&tmp->mac,
 774                                         (struct ether_addr *)&mcast.mac[j]);
 775                                 j++;
 776                         }
 777                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 778                                                     ECORE_SPQ_MODE_CB, NULL);
 779                 }
 780                 if (rc != ECORE_SUCCESS) {
 781                         DP_ERR(edev, "Failed to add multicast filter"
 782                                " rc = %d, op = %d\n", rc, add);
 783                 }
 784         } else { /* Unicast */
 785                 if (add) {
 786                         if (qdev->num_uc_addr >=
 787                             qdev->dev_info.num_mac_filters) {
 788                                 DP_ERR(edev,
 789                                        "Ucast filter table limit exceeded,"
 790                                        " Please enable promisc mode\n");
 791                                 return -ECORE_INVAL;
 792                         }
 793                 }
 794                 rc = qede_ucast_filter(eth_dev, ucast, add);
 795                 if (rc == 0)
 796                         rc = ecore_filter_ucast_cmd(edev, ucast,
 797                                                     ECORE_SPQ_MODE_CB, NULL);
 798                 if (rc != ECORE_SUCCESS) {
 799                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 800                                rc, add);
 801                 }
 802         }
 803
 804         return rc;
 805 }
 806
 807 static int
 808 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 809                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 810 {
 811         struct ecore_filter_ucast ucast;
 812         int re;
 813
 814         qede_set_ucast_cmn_params(&ucast);
 815         ucast.type = ECORE_FILTER_MAC;
 816         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 817         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 818         return re;
 819 }
 820
 821 static void
 822 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 823 {
 824         struct qede_dev *qdev = eth_dev->data->dev_private;
 825         struct ecore_dev *edev = &qdev->edev;
 826         struct ecore_filter_ucast ucast;
 827
 828         PMD_INIT_FUNC_TRACE(edev);
 829
 830         if (index >= qdev->dev_info.num_mac_filters) {
 831                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 832                        index, qdev->dev_info.num_mac_filters);
 833                 return;
 834         }
 835
 836         qede_set_ucast_cmn_params(&ucast);
 837         ucast.opcode = ECORE_FILTER_REMOVE;
 838         ucast.type = ECORE_FILTER_MAC;
 839
 840         /* Use the index maintained by rte */
 841         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 842                         (struct ether_addr *)&ucast.mac);
 843
 844         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 845 }
 846
 847 static void
 848 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 849 {
 850         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 851         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 852
 853         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 854                                                mac_addr->addr_bytes)) {
 855                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 856                 ether_addr_copy(&qdev->primary_mac,
 857                                 &eth_dev->data->mac_addrs[0]);
 858                 return;
 859         }
 860
 861         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 862 }
 863
 864 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 865 {
 866         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 867         struct ecore_sp_vport_update_params params;
 868         struct ecore_hwfn *p_hwfn;
 869         uint8_t i;
 870         int rc;
 871
 872         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 873         params.vport_id = 0;
 874         params.update_accept_any_vlan_flg = 1;
 875         params.accept_any_vlan = flg;
 876         for_each_hwfn(edev, i) {
 877                 p_hwfn = &edev->hwfns[i];
 878                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 879                 rc = ecore_sp_vport_update(p_hwfn, &params,
 880                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 881                 if (rc != ECORE_SUCCESS) {
 882                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 883                         return;
 884                 }
 885         }
 886
 887         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 888 }
 889
 890 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 891 {
 892         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 893         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 894         struct ecore_sp_vport_update_params params;
 895         struct ecore_hwfn *p_hwfn;
 896         uint8_t i;
 897         int rc;
 898
 899         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 900         params.vport_id = 0;
 901         params.update_inner_vlan_removal_flg = 1;
 902         params.inner_vlan_removal_flg = flg;
 903         for_each_hwfn(edev, i) {
 904                 p_hwfn = &edev->hwfns[i];
 905                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 906                 rc = ecore_sp_vport_update(p_hwfn, &params,
 907                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 908                 if (rc != ECORE_SUCCESS) {
 909                         DP_ERR(edev, "Failed to update vport\n");
 910                         return -1;
 911                 }
 912         }
 913
 914         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 915         return 0;
 916 }
 917
 918 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 919                                 uint16_t vlan_id, int on)
 920 {
 921         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 922         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 923         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 924         struct qede_vlan_entry *tmp = NULL;
 925         struct qede_vlan_entry *vlan;
 926         struct ecore_filter_ucast ucast;
 927         int rc;
 928
 929         if (on) {
 930                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 931                         DP_ERR(edev, "Reached max VLAN filter limit"
 932                                       " enabling accept_any_vlan\n");
 933                         qede_config_accept_any_vlan(qdev, true);
 934                         return 0;
 935                 }
 936
 937                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 938                         if (tmp->vid == vlan_id) {
 939                                 DP_ERR(edev, "VLAN %u already configured\n",
 940                                        vlan_id);
 941                                 return -EEXIST;
 942                         }
 943                 }
 944
 945                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 946                                   RTE_CACHE_LINE_SIZE);
 947
 948                 if (!vlan) {
 949                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 950                         return -ENOMEM;
 951                 }
 952
 953                 qede_set_ucast_cmn_params(&ucast);
 954                 ucast.opcode = ECORE_FILTER_ADD;
 955                 ucast.type = ECORE_FILTER_VLAN;
 956                 ucast.vlan = vlan_id;
 957                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 958                                             NULL);
 959                 if (rc != 0) {
 960                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 961                                rc);
 962                         rte_free(vlan);
 963                 } else {
 964                         vlan->vid = vlan_id;
 965                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 966                         qdev->configured_vlans++;
 967                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 968                                 vlan_id, qdev->configured_vlans);
 969                 }
 970         } else {
 971                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 972                         if (tmp->vid == vlan_id)
 973                                 break;
 974                 }
 975
 976                 if (!tmp) {
 977                         if (qdev->configured_vlans == 0) {
 978                                 DP_INFO(edev,
 979                                         "No VLAN filters configured yet\n");
 980                                 return 0;
 981                         }
 982
 983                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 984                         return -EINVAL;
 985                 }
 986
 987                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 988
 989                 qede_set_ucast_cmn_params(&ucast);
 990                 ucast.opcode = ECORE_FILTER_REMOVE;
 991                 ucast.type = ECORE_FILTER_VLAN;
 992                 ucast.vlan = vlan_id;
 993                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 994                                             NULL);
 995                 if (rc != 0) {
 996                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 997                                vlan_id, rc);
 998                 } else {
 999                         qdev->configured_vlans--;
1000                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1001                                 vlan_id, qdev->configured_vlans);
1002                 }
1003         }
1004
1005         return rc;
1006 }
1007
1008 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1009 {
1010         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1011         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1012         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1013
1014         if (mask & ETH_VLAN_STRIP_MASK) {
1015                 if (rxmode->hw_vlan_strip)
1016                         (void)qede_vlan_stripping(eth_dev, 1);
1017                 else
1018                         (void)qede_vlan_stripping(eth_dev, 0);
1019         }
1020
1021         if (mask & ETH_VLAN_FILTER_MASK) {
1022                 /* VLAN filtering kicks in when a VLAN is added */
1023                 if (rxmode->hw_vlan_filter) {
1024                         qede_vlan_filter_set(eth_dev, 0, 1);
1025                 } else {
1026                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1027                                 DP_ERR(edev,
1028                                   " Please remove existing VLAN filters"
1029                                   " before disabling VLAN filtering\n");
1030                                 /* Signal app that VLAN filtering is still
1031                                  * enabled
1032                                  */
1033                                 rxmode->hw_vlan_filter = true;
1034                         } else {
1035                                 qede_vlan_filter_set(eth_dev, 0, 0);
1036                         }
1037                 }
1038         }
1039
1040         if (mask & ETH_VLAN_EXTEND_MASK)
1041                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1042                         " and classification is based on outer tag only\n");
1043
1044         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1045                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1046 }
1047
1048 static void qede_prandom_bytes(uint32_t *buff)
1049 {
1050         uint8_t i;
1051
1052         srand((unsigned int)time(NULL));
1053         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1054                 buff[i] = rand();
1055 }
1056
1057 int qede_config_rss(struct rte_eth_dev *eth_dev)
1058 {
1059         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1060 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1061         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1062 #endif
1063         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1064         struct rte_eth_rss_reta_entry64 reta_conf[2];
1065         struct rte_eth_rss_conf rss_conf;
1066         uint32_t i, id, pos, q;
1067
1068         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1069         if (!rss_conf.rss_key) {
1070                 DP_INFO(edev, "Applying driver default key\n");
1071                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1072                 qede_prandom_bytes(&def_rss_key[0]);
1073                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1074         }
1075
1076         /* Configure RSS hash */
1077         if (qede_rss_hash_update(eth_dev, &rss_conf))
1078                 return -EINVAL;
1079
1080         /* Configure default RETA */
1081         memset(reta_conf, 0, sizeof(reta_conf));
1082         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1083                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1084
1085         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1086                 id = i / RTE_RETA_GROUP_SIZE;
1087                 pos = i % RTE_RETA_GROUP_SIZE;
1088                 q = i % QEDE_RSS_COUNT(qdev);
1089                 reta_conf[id].reta[pos] = q;
1090         }
1091         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1092                                  ECORE_RSS_IND_TABLE_SIZE))
1093                 return -EINVAL;
1094
1095         return 0;
1096 }
1097
1098 static void qede_fastpath_start(struct ecore_dev *edev)
1099 {
1100         struct ecore_hwfn *p_hwfn;
1101         int i;
1102
1103         for_each_hwfn(edev, i) {
1104                 p_hwfn = &edev->hwfns[i];
1105                 ecore_hw_start_fastpath(p_hwfn);
1106         }
1107 }
1108
1109 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1110 {
1111         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1112         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1113         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1114
1115         PMD_INIT_FUNC_TRACE(edev);
1116
1117         /* Update MTU only if it has changed */
1118         if (qdev->mtu != qdev->new_mtu) {
1119                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1120                         goto err;
1121                 qdev->mtu = qdev->new_mtu;
1122         }
1123
1124         /* Configure TPA parameters */
1125         if (rxmode->enable_lro) {
1126                 if (qede_enable_tpa(eth_dev, true))
1127                         return -EINVAL;
1128                 /* Enable scatter mode for LRO */
1129                 if (!rxmode->enable_scatter)
1130                         eth_dev->data->scattered_rx = 1;
1131         }
1132
1133         /* Start queues */
1134         if (qede_start_queues(eth_dev))
1135                 goto err;
1136
1137         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1138          * enabling RSS. Hence RSS configuration is deferred upto this point.
1139          * Also, we would like to retain similar behavior in PF case, so we
1140          * don't do PF/VF specific check here.
1141          */
1142         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1143                 if (qede_config_rss(eth_dev))
1144                         goto err;
1145
1146         /* Enable vport*/
1147         if (qede_activate_vport(eth_dev, true))
1148                 goto err;
1149
1150         /* Bring-up the link */
1151         qede_dev_set_link_state(eth_dev, true);
1152
1153         /* Start/resume traffic */
1154         qede_fastpath_start(edev);
1155
1156         DP_INFO(edev, "Device started\n");
1157
1158         return 0;
1159 err:
1160         DP_ERR(edev, "Device start fails\n");
1161         return -1; /* common error code is < 0 */
1162 }
1163
1164 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1165 {
1166         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1167         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1168
1169         PMD_INIT_FUNC_TRACE(edev);
1170
1171         /* Disable vport */
1172         if (qede_activate_vport(eth_dev, false))
1173                 return;
1174
1175         if (qdev->enable_lro)
1176                 qede_enable_tpa(eth_dev, false);
1177
1178         /* Stop queues */
1179         qede_stop_queues(eth_dev);
1180
1181         /* Disable traffic */
1182         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1183
1184         /* Bring the link down */
1185         qede_dev_set_link_state(eth_dev, false);
1186
1187         DP_INFO(edev, "Device is stopped\n");
1188 }
1189
1190 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1191 {
1192         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1193         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1194         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1195
1196         PMD_INIT_FUNC_TRACE(edev);
1197
1198         /* Check requirements for 100G mode */
1199         if (ECORE_IS_CMT(edev)) {
1200                 if (eth_dev->data->nb_rx_queues < 2 ||
1201                                 eth_dev->data->nb_tx_queues < 2) {
1202                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1203                         return -EINVAL;
1204                 }
1205
1206                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1207                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1208                         DP_ERR(edev,
1209                                         "100G mode needs even no. of RX/TX queues\n");
1210                         return -EINVAL;
1211                 }
1212         }
1213
1214         /* Sanity checks and throw warnings */
1215         if (rxmode->enable_scatter)
1216                 eth_dev->data->scattered_rx = 1;
1217
1218         if (!rxmode->hw_strip_crc)
1219                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1220
1221         if (!rxmode->hw_ip_checksum)
1222                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1223                                 "in hw\n");
1224         if (rxmode->header_split)
1225                 DP_INFO(edev, "Header split enable is not supported\n");
1226         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1227                                 ETH_MQ_RX_RSS)) {
1228                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1229                 return -ENOTSUP;
1230         }
1231         /* Flow director mode check */
1232         if (qede_check_fdir_support(eth_dev))
1233                 return -ENOTSUP;
1234
1235         /* Deallocate resources if held previously. It is needed only if the
1236          * queue count has been changed from previous configuration. If its
1237          * going to change then it means RX/TX queue setup will be called
1238          * again and the fastpath pointers will be reinitialized there.
1239          */
1240         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1241             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1242                 qede_dealloc_fp_resc(eth_dev);
1243                 /* Proceed with updated queue count */
1244                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1245                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1246                 if (qede_alloc_fp_resc(qdev))
1247                         return -ENOMEM;
1248         }
1249
1250         /* VF's MTU has to be set using vport-start where as
1251          * PF's MTU can be updated via vport-update.
1252          */
1253         if (IS_VF(edev)) {
1254                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1255                         return -1;
1256         } else {
1257                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1258                         return -1;
1259         }
1260
1261         qdev->mtu = rxmode->max_rx_pkt_len;
1262         qdev->new_mtu = qdev->mtu;
1263
1264         /* Enable VLAN offloads by default */
1265         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1266                         ETH_VLAN_FILTER_MASK |
1267                         ETH_VLAN_EXTEND_MASK);
1268
1269         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1270                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1271
1272         return 0;
1273 }
1274
1275 /* Info about HW descriptor ring limitations */
1276 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1277         .nb_max = 0x8000, /* 32K */
1278         .nb_min = 128,
1279         .nb_align = 128 /* lowest common multiple */
1280 };
1281
1282 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1283         .nb_max = 0x8000, /* 32K */
1284         .nb_min = 256,
1285         .nb_align = 256,
1286         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1287         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1288 };
1289
1290 static void
1291 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1292                   struct rte_eth_dev_info *dev_info)
1293 {
1294         struct qede_dev *qdev = eth_dev->data->dev_private;
1295         struct ecore_dev *edev = &qdev->edev;
1296         struct qed_link_output link;
1297         uint32_t speed_cap = 0;
1298
1299         PMD_INIT_FUNC_TRACE(edev);
1300
1301         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1302         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1303         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1304         dev_info->rx_desc_lim = qede_rx_desc_lim;
1305         dev_info->tx_desc_lim = qede_tx_desc_lim;
1306
1307         if (IS_PF(edev))
1308                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1309                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1310         else
1311                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1312                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1313         dev_info->max_tx_queues = dev_info->max_rx_queues;
1314
1315         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1316         dev_info->max_vfs = 0;
1317         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1318         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1319         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1320
1321         dev_info->default_txconf = (struct rte_eth_txconf) {
1322                 .txq_flags = QEDE_TXQ_FLAGS,
1323         };
1324
1325         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1326                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1327                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1328                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1329                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1330                                      DEV_RX_OFFLOAD_TCP_LRO);
1331
1332         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1333                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1334                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1335                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1336                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1337                                      DEV_TX_OFFLOAD_TCP_TSO |
1338                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1339
1340         memset(&link, 0, sizeof(struct qed_link_output));
1341         qdev->ops->common->get_link(edev, &link);
1342         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1343                 speed_cap |= ETH_LINK_SPEED_1G;
1344         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1345                 speed_cap |= ETH_LINK_SPEED_10G;
1346         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1347                 speed_cap |= ETH_LINK_SPEED_25G;
1348         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1349                 speed_cap |= ETH_LINK_SPEED_40G;
1350         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1351                 speed_cap |= ETH_LINK_SPEED_50G;
1352         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1353                 speed_cap |= ETH_LINK_SPEED_100G;
1354         dev_info->speed_capa = speed_cap;
1355 }
1356
1357 /* return 0 means link status changed, -1 means not changed */
1358 static int
1359 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1360 {
1361         struct qede_dev *qdev = eth_dev->data->dev_private;
1362         struct ecore_dev *edev = &qdev->edev;
1363         uint16_t link_duplex;
1364         struct qed_link_output link;
1365         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1366
1367         memset(&link, 0, sizeof(struct qed_link_output));
1368         qdev->ops->common->get_link(edev, &link);
1369
1370         /* Link Speed */
1371         curr->link_speed = link.speed;
1372
1373         /* Link Mode */
1374         switch (link.duplex) {
1375         case QEDE_DUPLEX_HALF:
1376                 link_duplex = ETH_LINK_HALF_DUPLEX;
1377                 break;
1378         case QEDE_DUPLEX_FULL:
1379                 link_duplex = ETH_LINK_FULL_DUPLEX;
1380                 break;
1381         case QEDE_DUPLEX_UNKNOWN:
1382         default:
1383                 link_duplex = -1;
1384         }
1385         curr->link_duplex = link_duplex;
1386
1387         /* Link Status */
1388         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1389
1390         /* AN */
1391         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1392                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1393
1394         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1395                 curr->link_speed, curr->link_duplex,
1396                 curr->link_autoneg, curr->link_status);
1397
1398         /* return 0 means link status changed, -1 means not changed */
1399         return ((curr->link_status == link.link_up) ? -1 : 0);
1400 }
1401
1402 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1403 {
1404 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1405         struct qede_dev *qdev = eth_dev->data->dev_private;
1406         struct ecore_dev *edev = &qdev->edev;
1407
1408         PMD_INIT_FUNC_TRACE(edev);
1409 #endif
1410
1411         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1412
1413         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1414                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1415
1416         qed_configure_filter_rx_mode(eth_dev, type);
1417 }
1418
1419 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1420 {
1421 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1422         struct qede_dev *qdev = eth_dev->data->dev_private;
1423         struct ecore_dev *edev = &qdev->edev;
1424
1425         PMD_INIT_FUNC_TRACE(edev);
1426 #endif
1427
1428         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1429                 qed_configure_filter_rx_mode(eth_dev,
1430                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1431         else
1432                 qed_configure_filter_rx_mode(eth_dev,
1433                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1434 }
1435
1436 static void qede_poll_sp_sb_cb(void *param)
1437 {
1438         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1439         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1440         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1441         int rc;
1442
1443         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1444         qede_interrupt_action(&edev->hwfns[1]);
1445
1446         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1447                                qede_poll_sp_sb_cb,
1448                                (void *)eth_dev);
1449         if (rc != 0) {
1450                 DP_ERR(edev, "Unable to start periodic"
1451                              " timer rc %d\n", rc);
1452                 assert(false && "Unable to start periodic timer");
1453         }
1454 }
1455
1456 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1457 {
1458         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1459         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1460         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1461
1462         PMD_INIT_FUNC_TRACE(edev);
1463
1464         /* dev_stop() shall cleanup fp resources in hw but without releasing
1465          * dma memories and sw structures so that dev_start() can be called
1466          * by the app without reconfiguration. However, in dev_close() we
1467          * can release all the resources and device can be brought up newly
1468          */
1469         if (eth_dev->data->dev_started)
1470                 qede_dev_stop(eth_dev);
1471
1472         qede_stop_vport(edev);
1473         qede_fdir_dealloc_resc(eth_dev);
1474         qede_dealloc_fp_resc(eth_dev);
1475
1476         eth_dev->data->nb_rx_queues = 0;
1477         eth_dev->data->nb_tx_queues = 0;
1478
1479         qdev->ops->common->slowpath_stop(edev);
1480         qdev->ops->common->remove(edev);
1481         rte_intr_disable(&pci_dev->intr_handle);
1482         rte_intr_callback_unregister(&pci_dev->intr_handle,
1483                                      qede_interrupt_handler, (void *)eth_dev);
1484         if (ECORE_IS_CMT(edev))
1485                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1486 }
1487
1488 static int
1489 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1490 {
1491         struct qede_dev *qdev = eth_dev->data->dev_private;
1492         struct ecore_dev *edev = &qdev->edev;
1493         struct ecore_eth_stats stats;
1494         unsigned int i = 0, j = 0, qid;
1495         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1496         struct qede_tx_queue *txq;
1497
1498         ecore_get_vport_stats(edev, &stats);
1499
1500         /* RX Stats */
1501         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1502             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1503
1504         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1505             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1506
1507         eth_stats->ierrors = stats.common.rx_crc_errors +
1508             stats.common.rx_align_errors +
1509             stats.common.rx_carrier_errors +
1510             stats.common.rx_oversize_packets +
1511             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1512
1513         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1514
1515         eth_stats->imissed = stats.common.mftag_filter_discards +
1516             stats.common.mac_filter_discards +
1517             stats.common.no_buff_discards +
1518             stats.common.brb_truncates + stats.common.brb_discards;
1519
1520         /* TX stats */
1521         eth_stats->opackets = stats.common.tx_ucast_pkts +
1522             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1523
1524         eth_stats->obytes = stats.common.tx_ucast_bytes +
1525             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1526
1527         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1528
1529         /* Queue stats */
1530         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1531                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1532         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1533                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1534         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1535             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1536                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1537                        "Not all the queue stats will be displayed. Set"
1538                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1539                        " appropriately and retry.\n");
1540
1541         for_each_rss(qid) {
1542                 eth_stats->q_ipackets[i] =
1543                         *(uint64_t *)(
1544                                 ((char *)(qdev->fp_array[qid].rxq)) +
1545                                 offsetof(struct qede_rx_queue,
1546                                 rcv_pkts));
1547                 eth_stats->q_errors[i] =
1548                         *(uint64_t *)(
1549                                 ((char *)(qdev->fp_array[qid].rxq)) +
1550                                 offsetof(struct qede_rx_queue,
1551                                 rx_hw_errors)) +
1552                         *(uint64_t *)(
1553                                 ((char *)(qdev->fp_array[qid].rxq)) +
1554                                 offsetof(struct qede_rx_queue,
1555                                 rx_alloc_errors));
1556                 i++;
1557                 if (i == rxq_stat_cntrs)
1558                         break;
1559         }
1560
1561         for_each_tss(qid) {
1562                 txq = qdev->fp_array[qid].txq;
1563                 eth_stats->q_opackets[j] =
1564                         *((uint64_t *)(uintptr_t)
1565                                 (((uint64_t)(uintptr_t)(txq)) +
1566                                  offsetof(struct qede_tx_queue,
1567                                           xmit_pkts)));
1568                 j++;
1569                 if (j == txq_stat_cntrs)
1570                         break;
1571         }
1572
1573         return 0;
1574 }
1575
1576 static unsigned
1577 qede_get_xstats_count(struct qede_dev *qdev) {
1578         if (ECORE_IS_BB(&qdev->edev))
1579                 return RTE_DIM(qede_xstats_strings) +
1580                        RTE_DIM(qede_bb_xstats_strings) +
1581                        (RTE_DIM(qede_rxq_xstats_strings) *
1582                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1583                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1584         else
1585                 return RTE_DIM(qede_xstats_strings) +
1586                        RTE_DIM(qede_ah_xstats_strings) +
1587                        (RTE_DIM(qede_rxq_xstats_strings) *
1588                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1589                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1590 }
1591
1592 static int
1593 qede_get_xstats_names(struct rte_eth_dev *dev,
1594                       struct rte_eth_xstat_name *xstats_names,
1595                       __rte_unused unsigned int limit)
1596 {
1597         struct qede_dev *qdev = dev->data->dev_private;
1598         struct ecore_dev *edev = &qdev->edev;
1599         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1600         unsigned int i, qid, stat_idx = 0;
1601         unsigned int rxq_stat_cntrs;
1602
1603         if (xstats_names != NULL) {
1604                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1605                         snprintf(xstats_names[stat_idx].name,
1606                                 sizeof(xstats_names[stat_idx].name),
1607                                 "%s",
1608                                 qede_xstats_strings[i].name);
1609                         stat_idx++;
1610                 }
1611
1612                 if (ECORE_IS_BB(edev)) {
1613                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1614                                 snprintf(xstats_names[stat_idx].name,
1615                                         sizeof(xstats_names[stat_idx].name),
1616                                         "%s",
1617                                         qede_bb_xstats_strings[i].name);
1618                                 stat_idx++;
1619                         }
1620                 } else {
1621                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1622                                 snprintf(xstats_names[stat_idx].name,
1623                                         sizeof(xstats_names[stat_idx].name),
1624                                         "%s",
1625                                         qede_ah_xstats_strings[i].name);
1626                                 stat_idx++;
1627                         }
1628                 }
1629
1630                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1631                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1632                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1633                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1634                                 snprintf(xstats_names[stat_idx].name,
1635                                         sizeof(xstats_names[stat_idx].name),
1636                                         "%.4s%d%s",
1637                                         qede_rxq_xstats_strings[i].name, qid,
1638                                         qede_rxq_xstats_strings[i].name + 4);
1639                                 stat_idx++;
1640                         }
1641                 }
1642         }
1643
1644         return stat_cnt;
1645 }
1646
1647 static int
1648 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1649                 unsigned int n)
1650 {
1651         struct qede_dev *qdev = dev->data->dev_private;
1652         struct ecore_dev *edev = &qdev->edev;
1653         struct ecore_eth_stats stats;
1654         const unsigned int num = qede_get_xstats_count(qdev);
1655         unsigned int i, qid, stat_idx = 0;
1656         unsigned int rxq_stat_cntrs;
1657
1658         if (n < num)
1659                 return num;
1660
1661         ecore_get_vport_stats(edev, &stats);
1662
1663         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1664                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1665                                              qede_xstats_strings[i].offset);
1666                 xstats[stat_idx].id = stat_idx;
1667                 stat_idx++;
1668         }
1669
1670         if (ECORE_IS_BB(edev)) {
1671                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1672                         xstats[stat_idx].value =
1673                                         *(uint64_t *)(((char *)&stats) +
1674                                         qede_bb_xstats_strings[i].offset);
1675                         xstats[stat_idx].id = stat_idx;
1676                         stat_idx++;
1677                 }
1678         } else {
1679                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1680                         xstats[stat_idx].value =
1681                                         *(uint64_t *)(((char *)&stats) +
1682                                         qede_ah_xstats_strings[i].offset);
1683                         xstats[stat_idx].id = stat_idx;
1684                         stat_idx++;
1685                 }
1686         }
1687
1688         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1689                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1690         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1691                 for_each_rss(qid) {
1692                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1693                                 xstats[stat_idx].value = *(uint64_t *)(
1694                                         ((char *)(qdev->fp_array[qid].rxq)) +
1695                                          qede_rxq_xstats_strings[i].offset);
1696                                 xstats[stat_idx].id = stat_idx;
1697                                 stat_idx++;
1698                         }
1699                 }
1700         }
1701
1702         return stat_idx;
1703 }
1704
1705 static void
1706 qede_reset_xstats(struct rte_eth_dev *dev)
1707 {
1708         struct qede_dev *qdev = dev->data->dev_private;
1709         struct ecore_dev *edev = &qdev->edev;
1710
1711         ecore_reset_vport_stats(edev);
1712 }
1713
1714 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1715 {
1716         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1717         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1718         struct qed_link_params link_params;
1719         int rc;
1720
1721         DP_INFO(edev, "setting link state %d\n", link_up);
1722         memset(&link_params, 0, sizeof(link_params));
1723         link_params.link_up = link_up;
1724         rc = qdev->ops->common->set_link(edev, &link_params);
1725         if (rc != ECORE_SUCCESS)
1726                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1727
1728         return rc;
1729 }
1730
1731 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1732 {
1733         return qede_dev_set_link_state(eth_dev, true);
1734 }
1735
1736 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1737 {
1738         return qede_dev_set_link_state(eth_dev, false);
1739 }
1740
1741 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1742 {
1743         struct qede_dev *qdev = eth_dev->data->dev_private;
1744         struct ecore_dev *edev = &qdev->edev;
1745
1746         ecore_reset_vport_stats(edev);
1747 }
1748
1749 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1750 {
1751         enum qed_filter_rx_mode_type type =
1752             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1753
1754         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1755                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1756
1757         qed_configure_filter_rx_mode(eth_dev, type);
1758 }
1759
1760 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1761 {
1762         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1763                 qed_configure_filter_rx_mode(eth_dev,
1764                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1765         else
1766                 qed_configure_filter_rx_mode(eth_dev,
1767                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1768 }
1769
1770 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1771                               struct rte_eth_fc_conf *fc_conf)
1772 {
1773         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1774         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1775         struct qed_link_output current_link;
1776         struct qed_link_params params;
1777
1778         memset(&current_link, 0, sizeof(current_link));
1779         qdev->ops->common->get_link(edev, &current_link);
1780
1781         memset(&params, 0, sizeof(params));
1782         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1783         if (fc_conf->autoneg) {
1784                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1785                         DP_ERR(edev, "Autoneg not supported\n");
1786                         return -EINVAL;
1787                 }
1788                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1789         }
1790
1791         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1792         if (fc_conf->mode == RTE_FC_FULL)
1793                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1794                                         QED_LINK_PAUSE_RX_ENABLE);
1795         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1796                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1797         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1798                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1799
1800         params.link_up = true;
1801         (void)qdev->ops->common->set_link(edev, &params);
1802
1803         return 0;
1804 }
1805
1806 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1807                               struct rte_eth_fc_conf *fc_conf)
1808 {
1809         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1810         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1811         struct qed_link_output current_link;
1812
1813         memset(&current_link, 0, sizeof(current_link));
1814         qdev->ops->common->get_link(edev, &current_link);
1815
1816         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1817                 fc_conf->autoneg = true;
1818
1819         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1820                                          QED_LINK_PAUSE_TX_ENABLE))
1821                 fc_conf->mode = RTE_FC_FULL;
1822         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1823                 fc_conf->mode = RTE_FC_RX_PAUSE;
1824         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1825                 fc_conf->mode = RTE_FC_TX_PAUSE;
1826         else
1827                 fc_conf->mode = RTE_FC_NONE;
1828
1829         return 0;
1830 }
1831
1832 static const uint32_t *
1833 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1834 {
1835         static const uint32_t ptypes[] = {
1836                 RTE_PTYPE_L2_ETHER,
1837                 RTE_PTYPE_L2_ETHER_VLAN,
1838                 RTE_PTYPE_L3_IPV4,
1839                 RTE_PTYPE_L3_IPV6,
1840                 RTE_PTYPE_L4_TCP,
1841                 RTE_PTYPE_L4_UDP,
1842                 RTE_PTYPE_TUNNEL_VXLAN,
1843                 RTE_PTYPE_L4_FRAG,
1844                 /* Inner */
1845                 RTE_PTYPE_INNER_L2_ETHER,
1846                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1847                 RTE_PTYPE_INNER_L3_IPV4,
1848                 RTE_PTYPE_INNER_L3_IPV6,
1849                 RTE_PTYPE_INNER_L4_TCP,
1850                 RTE_PTYPE_INNER_L4_UDP,
1851                 RTE_PTYPE_INNER_L4_FRAG,
1852                 RTE_PTYPE_UNKNOWN
1853         };
1854
1855         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1856                 return ptypes;
1857
1858         return NULL;
1859 }
1860
1861 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1862 {
1863         *rss_caps = 0;
1864         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1865         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1866         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1867         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1868         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1869         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1870         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1871         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1872 }
1873
1874 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1875                          struct rte_eth_rss_conf *rss_conf)
1876 {
1877         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1878         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1879         struct ecore_sp_vport_update_params vport_update_params;
1880         struct ecore_rss_params rss_params;
1881         struct ecore_hwfn *p_hwfn;
1882         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1883         uint64_t hf = rss_conf->rss_hf;
1884         uint8_t len = rss_conf->rss_key_len;
1885         uint8_t idx;
1886         uint8_t i;
1887         int rc;
1888
1889         memset(&vport_update_params, 0, sizeof(vport_update_params));
1890         memset(&rss_params, 0, sizeof(rss_params));
1891
1892         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1893                 (unsigned long)hf, len, key);
1894
1895         if (hf != 0) {
1896                 /* Enabling RSS */
1897                 DP_INFO(edev, "Enabling rss\n");
1898
1899                 /* RSS caps */
1900                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1901                 rss_params.update_rss_capabilities = 1;
1902
1903                 /* RSS hash key */
1904                 if (key) {
1905                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1906                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1907                                 return -EINVAL;
1908                         }
1909                         DP_INFO(edev, "Applying user supplied hash key\n");
1910                         rss_params.update_rss_key = 1;
1911                         memcpy(&rss_params.rss_key, key, len);
1912                 }
1913                 rss_params.rss_enable = 1;
1914         }
1915
1916         rss_params.update_rss_config = 1;
1917         /* tbl_size has to be set with capabilities */
1918         rss_params.rss_table_size_log = 7;
1919         vport_update_params.vport_id = 0;
1920         /* pass the L2 handles instead of qids */
1921         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1922                 idx = qdev->rss_ind_table[i];
1923                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1924         }
1925         vport_update_params.rss_params = &rss_params;
1926
1927         for_each_hwfn(edev, i) {
1928                 p_hwfn = &edev->hwfns[i];
1929                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1930                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1931                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1932                 if (rc) {
1933                         DP_ERR(edev, "vport-update for RSS failed\n");
1934                         return rc;
1935                 }
1936         }
1937         qdev->rss_enable = rss_params.rss_enable;
1938
1939         /* Update local structure for hash query */
1940         qdev->rss_conf.rss_hf = hf;
1941         qdev->rss_conf.rss_key_len = len;
1942         if (qdev->rss_enable) {
1943                 if  (qdev->rss_conf.rss_key == NULL) {
1944                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1945                         if (qdev->rss_conf.rss_key == NULL) {
1946                                 DP_ERR(edev, "No memory to store RSS key\n");
1947                                 return -ENOMEM;
1948                         }
1949                 }
1950                 if (key && len) {
1951                         DP_INFO(edev, "Storing RSS key\n");
1952                         memcpy(qdev->rss_conf.rss_key, key, len);
1953                 }
1954         } else if (!qdev->rss_enable && len == 0) {
1955                 if (qdev->rss_conf.rss_key) {
1956                         free(qdev->rss_conf.rss_key);
1957                         qdev->rss_conf.rss_key = NULL;
1958                         DP_INFO(edev, "Free RSS key\n");
1959                 }
1960         }
1961
1962         return 0;
1963 }
1964
1965 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1966                            struct rte_eth_rss_conf *rss_conf)
1967 {
1968         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1969
1970         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1971         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1972
1973         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1974                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1975                        rss_conf->rss_key_len);
1976         return 0;
1977 }
1978
1979 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1980                                     struct ecore_rss_params *rss)
1981 {
1982         int i, fn;
1983         bool rss_mode = 1; /* enable */
1984         struct ecore_queue_cid *cid;
1985         struct ecore_rss_params *t_rss;
1986
1987         /* In regular scenario, we'd simply need to take input handlers.
1988          * But in CMT, we'd have to split the handlers according to the
1989          * engine they were configured on. We'd then have to understand
1990          * whether RSS is really required, since 2-queues on CMT doesn't
1991          * require RSS.
1992          */
1993
1994         /* CMT should be round-robin */
1995         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1996                 cid = rss->rss_ind_table[i];
1997
1998                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1999                         t_rss = &rss[0];
2000                 else
2001                         t_rss = &rss[1];
2002
2003                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2004         }
2005
2006         t_rss = &rss[1];
2007         t_rss->update_rss_ind_table = 1;
2008         t_rss->rss_table_size_log = 7;
2009         t_rss->update_rss_config = 1;
2010
2011         /* Make sure RSS is actually required */
2012         for_each_hwfn(edev, fn) {
2013                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2014                      i++) {
2015                         if (rss[fn].rss_ind_table[i] !=
2016                             rss[fn].rss_ind_table[0])
2017                                 break;
2018                 }
2019
2020                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2021                         DP_INFO(edev,
2022                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2023                         rss_mode = 0;
2024                         goto out;
2025                 }
2026         }
2027
2028 out:
2029         t_rss->rss_enable = rss_mode;
2030
2031         return rss_mode;
2032 }
2033
2034 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2035                          struct rte_eth_rss_reta_entry64 *reta_conf,
2036                          uint16_t reta_size)
2037 {
2038         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2039         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2040         struct ecore_sp_vport_update_params vport_update_params;
2041         struct ecore_rss_params *params;
2042         struct ecore_hwfn *p_hwfn;
2043         uint16_t i, idx, shift;
2044         uint8_t entry;
2045         int rc = 0;
2046
2047         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2048                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2049                        reta_size);
2050                 return -EINVAL;
2051         }
2052
2053         memset(&vport_update_params, 0, sizeof(vport_update_params));
2054         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2055                              RTE_CACHE_LINE_SIZE);
2056         if (params == NULL) {
2057                 DP_ERR(edev, "failed to allocate memory\n");
2058                 return -ENOMEM;
2059         }
2060
2061         for (i = 0; i < reta_size; i++) {
2062                 idx = i / RTE_RETA_GROUP_SIZE;
2063                 shift = i % RTE_RETA_GROUP_SIZE;
2064                 if (reta_conf[idx].mask & (1ULL << shift)) {
2065                         entry = reta_conf[idx].reta[shift];
2066                         /* Pass rxq handles to ecore */
2067                         params->rss_ind_table[i] =
2068                                         qdev->fp_array[entry].rxq->handle;
2069                         /* Update the local copy for RETA query command */
2070                         qdev->rss_ind_table[i] = entry;
2071                 }
2072         }
2073
2074         params->update_rss_ind_table = 1;
2075         params->rss_table_size_log = 7;
2076         params->update_rss_config = 1;
2077
2078         /* Fix up RETA for CMT mode device */
2079         if (ECORE_IS_CMT(edev))
2080                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2081                                                             params);
2082         vport_update_params.vport_id = 0;
2083         /* Use the current value of rss_enable */
2084         params->rss_enable = qdev->rss_enable;
2085         vport_update_params.rss_params = params;
2086
2087         for_each_hwfn(edev, i) {
2088                 p_hwfn = &edev->hwfns[i];
2089                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2090                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2091                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2092                 if (rc) {
2093                         DP_ERR(edev, "vport-update for RSS failed\n");
2094                         goto out;
2095                 }
2096         }
2097
2098 out:
2099         rte_free(params);
2100         return rc;
2101 }
2102
2103 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2104                                struct rte_eth_rss_reta_entry64 *reta_conf,
2105                                uint16_t reta_size)
2106 {
2107         struct qede_dev *qdev = eth_dev->data->dev_private;
2108         struct ecore_dev *edev = &qdev->edev;
2109         uint16_t i, idx, shift;
2110         uint8_t entry;
2111
2112         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2113                 DP_ERR(edev, "reta_size %d is not supported\n",
2114                        reta_size);
2115                 return -EINVAL;
2116         }
2117
2118         for (i = 0; i < reta_size; i++) {
2119                 idx = i / RTE_RETA_GROUP_SIZE;
2120                 shift = i % RTE_RETA_GROUP_SIZE;
2121                 if (reta_conf[idx].mask & (1ULL << shift)) {
2122                         entry = qdev->rss_ind_table[i];
2123                         reta_conf[idx].reta[shift] = entry;
2124                 }
2125         }
2126
2127         return 0;
2128 }
2129
2130
2131
2132 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2133 {
2134         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2135         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2136         struct rte_eth_dev_info dev_info = {0};
2137         struct qede_fastpath *fp;
2138         uint32_t frame_size;
2139         uint16_t rx_buf_size;
2140         uint16_t bufsz;
2141         int i;
2142
2143         PMD_INIT_FUNC_TRACE(edev);
2144         qede_dev_info_get(dev, &dev_info);
2145         frame_size = mtu + QEDE_ETH_OVERHEAD;
2146         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2147                 DP_ERR(edev, "MTU %u out of range\n", mtu);
2148                 return -EINVAL;
2149         }
2150         if (!dev->data->scattered_rx &&
2151             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2152                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2153                         dev->data->min_rx_buf_size);
2154                 return -EINVAL;
2155         }
2156         /* Temporarily replace I/O functions with dummy ones. It cannot
2157          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2158          */
2159         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2160         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2161         qede_dev_stop(dev);
2162         rte_delay_ms(1000);
2163         qdev->mtu = mtu;
2164         /* Fix up RX buf size for all queues of the port */
2165         for_each_rss(i) {
2166                 fp = &qdev->fp_array[i];
2167                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2168                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2169                 if (dev->data->scattered_rx)
2170                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2171                 else
2172                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2173                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2174                 fp->rxq->rx_buf_size = rx_buf_size;
2175                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2176         }
2177         qede_dev_start(dev);
2178         if (frame_size > ETHER_MAX_LEN)
2179                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2180         else
2181                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2182         /* update max frame size */
2183         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2184         /* Reassign back */
2185         dev->rx_pkt_burst = qede_recv_pkts;
2186         dev->tx_pkt_burst = qede_xmit_pkts;
2187
2188         return 0;
2189 }
2190
2191 static int
2192 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2193                        struct rte_eth_udp_tunnel *tunnel_udp,
2194                        bool add)
2195 {
2196         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2197         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2198         struct ecore_tunnel_info tunn; /* @DPDK */
2199         struct ecore_hwfn *p_hwfn;
2200         struct ecore_ptt *p_ptt;
2201         uint16_t udp_port;
2202         int rc, i;
2203
2204         PMD_INIT_FUNC_TRACE(edev);
2205
2206         memset(&tunn, 0, sizeof(tunn));
2207         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2208                 /* Enable VxLAN tunnel if needed before UDP port update using
2209                  * default MAC/VLAN classification.
2210                  */
2211                 if (add) {
2212                         if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2213                                 DP_INFO(edev,
2214                                         "UDP port %u was already configured\n",
2215                                         tunnel_udp->udp_port);
2216                                 return ECORE_SUCCESS;
2217                         }
2218                         /* Enable VXLAN if it was not enabled while adding
2219                          * VXLAN filter.
2220                          */
2221                         if (!qdev->vxlan.enable) {
2222                                 rc = qede_vxlan_enable(eth_dev,
2223                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2224                                 if (rc != ECORE_SUCCESS) {
2225                                         DP_ERR(edev, "Failed to enable VXLAN "
2226                                                 "prior to updating UDP port\n");
2227                                         return rc;
2228                                 }
2229                         }
2230                         udp_port = tunnel_udp->udp_port;
2231                 } else {
2232                         if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2233                                 DP_ERR(edev, "UDP port %u doesn't exist\n",
2234                                         tunnel_udp->udp_port);
2235                                 return ECORE_INVAL;
2236                         }
2237                         udp_port = 0;
2238                 }
2239
2240                 tunn.vxlan_port.b_update_port = true;
2241                 tunn.vxlan_port.port = udp_port;
2242                 for_each_hwfn(edev, i) {
2243                         p_hwfn = &edev->hwfns[i];
2244                         p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
2245                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2246                                                 ECORE_SPQ_MODE_CB, NULL);
2247                         if (rc != ECORE_SUCCESS) {
2248                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2249                                        tunn.vxlan_port.port);
2250                                 if (IS_PF(edev))
2251                                         ecore_ptt_release(p_hwfn, p_ptt);
2252                                 return rc;
2253                         }
2254                 }
2255
2256                 qdev->vxlan.udp_port = udp_port;
2257                 /* If the request is to delete UDP port and if the number of
2258                  * VXLAN filters have reached 0 then VxLAN offload can be be
2259                  * disabled.
2260                  */
2261                 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2262                         return qede_vxlan_enable(eth_dev,
2263                                         ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2264         }
2265
2266         return 0;
2267 }
2268
2269 static int
2270 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2271                       struct rte_eth_udp_tunnel *tunnel_udp)
2272 {
2273         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2274 }
2275
2276 static int
2277 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2278                       struct rte_eth_udp_tunnel *tunnel_udp)
2279 {
2280         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2281 }
2282
2283 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2284                                        uint32_t *clss, char *str)
2285 {
2286         uint16_t j;
2287         *clss = MAX_ECORE_TUNN_CLSS;
2288
2289         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2290                 if (filter == qede_tunn_types[j].rte_filter_type) {
2291                         *type = qede_tunn_types[j].qede_type;
2292                         *clss = qede_tunn_types[j].qede_tunn_clss;
2293                         strcpy(str, qede_tunn_types[j].string);
2294                         return;
2295                 }
2296         }
2297 }
2298
2299 static int
2300 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2301                               const struct rte_eth_tunnel_filter_conf *conf,
2302                               uint32_t type)
2303 {
2304         /* Init commmon ucast params first */
2305         qede_set_ucast_cmn_params(ucast);
2306
2307         /* Copy out the required fields based on classification type */
2308         ucast->type = type;
2309
2310         switch (type) {
2311         case ECORE_FILTER_VNI:
2312                 ucast->vni = conf->tenant_id;
2313         break;
2314         case ECORE_FILTER_INNER_VLAN:
2315                 ucast->vlan = conf->inner_vlan;
2316         break;
2317         case ECORE_FILTER_MAC:
2318                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2319                        ETHER_ADDR_LEN);
2320         break;
2321         case ECORE_FILTER_INNER_MAC:
2322                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2323                        ETHER_ADDR_LEN);
2324         break;
2325         case ECORE_FILTER_MAC_VNI_PAIR:
2326                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2327                         ETHER_ADDR_LEN);
2328                 ucast->vni = conf->tenant_id;
2329         break;
2330         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2331                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2332                         ETHER_ADDR_LEN);
2333                 ucast->vni = conf->tenant_id;
2334         break;
2335         case ECORE_FILTER_INNER_PAIR:
2336                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2337                         ETHER_ADDR_LEN);
2338                 ucast->vlan = conf->inner_vlan;
2339         break;
2340         default:
2341                 return -EINVAL;
2342         }
2343
2344         return ECORE_SUCCESS;
2345 }
2346
2347 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2348                                   enum rte_filter_op filter_op,
2349                                   const struct rte_eth_tunnel_filter_conf *conf)
2350 {
2351         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2352         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2353         enum ecore_filter_ucast_type type;
2354         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2355         struct ecore_filter_ucast ucast = {0};
2356         char str[80];
2357         uint16_t filter_type = 0;
2358         int rc;
2359
2360         PMD_INIT_FUNC_TRACE(edev);
2361
2362         switch (filter_op) {
2363         case RTE_ETH_FILTER_ADD:
2364                 if (IS_VF(edev))
2365                         return qede_vxlan_enable(eth_dev,
2366                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2367
2368                 filter_type = conf->filter_type;
2369                 /* Determine if the given filter classification is supported */
2370                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2371                 if (clss == MAX_ECORE_TUNN_CLSS) {
2372                         DP_ERR(edev, "Unsupported filter type\n");
2373                         return -EINVAL;
2374                 }
2375                 /* Init tunnel ucast params */
2376                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2377                 if (rc != ECORE_SUCCESS) {
2378                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2379                         conf->filter_type);
2380                         return rc;
2381                 }
2382                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2383                         str, filter_op, ucast.type);
2384
2385                 ucast.opcode = ECORE_FILTER_ADD;
2386
2387                 /* Skip MAC/VLAN if filter is based on VNI */
2388                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2389                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2390                         if (rc == 0) {
2391                                 /* Enable accept anyvlan */
2392                                 qede_config_accept_any_vlan(qdev, true);
2393                         }
2394                 } else {
2395                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2396                         if (rc == 0)
2397                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2398                                                     ECORE_SPQ_MODE_CB, NULL);
2399                 }
2400
2401                 if (rc != ECORE_SUCCESS)
2402                         return rc;
2403
2404                 qdev->vxlan.num_filters++;
2405                 qdev->vxlan.filter_type = filter_type;
2406                 if (!qdev->vxlan.enable)
2407                         return qede_vxlan_enable(eth_dev, clss, true, true);
2408
2409         break;
2410         case RTE_ETH_FILTER_DELETE:
2411                 if (IS_VF(edev))
2412                         return qede_vxlan_enable(eth_dev,
2413                                 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2414
2415                 ucast.opcode = ECORE_FILTER_REMOVE;
2416
2417                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2418                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2419                 } else {
2420                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2421                         if (rc == 0)
2422                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2423                                                     ECORE_SPQ_MODE_CB, NULL);
2424                 }
2425                 if (rc != ECORE_SUCCESS)
2426                         return rc;
2427
2428                 /* Disable VXLAN if VXLAN filters become 0 */
2429                 if (qdev->vxlan.num_filters == 0)
2430                         return qede_vxlan_enable(eth_dev, clss, false, true);
2431         break;
2432         default:
2433                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2434                 return -EINVAL;
2435         }
2436
2437         return 0;
2438 }
2439
2440 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2441                          enum rte_filter_type filter_type,
2442                          enum rte_filter_op filter_op,
2443                          void *arg)
2444 {
2445         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2446         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2447         struct rte_eth_tunnel_filter_conf *filter_conf =
2448                         (struct rte_eth_tunnel_filter_conf *)arg;
2449
2450         switch (filter_type) {
2451         case RTE_ETH_FILTER_TUNNEL:
2452                 switch (filter_conf->tunnel_type) {
2453                 case RTE_TUNNEL_TYPE_VXLAN:
2454                         DP_INFO(edev,
2455                                 "Packet steering to the specified Rx queue"
2456                                 " is not supported with VXLAN tunneling");
2457                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2458                                                       filter_conf));
2459                 /* Place holders for future tunneling support */
2460                 case RTE_TUNNEL_TYPE_GENEVE:
2461                 case RTE_TUNNEL_TYPE_TEREDO:
2462                 case RTE_TUNNEL_TYPE_NVGRE:
2463                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2464                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2465                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2466                                 filter_conf->tunnel_type);
2467                         return -EINVAL;
2468                 case RTE_TUNNEL_TYPE_NONE:
2469                 default:
2470                         return 0;
2471                 }
2472                 break;
2473         case RTE_ETH_FILTER_FDIR:
2474                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2475         case RTE_ETH_FILTER_NTUPLE:
2476                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2477         case RTE_ETH_FILTER_MACVLAN:
2478         case RTE_ETH_FILTER_ETHERTYPE:
2479         case RTE_ETH_FILTER_FLEXIBLE:
2480         case RTE_ETH_FILTER_SYN:
2481         case RTE_ETH_FILTER_HASH:
2482         case RTE_ETH_FILTER_L2_TUNNEL:
2483         case RTE_ETH_FILTER_MAX:
2484         default:
2485                 DP_ERR(edev, "Unsupported filter type %d\n",
2486                         filter_type);
2487                 return -EINVAL;
2488         }
2489
2490         return 0;
2491 }
2492
2493 static const struct eth_dev_ops qede_eth_dev_ops = {
2494         .dev_configure = qede_dev_configure,
2495         .dev_infos_get = qede_dev_info_get,
2496         .rx_queue_setup = qede_rx_queue_setup,
2497         .rx_queue_release = qede_rx_queue_release,
2498         .tx_queue_setup = qede_tx_queue_setup,
2499         .tx_queue_release = qede_tx_queue_release,
2500         .dev_start = qede_dev_start,
2501         .dev_set_link_up = qede_dev_set_link_up,
2502         .dev_set_link_down = qede_dev_set_link_down,
2503         .link_update = qede_link_update,
2504         .promiscuous_enable = qede_promiscuous_enable,
2505         .promiscuous_disable = qede_promiscuous_disable,
2506         .allmulticast_enable = qede_allmulticast_enable,
2507         .allmulticast_disable = qede_allmulticast_disable,
2508         .dev_stop = qede_dev_stop,
2509         .dev_close = qede_dev_close,
2510         .stats_get = qede_get_stats,
2511         .stats_reset = qede_reset_stats,
2512         .xstats_get = qede_get_xstats,
2513         .xstats_reset = qede_reset_xstats,
2514         .xstats_get_names = qede_get_xstats_names,
2515         .mac_addr_add = qede_mac_addr_add,
2516         .mac_addr_remove = qede_mac_addr_remove,
2517         .mac_addr_set = qede_mac_addr_set,
2518         .vlan_offload_set = qede_vlan_offload_set,
2519         .vlan_filter_set = qede_vlan_filter_set,
2520         .flow_ctrl_set = qede_flow_ctrl_set,
2521         .flow_ctrl_get = qede_flow_ctrl_get,
2522         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2523         .rss_hash_update = qede_rss_hash_update,
2524         .rss_hash_conf_get = qede_rss_hash_conf_get,
2525         .reta_update  = qede_rss_reta_update,
2526         .reta_query  = qede_rss_reta_query,
2527         .mtu_set = qede_set_mtu,
2528         .filter_ctrl = qede_dev_filter_ctrl,
2529         .udp_tunnel_port_add = qede_udp_dst_port_add,
2530         .udp_tunnel_port_del = qede_udp_dst_port_del,
2531 };
2532
2533 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2534         .dev_configure = qede_dev_configure,
2535         .dev_infos_get = qede_dev_info_get,
2536         .rx_queue_setup = qede_rx_queue_setup,
2537         .rx_queue_release = qede_rx_queue_release,
2538         .tx_queue_setup = qede_tx_queue_setup,
2539         .tx_queue_release = qede_tx_queue_release,
2540         .dev_start = qede_dev_start,
2541         .dev_set_link_up = qede_dev_set_link_up,
2542         .dev_set_link_down = qede_dev_set_link_down,
2543         .link_update = qede_link_update,
2544         .promiscuous_enable = qede_promiscuous_enable,
2545         .promiscuous_disable = qede_promiscuous_disable,
2546         .allmulticast_enable = qede_allmulticast_enable,
2547         .allmulticast_disable = qede_allmulticast_disable,
2548         .dev_stop = qede_dev_stop,
2549         .dev_close = qede_dev_close,
2550         .stats_get = qede_get_stats,
2551         .stats_reset = qede_reset_stats,
2552         .xstats_get = qede_get_xstats,
2553         .xstats_reset = qede_reset_xstats,
2554         .xstats_get_names = qede_get_xstats_names,
2555         .vlan_offload_set = qede_vlan_offload_set,
2556         .vlan_filter_set = qede_vlan_filter_set,
2557         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2558         .rss_hash_update = qede_rss_hash_update,
2559         .rss_hash_conf_get = qede_rss_hash_conf_get,
2560         .reta_update  = qede_rss_reta_update,
2561         .reta_query  = qede_rss_reta_query,
2562         .mtu_set = qede_set_mtu,
2563         .udp_tunnel_port_add = qede_udp_dst_port_add,
2564         .udp_tunnel_port_del = qede_udp_dst_port_del,
2565 };
2566
2567 static void qede_update_pf_params(struct ecore_dev *edev)
2568 {
2569         struct ecore_pf_params pf_params;
2570
2571         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2572         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2573         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2574         qed_ops->common->update_pf_params(edev, &pf_params);
2575 }
2576
2577 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2578 {
2579         struct rte_pci_device *pci_dev;
2580         struct rte_pci_addr pci_addr;
2581         struct qede_dev *adapter;
2582         struct ecore_dev *edev;
2583         struct qed_dev_eth_info dev_info;
2584         struct qed_slowpath_params params;
2585         static bool do_once = true;
2586         uint8_t bulletin_change;
2587         uint8_t vf_mac[ETHER_ADDR_LEN];
2588         uint8_t is_mac_forced;
2589         bool is_mac_exist;
2590         /* Fix up ecore debug level */
2591         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2592         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2593         int rc;
2594
2595         /* Extract key data structures */
2596         adapter = eth_dev->data->dev_private;
2597         edev = &adapter->edev;
2598         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2599         pci_addr = pci_dev->addr;
2600
2601         PMD_INIT_FUNC_TRACE(edev);
2602
2603         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2604                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2605                  eth_dev->data->port_id);
2606
2607         eth_dev->rx_pkt_burst = qede_recv_pkts;
2608         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2609         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2610
2611         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2612                 DP_ERR(edev, "Skipping device init from secondary process\n");
2613                 return 0;
2614         }
2615
2616         rte_eth_copy_pci_info(eth_dev, pci_dev);
2617
2618         /* @DPDK */
2619         edev->vendor_id = pci_dev->id.vendor_id;
2620         edev->device_id = pci_dev->id.device_id;
2621
2622         qed_ops = qed_get_eth_ops();
2623         if (!qed_ops) {
2624                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2625                 return -EINVAL;
2626         }
2627
2628         DP_INFO(edev, "Starting qede probe\n");
2629         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2630                                     dp_level, is_vf);
2631         if (rc != 0) {
2632                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2633                 return -ENODEV;
2634         }
2635         qede_update_pf_params(edev);
2636         rte_intr_callback_register(&pci_dev->intr_handle,
2637                                    qede_interrupt_handler, (void *)eth_dev);
2638         if (rte_intr_enable(&pci_dev->intr_handle)) {
2639                 DP_ERR(edev, "rte_intr_enable() failed\n");
2640                 return -ENODEV;
2641         }
2642
2643         /* Start the Slowpath-process */
2644         memset(&params, 0, sizeof(struct qed_slowpath_params));
2645         params.int_mode = ECORE_INT_MODE_MSIX;
2646         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2647         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2648         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2649         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2650         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2651                 QEDE_PMD_DRV_VER_STR_SIZE);
2652
2653         /* For CMT mode device do periodic polling for slowpath events.
2654          * This is required since uio device uses only one MSI-x
2655          * interrupt vector but we need one for each engine.
2656          */
2657         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2658                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2659                                        qede_poll_sp_sb_cb,
2660                                        (void *)eth_dev);
2661                 if (rc != 0) {
2662                         DP_ERR(edev, "Unable to start periodic"
2663                                      " timer rc %d\n", rc);
2664                         return -EINVAL;
2665                 }
2666         }
2667
2668         rc = qed_ops->common->slowpath_start(edev, &params);
2669         if (rc) {
2670                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2671                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2672                                      (void *)eth_dev);
2673                 return -ENODEV;
2674         }
2675
2676         rc = qed_ops->fill_dev_info(edev, &dev_info);
2677         if (rc) {
2678                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2679                 qed_ops->common->slowpath_stop(edev);
2680                 qed_ops->common->remove(edev);
2681                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2682                                      (void *)eth_dev);
2683                 return -ENODEV;
2684         }
2685
2686         qede_alloc_etherdev(adapter, &dev_info);
2687
2688         adapter->ops->common->set_name(edev, edev->name);
2689
2690         if (!is_vf)
2691                 adapter->dev_info.num_mac_filters =
2692                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2693                                             ECORE_MAC);
2694         else
2695                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2696                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2697
2698         /* Allocate memory for storing MAC addr */
2699         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2700                                         (ETHER_ADDR_LEN *
2701                                         adapter->dev_info.num_mac_filters),
2702                                         RTE_CACHE_LINE_SIZE);
2703
2704         if (eth_dev->data->mac_addrs == NULL) {
2705                 DP_ERR(edev, "Failed to allocate MAC address\n");
2706                 qed_ops->common->slowpath_stop(edev);
2707                 qed_ops->common->remove(edev);
2708                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2709                                      (void *)eth_dev);
2710                 return -ENOMEM;
2711         }
2712
2713         if (!is_vf) {
2714                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2715                                 hw_info.hw_mac_addr,
2716                                 &eth_dev->data->mac_addrs[0]);
2717                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2718                                 &adapter->primary_mac);
2719         } else {
2720                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2721                                        &bulletin_change);
2722                 if (bulletin_change) {
2723                         is_mac_exist =
2724                             ecore_vf_bulletin_get_forced_mac(
2725                                                 ECORE_LEADING_HWFN(edev),
2726                                                 vf_mac,
2727                                                 &is_mac_forced);
2728                         if (is_mac_exist && is_mac_forced) {
2729                                 DP_INFO(edev, "VF macaddr received from PF\n");
2730                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2731                                                 &eth_dev->data->mac_addrs[0]);
2732                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2733                                                 &adapter->primary_mac);
2734                         } else {
2735                                 DP_ERR(edev, "No VF macaddr assigned\n");
2736                         }
2737                 }
2738         }
2739
2740         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2741
2742         if (do_once) {
2743 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2744                 qede_print_adapter_info(adapter);
2745 #endif
2746                 do_once = false;
2747         }
2748
2749         adapter->num_tx_queues = 0;
2750         adapter->num_rx_queues = 0;
2751         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2752         SLIST_INIT(&adapter->vlan_list_head);
2753         SLIST_INIT(&adapter->uc_list_head);
2754         adapter->mtu = ETHER_MTU;
2755         adapter->new_mtu = ETHER_MTU;
2756         if (!is_vf)
2757                 if (qede_start_vport(adapter, adapter->mtu))
2758                         return -1;
2759
2760         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2761                 adapter->primary_mac.addr_bytes[0],
2762                 adapter->primary_mac.addr_bytes[1],
2763                 adapter->primary_mac.addr_bytes[2],
2764                 adapter->primary_mac.addr_bytes[3],
2765                 adapter->primary_mac.addr_bytes[4],
2766                 adapter->primary_mac.addr_bytes[5]);
2767
2768         DP_INFO(edev, "Device initialized\n");
2769
2770         return 0;
2771 }
2772
2773 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2774 {
2775         return qede_common_dev_init(eth_dev, 1);
2776 }
2777
2778 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2779 {
2780         return qede_common_dev_init(eth_dev, 0);
2781 }
2782
2783 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2784 {
2785 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2786         struct qede_dev *qdev = eth_dev->data->dev_private;
2787         struct ecore_dev *edev = &qdev->edev;
2788
2789         PMD_INIT_FUNC_TRACE(edev);
2790 #endif
2791
2792         /* only uninitialize in the primary process */
2793         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2794                 return 0;
2795
2796         /* safe to close dev here */
2797         qede_dev_close(eth_dev);
2798
2799         eth_dev->dev_ops = NULL;
2800         eth_dev->rx_pkt_burst = NULL;
2801         eth_dev->tx_pkt_burst = NULL;
2802
2803         if (eth_dev->data->mac_addrs)
2804                 rte_free(eth_dev->data->mac_addrs);
2805
2806         eth_dev->data->mac_addrs = NULL;
2807
2808         return 0;
2809 }
2810
2811 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2812 {
2813         return qede_dev_common_uninit(eth_dev);
2814 }
2815
2816 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2817 {
2818         return qede_dev_common_uninit(eth_dev);
2819 }
2820
2821 static const struct rte_pci_id pci_id_qedevf_map[] = {
2822 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2823         {
2824                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2825         },
2826         {
2827                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2828         },
2829         {
2830                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2831         },
2832         {.vendor_id = 0,}
2833 };
2834
2835 static const struct rte_pci_id pci_id_qede_map[] = {
2836 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2837         {
2838                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2839         },
2840         {
2841                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2842         },
2843         {
2844                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2845         },
2846         {
2847                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2848         },
2849         {
2850                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2851         },
2852         {
2853                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2854         },
2855         {
2856                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2857         },
2858         {
2859                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2860         },
2861         {
2862                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2863         },
2864         {
2865                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2866         },
2867         {.vendor_id = 0,}
2868 };
2869
2870 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2871         struct rte_pci_device *pci_dev)
2872 {
2873         return rte_eth_dev_pci_generic_probe(pci_dev,
2874                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2875 }
2876
2877 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2878 {
2879         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2880 }
2881
2882 static struct rte_pci_driver rte_qedevf_pmd = {
2883         .id_table = pci_id_qedevf_map,
2884         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2885         .probe = qedevf_eth_dev_pci_probe,
2886         .remove = qedevf_eth_dev_pci_remove,
2887 };
2888
2889 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2890         struct rte_pci_device *pci_dev)
2891 {
2892         return rte_eth_dev_pci_generic_probe(pci_dev,
2893                 sizeof(struct qede_dev), qede_eth_dev_init);
2894 }
2895
2896 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2897 {
2898         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2899 }
2900
2901 static struct rte_pci_driver rte_qede_pmd = {
2902         .id_table = pci_id_qede_map,
2903         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2904         .probe = qede_eth_dev_pci_probe,
2905         .remove = qede_eth_dev_pci_remove,
2906 };
2907
2908 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2909 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2910 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2911 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2912 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2913 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");