drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes",
 129                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 130         {"rx_multicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 132         {"rx_broadcast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 134         {"rx_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 136         {"rx_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 138         {"rx_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 140
 141         {"tx_unicast_bytes",
 142                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 143         {"tx_multicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 145         {"tx_broadcast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 147         {"tx_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 149         {"tx_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 151         {"tx_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 153
 154         {"rx_64_byte_packets",
 155                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 156         {"rx_65_to_127_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          rx_65_to_127_byte_packets)},
 159         {"rx_128_to_255_byte_packets",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          rx_128_to_255_byte_packets)},
 162         {"rx_256_to_511_byte_packets",
 163                 offsetof(struct ecore_eth_stats_common,
 164                          rx_256_to_511_byte_packets)},
 165         {"rx_512_to_1023_byte_packets",
 166                 offsetof(struct ecore_eth_stats_common,
 167                          rx_512_to_1023_byte_packets)},
 168         {"rx_1024_to_1518_byte_packets",
 169                 offsetof(struct ecore_eth_stats_common,
 170                          rx_1024_to_1518_byte_packets)},
 171         {"tx_64_byte_packets",
 172                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 173         {"tx_65_to_127_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common,
 175                          tx_65_to_127_byte_packets)},
 176         {"tx_128_to_255_byte_packets",
 177                 offsetof(struct ecore_eth_stats_common,
 178                          tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats_common,
 181                          tx_256_to_511_byte_packets)},
 182         {"tx_512_to_1023_byte_packets",
 183                 offsetof(struct ecore_eth_stats_common,
 184                          tx_512_to_1023_byte_packets)},
 185         {"tx_1024_to_1518_byte_packets",
 186                 offsetof(struct ecore_eth_stats_common,
 187                          tx_1024_to_1518_byte_packets)},
 188
 189         {"rx_mac_crtl_frames",
 190                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 191         {"tx_mac_control_frames",
 192                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 193         {"rx_pause_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 195         {"tx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 197         {"rx_priority_flow_control_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 199         {"tx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 201
 202         {"rx_crc_errors",
 203                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 204         {"rx_align_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 206         {"rx_carrier_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 208         {"rx_oversize_packet_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 210         {"rx_jabber_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 212         {"rx_undersize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 214         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 215         {"rx_host_buffer_not_available",
 216                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 217         /* Number of packets discarded because they are bigger than MTU */
 218         {"rx_packet_too_big_discards",
 219                 offsetof(struct ecore_eth_stats_common,
 220                          packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 231         {"tx_error_drop_packets",
 232                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 233
 234         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 235         {"rx_mac_unicast_packets",
 236                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 237         {"rx_mac_multicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 239         {"rx_mac_broadcast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 241         {"rx_mac_frames_ok",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 243         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 244         {"tx_mac_unicast_packets",
 245                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 246         {"tx_mac_multicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 248         {"tx_mac_broadcast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 250
 251         {"lro_coalesced_packets",
 252                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 253         {"lro_coalesced_events",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 255         {"lro_aborts_num",
 256                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 257         {"lro_not_coalesced_packets",
 258                 offsetof(struct ecore_eth_stats_common,
 259                          tpa_not_coalesced_pkts)},
 260         {"lro_coalesced_bytes",
 261                 offsetof(struct ecore_eth_stats_common,
 262                          tpa_coalesced_bytes)},
 263 };
 264
 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 266         {"rx_1519_to_1522_byte_packets",
 267                 offsetof(struct ecore_eth_stats, bb) +
 268                 offsetof(struct ecore_eth_stats_bb,
 269                          rx_1519_to_1522_byte_packets)},
 270         {"rx_1519_to_2047_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_2047_byte_packets)},
 274         {"rx_2048_to_4095_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_2048_to_4095_byte_packets)},
 278         {"rx_4096_to_9216_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_4096_to_9216_byte_packets)},
 282         {"rx_9217_to_16383_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_9217_to_16383_byte_packets)},
 286
 287         {"tx_1519_to_2047_byte_packets",
 288                 offsetof(struct ecore_eth_stats, bb) +
 289                 offsetof(struct ecore_eth_stats_bb,
 290                          tx_1519_to_2047_byte_packets)},
 291         {"tx_2048_to_4095_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_2048_to_4095_byte_packets)},
 295         {"tx_4096_to_9216_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_4096_to_9216_byte_packets)},
 299         {"tx_9217_to_16383_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_9217_to_16383_byte_packets)},
 303
 304         {"tx_lpi_entry_count",
 305                 offsetof(struct ecore_eth_stats, bb) +
 306                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 307         {"tx_total_collisions",
 308                 offsetof(struct ecore_eth_stats, bb) +
 309                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 310 };
 311
 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 313         {"rx_1519_to_max_byte_packets",
 314                 offsetof(struct ecore_eth_stats, ah) +
 315                 offsetof(struct ecore_eth_stats_ah,
 316                          rx_1519_to_max_byte_packets)},
 317         {"tx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          tx_1519_to_max_byte_packets)},
 321 };
 322
 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 324         {"rx_q_segments",
 325                 offsetof(struct qede_rx_queue, rx_segs)},
 326         {"rx_q_hw_errors",
 327                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 328         {"rx_q_allocation_errors",
 329                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 330 };
 331
 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 333 {
 334         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 335 }
 336
 337 static void
 338 qede_interrupt_handler(void *param)
 339 {
 340         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 341         struct qede_dev *qdev = eth_dev->data->dev_private;
 342         struct ecore_dev *edev = &qdev->edev;
 343
 344         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 345         if (rte_intr_enable(eth_dev->intr_handle))
 346                 DP_ERR(edev, "rte_intr_enable failed\n");
 347 }
 348
 349 static void
 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 351 {
 352         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 353         qdev->ops = qed_ops;
 354 }
 355
 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 357 static void qede_print_adapter_info(struct qede_dev *qdev)
 358 {
 359         struct ecore_dev *edev = &qdev->edev;
 360         struct qed_dev_info *info = &qdev->dev_info.common;
 361         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 362         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 363
 364         DP_INFO(edev, "*********************************\n");
 365         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 366         DP_INFO(edev, " Chip details : %s %c%d\n",
 367                   ECORE_IS_BB(edev) ? "BB" : "AH",
 368                   'A' + edev->chip_rev,
 369                   (int)edev->chip_metal);
 370         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 371                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 372         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 373                  ver_str, QEDE_PMD_VERSION);
 374         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 375         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 376
 377         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 378                  "%d.%d.%d.%d",
 379                 (info->mfw_rev >> 24) & 0xff,
 380                 (info->mfw_rev >> 16) & 0xff,
 381                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 382         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 383         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 384         DP_INFO(edev, "*********************************\n");
 385 }
 386 #endif
 387
 388 static int
 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 390 {
 391         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 392         struct ecore_sp_vport_start_params params;
 393         struct ecore_hwfn *p_hwfn;
 394         int rc;
 395         int i;
 396
 397         memset(&params, 0, sizeof(params));
 398         params.vport_id = 0;
 399         params.mtu = mtu;
 400         /* @DPDK - Disable FW placement */
 401         params.zero_placement_offset = 1;
 402         for_each_hwfn(edev, i) {
 403                 p_hwfn = &edev->hwfns[i];
 404                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 405                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 406                 rc = ecore_sp_vport_start(p_hwfn, &params);
 407                 if (rc != ECORE_SUCCESS) {
 408                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 409                         return rc;
 410                 }
 411         }
 412         ecore_reset_vport_stats(edev);
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 static int
 419 qede_stop_vport(struct ecore_dev *edev)
 420 {
 421         struct ecore_hwfn *p_hwfn;
 422         uint8_t vport_id;
 423         int rc;
 424         int i;
 425
 426         vport_id = 0;
 427         for_each_hwfn(edev, i) {
 428                 p_hwfn = &edev->hwfns[i];
 429                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 430                                          vport_id);
 431                 if (rc != ECORE_SUCCESS) {
 432                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 433                         return rc;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Activate or deactivate vport via vport-update */
 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_hwfn *p_hwfn;
 447         uint8_t i;
 448         int rc = -1;
 449
 450         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 451         params.vport_id = 0;
 452         params.update_vport_active_rx_flg = 1;
 453         params.update_vport_active_tx_flg = 1;
 454         params.vport_active_rx_flg = flg;
 455         params.vport_active_tx_flg = flg;
 456         for_each_hwfn(edev, i) {
 457                 p_hwfn = &edev->hwfns[i];
 458                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 459                 rc = ecore_sp_vport_update(p_hwfn, &params,
 460                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 461                 if (rc != ECORE_SUCCESS) {
 462                         DP_ERR(edev, "Failed to update vport\n");
 463                         break;
 464                 }
 465         }
 466         DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
 467         return rc;
 468 }
 469
 470 static void
 471 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 472                            uint16_t mtu, bool enable)
 473 {
 474         /* Enable LRO in split mode */
 475         sge_tpa_params->tpa_ipv4_en_flg = enable;
 476         sge_tpa_params->tpa_ipv6_en_flg = enable;
 477         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 478         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 479         /* set if tpa enable changes */
 480         sge_tpa_params->update_tpa_en_flg = 1;
 481         /* set if tpa parameters should be handled */
 482         sge_tpa_params->update_tpa_param_flg = enable;
 483
 484         sge_tpa_params->max_buffers_per_cqe = 20;
 485         /* Enable TPA in split mode. In this mode each TPA segment
 486          * starts on the new BD, so there is one BD per segment.
 487          */
 488         sge_tpa_params->tpa_pkt_split_flg = 1;
 489         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 490         sge_tpa_params->tpa_gro_consistent_flg = 0;
 491         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 492         sge_tpa_params->tpa_max_size = 0x7FFF;
 493         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 494         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 495 }
 496
 497 /* Enable/disable LRO via vport-update */
 498 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 499 {
 500         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 501         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 502         struct ecore_sp_vport_update_params params;
 503         struct ecore_sge_tpa_params tpa_params;
 504         struct ecore_hwfn *p_hwfn;
 505         int rc;
 506         int i;
 507
 508         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 509         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 510         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 511         params.vport_id = 0;
 512         params.sge_tpa_params = &tpa_params;
 513         for_each_hwfn(edev, i) {
 514                 p_hwfn = &edev->hwfns[i];
 515                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 516                 rc = ecore_sp_vport_update(p_hwfn, &params,
 517                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 518                 if (rc != ECORE_SUCCESS) {
 519                         DP_ERR(edev, "Failed to update LRO\n");
 520                         return -1;
 521                 }
 522         }
 523
 524         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 525
 526         return 0;
 527 }
 528
 529 /* Update MTU via vport-update without doing port restart.
 530  * The vport must be deactivated before calling this API.
 531  */
 532 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 533 {
 534         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 535         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 536         struct ecore_sp_vport_update_params params;
 537         struct ecore_hwfn *p_hwfn;
 538         int rc;
 539         int i;
 540
 541         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 542         params.vport_id = 0;
 543         params.mtu = mtu;
 544         params.vport_id = 0;
 545         for_each_hwfn(edev, i) {
 546                 p_hwfn = &edev->hwfns[i];
 547                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 548                 rc = ecore_sp_vport_update(p_hwfn, &params,
 549                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 550                 if (rc != ECORE_SUCCESS) {
 551                         DP_ERR(edev, "Failed to update MTU\n");
 552                         return -1;
 553                 }
 554         }
 555         DP_INFO(edev, "MTU updated to %u\n", mtu);
 556
 557         return 0;
 558 }
 559
 560 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 561 {
 562         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 563         ucast->is_rx_filter = true;
 564         ucast->is_tx_filter = true;
 565         /* ucast->assert_on_error = true; - For debug */
 566 }
 567
 568 static int
 569 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 570                              enum qed_filter_rx_mode_type type)
 571 {
 572         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 573         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 574         struct ecore_filter_accept_flags flags;
 575
 576         memset(&flags, 0, sizeof(flags));
 577
 578         flags.update_rx_mode_config = 1;
 579         flags.update_tx_mode_config = 1;
 580         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 581                 ECORE_ACCEPT_MCAST_MATCHED |
 582                 ECORE_ACCEPT_BCAST;
 583
 584         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 585                 ECORE_ACCEPT_MCAST_MATCHED |
 586                 ECORE_ACCEPT_BCAST;
 587
 588         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 589                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 590                 if (IS_VF(edev)) {
 591                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 592                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 593                 }
 594         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 595                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 596         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 597                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 598                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 599                         ECORE_ACCEPT_MCAST_UNMATCHED;
 600         }
 601
 602         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 603                         ECORE_SPQ_MODE_CB, NULL);
 604 }
 605
 606 static int
 607 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 608                   bool enable, bool mask)
 609 {
 610         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 611         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 612         enum _ecore_status_t rc = ECORE_INVAL;
 613         struct ecore_ptt *p_ptt;
 614         struct ecore_tunnel_info tunn;
 615         struct ecore_hwfn *p_hwfn;
 616         int i;
 617
 618         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 619         tunn.vxlan.b_update_mode = enable;
 620         tunn.vxlan.b_mode_enabled = mask;
 621         tunn.b_update_rx_cls = true;
 622         tunn.b_update_tx_cls = true;
 623         tunn.vxlan.tun_cls = clss;
 624
 625         for_each_hwfn(edev, i) {
 626                 p_hwfn = &edev->hwfns[i];
 627                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 628                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 629                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
 630                 if (rc != ECORE_SUCCESS) {
 631                         DP_ERR(edev, "Failed to update tunn_clss %u\n",
 632                                         tunn.vxlan.tun_cls);
 633                         break;
 634                 }
 635         }
 636
 637         if (rc == ECORE_SUCCESS) {
 638                 qdev->vxlan.enable = enable;
 639                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 640                 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
 641         }
 642
 643         return rc;
 644 }
 645
 646 static int
 647 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 648                   bool add)
 649 {
 650         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 651         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 652         struct qede_ucast_entry *tmp = NULL;
 653         struct qede_ucast_entry *u;
 654         struct ether_addr *mac_addr;
 655
 656         mac_addr  = (struct ether_addr *)ucast->mac;
 657         if (add) {
 658                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 659                         if ((memcmp(mac_addr, &tmp->mac,
 660                                     ETHER_ADDR_LEN) == 0) &&
 661                              ucast->vni == tmp->vni &&
 662                              ucast->vlan == tmp->vlan) {
 663                                 DP_ERR(edev, "Unicast MAC is already added"
 664                                        " with vlan = %u, vni = %u\n",
 665                                        ucast->vlan,  ucast->vni);
 666                                         return -EEXIST;
 667                         }
 668                 }
 669                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 670                                RTE_CACHE_LINE_SIZE);
 671                 if (!u) {
 672                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 673                         return -ENOMEM;
 674                 }
 675                 ether_addr_copy(mac_addr, &u->mac);
 676                 u->vlan = ucast->vlan;
 677                 u->vni = ucast->vni;
 678                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 679                 qdev->num_uc_addr++;
 680         } else {
 681                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 682                         if ((memcmp(mac_addr, &tmp->mac,
 683                                     ETHER_ADDR_LEN) == 0) &&
 684                             ucast->vlan == tmp->vlan      &&
 685                             ucast->vni == tmp->vni)
 686                         break;
 687                 }
 688                 if (tmp == NULL) {
 689                         DP_INFO(edev, "Unicast MAC is not found\n");
 690                         return -EINVAL;
 691                 }
 692                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 693                 qdev->num_uc_addr--;
 694         }
 695
 696         return 0;
 697 }
 698
 699 static int
 700 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 701                   bool add)
 702 {
 703         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 704         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 705         struct ether_addr *mac_addr;
 706         struct qede_mcast_entry *tmp = NULL;
 707         struct qede_mcast_entry *m;
 708
 709         mac_addr  = (struct ether_addr *)mcast->mac;
 710         if (add) {
 711                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 712                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 713                                 DP_ERR(edev,
 714                                         "Multicast MAC is already added\n");
 715                                 return -EEXIST;
 716                         }
 717                 }
 718                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 719                         RTE_CACHE_LINE_SIZE);
 720                 if (!m) {
 721                         DP_ERR(edev,
 722                                 "Did not allocate memory for mcast\n");
 723                         return -ENOMEM;
 724                 }
 725                 ether_addr_copy(mac_addr, &m->mac);
 726                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 727                 qdev->num_mc_addr++;
 728         } else {
 729                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 730                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 731                                 break;
 732                 }
 733                 if (tmp == NULL) {
 734                         DP_INFO(edev, "Multicast mac is not found\n");
 735                         return -EINVAL;
 736                 }
 737                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 738                              qede_mcast_entry, list);
 739                 qdev->num_mc_addr--;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static enum _ecore_status_t
 746 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 747                  bool add)
 748 {
 749         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 750         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 751         enum _ecore_status_t rc;
 752         struct ecore_filter_mcast mcast;
 753         struct qede_mcast_entry *tmp;
 754         uint16_t j = 0;
 755
 756         /* Multicast */
 757         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 758                 if (add) {
 759                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 760                                 DP_ERR(edev,
 761                                        "Mcast filter table limit exceeded, "
 762                                        "Please enable mcast promisc mode\n");
 763                                 return -ECORE_INVAL;
 764                         }
 765                 }
 766                 rc = qede_mcast_filter(eth_dev, ucast, add);
 767                 if (rc == 0) {
 768                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 769                         memset(&mcast, 0, sizeof(mcast));
 770                         mcast.num_mc_addrs = qdev->num_mc_addr;
 771                         mcast.opcode = ECORE_FILTER_ADD;
 772                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 773                                 ether_addr_copy(&tmp->mac,
 774                                         (struct ether_addr *)&mcast.mac[j]);
 775                                 j++;
 776                         }
 777                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 778                                                     ECORE_SPQ_MODE_CB, NULL);
 779                 }
 780                 if (rc != ECORE_SUCCESS) {
 781                         DP_ERR(edev, "Failed to add multicast filter"
 782                                " rc = %d, op = %d\n", rc, add);
 783                 }
 784         } else { /* Unicast */
 785                 if (add) {
 786                         if (qdev->num_uc_addr >=
 787                             qdev->dev_info.num_mac_filters) {
 788                                 DP_ERR(edev,
 789                                        "Ucast filter table limit exceeded,"
 790                                        " Please enable promisc mode\n");
 791                                 return -ECORE_INVAL;
 792                         }
 793                 }
 794                 rc = qede_ucast_filter(eth_dev, ucast, add);
 795                 if (rc == 0)
 796                         rc = ecore_filter_ucast_cmd(edev, ucast,
 797                                                     ECORE_SPQ_MODE_CB, NULL);
 798                 if (rc != ECORE_SUCCESS) {
 799                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 800                                rc, add);
 801                 }
 802         }
 803
 804         return rc;
 805 }
 806
 807 static int
 808 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 809                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 810 {
 811         struct ecore_filter_ucast ucast;
 812         int re;
 813
 814         qede_set_ucast_cmn_params(&ucast);
 815         ucast.type = ECORE_FILTER_MAC;
 816         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 817         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 818         return re;
 819 }
 820
 821 static void
 822 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 823 {
 824         struct qede_dev *qdev = eth_dev->data->dev_private;
 825         struct ecore_dev *edev = &qdev->edev;
 826         struct ecore_filter_ucast ucast;
 827
 828         PMD_INIT_FUNC_TRACE(edev);
 829
 830         if (index >= qdev->dev_info.num_mac_filters) {
 831                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 832                        index, qdev->dev_info.num_mac_filters);
 833                 return;
 834         }
 835
 836         qede_set_ucast_cmn_params(&ucast);
 837         ucast.opcode = ECORE_FILTER_REMOVE;
 838         ucast.type = ECORE_FILTER_MAC;
 839
 840         /* Use the index maintained by rte */
 841         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 842                         (struct ether_addr *)&ucast.mac);
 843
 844         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 845 }
 846
 847 static void
 848 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 849 {
 850         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 851         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 852
 853         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 854                                                mac_addr->addr_bytes)) {
 855                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 856                 ether_addr_copy(&qdev->primary_mac,
 857                                 &eth_dev->data->mac_addrs[0]);
 858                 return;
 859         }
 860
 861         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 862 }
 863
 864 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 865 {
 866         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 867         struct ecore_sp_vport_update_params params;
 868         struct ecore_hwfn *p_hwfn;
 869         uint8_t i;
 870         int rc;
 871
 872         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 873         params.vport_id = 0;
 874         params.update_accept_any_vlan_flg = 1;
 875         params.accept_any_vlan = flg;
 876         for_each_hwfn(edev, i) {
 877                 p_hwfn = &edev->hwfns[i];
 878                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 879                 rc = ecore_sp_vport_update(p_hwfn, &params,
 880                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 881                 if (rc != ECORE_SUCCESS) {
 882                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 883                         return;
 884                 }
 885         }
 886
 887         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 888 }
 889
 890 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 891 {
 892         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 893         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 894         struct ecore_sp_vport_update_params params;
 895         struct ecore_hwfn *p_hwfn;
 896         uint8_t i;
 897         int rc;
 898
 899         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 900         params.vport_id = 0;
 901         params.update_inner_vlan_removal_flg = 1;
 902         params.inner_vlan_removal_flg = flg;
 903         for_each_hwfn(edev, i) {
 904                 p_hwfn = &edev->hwfns[i];
 905                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 906                 rc = ecore_sp_vport_update(p_hwfn, &params,
 907                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 908                 if (rc != ECORE_SUCCESS) {
 909                         DP_ERR(edev, "Failed to update vport\n");
 910                         return -1;
 911                 }
 912         }
 913
 914         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 915         return 0;
 916 }
 917
 918 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 919                                 uint16_t vlan_id, int on)
 920 {
 921         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 922         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 923         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 924         struct qede_vlan_entry *tmp = NULL;
 925         struct qede_vlan_entry *vlan;
 926         struct ecore_filter_ucast ucast;
 927         int rc;
 928
 929         if (on) {
 930                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 931                         DP_ERR(edev, "Reached max VLAN filter limit"
 932                                       " enabling accept_any_vlan\n");
 933                         qede_config_accept_any_vlan(qdev, true);
 934                         return 0;
 935                 }
 936
 937                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 938                         if (tmp->vid == vlan_id) {
 939                                 DP_ERR(edev, "VLAN %u already configured\n",
 940                                        vlan_id);
 941                                 return -EEXIST;
 942                         }
 943                 }
 944
 945                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 946                                   RTE_CACHE_LINE_SIZE);
 947
 948                 if (!vlan) {
 949                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 950                         return -ENOMEM;
 951                 }
 952
 953                 qede_set_ucast_cmn_params(&ucast);
 954                 ucast.opcode = ECORE_FILTER_ADD;
 955                 ucast.type = ECORE_FILTER_VLAN;
 956                 ucast.vlan = vlan_id;
 957                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 958                                             NULL);
 959                 if (rc != 0) {
 960                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 961                                rc);
 962                         rte_free(vlan);
 963                 } else {
 964                         vlan->vid = vlan_id;
 965                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 966                         qdev->configured_vlans++;
 967                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 968                                 vlan_id, qdev->configured_vlans);
 969                 }
 970         } else {
 971                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 972                         if (tmp->vid == vlan_id)
 973                                 break;
 974                 }
 975
 976                 if (!tmp) {
 977                         if (qdev->configured_vlans == 0) {
 978                                 DP_INFO(edev,
 979                                         "No VLAN filters configured yet\n");
 980                                 return 0;
 981                         }
 982
 983                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 984                         return -EINVAL;
 985                 }
 986
 987                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 988
 989                 qede_set_ucast_cmn_params(&ucast);
 990                 ucast.opcode = ECORE_FILTER_REMOVE;
 991                 ucast.type = ECORE_FILTER_VLAN;
 992                 ucast.vlan = vlan_id;
 993                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 994                                             NULL);
 995                 if (rc != 0) {
 996                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 997                                vlan_id, rc);
 998                 } else {
 999                         qdev->configured_vlans--;
1000                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1001                                 vlan_id, qdev->configured_vlans);
1002                 }
1003         }
1004
1005         return rc;
1006 }
1007
1008 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1009 {
1010         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1011         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1012         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1013
1014         if (mask & ETH_VLAN_STRIP_MASK) {
1015                 if (rxmode->hw_vlan_strip)
1016                         (void)qede_vlan_stripping(eth_dev, 1);
1017                 else
1018                         (void)qede_vlan_stripping(eth_dev, 0);
1019         }
1020
1021         if (mask & ETH_VLAN_FILTER_MASK) {
1022                 /* VLAN filtering kicks in when a VLAN is added */
1023                 if (rxmode->hw_vlan_filter) {
1024                         qede_vlan_filter_set(eth_dev, 0, 1);
1025                 } else {
1026                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1027                                 DP_ERR(edev,
1028                                   " Please remove existing VLAN filters"
1029                                   " before disabling VLAN filtering\n");
1030                                 /* Signal app that VLAN filtering is still
1031                                  * enabled
1032                                  */
1033                                 rxmode->hw_vlan_filter = true;
1034                         } else {
1035                                 qede_vlan_filter_set(eth_dev, 0, 0);
1036                         }
1037                 }
1038         }
1039
1040         if (mask & ETH_VLAN_EXTEND_MASK)
1041                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1042                         " and classification is based on outer tag only\n");
1043
1044         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1045                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1046 }
1047
1048 static void qede_prandom_bytes(uint32_t *buff)
1049 {
1050         uint8_t i;
1051
1052         srand((unsigned int)time(NULL));
1053         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1054                 buff[i] = rand();
1055 }
1056
1057 int qede_config_rss(struct rte_eth_dev *eth_dev)
1058 {
1059         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1060 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1061         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1062 #endif
1063         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1064         struct rte_eth_rss_reta_entry64 reta_conf[2];
1065         struct rte_eth_rss_conf rss_conf;
1066         uint32_t i, id, pos, q;
1067
1068         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1069         if (!rss_conf.rss_key) {
1070                 DP_INFO(edev, "Applying driver default key\n");
1071                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1072                 qede_prandom_bytes(&def_rss_key[0]);
1073                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1074         }
1075
1076         /* Configure RSS hash */
1077         if (qede_rss_hash_update(eth_dev, &rss_conf))
1078                 return -EINVAL;
1079
1080         /* Configure default RETA */
1081         memset(reta_conf, 0, sizeof(reta_conf));
1082         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1083                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1084
1085         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1086                 id = i / RTE_RETA_GROUP_SIZE;
1087                 pos = i % RTE_RETA_GROUP_SIZE;
1088                 q = i % QEDE_RSS_COUNT(qdev);
1089                 reta_conf[id].reta[pos] = q;
1090         }
1091         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1092                                  ECORE_RSS_IND_TABLE_SIZE))
1093                 return -EINVAL;
1094
1095         return 0;
1096 }
1097
1098 static void qede_fastpath_start(struct ecore_dev *edev)
1099 {
1100         struct ecore_hwfn *p_hwfn;
1101         int i;
1102
1103         for_each_hwfn(edev, i) {
1104                 p_hwfn = &edev->hwfns[i];
1105                 ecore_hw_start_fastpath(p_hwfn);
1106         }
1107 }
1108
1109 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1110 {
1111         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1112         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1113
1114         PMD_INIT_FUNC_TRACE(edev);
1115
1116         /* Update MTU only if it has changed */
1117         if (qdev->mtu != qdev->new_mtu) {
1118                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1119                         goto err;
1120                 qdev->mtu = qdev->new_mtu;
1121                 /* If MTU has changed then update TPA too */
1122                 if (qdev->enable_lro)
1123                         if (qede_enable_tpa(eth_dev, true))
1124                                 goto err;
1125         }
1126
1127         /* Start queues */
1128         if (qede_start_queues(eth_dev))
1129                 goto err;
1130
1131         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1132          * enabling RSS. Hence RSS configuration is deferred upto this point.
1133          * Also, we would like to retain similar behavior in PF case, so we
1134          * don't do PF/VF specific check here.
1135          */
1136         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1137                 if (qede_config_rss(eth_dev))
1138                         goto err;
1139
1140         /* Enable vport*/
1141         if (qede_activate_vport(eth_dev, true))
1142                 goto err;
1143
1144         /* Bring-up the link */
1145         qede_dev_set_link_state(eth_dev, true);
1146
1147         /* Start/resume traffic */
1148         qede_fastpath_start(edev);
1149
1150         DP_INFO(edev, "Device started\n");
1151
1152         return 0;
1153 err:
1154         DP_ERR(edev, "Device start fails\n");
1155         return -1; /* common error code is < 0 */
1156 }
1157
1158 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1159 {
1160         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1161         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1162
1163         PMD_INIT_FUNC_TRACE(edev);
1164
1165         /* Disable vport */
1166         if (qede_activate_vport(eth_dev, false))
1167                 return;
1168
1169         if (qdev->enable_lro)
1170                 qede_enable_tpa(eth_dev, false);
1171
1172         /* TODO: Do we need disable LRO or RSS */
1173         /* Stop queues */
1174         qede_stop_queues(eth_dev);
1175
1176         /* Disable traffic */
1177         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1178
1179         /* Bring the link down */
1180         qede_dev_set_link_state(eth_dev, false);
1181
1182         DP_INFO(edev, "Device is stopped\n");
1183 }
1184
1185 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1186 {
1187         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1188         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1189         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1190
1191         PMD_INIT_FUNC_TRACE(edev);
1192
1193         /* Check requirements for 100G mode */
1194         if (ECORE_IS_CMT(edev)) {
1195                 if (eth_dev->data->nb_rx_queues < 2 ||
1196                                 eth_dev->data->nb_tx_queues < 2) {
1197                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1198                         return -EINVAL;
1199                 }
1200
1201                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1202                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1203                         DP_ERR(edev,
1204                                         "100G mode needs even no. of RX/TX queues\n");
1205                         return -EINVAL;
1206                 }
1207         }
1208
1209         /* Sanity checks and throw warnings */
1210         if (rxmode->enable_scatter)
1211                 eth_dev->data->scattered_rx = 1;
1212
1213         if (!rxmode->hw_strip_crc)
1214                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1215
1216         if (!rxmode->hw_ip_checksum)
1217                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1218                                 "in hw\n");
1219         if (rxmode->header_split)
1220                 DP_INFO(edev, "Header split enable is not supported\n");
1221         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1222                                 ETH_MQ_RX_RSS)) {
1223                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1224                 return -ENOTSUP;
1225         }
1226         /* Flow director mode check */
1227         if (qede_check_fdir_support(eth_dev))
1228                 return -ENOTSUP;
1229
1230         /* Deallocate resources if held previously. It is needed only if the
1231          * queue count has been changed from previous configuration. If its
1232          * going to change then it means RX/TX queue setup will be called
1233          * again and the fastpath pointers will be reinitialized there.
1234          */
1235         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1236             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1237                 qede_dealloc_fp_resc(eth_dev);
1238                 /* Proceed with updated queue count */
1239                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1240                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1241                 if (qede_alloc_fp_resc(qdev))
1242                         return -ENOMEM;
1243         }
1244
1245         /* VF's MTU has to be set using vport-start where as
1246          * PF's MTU can be updated via vport-update.
1247          */
1248         if (IS_VF(edev)) {
1249                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1250                         return -1;
1251         } else {
1252                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1253                         return -1;
1254         }
1255
1256         qdev->mtu = rxmode->max_rx_pkt_len;
1257         qdev->new_mtu = qdev->mtu;
1258
1259         /* Configure TPA parameters */
1260         if (rxmode->enable_lro) {
1261                 if (qede_enable_tpa(eth_dev, true))
1262                         return -EINVAL;
1263                 /* Enable scatter mode for LRO */
1264                 if (!rxmode->enable_scatter)
1265                         eth_dev->data->scattered_rx = 1;
1266         }
1267         qdev->enable_lro = rxmode->enable_lro;
1268
1269         /* Enable VLAN offloads by default */
1270         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1271                         ETH_VLAN_FILTER_MASK |
1272                         ETH_VLAN_EXTEND_MASK);
1273
1274         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1275                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1276
1277         return 0;
1278 }
1279
1280 /* Info about HW descriptor ring limitations */
1281 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1282         .nb_max = 0x8000, /* 32K */
1283         .nb_min = 128,
1284         .nb_align = 128 /* lowest common multiple */
1285 };
1286
1287 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1288         .nb_max = 0x8000, /* 32K */
1289         .nb_min = 256,
1290         .nb_align = 256,
1291         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1292         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1293 };
1294
1295 static void
1296 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1297                   struct rte_eth_dev_info *dev_info)
1298 {
1299         struct qede_dev *qdev = eth_dev->data->dev_private;
1300         struct ecore_dev *edev = &qdev->edev;
1301         struct qed_link_output link;
1302         uint32_t speed_cap = 0;
1303
1304         PMD_INIT_FUNC_TRACE(edev);
1305
1306         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1307         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1308         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1309         dev_info->rx_desc_lim = qede_rx_desc_lim;
1310         dev_info->tx_desc_lim = qede_tx_desc_lim;
1311
1312         if (IS_PF(edev))
1313                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1314                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1315         else
1316                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1317                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1318         dev_info->max_tx_queues = dev_info->max_rx_queues;
1319
1320         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1321         dev_info->max_vfs = 0;
1322         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1323         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1324         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1325
1326         dev_info->default_txconf = (struct rte_eth_txconf) {
1327                 .txq_flags = QEDE_TXQ_FLAGS,
1328         };
1329
1330         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1331                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1332                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1333                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1334                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1335                                      DEV_RX_OFFLOAD_TCP_LRO);
1336
1337         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1338                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1339                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1340                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1341                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1342                                      DEV_TX_OFFLOAD_TCP_TSO |
1343                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1344
1345         memset(&link, 0, sizeof(struct qed_link_output));
1346         qdev->ops->common->get_link(edev, &link);
1347         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1348                 speed_cap |= ETH_LINK_SPEED_1G;
1349         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1350                 speed_cap |= ETH_LINK_SPEED_10G;
1351         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1352                 speed_cap |= ETH_LINK_SPEED_25G;
1353         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1354                 speed_cap |= ETH_LINK_SPEED_40G;
1355         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1356                 speed_cap |= ETH_LINK_SPEED_50G;
1357         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1358                 speed_cap |= ETH_LINK_SPEED_100G;
1359         dev_info->speed_capa = speed_cap;
1360 }
1361
1362 /* return 0 means link status changed, -1 means not changed */
1363 static int
1364 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1365 {
1366         struct qede_dev *qdev = eth_dev->data->dev_private;
1367         struct ecore_dev *edev = &qdev->edev;
1368         uint16_t link_duplex;
1369         struct qed_link_output link;
1370         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1371
1372         memset(&link, 0, sizeof(struct qed_link_output));
1373         qdev->ops->common->get_link(edev, &link);
1374
1375         /* Link Speed */
1376         curr->link_speed = link.speed;
1377
1378         /* Link Mode */
1379         switch (link.duplex) {
1380         case QEDE_DUPLEX_HALF:
1381                 link_duplex = ETH_LINK_HALF_DUPLEX;
1382                 break;
1383         case QEDE_DUPLEX_FULL:
1384                 link_duplex = ETH_LINK_FULL_DUPLEX;
1385                 break;
1386         case QEDE_DUPLEX_UNKNOWN:
1387         default:
1388                 link_duplex = -1;
1389         }
1390         curr->link_duplex = link_duplex;
1391
1392         /* Link Status */
1393         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1394
1395         /* AN */
1396         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1397                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1398
1399         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1400                 curr->link_speed, curr->link_duplex,
1401                 curr->link_autoneg, curr->link_status);
1402
1403         /* return 0 means link status changed, -1 means not changed */
1404         return ((curr->link_status == link.link_up) ? -1 : 0);
1405 }
1406
1407 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1408 {
1409 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1410         struct qede_dev *qdev = eth_dev->data->dev_private;
1411         struct ecore_dev *edev = &qdev->edev;
1412
1413         PMD_INIT_FUNC_TRACE(edev);
1414 #endif
1415
1416         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1417
1418         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1419                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1420
1421         qed_configure_filter_rx_mode(eth_dev, type);
1422 }
1423
1424 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1425 {
1426 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1427         struct qede_dev *qdev = eth_dev->data->dev_private;
1428         struct ecore_dev *edev = &qdev->edev;
1429
1430         PMD_INIT_FUNC_TRACE(edev);
1431 #endif
1432
1433         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1434                 qed_configure_filter_rx_mode(eth_dev,
1435                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1436         else
1437                 qed_configure_filter_rx_mode(eth_dev,
1438                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1439 }
1440
1441 static void qede_poll_sp_sb_cb(void *param)
1442 {
1443         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1444         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1445         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1446         int rc;
1447
1448         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1449         qede_interrupt_action(&edev->hwfns[1]);
1450
1451         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1452                                qede_poll_sp_sb_cb,
1453                                (void *)eth_dev);
1454         if (rc != 0) {
1455                 DP_ERR(edev, "Unable to start periodic"
1456                              " timer rc %d\n", rc);
1457                 assert(false && "Unable to start periodic timer");
1458         }
1459 }
1460
1461 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1462 {
1463         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1464         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1465         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1466
1467         PMD_INIT_FUNC_TRACE(edev);
1468
1469         /* dev_stop() shall cleanup fp resources in hw but without releasing
1470          * dma memories and sw structures so that dev_start() can be called
1471          * by the app without reconfiguration. However, in dev_close() we
1472          * can release all the resources and device can be brought up newly
1473          */
1474         if (eth_dev->data->dev_started)
1475                 qede_dev_stop(eth_dev);
1476
1477         qede_stop_vport(edev);
1478         qede_fdir_dealloc_resc(eth_dev);
1479         qede_dealloc_fp_resc(eth_dev);
1480
1481         eth_dev->data->nb_rx_queues = 0;
1482         eth_dev->data->nb_tx_queues = 0;
1483
1484         qdev->ops->common->slowpath_stop(edev);
1485         qdev->ops->common->remove(edev);
1486         rte_intr_disable(&pci_dev->intr_handle);
1487         rte_intr_callback_unregister(&pci_dev->intr_handle,
1488                                      qede_interrupt_handler, (void *)eth_dev);
1489         if (ECORE_IS_CMT(edev))
1490                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1491 }
1492
1493 static int
1494 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1495 {
1496         struct qede_dev *qdev = eth_dev->data->dev_private;
1497         struct ecore_dev *edev = &qdev->edev;
1498         struct ecore_eth_stats stats;
1499         unsigned int i = 0, j = 0, qid;
1500         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1501         struct qede_tx_queue *txq;
1502
1503         ecore_get_vport_stats(edev, &stats);
1504
1505         /* RX Stats */
1506         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1507             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1508
1509         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1510             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1511
1512         eth_stats->ierrors = stats.common.rx_crc_errors +
1513             stats.common.rx_align_errors +
1514             stats.common.rx_carrier_errors +
1515             stats.common.rx_oversize_packets +
1516             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1517
1518         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1519
1520         eth_stats->imissed = stats.common.mftag_filter_discards +
1521             stats.common.mac_filter_discards +
1522             stats.common.no_buff_discards +
1523             stats.common.brb_truncates + stats.common.brb_discards;
1524
1525         /* TX stats */
1526         eth_stats->opackets = stats.common.tx_ucast_pkts +
1527             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1528
1529         eth_stats->obytes = stats.common.tx_ucast_bytes +
1530             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1531
1532         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1533
1534         /* Queue stats */
1535         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1536                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1537         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1538                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1539         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1540             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1541                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1542                        "Not all the queue stats will be displayed. Set"
1543                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1544                        " appropriately and retry.\n");
1545
1546         for_each_rss(qid) {
1547                 eth_stats->q_ipackets[i] =
1548                         *(uint64_t *)(
1549                                 ((char *)(qdev->fp_array[qid].rxq)) +
1550                                 offsetof(struct qede_rx_queue,
1551                                 rcv_pkts));
1552                 eth_stats->q_errors[i] =
1553                         *(uint64_t *)(
1554                                 ((char *)(qdev->fp_array[qid].rxq)) +
1555                                 offsetof(struct qede_rx_queue,
1556                                 rx_hw_errors)) +
1557                         *(uint64_t *)(
1558                                 ((char *)(qdev->fp_array[qid].rxq)) +
1559                                 offsetof(struct qede_rx_queue,
1560                                 rx_alloc_errors));
1561                 i++;
1562                 if (i == rxq_stat_cntrs)
1563                         break;
1564         }
1565
1566         for_each_tss(qid) {
1567                 txq = qdev->fp_array[qid].txq;
1568                 eth_stats->q_opackets[j] =
1569                         *((uint64_t *)(uintptr_t)
1570                                 (((uint64_t)(uintptr_t)(txq)) +
1571                                  offsetof(struct qede_tx_queue,
1572                                           xmit_pkts)));
1573                 j++;
1574                 if (j == txq_stat_cntrs)
1575                         break;
1576         }
1577
1578         return 0;
1579 }
1580
1581 static unsigned
1582 qede_get_xstats_count(struct qede_dev *qdev) {
1583         if (ECORE_IS_BB(&qdev->edev))
1584                 return RTE_DIM(qede_xstats_strings) +
1585                        RTE_DIM(qede_bb_xstats_strings) +
1586                        (RTE_DIM(qede_rxq_xstats_strings) *
1587                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1588                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1589         else
1590                 return RTE_DIM(qede_xstats_strings) +
1591                        RTE_DIM(qede_ah_xstats_strings) +
1592                        (RTE_DIM(qede_rxq_xstats_strings) *
1593                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1594                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1595 }
1596
1597 static int
1598 qede_get_xstats_names(struct rte_eth_dev *dev,
1599                       struct rte_eth_xstat_name *xstats_names,
1600                       __rte_unused unsigned int limit)
1601 {
1602         struct qede_dev *qdev = dev->data->dev_private;
1603         struct ecore_dev *edev = &qdev->edev;
1604         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1605         unsigned int i, qid, stat_idx = 0;
1606         unsigned int rxq_stat_cntrs;
1607
1608         if (xstats_names != NULL) {
1609                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1610                         snprintf(xstats_names[stat_idx].name,
1611                                 sizeof(xstats_names[stat_idx].name),
1612                                 "%s",
1613                                 qede_xstats_strings[i].name);
1614                         stat_idx++;
1615                 }
1616
1617                 if (ECORE_IS_BB(edev)) {
1618                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1619                                 snprintf(xstats_names[stat_idx].name,
1620                                         sizeof(xstats_names[stat_idx].name),
1621                                         "%s",
1622                                         qede_bb_xstats_strings[i].name);
1623                                 stat_idx++;
1624                         }
1625                 } else {
1626                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1627                                 snprintf(xstats_names[stat_idx].name,
1628                                         sizeof(xstats_names[stat_idx].name),
1629                                         "%s",
1630                                         qede_ah_xstats_strings[i].name);
1631                                 stat_idx++;
1632                         }
1633                 }
1634
1635                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1636                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1637                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1638                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1639                                 snprintf(xstats_names[stat_idx].name,
1640                                         sizeof(xstats_names[stat_idx].name),
1641                                         "%.4s%d%s",
1642                                         qede_rxq_xstats_strings[i].name, qid,
1643                                         qede_rxq_xstats_strings[i].name + 4);
1644                                 stat_idx++;
1645                         }
1646                 }
1647         }
1648
1649         return stat_cnt;
1650 }
1651
1652 static int
1653 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1654                 unsigned int n)
1655 {
1656         struct qede_dev *qdev = dev->data->dev_private;
1657         struct ecore_dev *edev = &qdev->edev;
1658         struct ecore_eth_stats stats;
1659         const unsigned int num = qede_get_xstats_count(qdev);
1660         unsigned int i, qid, stat_idx = 0;
1661         unsigned int rxq_stat_cntrs;
1662
1663         if (n < num)
1664                 return num;
1665
1666         ecore_get_vport_stats(edev, &stats);
1667
1668         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1669                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1670                                              qede_xstats_strings[i].offset);
1671                 xstats[stat_idx].id = stat_idx;
1672                 stat_idx++;
1673         }
1674
1675         if (ECORE_IS_BB(edev)) {
1676                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1677                         xstats[stat_idx].value =
1678                                         *(uint64_t *)(((char *)&stats) +
1679                                         qede_bb_xstats_strings[i].offset);
1680                         xstats[stat_idx].id = stat_idx;
1681                         stat_idx++;
1682                 }
1683         } else {
1684                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1685                         xstats[stat_idx].value =
1686                                         *(uint64_t *)(((char *)&stats) +
1687                                         qede_ah_xstats_strings[i].offset);
1688                         xstats[stat_idx].id = stat_idx;
1689                         stat_idx++;
1690                 }
1691         }
1692
1693         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1694                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1695         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1696                 for_each_rss(qid) {
1697                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1698                                 xstats[stat_idx].value = *(uint64_t *)(
1699                                         ((char *)(qdev->fp_array[qid].rxq)) +
1700                                          qede_rxq_xstats_strings[i].offset);
1701                                 xstats[stat_idx].id = stat_idx;
1702                                 stat_idx++;
1703                         }
1704                 }
1705         }
1706
1707         return stat_idx;
1708 }
1709
1710 static void
1711 qede_reset_xstats(struct rte_eth_dev *dev)
1712 {
1713         struct qede_dev *qdev = dev->data->dev_private;
1714         struct ecore_dev *edev = &qdev->edev;
1715
1716         ecore_reset_vport_stats(edev);
1717 }
1718
1719 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1720 {
1721         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1722         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1723         struct qed_link_params link_params;
1724         int rc;
1725
1726         DP_INFO(edev, "setting link state %d\n", link_up);
1727         memset(&link_params, 0, sizeof(link_params));
1728         link_params.link_up = link_up;
1729         rc = qdev->ops->common->set_link(edev, &link_params);
1730         if (rc != ECORE_SUCCESS)
1731                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1732
1733         return rc;
1734 }
1735
1736 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1737 {
1738         return qede_dev_set_link_state(eth_dev, true);
1739 }
1740
1741 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1742 {
1743         return qede_dev_set_link_state(eth_dev, false);
1744 }
1745
1746 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1747 {
1748         struct qede_dev *qdev = eth_dev->data->dev_private;
1749         struct ecore_dev *edev = &qdev->edev;
1750
1751         ecore_reset_vport_stats(edev);
1752 }
1753
1754 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1755 {
1756         enum qed_filter_rx_mode_type type =
1757             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1758
1759         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1760                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1761
1762         qed_configure_filter_rx_mode(eth_dev, type);
1763 }
1764
1765 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1766 {
1767         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1768                 qed_configure_filter_rx_mode(eth_dev,
1769                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1770         else
1771                 qed_configure_filter_rx_mode(eth_dev,
1772                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1773 }
1774
1775 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1776                               struct rte_eth_fc_conf *fc_conf)
1777 {
1778         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1779         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1780         struct qed_link_output current_link;
1781         struct qed_link_params params;
1782
1783         memset(&current_link, 0, sizeof(current_link));
1784         qdev->ops->common->get_link(edev, &current_link);
1785
1786         memset(&params, 0, sizeof(params));
1787         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1788         if (fc_conf->autoneg) {
1789                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1790                         DP_ERR(edev, "Autoneg not supported\n");
1791                         return -EINVAL;
1792                 }
1793                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1794         }
1795
1796         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1797         if (fc_conf->mode == RTE_FC_FULL)
1798                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1799                                         QED_LINK_PAUSE_RX_ENABLE);
1800         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1801                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1802         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1803                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1804
1805         params.link_up = true;
1806         (void)qdev->ops->common->set_link(edev, &params);
1807
1808         return 0;
1809 }
1810
1811 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1812                               struct rte_eth_fc_conf *fc_conf)
1813 {
1814         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1815         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1816         struct qed_link_output current_link;
1817
1818         memset(&current_link, 0, sizeof(current_link));
1819         qdev->ops->common->get_link(edev, &current_link);
1820
1821         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1822                 fc_conf->autoneg = true;
1823
1824         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1825                                          QED_LINK_PAUSE_TX_ENABLE))
1826                 fc_conf->mode = RTE_FC_FULL;
1827         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1828                 fc_conf->mode = RTE_FC_RX_PAUSE;
1829         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1830                 fc_conf->mode = RTE_FC_TX_PAUSE;
1831         else
1832                 fc_conf->mode = RTE_FC_NONE;
1833
1834         return 0;
1835 }
1836
1837 static const uint32_t *
1838 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1839 {
1840         static const uint32_t ptypes[] = {
1841                 RTE_PTYPE_L2_ETHER,
1842                 RTE_PTYPE_L2_ETHER_VLAN,
1843                 RTE_PTYPE_L3_IPV4,
1844                 RTE_PTYPE_L3_IPV6,
1845                 RTE_PTYPE_L4_TCP,
1846                 RTE_PTYPE_L4_UDP,
1847                 RTE_PTYPE_TUNNEL_VXLAN,
1848                 RTE_PTYPE_L4_FRAG,
1849                 /* Inner */
1850                 RTE_PTYPE_INNER_L2_ETHER,
1851                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1852                 RTE_PTYPE_INNER_L3_IPV4,
1853                 RTE_PTYPE_INNER_L3_IPV6,
1854                 RTE_PTYPE_INNER_L4_TCP,
1855                 RTE_PTYPE_INNER_L4_UDP,
1856                 RTE_PTYPE_INNER_L4_FRAG,
1857                 RTE_PTYPE_UNKNOWN
1858         };
1859
1860         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1861                 return ptypes;
1862
1863         return NULL;
1864 }
1865
1866 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1867 {
1868         *rss_caps = 0;
1869         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1870         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1871         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1872         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1873         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1874         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1875         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1876         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1877 }
1878
1879 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1880                          struct rte_eth_rss_conf *rss_conf)
1881 {
1882         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1883         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1884         struct ecore_sp_vport_update_params vport_update_params;
1885         struct ecore_rss_params rss_params;
1886         struct ecore_hwfn *p_hwfn;
1887         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1888         uint64_t hf = rss_conf->rss_hf;
1889         uint8_t len = rss_conf->rss_key_len;
1890         uint8_t idx;
1891         uint8_t i;
1892         int rc;
1893
1894         memset(&vport_update_params, 0, sizeof(vport_update_params));
1895         memset(&rss_params, 0, sizeof(rss_params));
1896
1897         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1898                 (unsigned long)hf, len, key);
1899
1900         if (hf != 0) {
1901                 /* Enabling RSS */
1902                 DP_INFO(edev, "Enabling rss\n");
1903
1904                 /* RSS caps */
1905                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1906                 rss_params.update_rss_capabilities = 1;
1907
1908                 /* RSS hash key */
1909                 if (key) {
1910                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1911                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1912                                 return -EINVAL;
1913                         }
1914                         DP_INFO(edev, "Applying user supplied hash key\n");
1915                         rss_params.update_rss_key = 1;
1916                         memcpy(&rss_params.rss_key, key, len);
1917                 }
1918                 rss_params.rss_enable = 1;
1919         }
1920
1921         rss_params.update_rss_config = 1;
1922         /* tbl_size has to be set with capabilities */
1923         rss_params.rss_table_size_log = 7;
1924         vport_update_params.vport_id = 0;
1925         /* pass the L2 handles instead of qids */
1926         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1927                 idx = qdev->rss_ind_table[i];
1928                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1929         }
1930         vport_update_params.rss_params = &rss_params;
1931
1932         for_each_hwfn(edev, i) {
1933                 p_hwfn = &edev->hwfns[i];
1934                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1935                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1936                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1937                 if (rc) {
1938                         DP_ERR(edev, "vport-update for RSS failed\n");
1939                         return rc;
1940                 }
1941         }
1942         qdev->rss_enable = rss_params.rss_enable;
1943
1944         /* Update local structure for hash query */
1945         qdev->rss_conf.rss_hf = hf;
1946         qdev->rss_conf.rss_key_len = len;
1947         if (qdev->rss_enable) {
1948                 if  (qdev->rss_conf.rss_key == NULL) {
1949                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1950                         if (qdev->rss_conf.rss_key == NULL) {
1951                                 DP_ERR(edev, "No memory to store RSS key\n");
1952                                 return -ENOMEM;
1953                         }
1954                 }
1955                 if (key && len) {
1956                         DP_INFO(edev, "Storing RSS key\n");
1957                         memcpy(qdev->rss_conf.rss_key, key, len);
1958                 }
1959         } else if (!qdev->rss_enable && len == 0) {
1960                 if (qdev->rss_conf.rss_key) {
1961                         free(qdev->rss_conf.rss_key);
1962                         qdev->rss_conf.rss_key = NULL;
1963                         DP_INFO(edev, "Free RSS key\n");
1964                 }
1965         }
1966
1967         return 0;
1968 }
1969
1970 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1971                            struct rte_eth_rss_conf *rss_conf)
1972 {
1973         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1974
1975         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1976         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1977
1978         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1979                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1980                        rss_conf->rss_key_len);
1981         return 0;
1982 }
1983
1984 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1985                                     struct ecore_rss_params *rss)
1986 {
1987         int i, fn;
1988         bool rss_mode = 1; /* enable */
1989         struct ecore_queue_cid *cid;
1990         struct ecore_rss_params *t_rss;
1991
1992         /* In regular scenario, we'd simply need to take input handlers.
1993          * But in CMT, we'd have to split the handlers according to the
1994          * engine they were configured on. We'd then have to understand
1995          * whether RSS is really required, since 2-queues on CMT doesn't
1996          * require RSS.
1997          */
1998
1999         /* CMT should be round-robin */
2000         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2001                 cid = rss->rss_ind_table[i];
2002
2003                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2004                         t_rss = &rss[0];
2005                 else
2006                         t_rss = &rss[1];
2007
2008                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2009         }
2010
2011         t_rss = &rss[1];
2012         t_rss->update_rss_ind_table = 1;
2013         t_rss->rss_table_size_log = 7;
2014         t_rss->update_rss_config = 1;
2015
2016         /* Make sure RSS is actually required */
2017         for_each_hwfn(edev, fn) {
2018                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2019                      i++) {
2020                         if (rss[fn].rss_ind_table[i] !=
2021                             rss[fn].rss_ind_table[0])
2022                                 break;
2023                 }
2024
2025                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2026                         DP_INFO(edev,
2027                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2028                         rss_mode = 0;
2029                         goto out;
2030                 }
2031         }
2032
2033 out:
2034         t_rss->rss_enable = rss_mode;
2035
2036         return rss_mode;
2037 }
2038
2039 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2040                          struct rte_eth_rss_reta_entry64 *reta_conf,
2041                          uint16_t reta_size)
2042 {
2043         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2044         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2045         struct ecore_sp_vport_update_params vport_update_params;
2046         struct ecore_rss_params *params;
2047         struct ecore_hwfn *p_hwfn;
2048         uint16_t i, idx, shift;
2049         uint8_t entry;
2050         int rc = 0;
2051
2052         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2053                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2054                        reta_size);
2055                 return -EINVAL;
2056         }
2057
2058         memset(&vport_update_params, 0, sizeof(vport_update_params));
2059         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2060                              RTE_CACHE_LINE_SIZE);
2061         if (params == NULL) {
2062                 DP_ERR(edev, "failed to allocate memory\n");
2063                 return -ENOMEM;
2064         }
2065
2066         for (i = 0; i < reta_size; i++) {
2067                 idx = i / RTE_RETA_GROUP_SIZE;
2068                 shift = i % RTE_RETA_GROUP_SIZE;
2069                 if (reta_conf[idx].mask & (1ULL << shift)) {
2070                         entry = reta_conf[idx].reta[shift];
2071                         /* Pass rxq handles to ecore */
2072                         params->rss_ind_table[i] =
2073                                         qdev->fp_array[entry].rxq->handle;
2074                         /* Update the local copy for RETA query command */
2075                         qdev->rss_ind_table[i] = entry;
2076                 }
2077         }
2078
2079         params->update_rss_ind_table = 1;
2080         params->rss_table_size_log = 7;
2081         params->update_rss_config = 1;
2082
2083         /* Fix up RETA for CMT mode device */
2084         if (ECORE_IS_CMT(edev))
2085                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2086                                                             params);
2087         vport_update_params.vport_id = 0;
2088         /* Use the current value of rss_enable */
2089         params->rss_enable = qdev->rss_enable;
2090         vport_update_params.rss_params = params;
2091
2092         for_each_hwfn(edev, i) {
2093                 p_hwfn = &edev->hwfns[i];
2094                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2095                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2096                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2097                 if (rc) {
2098                         DP_ERR(edev, "vport-update for RSS failed\n");
2099                         goto out;
2100                 }
2101         }
2102
2103 out:
2104         rte_free(params);
2105         return rc;
2106 }
2107
2108 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2109                                struct rte_eth_rss_reta_entry64 *reta_conf,
2110                                uint16_t reta_size)
2111 {
2112         struct qede_dev *qdev = eth_dev->data->dev_private;
2113         struct ecore_dev *edev = &qdev->edev;
2114         uint16_t i, idx, shift;
2115         uint8_t entry;
2116
2117         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2118                 DP_ERR(edev, "reta_size %d is not supported\n",
2119                        reta_size);
2120                 return -EINVAL;
2121         }
2122
2123         for (i = 0; i < reta_size; i++) {
2124                 idx = i / RTE_RETA_GROUP_SIZE;
2125                 shift = i % RTE_RETA_GROUP_SIZE;
2126                 if (reta_conf[idx].mask & (1ULL << shift)) {
2127                         entry = qdev->rss_ind_table[i];
2128                         reta_conf[idx].reta[shift] = entry;
2129                 }
2130         }
2131
2132         return 0;
2133 }
2134
2135
2136
2137 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2138 {
2139         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2140         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2141         struct rte_eth_dev_info dev_info = {0};
2142         struct qede_fastpath *fp;
2143         uint32_t frame_size;
2144         uint16_t rx_buf_size;
2145         uint16_t bufsz;
2146         int i;
2147
2148         PMD_INIT_FUNC_TRACE(edev);
2149         qede_dev_info_get(dev, &dev_info);
2150         frame_size = mtu + QEDE_ETH_OVERHEAD;
2151         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2152                 DP_ERR(edev, "MTU %u out of range\n", mtu);
2153                 return -EINVAL;
2154         }
2155         if (!dev->data->scattered_rx &&
2156             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2157                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2158                         dev->data->min_rx_buf_size);
2159                 return -EINVAL;
2160         }
2161         /* Temporarily replace I/O functions with dummy ones. It cannot
2162          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2163          */
2164         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2165         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2166         qede_dev_stop(dev);
2167         rte_delay_ms(1000);
2168         qdev->mtu = mtu;
2169         /* Fix up RX buf size for all queues of the port */
2170         for_each_rss(i) {
2171                 fp = &qdev->fp_array[i];
2172                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2173                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2174                 if (dev->data->scattered_rx)
2175                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2176                 else
2177                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2178                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2179                 fp->rxq->rx_buf_size = rx_buf_size;
2180                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2181         }
2182         qede_dev_start(dev);
2183         if (frame_size > ETHER_MAX_LEN)
2184                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2185         else
2186                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2187         /* update max frame size */
2188         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2189         /* Reassign back */
2190         dev->rx_pkt_burst = qede_recv_pkts;
2191         dev->tx_pkt_burst = qede_xmit_pkts;
2192
2193         return 0;
2194 }
2195
2196 static int
2197 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2198                        struct rte_eth_udp_tunnel *tunnel_udp,
2199                        bool add)
2200 {
2201         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2202         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2203         struct ecore_tunnel_info tunn; /* @DPDK */
2204         struct ecore_hwfn *p_hwfn;
2205         struct ecore_ptt *p_ptt;
2206         uint16_t udp_port;
2207         int rc, i;
2208
2209         PMD_INIT_FUNC_TRACE(edev);
2210
2211         memset(&tunn, 0, sizeof(tunn));
2212         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2213                 /* Enable VxLAN tunnel if needed before UDP port update using
2214                  * default MAC/VLAN classification.
2215                  */
2216                 if (add) {
2217                         if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2218                                 DP_INFO(edev,
2219                                         "UDP port %u was already configured\n",
2220                                         tunnel_udp->udp_port);
2221                                 return ECORE_SUCCESS;
2222                         }
2223                         /* Enable VXLAN if it was not enabled while adding
2224                          * VXLAN filter.
2225                          */
2226                         if (!qdev->vxlan.enable) {
2227                                 rc = qede_vxlan_enable(eth_dev,
2228                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2229                                 if (rc != ECORE_SUCCESS) {
2230                                         DP_ERR(edev, "Failed to enable VXLAN "
2231                                                 "prior to updating UDP port\n");
2232                                         return rc;
2233                                 }
2234                         }
2235                         udp_port = tunnel_udp->udp_port;
2236                 } else {
2237                         if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2238                                 DP_ERR(edev, "UDP port %u doesn't exist\n",
2239                                         tunnel_udp->udp_port);
2240                                 return ECORE_INVAL;
2241                         }
2242                         udp_port = 0;
2243                 }
2244
2245                 tunn.vxlan_port.b_update_port = true;
2246                 tunn.vxlan_port.port = udp_port;
2247                 for_each_hwfn(edev, i) {
2248                         p_hwfn = &edev->hwfns[i];
2249                         p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
2250                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2251                                                 ECORE_SPQ_MODE_CB, NULL);
2252                         if (rc != ECORE_SUCCESS) {
2253                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2254                                        tunn.vxlan_port.port);
2255                                 if (IS_PF(edev))
2256                                         ecore_ptt_release(p_hwfn, p_ptt);
2257                                 return rc;
2258                         }
2259                 }
2260
2261                 qdev->vxlan.udp_port = udp_port;
2262                 /* If the request is to delete UDP port and if the number of
2263                  * VXLAN filters have reached 0 then VxLAN offload can be be
2264                  * disabled.
2265                  */
2266                 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2267                         return qede_vxlan_enable(eth_dev,
2268                                         ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2269         }
2270
2271         return 0;
2272 }
2273
2274 static int
2275 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2276                       struct rte_eth_udp_tunnel *tunnel_udp)
2277 {
2278         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2279 }
2280
2281 static int
2282 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2283                       struct rte_eth_udp_tunnel *tunnel_udp)
2284 {
2285         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2286 }
2287
2288 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2289                                        uint32_t *clss, char *str)
2290 {
2291         uint16_t j;
2292         *clss = MAX_ECORE_TUNN_CLSS;
2293
2294         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2295                 if (filter == qede_tunn_types[j].rte_filter_type) {
2296                         *type = qede_tunn_types[j].qede_type;
2297                         *clss = qede_tunn_types[j].qede_tunn_clss;
2298                         strcpy(str, qede_tunn_types[j].string);
2299                         return;
2300                 }
2301         }
2302 }
2303
2304 static int
2305 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2306                               const struct rte_eth_tunnel_filter_conf *conf,
2307                               uint32_t type)
2308 {
2309         /* Init commmon ucast params first */
2310         qede_set_ucast_cmn_params(ucast);
2311
2312         /* Copy out the required fields based on classification type */
2313         ucast->type = type;
2314
2315         switch (type) {
2316         case ECORE_FILTER_VNI:
2317                 ucast->vni = conf->tenant_id;
2318         break;
2319         case ECORE_FILTER_INNER_VLAN:
2320                 ucast->vlan = conf->inner_vlan;
2321         break;
2322         case ECORE_FILTER_MAC:
2323                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2324                        ETHER_ADDR_LEN);
2325         break;
2326         case ECORE_FILTER_INNER_MAC:
2327                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2328                        ETHER_ADDR_LEN);
2329         break;
2330         case ECORE_FILTER_MAC_VNI_PAIR:
2331                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2332                         ETHER_ADDR_LEN);
2333                 ucast->vni = conf->tenant_id;
2334         break;
2335         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2336                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2337                         ETHER_ADDR_LEN);
2338                 ucast->vni = conf->tenant_id;
2339         break;
2340         case ECORE_FILTER_INNER_PAIR:
2341                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2342                         ETHER_ADDR_LEN);
2343                 ucast->vlan = conf->inner_vlan;
2344         break;
2345         default:
2346                 return -EINVAL;
2347         }
2348
2349         return ECORE_SUCCESS;
2350 }
2351
2352 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2353                                   enum rte_filter_op filter_op,
2354                                   const struct rte_eth_tunnel_filter_conf *conf)
2355 {
2356         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2357         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2358         enum ecore_filter_ucast_type type;
2359         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2360         struct ecore_filter_ucast ucast = {0};
2361         char str[80];
2362         uint16_t filter_type = 0;
2363         int rc;
2364
2365         PMD_INIT_FUNC_TRACE(edev);
2366
2367         switch (filter_op) {
2368         case RTE_ETH_FILTER_ADD:
2369                 if (IS_VF(edev))
2370                         return qede_vxlan_enable(eth_dev,
2371                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2372
2373                 filter_type = conf->filter_type;
2374                 /* Determine if the given filter classification is supported */
2375                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2376                 if (clss == MAX_ECORE_TUNN_CLSS) {
2377                         DP_ERR(edev, "Unsupported filter type\n");
2378                         return -EINVAL;
2379                 }
2380                 /* Init tunnel ucast params */
2381                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2382                 if (rc != ECORE_SUCCESS) {
2383                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2384                         conf->filter_type);
2385                         return rc;
2386                 }
2387                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2388                         str, filter_op, ucast.type);
2389
2390                 ucast.opcode = ECORE_FILTER_ADD;
2391
2392                 /* Skip MAC/VLAN if filter is based on VNI */
2393                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2394                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2395                         if (rc == 0) {
2396                                 /* Enable accept anyvlan */
2397                                 qede_config_accept_any_vlan(qdev, true);
2398                         }
2399                 } else {
2400                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2401                         if (rc == 0)
2402                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2403                                                     ECORE_SPQ_MODE_CB, NULL);
2404                 }
2405
2406                 if (rc != ECORE_SUCCESS)
2407                         return rc;
2408
2409                 qdev->vxlan.num_filters++;
2410                 qdev->vxlan.filter_type = filter_type;
2411                 if (!qdev->vxlan.enable)
2412                         return qede_vxlan_enable(eth_dev, clss, true, true);
2413
2414         break;
2415         case RTE_ETH_FILTER_DELETE:
2416                 if (IS_VF(edev))
2417                         return qede_vxlan_enable(eth_dev,
2418                                 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2419
2420                 ucast.opcode = ECORE_FILTER_REMOVE;
2421
2422                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2423                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2424                 } else {
2425                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2426                         if (rc == 0)
2427                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2428                                                     ECORE_SPQ_MODE_CB, NULL);
2429                 }
2430                 if (rc != ECORE_SUCCESS)
2431                         return rc;
2432
2433                 /* Disable VXLAN if VXLAN filters become 0 */
2434                 if (qdev->vxlan.num_filters == 0)
2435                         return qede_vxlan_enable(eth_dev, clss, false, true);
2436         break;
2437         default:
2438                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2439                 return -EINVAL;
2440         }
2441
2442         return 0;
2443 }
2444
2445 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2446                          enum rte_filter_type filter_type,
2447                          enum rte_filter_op filter_op,
2448                          void *arg)
2449 {
2450         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2451         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2452         struct rte_eth_tunnel_filter_conf *filter_conf =
2453                         (struct rte_eth_tunnel_filter_conf *)arg;
2454
2455         switch (filter_type) {
2456         case RTE_ETH_FILTER_TUNNEL:
2457                 switch (filter_conf->tunnel_type) {
2458                 case RTE_TUNNEL_TYPE_VXLAN:
2459                         DP_INFO(edev,
2460                                 "Packet steering to the specified Rx queue"
2461                                 " is not supported with VXLAN tunneling");
2462                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2463                                                       filter_conf));
2464                 /* Place holders for future tunneling support */
2465                 case RTE_TUNNEL_TYPE_GENEVE:
2466                 case RTE_TUNNEL_TYPE_TEREDO:
2467                 case RTE_TUNNEL_TYPE_NVGRE:
2468                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2469                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2470                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2471                                 filter_conf->tunnel_type);
2472                         return -EINVAL;
2473                 case RTE_TUNNEL_TYPE_NONE:
2474                 default:
2475                         return 0;
2476                 }
2477                 break;
2478         case RTE_ETH_FILTER_FDIR:
2479                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2480         case RTE_ETH_FILTER_NTUPLE:
2481                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2482         case RTE_ETH_FILTER_MACVLAN:
2483         case RTE_ETH_FILTER_ETHERTYPE:
2484         case RTE_ETH_FILTER_FLEXIBLE:
2485         case RTE_ETH_FILTER_SYN:
2486         case RTE_ETH_FILTER_HASH:
2487         case RTE_ETH_FILTER_L2_TUNNEL:
2488         case RTE_ETH_FILTER_MAX:
2489         default:
2490                 DP_ERR(edev, "Unsupported filter type %d\n",
2491                         filter_type);
2492                 return -EINVAL;
2493         }
2494
2495         return 0;
2496 }
2497
2498 static const struct eth_dev_ops qede_eth_dev_ops = {
2499         .dev_configure = qede_dev_configure,
2500         .dev_infos_get = qede_dev_info_get,
2501         .rx_queue_setup = qede_rx_queue_setup,
2502         .rx_queue_release = qede_rx_queue_release,
2503         .tx_queue_setup = qede_tx_queue_setup,
2504         .tx_queue_release = qede_tx_queue_release,
2505         .dev_start = qede_dev_start,
2506         .dev_set_link_up = qede_dev_set_link_up,
2507         .dev_set_link_down = qede_dev_set_link_down,
2508         .link_update = qede_link_update,
2509         .promiscuous_enable = qede_promiscuous_enable,
2510         .promiscuous_disable = qede_promiscuous_disable,
2511         .allmulticast_enable = qede_allmulticast_enable,
2512         .allmulticast_disable = qede_allmulticast_disable,
2513         .dev_stop = qede_dev_stop,
2514         .dev_close = qede_dev_close,
2515         .stats_get = qede_get_stats,
2516         .stats_reset = qede_reset_stats,
2517         .xstats_get = qede_get_xstats,
2518         .xstats_reset = qede_reset_xstats,
2519         .xstats_get_names = qede_get_xstats_names,
2520         .mac_addr_add = qede_mac_addr_add,
2521         .mac_addr_remove = qede_mac_addr_remove,
2522         .mac_addr_set = qede_mac_addr_set,
2523         .vlan_offload_set = qede_vlan_offload_set,
2524         .vlan_filter_set = qede_vlan_filter_set,
2525         .flow_ctrl_set = qede_flow_ctrl_set,
2526         .flow_ctrl_get = qede_flow_ctrl_get,
2527         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2528         .rss_hash_update = qede_rss_hash_update,
2529         .rss_hash_conf_get = qede_rss_hash_conf_get,
2530         .reta_update  = qede_rss_reta_update,
2531         .reta_query  = qede_rss_reta_query,
2532         .mtu_set = qede_set_mtu,
2533         .filter_ctrl = qede_dev_filter_ctrl,
2534         .udp_tunnel_port_add = qede_udp_dst_port_add,
2535         .udp_tunnel_port_del = qede_udp_dst_port_del,
2536 };
2537
2538 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2539         .dev_configure = qede_dev_configure,
2540         .dev_infos_get = qede_dev_info_get,
2541         .rx_queue_setup = qede_rx_queue_setup,
2542         .rx_queue_release = qede_rx_queue_release,
2543         .tx_queue_setup = qede_tx_queue_setup,
2544         .tx_queue_release = qede_tx_queue_release,
2545         .dev_start = qede_dev_start,
2546         .dev_set_link_up = qede_dev_set_link_up,
2547         .dev_set_link_down = qede_dev_set_link_down,
2548         .link_update = qede_link_update,
2549         .promiscuous_enable = qede_promiscuous_enable,
2550         .promiscuous_disable = qede_promiscuous_disable,
2551         .allmulticast_enable = qede_allmulticast_enable,
2552         .allmulticast_disable = qede_allmulticast_disable,
2553         .dev_stop = qede_dev_stop,
2554         .dev_close = qede_dev_close,
2555         .stats_get = qede_get_stats,
2556         .stats_reset = qede_reset_stats,
2557         .xstats_get = qede_get_xstats,
2558         .xstats_reset = qede_reset_xstats,
2559         .xstats_get_names = qede_get_xstats_names,
2560         .vlan_offload_set = qede_vlan_offload_set,
2561         .vlan_filter_set = qede_vlan_filter_set,
2562         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2563         .rss_hash_update = qede_rss_hash_update,
2564         .rss_hash_conf_get = qede_rss_hash_conf_get,
2565         .reta_update  = qede_rss_reta_update,
2566         .reta_query  = qede_rss_reta_query,
2567         .mtu_set = qede_set_mtu,
2568         .udp_tunnel_port_add = qede_udp_dst_port_add,
2569         .udp_tunnel_port_del = qede_udp_dst_port_del,
2570 };
2571
2572 static void qede_update_pf_params(struct ecore_dev *edev)
2573 {
2574         struct ecore_pf_params pf_params;
2575
2576         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2577         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2578         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2579         qed_ops->common->update_pf_params(edev, &pf_params);
2580 }
2581
2582 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2583 {
2584         struct rte_pci_device *pci_dev;
2585         struct rte_pci_addr pci_addr;
2586         struct qede_dev *adapter;
2587         struct ecore_dev *edev;
2588         struct qed_dev_eth_info dev_info;
2589         struct qed_slowpath_params params;
2590         static bool do_once = true;
2591         uint8_t bulletin_change;
2592         uint8_t vf_mac[ETHER_ADDR_LEN];
2593         uint8_t is_mac_forced;
2594         bool is_mac_exist;
2595         /* Fix up ecore debug level */
2596         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2597         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2598         int rc;
2599
2600         /* Extract key data structures */
2601         adapter = eth_dev->data->dev_private;
2602         edev = &adapter->edev;
2603         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2604         pci_addr = pci_dev->addr;
2605
2606         PMD_INIT_FUNC_TRACE(edev);
2607
2608         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2609                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2610                  eth_dev->data->port_id);
2611
2612         eth_dev->rx_pkt_burst = qede_recv_pkts;
2613         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2614         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2615
2616         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2617                 DP_ERR(edev, "Skipping device init from secondary process\n");
2618                 return 0;
2619         }
2620
2621         rte_eth_copy_pci_info(eth_dev, pci_dev);
2622
2623         /* @DPDK */
2624         edev->vendor_id = pci_dev->id.vendor_id;
2625         edev->device_id = pci_dev->id.device_id;
2626
2627         qed_ops = qed_get_eth_ops();
2628         if (!qed_ops) {
2629                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2630                 return -EINVAL;
2631         }
2632
2633         DP_INFO(edev, "Starting qede probe\n");
2634         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2635                                     dp_level, is_vf);
2636         if (rc != 0) {
2637                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2638                 return -ENODEV;
2639         }
2640         qede_update_pf_params(edev);
2641         rte_intr_callback_register(&pci_dev->intr_handle,
2642                                    qede_interrupt_handler, (void *)eth_dev);
2643         if (rte_intr_enable(&pci_dev->intr_handle)) {
2644                 DP_ERR(edev, "rte_intr_enable() failed\n");
2645                 return -ENODEV;
2646         }
2647
2648         /* Start the Slowpath-process */
2649         memset(&params, 0, sizeof(struct qed_slowpath_params));
2650         params.int_mode = ECORE_INT_MODE_MSIX;
2651         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2652         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2653         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2654         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2655         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2656                 QEDE_PMD_DRV_VER_STR_SIZE);
2657
2658         /* For CMT mode device do periodic polling for slowpath events.
2659          * This is required since uio device uses only one MSI-x
2660          * interrupt vector but we need one for each engine.
2661          */
2662         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2663                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2664                                        qede_poll_sp_sb_cb,
2665                                        (void *)eth_dev);
2666                 if (rc != 0) {
2667                         DP_ERR(edev, "Unable to start periodic"
2668                                      " timer rc %d\n", rc);
2669                         return -EINVAL;
2670                 }
2671         }
2672
2673         rc = qed_ops->common->slowpath_start(edev, &params);
2674         if (rc) {
2675                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2676                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2677                                      (void *)eth_dev);
2678                 return -ENODEV;
2679         }
2680
2681         rc = qed_ops->fill_dev_info(edev, &dev_info);
2682         if (rc) {
2683                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2684                 qed_ops->common->slowpath_stop(edev);
2685                 qed_ops->common->remove(edev);
2686                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2687                                      (void *)eth_dev);
2688                 return -ENODEV;
2689         }
2690
2691         qede_alloc_etherdev(adapter, &dev_info);
2692
2693         adapter->ops->common->set_name(edev, edev->name);
2694
2695         if (!is_vf)
2696                 adapter->dev_info.num_mac_filters =
2697                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2698                                             ECORE_MAC);
2699         else
2700                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2701                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2702
2703         /* Allocate memory for storing MAC addr */
2704         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2705                                         (ETHER_ADDR_LEN *
2706                                         adapter->dev_info.num_mac_filters),
2707                                         RTE_CACHE_LINE_SIZE);
2708
2709         if (eth_dev->data->mac_addrs == NULL) {
2710                 DP_ERR(edev, "Failed to allocate MAC address\n");
2711                 qed_ops->common->slowpath_stop(edev);
2712                 qed_ops->common->remove(edev);
2713                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2714                                      (void *)eth_dev);
2715                 return -ENOMEM;
2716         }
2717
2718         if (!is_vf) {
2719                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2720                                 hw_info.hw_mac_addr,
2721                                 &eth_dev->data->mac_addrs[0]);
2722                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2723                                 &adapter->primary_mac);
2724         } else {
2725                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2726                                        &bulletin_change);
2727                 if (bulletin_change) {
2728                         is_mac_exist =
2729                             ecore_vf_bulletin_get_forced_mac(
2730                                                 ECORE_LEADING_HWFN(edev),
2731                                                 vf_mac,
2732                                                 &is_mac_forced);
2733                         if (is_mac_exist && is_mac_forced) {
2734                                 DP_INFO(edev, "VF macaddr received from PF\n");
2735                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2736                                                 &eth_dev->data->mac_addrs[0]);
2737                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2738                                                 &adapter->primary_mac);
2739                         } else {
2740                                 DP_ERR(edev, "No VF macaddr assigned\n");
2741                         }
2742                 }
2743         }
2744
2745         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2746
2747         if (do_once) {
2748 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2749                 qede_print_adapter_info(adapter);
2750 #endif
2751                 do_once = false;
2752         }
2753
2754         adapter->num_tx_queues = 0;
2755         adapter->num_rx_queues = 0;
2756         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2757         SLIST_INIT(&adapter->vlan_list_head);
2758         SLIST_INIT(&adapter->uc_list_head);
2759         adapter->mtu = ETHER_MTU;
2760         adapter->new_mtu = ETHER_MTU;
2761         if (!is_vf)
2762                 if (qede_start_vport(adapter, adapter->mtu))
2763                         return -1;
2764
2765         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2766                 adapter->primary_mac.addr_bytes[0],
2767                 adapter->primary_mac.addr_bytes[1],
2768                 adapter->primary_mac.addr_bytes[2],
2769                 adapter->primary_mac.addr_bytes[3],
2770                 adapter->primary_mac.addr_bytes[4],
2771                 adapter->primary_mac.addr_bytes[5]);
2772
2773         DP_INFO(edev, "Device initialized\n");
2774
2775         return 0;
2776 }
2777
2778 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2779 {
2780         return qede_common_dev_init(eth_dev, 1);
2781 }
2782
2783 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2784 {
2785         return qede_common_dev_init(eth_dev, 0);
2786 }
2787
2788 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2789 {
2790 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2791         struct qede_dev *qdev = eth_dev->data->dev_private;
2792         struct ecore_dev *edev = &qdev->edev;
2793
2794         PMD_INIT_FUNC_TRACE(edev);
2795 #endif
2796
2797         /* only uninitialize in the primary process */
2798         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2799                 return 0;
2800
2801         /* safe to close dev here */
2802         qede_dev_close(eth_dev);
2803
2804         eth_dev->dev_ops = NULL;
2805         eth_dev->rx_pkt_burst = NULL;
2806         eth_dev->tx_pkt_burst = NULL;
2807
2808         if (eth_dev->data->mac_addrs)
2809                 rte_free(eth_dev->data->mac_addrs);
2810
2811         eth_dev->data->mac_addrs = NULL;
2812
2813         return 0;
2814 }
2815
2816 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2817 {
2818         return qede_dev_common_uninit(eth_dev);
2819 }
2820
2821 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2822 {
2823         return qede_dev_common_uninit(eth_dev);
2824 }
2825
2826 static const struct rte_pci_id pci_id_qedevf_map[] = {
2827 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2828         {
2829                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2830         },
2831         {
2832                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2833         },
2834         {
2835                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2836         },
2837         {.vendor_id = 0,}
2838 };
2839
2840 static const struct rte_pci_id pci_id_qede_map[] = {
2841 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2842         {
2843                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2844         },
2845         {
2846                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2847         },
2848         {
2849                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2850         },
2851         {
2852                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2853         },
2854         {
2855                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2856         },
2857         {
2858                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2859         },
2860         {
2861                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2862         },
2863         {
2864                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2865         },
2866         {
2867                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2868         },
2869         {
2870                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2871         },
2872         {.vendor_id = 0,}
2873 };
2874
2875 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2876         struct rte_pci_device *pci_dev)
2877 {
2878         return rte_eth_dev_pci_generic_probe(pci_dev,
2879                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2880 }
2881
2882 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2883 {
2884         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2885 }
2886
2887 static struct rte_pci_driver rte_qedevf_pmd = {
2888         .id_table = pci_id_qedevf_map,
2889         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2890         .probe = qedevf_eth_dev_pci_probe,
2891         .remove = qedevf_eth_dev_pci_remove,
2892 };
2893
2894 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2895         struct rte_pci_device *pci_dev)
2896 {
2897         return rte_eth_dev_pci_generic_probe(pci_dev,
2898                 sizeof(struct qede_dev), qede_eth_dev_init);
2899 }
2900
2901 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2902 {
2903         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2904 }
2905
2906 static struct rte_pci_driver rte_qede_pmd = {
2907         .id_table = pci_id_qede_map,
2908         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2909         .probe = qede_eth_dev_pci_probe,
2910         .remove = qede_eth_dev_pci_remove,
2911 };
2912
2913 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2914 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2915 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2916 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2917 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2918 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");