drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12 #include <rte_kvargs.h>
  13
  14 /* Globals */
  15 int qede_logtype_init;
  16 int qede_logtype_driver;
  17
  18 static const struct qed_eth_ops *qed_ops;
  19 static int64_t timer_period = 1;
  20
  21 /* VXLAN tunnel classification mapping */
  22 const struct _qede_udp_tunn_types {
  23         uint16_t rte_filter_type;
  24         enum ecore_filter_ucast_type qede_type;
  25         enum ecore_tunn_clss qede_tunn_clss;
  26         const char *string;
  27 } qede_tunn_types[] = {
  28         {
  29                 ETH_TUNNEL_FILTER_OMAC,
  30                 ECORE_FILTER_MAC,
  31                 ECORE_TUNN_CLSS_MAC_VLAN,
  32                 "outer-mac"
  33         },
  34         {
  35                 ETH_TUNNEL_FILTER_TENID,
  36                 ECORE_FILTER_VNI,
  37                 ECORE_TUNN_CLSS_MAC_VNI,
  38                 "vni"
  39         },
  40         {
  41                 ETH_TUNNEL_FILTER_IMAC,
  42                 ECORE_FILTER_INNER_MAC,
  43                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  44                 "inner-mac"
  45         },
  46         {
  47                 ETH_TUNNEL_FILTER_IVLAN,
  48                 ECORE_FILTER_INNER_VLAN,
  49                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  50                 "inner-vlan"
  51         },
  52         {
  53                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  54                 ECORE_FILTER_MAC_VNI_PAIR,
  55                 ECORE_TUNN_CLSS_MAC_VNI,
  56                 "outer-mac and vni"
  57         },
  58         {
  59                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  60                 ECORE_FILTER_UNUSED,
  61                 MAX_ECORE_TUNN_CLSS,
  62                 "outer-mac and inner-mac"
  63         },
  64         {
  65                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  66                 ECORE_FILTER_UNUSED,
  67                 MAX_ECORE_TUNN_CLSS,
  68                 "outer-mac and inner-vlan"
  69         },
  70         {
  71                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  72                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  73                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  74                 "vni and inner-mac",
  75         },
  76         {
  77                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  78                 ECORE_FILTER_UNUSED,
  79                 MAX_ECORE_TUNN_CLSS,
  80                 "vni and inner-vlan",
  81         },
  82         {
  83                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  84                 ECORE_FILTER_INNER_PAIR,
  85                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  86                 "inner-mac and inner-vlan",
  87         },
  88         {
  89                 ETH_TUNNEL_FILTER_OIP,
  90                 ECORE_FILTER_UNUSED,
  91                 MAX_ECORE_TUNN_CLSS,
  92                 "outer-IP"
  93         },
  94         {
  95                 ETH_TUNNEL_FILTER_IIP,
  96                 ECORE_FILTER_UNUSED,
  97                 MAX_ECORE_TUNN_CLSS,
  98                 "inner-IP"
  99         },
 100         {
 101                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
 102                 ECORE_FILTER_UNUSED,
 103                 MAX_ECORE_TUNN_CLSS,
 104                 "IMAC_IVLAN"
 105         },
 106         {
 107                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 108                 ECORE_FILTER_UNUSED,
 109                 MAX_ECORE_TUNN_CLSS,
 110                 "IMAC_IVLAN_TENID"
 111         },
 112         {
 113                 RTE_TUNNEL_FILTER_IMAC_TENID,
 114                 ECORE_FILTER_UNUSED,
 115                 MAX_ECORE_TUNN_CLSS,
 116                 "IMAC_TENID"
 117         },
 118         {
 119                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 120                 ECORE_FILTER_UNUSED,
 121                 MAX_ECORE_TUNN_CLSS,
 122                 "OMAC_TENID_IMAC"
 123         },
 124 };
 125
 126 struct rte_qede_xstats_name_off {
 127         char name[RTE_ETH_XSTATS_NAME_SIZE];
 128         uint64_t offset;
 129 };
 130
 131 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 132         {"rx_unicast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 134         {"rx_multicast_bytes",
 135                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 136         {"rx_broadcast_bytes",
 137                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 138         {"rx_unicast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 140         {"rx_multicast_packets",
 141                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 142         {"rx_broadcast_packets",
 143                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 144
 145         {"tx_unicast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 147         {"tx_multicast_bytes",
 148                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 149         {"tx_broadcast_bytes",
 150                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 151         {"tx_unicast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 153         {"tx_multicast_packets",
 154                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 155         {"tx_broadcast_packets",
 156                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 157
 158         {"rx_64_byte_packets",
 159                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 160         {"rx_65_to_127_byte_packets",
 161                 offsetof(struct ecore_eth_stats_common,
 162                          rx_65_to_127_byte_packets)},
 163         {"rx_128_to_255_byte_packets",
 164                 offsetof(struct ecore_eth_stats_common,
 165                          rx_128_to_255_byte_packets)},
 166         {"rx_256_to_511_byte_packets",
 167                 offsetof(struct ecore_eth_stats_common,
 168                          rx_256_to_511_byte_packets)},
 169         {"rx_512_to_1023_byte_packets",
 170                 offsetof(struct ecore_eth_stats_common,
 171                          rx_512_to_1023_byte_packets)},
 172         {"rx_1024_to_1518_byte_packets",
 173                 offsetof(struct ecore_eth_stats_common,
 174                          rx_1024_to_1518_byte_packets)},
 175         {"tx_64_byte_packets",
 176                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 177         {"tx_65_to_127_byte_packets",
 178                 offsetof(struct ecore_eth_stats_common,
 179                          tx_65_to_127_byte_packets)},
 180         {"tx_128_to_255_byte_packets",
 181                 offsetof(struct ecore_eth_stats_common,
 182                          tx_128_to_255_byte_packets)},
 183         {"tx_256_to_511_byte_packets",
 184                 offsetof(struct ecore_eth_stats_common,
 185                          tx_256_to_511_byte_packets)},
 186         {"tx_512_to_1023_byte_packets",
 187                 offsetof(struct ecore_eth_stats_common,
 188                          tx_512_to_1023_byte_packets)},
 189         {"tx_1024_to_1518_byte_packets",
 190                 offsetof(struct ecore_eth_stats_common,
 191                          tx_1024_to_1518_byte_packets)},
 192
 193         {"rx_mac_crtl_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 195         {"tx_mac_control_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 197         {"rx_pause_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 199         {"tx_pause_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 205
 206         {"rx_crc_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 208         {"rx_align_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 210         {"rx_carrier_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 212         {"rx_oversize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 214         {"rx_jabber_errors",
 215                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 216         {"rx_undersize_packet_errors",
 217                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 218         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 219         {"rx_host_buffer_not_available",
 220                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 221         /* Number of packets discarded because they are bigger than MTU */
 222         {"rx_packet_too_big_discards",
 223                 offsetof(struct ecore_eth_stats_common,
 224                          packet_too_big_discard)},
 225         {"rx_ttl_zero_discards",
 226                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 227         {"rx_multi_function_tag_filter_discards",
 228                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 229         {"rx_mac_filter_discards",
 230                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 231         {"rx_hw_buffer_truncates",
 232                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 233         {"rx_hw_buffer_discards",
 234                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats_common,
 263                          tpa_not_coalesced_pkts)},
 264         {"lro_coalesced_bytes",
 265                 offsetof(struct ecore_eth_stats_common,
 266                          tpa_coalesced_bytes)},
 267 };
 268
 269 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 270         {"rx_1519_to_1522_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_1522_byte_packets)},
 274         {"rx_1519_to_2047_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_1519_to_2047_byte_packets)},
 278         {"rx_2048_to_4095_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_2048_to_4095_byte_packets)},
 282         {"rx_4096_to_9216_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_4096_to_9216_byte_packets)},
 286         {"rx_9217_to_16383_byte_packets",
 287                 offsetof(struct ecore_eth_stats, bb) +
 288                 offsetof(struct ecore_eth_stats_bb,
 289                          rx_9217_to_16383_byte_packets)},
 290
 291         {"tx_1519_to_2047_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_1519_to_2047_byte_packets)},
 295         {"tx_2048_to_4095_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_2048_to_4095_byte_packets)},
 299         {"tx_4096_to_9216_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_4096_to_9216_byte_packets)},
 303         {"tx_9217_to_16383_byte_packets",
 304                 offsetof(struct ecore_eth_stats, bb) +
 305                 offsetof(struct ecore_eth_stats_bb,
 306                          tx_9217_to_16383_byte_packets)},
 307
 308         {"tx_lpi_entry_count",
 309                 offsetof(struct ecore_eth_stats, bb) +
 310                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 311         {"tx_total_collisions",
 312                 offsetof(struct ecore_eth_stats, bb) +
 313                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 314 };
 315
 316 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 317         {"rx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          rx_1519_to_max_byte_packets)},
 321         {"tx_1519_to_max_byte_packets",
 322                 offsetof(struct ecore_eth_stats, ah) +
 323                 offsetof(struct ecore_eth_stats_ah,
 324                          tx_1519_to_max_byte_packets)},
 325 };
 326
 327 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 328         {"rx_q_segments",
 329                 offsetof(struct qede_rx_queue, rx_segs)},
 330         {"rx_q_hw_errors",
 331                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 332         {"rx_q_allocation_errors",
 333                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 334 };
 335
 336 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 337 {
 338         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 339 }
 340
 341 static void
 342 qede_interrupt_handler(void *param)
 343 {
 344         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 345         struct qede_dev *qdev = eth_dev->data->dev_private;
 346         struct ecore_dev *edev = &qdev->edev;
 347
 348         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 349         if (rte_intr_enable(eth_dev->intr_handle))
 350                 DP_ERR(edev, "rte_intr_enable failed\n");
 351 }
 352
 353 static void
 354 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 355 {
 356         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 357         qdev->ops = qed_ops;
 358 }
 359
 360 static void qede_print_adapter_info(struct qede_dev *qdev)
 361 {
 362         struct ecore_dev *edev = &qdev->edev;
 363         struct qed_dev_info *info = &qdev->dev_info.common;
 364         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 365         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 366
 367         DP_INFO(edev, "*********************************\n");
 368         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 369         DP_INFO(edev, " Chip details : %s %c%d\n",
 370                   ECORE_IS_BB(edev) ? "BB" : "AH",
 371                   'A' + edev->chip_rev,
 372                   (int)edev->chip_metal);
 373         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 374                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 375         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 376                  ver_str, QEDE_PMD_VERSION);
 377         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 378         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 379
 380         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 381                  "%d.%d.%d.%d",
 382                 (info->mfw_rev >> 24) & 0xff,
 383                 (info->mfw_rev >> 16) & 0xff,
 384                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 385         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 386         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 387         DP_INFO(edev, "*********************************\n");
 388 }
 389
 390 static void qede_reset_queue_stats(struct qede_dev *qdev, bool xstats)
 391 {
 392         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 393         unsigned int i = 0, j = 0, qid;
 394         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
 395         struct qede_tx_queue *txq;
 396
 397         DP_VERBOSE(edev, ECORE_MSG_DEBUG, "Clearing queue stats\n");
 398
 399         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
 400                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 401         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
 402                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
 403
 404         for_each_rss(qid) {
 405                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 406                              offsetof(struct qede_rx_queue, rcv_pkts), 0,
 407                             sizeof(uint64_t));
 408                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 409                              offsetof(struct qede_rx_queue, rx_hw_errors), 0,
 410                             sizeof(uint64_t));
 411                 OSAL_MEMSET(((char *)(qdev->fp_array[qid].rxq)) +
 412                              offsetof(struct qede_rx_queue, rx_alloc_errors), 0,
 413                             sizeof(uint64_t));
 414
 415                 if (xstats)
 416                         for (j = 0; j < RTE_DIM(qede_rxq_xstats_strings); j++)
 417                                 OSAL_MEMSET((((char *)
 418                                               (qdev->fp_array[qid].rxq)) +
 419                                              qede_rxq_xstats_strings[j].offset),
 420                                             0,
 421                                             sizeof(uint64_t));
 422
 423                 i++;
 424                 if (i == rxq_stat_cntrs)
 425                         break;
 426         }
 427
 428         i = 0;
 429
 430         for_each_tss(qid) {
 431                 txq = qdev->fp_array[qid].txq;
 432
 433                 OSAL_MEMSET((uint64_t *)(uintptr_t)
 434                                 (((uint64_t)(uintptr_t)(txq)) +
 435                                  offsetof(struct qede_tx_queue, xmit_pkts)), 0,
 436                             sizeof(uint64_t));
 437
 438                 i++;
 439                 if (i == txq_stat_cntrs)
 440                         break;
 441         }
 442 }
 443
 444 static int
 445 qede_stop_vport(struct ecore_dev *edev)
 446 {
 447         struct ecore_hwfn *p_hwfn;
 448         uint8_t vport_id;
 449         int rc;
 450         int i;
 451
 452         vport_id = 0;
 453         for_each_hwfn(edev, i) {
 454                 p_hwfn = &edev->hwfns[i];
 455                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 456                                          vport_id);
 457                 if (rc != ECORE_SUCCESS) {
 458                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 459                         return rc;
 460                 }
 461         }
 462
 463         DP_INFO(edev, "vport stopped\n");
 464
 465         return 0;
 466 }
 467
 468 static int
 469 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 470 {
 471         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 472         struct ecore_sp_vport_start_params params;
 473         struct ecore_hwfn *p_hwfn;
 474         int rc;
 475         int i;
 476
 477         if (qdev->vport_started)
 478                 qede_stop_vport(edev);
 479
 480         memset(&params, 0, sizeof(params));
 481         params.vport_id = 0;
 482         params.mtu = mtu;
 483         /* @DPDK - Disable FW placement */
 484         params.zero_placement_offset = 1;
 485         for_each_hwfn(edev, i) {
 486                 p_hwfn = &edev->hwfns[i];
 487                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 488                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 489                 rc = ecore_sp_vport_start(p_hwfn, &params);
 490                 if (rc != ECORE_SUCCESS) {
 491                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 492                         return rc;
 493                 }
 494         }
 495         ecore_reset_vport_stats(edev);
 496         qdev->vport_started = true;
 497         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 498
 499         return 0;
 500 }
 501
 502 /* Activate or deactivate vport via vport-update */
 503 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 504 {
 505         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 506         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 507         struct ecore_sp_vport_update_params params;
 508         struct ecore_hwfn *p_hwfn;
 509         uint8_t i;
 510         int rc = -1;
 511
 512         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 513         params.vport_id = 0;
 514         params.update_vport_active_rx_flg = 1;
 515         params.update_vport_active_tx_flg = 1;
 516         params.vport_active_rx_flg = flg;
 517         params.vport_active_tx_flg = flg;
 518         if (!qdev->enable_tx_switching) {
 519                 if (IS_VF(edev)) {
 520                         params.update_tx_switching_flg = 1;
 521                         params.tx_switching_flg = !flg;
 522                         DP_INFO(edev, "VF tx-switching is disabled\n");
 523                 }
 524         }
 525         for_each_hwfn(edev, i) {
 526                 p_hwfn = &edev->hwfns[i];
 527                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 528                 rc = ecore_sp_vport_update(p_hwfn, &params,
 529                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 530                 if (rc != ECORE_SUCCESS) {
 531                         DP_ERR(edev, "Failed to update vport\n");
 532                         break;
 533                 }
 534         }
 535         DP_INFO(edev, "vport is %s\n", flg ? "activated" : "deactivated");
 536
 537         return rc;
 538 }
 539
 540 static void
 541 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 542                            uint16_t mtu, bool enable)
 543 {
 544         /* Enable LRO in split mode */
 545         sge_tpa_params->tpa_ipv4_en_flg = enable;
 546         sge_tpa_params->tpa_ipv6_en_flg = enable;
 547         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 548         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 549         /* set if tpa enable changes */
 550         sge_tpa_params->update_tpa_en_flg = 1;
 551         /* set if tpa parameters should be handled */
 552         sge_tpa_params->update_tpa_param_flg = enable;
 553
 554         sge_tpa_params->max_buffers_per_cqe = 20;
 555         /* Enable TPA in split mode. In this mode each TPA segment
 556          * starts on the new BD, so there is one BD per segment.
 557          */
 558         sge_tpa_params->tpa_pkt_split_flg = 1;
 559         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 560         sge_tpa_params->tpa_gro_consistent_flg = 0;
 561         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 562         sge_tpa_params->tpa_max_size = 0x7FFF;
 563         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 564         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 565 }
 566
 567 /* Enable/disable LRO via vport-update */
 568 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 569 {
 570         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 571         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 572         struct ecore_sp_vport_update_params params;
 573         struct ecore_sge_tpa_params tpa_params;
 574         struct ecore_hwfn *p_hwfn;
 575         int rc;
 576         int i;
 577
 578         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 579         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 580         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 581         params.vport_id = 0;
 582         params.sge_tpa_params = &tpa_params;
 583         for_each_hwfn(edev, i) {
 584                 p_hwfn = &edev->hwfns[i];
 585                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 586                 rc = ecore_sp_vport_update(p_hwfn, &params,
 587                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 588                 if (rc != ECORE_SUCCESS) {
 589                         DP_ERR(edev, "Failed to update LRO\n");
 590                         return -1;
 591                 }
 592         }
 593         qdev->enable_lro = flg;
 594         eth_dev->data->lro = flg;
 595
 596         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 597
 598         return 0;
 599 }
 600
 601 /* Update MTU via vport-update without doing port restart.
 602  * The vport must be deactivated before calling this API.
 603  */
 604 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 605 {
 606         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 607         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 608         struct ecore_sp_vport_update_params params;
 609         struct ecore_hwfn *p_hwfn;
 610         int rc;
 611         int i;
 612
 613         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 614         params.vport_id = 0;
 615         params.mtu = mtu;
 616         params.vport_id = 0;
 617         for_each_hwfn(edev, i) {
 618                 p_hwfn = &edev->hwfns[i];
 619                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 620                 rc = ecore_sp_vport_update(p_hwfn, &params,
 621                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 622                 if (rc != ECORE_SUCCESS) {
 623                         DP_ERR(edev, "Failed to update MTU\n");
 624                         return -1;
 625                 }
 626         }
 627         DP_INFO(edev, "MTU updated to %u\n", mtu);
 628
 629         return 0;
 630 }
 631
 632 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 633 {
 634         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 635         ucast->is_rx_filter = true;
 636         ucast->is_tx_filter = true;
 637         /* ucast->assert_on_error = true; - For debug */
 638 }
 639
 640 static int
 641 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 642                              enum qed_filter_rx_mode_type type)
 643 {
 644         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 645         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 646         struct ecore_filter_accept_flags flags;
 647
 648         memset(&flags, 0, sizeof(flags));
 649
 650         flags.update_rx_mode_config = 1;
 651         flags.update_tx_mode_config = 1;
 652         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 653                 ECORE_ACCEPT_MCAST_MATCHED |
 654                 ECORE_ACCEPT_BCAST;
 655
 656         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 657                 ECORE_ACCEPT_MCAST_MATCHED |
 658                 ECORE_ACCEPT_BCAST;
 659
 660         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 661                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 662                 if (IS_VF(edev)) {
 663                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 664                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 665                 }
 666         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 667                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 668         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 669                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 670                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 671                         ECORE_ACCEPT_MCAST_UNMATCHED;
 672         }
 673
 674         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 675                         ECORE_SPQ_MODE_CB, NULL);
 676 }
 677
 678 static int
 679 qede_tunnel_update(struct qede_dev *qdev,
 680                    struct ecore_tunnel_info *tunn_info)
 681 {
 682         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 683         enum _ecore_status_t rc = ECORE_INVAL;
 684         struct ecore_hwfn *p_hwfn;
 685         struct ecore_ptt *p_ptt;
 686         int i;
 687
 688         for_each_hwfn(edev, i) {
 689                 p_hwfn = &edev->hwfns[i];
 690                 if (IS_PF(edev)) {
 691                         p_ptt = ecore_ptt_acquire(p_hwfn);
 692                         if (!p_ptt) {
 693                                 DP_ERR(p_hwfn, "Can't acquire PTT\n");
 694                                 return -EAGAIN;
 695                         }
 696                 } else {
 697                         p_ptt = NULL;
 698                 }
 699
 700                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 701                                 tunn_info, ECORE_SPQ_MODE_CB, NULL);
 702                 if (IS_PF(edev))
 703                         ecore_ptt_release(p_hwfn, p_ptt);
 704
 705                 if (rc != ECORE_SUCCESS)
 706                         break;
 707         }
 708
 709         return rc;
 710 }
 711
 712 static int
 713 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 714                   bool enable)
 715 {
 716         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 717         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 718         enum _ecore_status_t rc = ECORE_INVAL;
 719         struct ecore_tunnel_info tunn;
 720
 721         if (qdev->vxlan.enable == enable)
 722                 return ECORE_SUCCESS;
 723
 724         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 725         tunn.vxlan.b_update_mode = true;
 726         tunn.vxlan.b_mode_enabled = enable;
 727         tunn.b_update_rx_cls = true;
 728         tunn.b_update_tx_cls = true;
 729         tunn.vxlan.tun_cls = clss;
 730
 731         tunn.vxlan_port.b_update_port = true;
 732         tunn.vxlan_port.port = enable ? QEDE_VXLAN_DEF_PORT : 0;
 733
 734         rc = qede_tunnel_update(qdev, &tunn);
 735         if (rc == ECORE_SUCCESS) {
 736                 qdev->vxlan.enable = enable;
 737                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 738                 DP_INFO(edev, "vxlan is %s, UDP port = %d\n",
 739                         enable ? "enabled" : "disabled", qdev->vxlan.udp_port);
 740         } else {
 741                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 742                        tunn.vxlan.tun_cls);
 743         }
 744
 745         return rc;
 746 }
 747
 748 static int
 749 qede_geneve_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 750                   bool enable)
 751 {
 752         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 753         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 754         enum _ecore_status_t rc = ECORE_INVAL;
 755         struct ecore_tunnel_info tunn;
 756
 757         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 758         tunn.l2_geneve.b_update_mode = true;
 759         tunn.l2_geneve.b_mode_enabled = enable;
 760         tunn.ip_geneve.b_update_mode = true;
 761         tunn.ip_geneve.b_mode_enabled = enable;
 762         tunn.l2_geneve.tun_cls = clss;
 763         tunn.ip_geneve.tun_cls = clss;
 764         tunn.b_update_rx_cls = true;
 765         tunn.b_update_tx_cls = true;
 766
 767         tunn.geneve_port.b_update_port = true;
 768         tunn.geneve_port.port = enable ? QEDE_GENEVE_DEF_PORT : 0;
 769
 770         rc = qede_tunnel_update(qdev, &tunn);
 771         if (rc == ECORE_SUCCESS) {
 772                 qdev->geneve.enable = enable;
 773                 qdev->geneve.udp_port = (enable) ? QEDE_GENEVE_DEF_PORT : 0;
 774                 DP_INFO(edev, "GENEVE is %s, UDP port = %d\n",
 775                         enable ? "enabled" : "disabled", qdev->geneve.udp_port);
 776         } else {
 777                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 778                        clss);
 779         }
 780
 781         return rc;
 782 }
 783
 784 static int
 785 qede_ipgre_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 786                   bool enable)
 787 {
 788         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 789         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 790         enum _ecore_status_t rc = ECORE_INVAL;
 791         struct ecore_tunnel_info tunn;
 792
 793         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 794         tunn.ip_gre.b_update_mode = true;
 795         tunn.ip_gre.b_mode_enabled = enable;
 796         tunn.ip_gre.tun_cls = clss;
 797         tunn.ip_gre.tun_cls = clss;
 798         tunn.b_update_rx_cls = true;
 799         tunn.b_update_tx_cls = true;
 800
 801         rc = qede_tunnel_update(qdev, &tunn);
 802         if (rc == ECORE_SUCCESS) {
 803                 qdev->ipgre.enable = enable;
 804                 DP_INFO(edev, "IPGRE is %s\n",
 805                         enable ? "enabled" : "disabled");
 806         } else {
 807                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
 808                        clss);
 809         }
 810
 811         return rc;
 812 }
 813
 814 static int
 815 qede_tunn_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 816                  enum rte_eth_tunnel_type tunn_type, bool enable)
 817 {
 818         int rc = -EINVAL;
 819
 820         switch (tunn_type) {
 821         case RTE_TUNNEL_TYPE_VXLAN:
 822                 rc = qede_vxlan_enable(eth_dev, clss, enable);
 823                 break;
 824         case RTE_TUNNEL_TYPE_GENEVE:
 825                 rc = qede_geneve_enable(eth_dev, clss, enable);
 826                 break;
 827         case RTE_TUNNEL_TYPE_IP_IN_GRE:
 828                 rc = qede_ipgre_enable(eth_dev, clss, enable);
 829                 break;
 830         default:
 831                 rc = -EINVAL;
 832                 break;
 833         }
 834
 835         return rc;
 836 }
 837
 838 static int
 839 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 840                   bool add)
 841 {
 842         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 843         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 844         struct qede_ucast_entry *tmp = NULL;
 845         struct qede_ucast_entry *u;
 846         struct ether_addr *mac_addr;
 847
 848         mac_addr  = (struct ether_addr *)ucast->mac;
 849         if (add) {
 850                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 851                         if ((memcmp(mac_addr, &tmp->mac,
 852                                     ETHER_ADDR_LEN) == 0) &&
 853                              ucast->vni == tmp->vni &&
 854                              ucast->vlan == tmp->vlan) {
 855                                 DP_ERR(edev, "Unicast MAC is already added"
 856                                        " with vlan = %u, vni = %u\n",
 857                                        ucast->vlan,  ucast->vni);
 858                                         return -EEXIST;
 859                         }
 860                 }
 861                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 862                                RTE_CACHE_LINE_SIZE);
 863                 if (!u) {
 864                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 865                         return -ENOMEM;
 866                 }
 867                 ether_addr_copy(mac_addr, &u->mac);
 868                 u->vlan = ucast->vlan;
 869                 u->vni = ucast->vni;
 870                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 871                 qdev->num_uc_addr++;
 872         } else {
 873                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 874                         if ((memcmp(mac_addr, &tmp->mac,
 875                                     ETHER_ADDR_LEN) == 0) &&
 876                             ucast->vlan == tmp->vlan      &&
 877                             ucast->vni == tmp->vni)
 878                         break;
 879                 }
 880                 if (tmp == NULL) {
 881                         DP_INFO(edev, "Unicast MAC is not found\n");
 882                         return -EINVAL;
 883                 }
 884                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 885                 qdev->num_uc_addr--;
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int
 892 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 893                   bool add)
 894 {
 895         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 896         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 897         struct ether_addr *mac_addr;
 898         struct qede_mcast_entry *tmp = NULL;
 899         struct qede_mcast_entry *m;
 900
 901         mac_addr  = (struct ether_addr *)mcast->mac;
 902         if (add) {
 903                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 904                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 905                                 DP_ERR(edev,
 906                                         "Multicast MAC is already added\n");
 907                                 return -EEXIST;
 908                         }
 909                 }
 910                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 911                         RTE_CACHE_LINE_SIZE);
 912                 if (!m) {
 913                         DP_ERR(edev,
 914                                 "Did not allocate memory for mcast\n");
 915                         return -ENOMEM;
 916                 }
 917                 ether_addr_copy(mac_addr, &m->mac);
 918                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 919                 qdev->num_mc_addr++;
 920         } else {
 921                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 922                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 923                                 break;
 924                 }
 925                 if (tmp == NULL) {
 926                         DP_INFO(edev, "Multicast mac is not found\n");
 927                         return -EINVAL;
 928                 }
 929                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 930                              qede_mcast_entry, list);
 931                 qdev->num_mc_addr--;
 932         }
 933
 934         return 0;
 935 }
 936
 937 static enum _ecore_status_t
 938 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 939                  bool add)
 940 {
 941         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 942         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 943         enum _ecore_status_t rc;
 944         struct ecore_filter_mcast mcast;
 945         struct qede_mcast_entry *tmp;
 946         uint16_t j = 0;
 947
 948         /* Multicast */
 949         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 950                 if (add) {
 951                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 952                                 DP_ERR(edev,
 953                                        "Mcast filter table limit exceeded, "
 954                                        "Please enable mcast promisc mode\n");
 955                                 return -ECORE_INVAL;
 956                         }
 957                 }
 958                 rc = qede_mcast_filter(eth_dev, ucast, add);
 959                 if (rc == 0) {
 960                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 961                         memset(&mcast, 0, sizeof(mcast));
 962                         mcast.num_mc_addrs = qdev->num_mc_addr;
 963                         mcast.opcode = ECORE_FILTER_ADD;
 964                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 965                                 ether_addr_copy(&tmp->mac,
 966                                         (struct ether_addr *)&mcast.mac[j]);
 967                                 j++;
 968                         }
 969                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 970                                                     ECORE_SPQ_MODE_CB, NULL);
 971                 }
 972                 if (rc != ECORE_SUCCESS) {
 973                         DP_ERR(edev, "Failed to add multicast filter"
 974                                " rc = %d, op = %d\n", rc, add);
 975                 }
 976         } else { /* Unicast */
 977                 if (add) {
 978                         if (qdev->num_uc_addr >=
 979                             qdev->dev_info.num_mac_filters) {
 980                                 DP_ERR(edev,
 981                                        "Ucast filter table limit exceeded,"
 982                                        " Please enable promisc mode\n");
 983                                 return -ECORE_INVAL;
 984                         }
 985                 }
 986                 rc = qede_ucast_filter(eth_dev, ucast, add);
 987                 if (rc == 0)
 988                         rc = ecore_filter_ucast_cmd(edev, ucast,
 989                                                     ECORE_SPQ_MODE_CB, NULL);
 990                 if (rc != ECORE_SUCCESS) {
 991                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 992                                rc, add);
 993                 }
 994         }
 995
 996         return rc;
 997 }
 998
 999 static int
1000 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
1001                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
1002 {
1003         struct ecore_filter_ucast ucast;
1004         int re;
1005
1006         qede_set_ucast_cmn_params(&ucast);
1007         ucast.type = ECORE_FILTER_MAC;
1008         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
1009         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
1010         return re;
1011 }
1012
1013 static void
1014 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
1015 {
1016         struct qede_dev *qdev = eth_dev->data->dev_private;
1017         struct ecore_dev *edev = &qdev->edev;
1018         struct ecore_filter_ucast ucast;
1019
1020         PMD_INIT_FUNC_TRACE(edev);
1021
1022         if (index >= qdev->dev_info.num_mac_filters) {
1023                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
1024                        index, qdev->dev_info.num_mac_filters);
1025                 return;
1026         }
1027
1028         qede_set_ucast_cmn_params(&ucast);
1029         ucast.opcode = ECORE_FILTER_REMOVE;
1030         ucast.type = ECORE_FILTER_MAC;
1031
1032         /* Use the index maintained by rte */
1033         ether_addr_copy(&eth_dev->data->mac_addrs[index],
1034                         (struct ether_addr *)&ucast.mac);
1035
1036         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
1037 }
1038
1039 static void
1040 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
1041 {
1042         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1043         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1044
1045         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
1046                                                mac_addr->addr_bytes)) {
1047                 DP_ERR(edev, "Setting MAC address is not allowed\n");
1048                 ether_addr_copy(&qdev->primary_mac,
1049                                 &eth_dev->data->mac_addrs[0]);
1050                 return;
1051         }
1052
1053         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
1054 }
1055
1056 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
1057 {
1058         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1059         struct ecore_sp_vport_update_params params;
1060         struct ecore_hwfn *p_hwfn;
1061         uint8_t i;
1062         int rc;
1063
1064         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1065         params.vport_id = 0;
1066         params.update_accept_any_vlan_flg = 1;
1067         params.accept_any_vlan = flg;
1068         for_each_hwfn(edev, i) {
1069                 p_hwfn = &edev->hwfns[i];
1070                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1071                 rc = ecore_sp_vport_update(p_hwfn, &params,
1072                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1073                 if (rc != ECORE_SUCCESS) {
1074                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
1075                         return;
1076                 }
1077         }
1078
1079         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
1080 }
1081
1082 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
1083 {
1084         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1085         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1086         struct ecore_sp_vport_update_params params;
1087         struct ecore_hwfn *p_hwfn;
1088         uint8_t i;
1089         int rc;
1090
1091         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
1092         params.vport_id = 0;
1093         params.update_inner_vlan_removal_flg = 1;
1094         params.inner_vlan_removal_flg = flg;
1095         for_each_hwfn(edev, i) {
1096                 p_hwfn = &edev->hwfns[i];
1097                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1098                 rc = ecore_sp_vport_update(p_hwfn, &params,
1099                                 ECORE_SPQ_MODE_EBLOCK, NULL);
1100                 if (rc != ECORE_SUCCESS) {
1101                         DP_ERR(edev, "Failed to update vport\n");
1102                         return -1;
1103                 }
1104         }
1105
1106         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
1107         return 0;
1108 }
1109
1110 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
1111                                 uint16_t vlan_id, int on)
1112 {
1113         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1114         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1115         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
1116         struct qede_vlan_entry *tmp = NULL;
1117         struct qede_vlan_entry *vlan;
1118         struct ecore_filter_ucast ucast;
1119         int rc;
1120
1121         if (on) {
1122                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
1123                         DP_ERR(edev, "Reached max VLAN filter limit"
1124                                       " enabling accept_any_vlan\n");
1125                         qede_config_accept_any_vlan(qdev, true);
1126                         return 0;
1127                 }
1128
1129                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1130                         if (tmp->vid == vlan_id) {
1131                                 DP_ERR(edev, "VLAN %u already configured\n",
1132                                        vlan_id);
1133                                 return -EEXIST;
1134                         }
1135                 }
1136
1137                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
1138                                   RTE_CACHE_LINE_SIZE);
1139
1140                 if (!vlan) {
1141                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
1142                         return -ENOMEM;
1143                 }
1144
1145                 qede_set_ucast_cmn_params(&ucast);
1146                 ucast.opcode = ECORE_FILTER_ADD;
1147                 ucast.type = ECORE_FILTER_VLAN;
1148                 ucast.vlan = vlan_id;
1149                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1150                                             NULL);
1151                 if (rc != 0) {
1152                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
1153                                rc);
1154                         rte_free(vlan);
1155                 } else {
1156                         vlan->vid = vlan_id;
1157                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
1158                         qdev->configured_vlans++;
1159                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
1160                                 vlan_id, qdev->configured_vlans);
1161                 }
1162         } else {
1163                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
1164                         if (tmp->vid == vlan_id)
1165                                 break;
1166                 }
1167
1168                 if (!tmp) {
1169                         if (qdev->configured_vlans == 0) {
1170                                 DP_INFO(edev,
1171                                         "No VLAN filters configured yet\n");
1172                                 return 0;
1173                         }
1174
1175                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
1176                         return -EINVAL;
1177                 }
1178
1179                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
1180
1181                 qede_set_ucast_cmn_params(&ucast);
1182                 ucast.opcode = ECORE_FILTER_REMOVE;
1183                 ucast.type = ECORE_FILTER_VLAN;
1184                 ucast.vlan = vlan_id;
1185                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1186                                             NULL);
1187                 if (rc != 0) {
1188                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1189                                vlan_id, rc);
1190                 } else {
1191                         qdev->configured_vlans--;
1192                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1193                                 vlan_id, qdev->configured_vlans);
1194                 }
1195         }
1196
1197         return rc;
1198 }
1199
1200 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1201 {
1202         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1203         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1204         uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads;
1205
1206         if (mask & ETH_VLAN_STRIP_MASK) {
1207                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1208                         (void)qede_vlan_stripping(eth_dev, 1);
1209                 else
1210                         (void)qede_vlan_stripping(eth_dev, 0);
1211         }
1212
1213         if (mask & ETH_VLAN_FILTER_MASK) {
1214                 /* VLAN filtering kicks in when a VLAN is added */
1215                 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) {
1216                         qede_vlan_filter_set(eth_dev, 0, 1);
1217                 } else {
1218                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1219                                 DP_ERR(edev,
1220                                   " Please remove existing VLAN filters"
1221                                   " before disabling VLAN filtering\n");
1222                                 /* Signal app that VLAN filtering is still
1223                                  * enabled
1224                                  */
1225                                 eth_dev->data->dev_conf.rxmode.offloads |=
1226                                                 DEV_RX_OFFLOAD_VLAN_FILTER;
1227                         } else {
1228                                 qede_vlan_filter_set(eth_dev, 0, 0);
1229                         }
1230                 }
1231         }
1232
1233         if (mask & ETH_VLAN_EXTEND_MASK)
1234                 DP_ERR(edev, "Extend VLAN not supported\n");
1235
1236         qdev->vlan_offload_mask = mask;
1237
1238         DP_INFO(edev, "VLAN offload mask %d\n", mask);
1239
1240         return 0;
1241 }
1242
1243 static void qede_prandom_bytes(uint32_t *buff)
1244 {
1245         uint8_t i;
1246
1247         srand((unsigned int)time(NULL));
1248         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1249                 buff[i] = rand();
1250 }
1251
1252 int qede_config_rss(struct rte_eth_dev *eth_dev)
1253 {
1254         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1255         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1256         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1257         struct rte_eth_rss_reta_entry64 reta_conf[2];
1258         struct rte_eth_rss_conf rss_conf;
1259         uint32_t i, id, pos, q;
1260
1261         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1262         if (!rss_conf.rss_key) {
1263                 DP_INFO(edev, "Applying driver default key\n");
1264                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1265                 qede_prandom_bytes(&def_rss_key[0]);
1266                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1267         }
1268
1269         /* Configure RSS hash */
1270         if (qede_rss_hash_update(eth_dev, &rss_conf))
1271                 return -EINVAL;
1272
1273         /* Configure default RETA */
1274         memset(reta_conf, 0, sizeof(reta_conf));
1275         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1276                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1277
1278         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1279                 id = i / RTE_RETA_GROUP_SIZE;
1280                 pos = i % RTE_RETA_GROUP_SIZE;
1281                 q = i % QEDE_RSS_COUNT(qdev);
1282                 reta_conf[id].reta[pos] = q;
1283         }
1284         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1285                                  ECORE_RSS_IND_TABLE_SIZE))
1286                 return -EINVAL;
1287
1288         return 0;
1289 }
1290
1291 static void qede_fastpath_start(struct ecore_dev *edev)
1292 {
1293         struct ecore_hwfn *p_hwfn;
1294         int i;
1295
1296         for_each_hwfn(edev, i) {
1297                 p_hwfn = &edev->hwfns[i];
1298                 ecore_hw_start_fastpath(p_hwfn);
1299         }
1300 }
1301
1302 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1303 {
1304         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1305         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1306         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1307
1308         PMD_INIT_FUNC_TRACE(edev);
1309
1310         /* Configure TPA parameters */
1311         if (rxmode->offloads & DEV_RX_OFFLOAD_TCP_LRO) {
1312                 if (qede_enable_tpa(eth_dev, true))
1313                         return -EINVAL;
1314                 /* Enable scatter mode for LRO */
1315                 if (!eth_dev->data->scattered_rx)
1316                         rxmode->offloads |= DEV_RX_OFFLOAD_SCATTER;
1317         }
1318
1319         /* Start queues */
1320         if (qede_start_queues(eth_dev))
1321                 goto err;
1322
1323         if (IS_PF(edev))
1324                 qede_reset_queue_stats(qdev, true);
1325
1326         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1327          * enabling RSS. Hence RSS configuration is deferred upto this point.
1328          * Also, we would like to retain similar behavior in PF case, so we
1329          * don't do PF/VF specific check here.
1330          */
1331         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1332                 if (qede_config_rss(eth_dev))
1333                         goto err;
1334
1335         /* Enable vport*/
1336         if (qede_activate_vport(eth_dev, true))
1337                 goto err;
1338
1339         /* Update link status */
1340         qede_link_update(eth_dev, 0);
1341
1342         /* Start/resume traffic */
1343         qede_fastpath_start(edev);
1344
1345         DP_INFO(edev, "Device started\n");
1346
1347         return 0;
1348 err:
1349         DP_ERR(edev, "Device start fails\n");
1350         return -1; /* common error code is < 0 */
1351 }
1352
1353 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1354 {
1355         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1356         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1357
1358         PMD_INIT_FUNC_TRACE(edev);
1359
1360         /* Disable vport */
1361         if (qede_activate_vport(eth_dev, false))
1362                 return;
1363
1364         if (qdev->enable_lro)
1365                 qede_enable_tpa(eth_dev, false);
1366
1367         /* Stop queues */
1368         qede_stop_queues(eth_dev);
1369
1370         /* Disable traffic */
1371         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1372
1373         DP_INFO(edev, "Device is stopped\n");
1374 }
1375
1376 #define QEDE_TX_SWITCHING               "vf_txswitch"
1377
1378 const char *valid_args[] = {
1379         QEDE_TX_SWITCHING,
1380         NULL,
1381 };
1382
1383 static int qede_args_check(const char *key, const char *val, void *opaque)
1384 {
1385         unsigned long tmp;
1386         int ret = 0;
1387         struct rte_eth_dev *eth_dev = opaque;
1388         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1389         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1390
1391         errno = 0;
1392         tmp = strtoul(val, NULL, 0);
1393         if (errno) {
1394                 DP_INFO(edev, "%s: \"%s\" is not a valid integer", key, val);
1395                 return errno;
1396         }
1397
1398         if (strcmp(QEDE_TX_SWITCHING, key) == 0)
1399                 qdev->enable_tx_switching = !!tmp;
1400
1401         return ret;
1402 }
1403
1404 static int qede_args(struct rte_eth_dev *eth_dev)
1405 {
1406         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(eth_dev->device);
1407         struct rte_kvargs *kvlist;
1408         struct rte_devargs *devargs;
1409         int ret;
1410         int i;
1411
1412         devargs = pci_dev->device.devargs;
1413         if (!devargs)
1414                 return 0; /* return success */
1415
1416         kvlist = rte_kvargs_parse(devargs->args, valid_args);
1417         if (kvlist == NULL)
1418                 return -EINVAL;
1419
1420          /* Process parameters. */
1421         for (i = 0; (valid_args[i] != NULL); ++i) {
1422                 if (rte_kvargs_count(kvlist, valid_args[i])) {
1423                         ret = rte_kvargs_process(kvlist, valid_args[i],
1424                                                  qede_args_check, eth_dev);
1425                         if (ret != ECORE_SUCCESS) {
1426                                 rte_kvargs_free(kvlist);
1427                                 return ret;
1428                         }
1429                 }
1430         }
1431         rte_kvargs_free(kvlist);
1432
1433         return 0;
1434 }
1435
1436 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1437 {
1438         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1439         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1440         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1441         int ret;
1442
1443         PMD_INIT_FUNC_TRACE(edev);
1444
1445         /* Check requirements for 100G mode */
1446         if (ECORE_IS_CMT(edev)) {
1447                 if (eth_dev->data->nb_rx_queues < 2 ||
1448                     eth_dev->data->nb_tx_queues < 2) {
1449                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1450                         return -EINVAL;
1451                 }
1452
1453                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1454                     (eth_dev->data->nb_tx_queues % 2 != 0)) {
1455                         DP_ERR(edev,
1456                                "100G mode needs even no. of RX/TX queues\n");
1457                         return -EINVAL;
1458                 }
1459         }
1460
1461         /* We need to have min 1 RX queue.There is no min check in
1462          * rte_eth_dev_configure(), so we are checking it here.
1463          */
1464         if (eth_dev->data->nb_rx_queues == 0) {
1465                 DP_ERR(edev, "Minimum one RX queue is required\n");
1466                 return -EINVAL;
1467         }
1468
1469         /* Enable Tx switching by default */
1470         qdev->enable_tx_switching = 1;
1471
1472         /* Parse devargs and fix up rxmode */
1473         if (qede_args(eth_dev))
1474                 return -ENOTSUP;
1475
1476         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE ||
1477               rxmode->mq_mode == ETH_MQ_RX_RSS)) {
1478                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1479                 return -ENOTSUP;
1480         }
1481         /* Flow director mode check */
1482         if (qede_check_fdir_support(eth_dev))
1483                 return -ENOTSUP;
1484
1485         qede_dealloc_fp_resc(eth_dev);
1486         qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1487         qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1488         if (qede_alloc_fp_resc(qdev))
1489                 return -ENOMEM;
1490
1491         /* If jumbo enabled adjust MTU */
1492         if (rxmode->offloads & DEV_RX_OFFLOAD_JUMBO_FRAME)
1493                 eth_dev->data->mtu =
1494                         eth_dev->data->dev_conf.rxmode.max_rx_pkt_len -
1495                         ETHER_HDR_LEN - ETHER_CRC_LEN;
1496
1497         if (rxmode->offloads & DEV_RX_OFFLOAD_SCATTER)
1498                 eth_dev->data->scattered_rx = 1;
1499
1500         if (qede_start_vport(qdev, eth_dev->data->mtu))
1501                 return -1;
1502
1503         qdev->mtu = eth_dev->data->mtu;
1504
1505         /* Enable VLAN offloads by default */
1506         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1507                                              ETH_VLAN_FILTER_MASK |
1508                                              ETH_VLAN_EXTEND_MASK);
1509         if (ret)
1510                 return ret;
1511
1512         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1513                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1514
1515         return 0;
1516 }
1517
1518 /* Info about HW descriptor ring limitations */
1519 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1520         .nb_max = 0x8000, /* 32K */
1521         .nb_min = 128,
1522         .nb_align = 128 /* lowest common multiple */
1523 };
1524
1525 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1526         .nb_max = 0x8000, /* 32K */
1527         .nb_min = 256,
1528         .nb_align = 256,
1529         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1530         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1531 };
1532
1533 static void
1534 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1535                   struct rte_eth_dev_info *dev_info)
1536 {
1537         struct qede_dev *qdev = eth_dev->data->dev_private;
1538         struct ecore_dev *edev = &qdev->edev;
1539         struct qed_link_output link;
1540         uint32_t speed_cap = 0;
1541
1542         PMD_INIT_FUNC_TRACE(edev);
1543
1544         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1545         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1546         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1547         dev_info->rx_desc_lim = qede_rx_desc_lim;
1548         dev_info->tx_desc_lim = qede_tx_desc_lim;
1549
1550         if (IS_PF(edev))
1551                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1552                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1553         else
1554                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1555                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1556         dev_info->max_tx_queues = dev_info->max_rx_queues;
1557
1558         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1559         dev_info->max_vfs = 0;
1560         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1561         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1562         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1563         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_IPV4_CKSUM  |
1564                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1565                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1566                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1567                                      DEV_RX_OFFLOAD_TCP_LRO     |
1568                                      DEV_RX_OFFLOAD_CRC_STRIP   |
1569                                      DEV_RX_OFFLOAD_SCATTER     |
1570                                      DEV_RX_OFFLOAD_JUMBO_FRAME |
1571                                      DEV_RX_OFFLOAD_VLAN_FILTER |
1572                                      DEV_RX_OFFLOAD_VLAN_STRIP);
1573         dev_info->rx_queue_offload_capa = 0;
1574
1575         /* TX offloads are on a per-packet basis, so it is applicable
1576          * to both at port and queue levels.
1577          */
1578         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1579                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1580                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1581                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1582                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1583                                      DEV_TX_OFFLOAD_QINQ_INSERT |
1584                                      DEV_TX_OFFLOAD_MULTI_SEGS  |
1585                                      DEV_TX_OFFLOAD_TCP_TSO     |
1586                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
1587                                      DEV_TX_OFFLOAD_GENEVE_TNL_TSO);
1588         dev_info->tx_queue_offload_capa = dev_info->tx_offload_capa;
1589
1590         dev_info->default_txconf = (struct rte_eth_txconf) {
1591                 .txq_flags = DEV_TX_OFFLOAD_MULTI_SEGS,
1592         };
1593
1594         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1595                 /* Packets are always dropped if no descriptors are available */
1596                 .rx_drop_en = 1,
1597                 /* The below RX offloads are always enabled */
1598                 .offloads = (DEV_RX_OFFLOAD_CRC_STRIP  |
1599                              DEV_RX_OFFLOAD_IPV4_CKSUM |
1600                              DEV_RX_OFFLOAD_TCP_CKSUM  |
1601                              DEV_RX_OFFLOAD_UDP_CKSUM),
1602         };
1603
1604         memset(&link, 0, sizeof(struct qed_link_output));
1605         qdev->ops->common->get_link(edev, &link);
1606         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1607                 speed_cap |= ETH_LINK_SPEED_1G;
1608         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1609                 speed_cap |= ETH_LINK_SPEED_10G;
1610         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1611                 speed_cap |= ETH_LINK_SPEED_25G;
1612         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1613                 speed_cap |= ETH_LINK_SPEED_40G;
1614         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1615                 speed_cap |= ETH_LINK_SPEED_50G;
1616         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1617                 speed_cap |= ETH_LINK_SPEED_100G;
1618         dev_info->speed_capa = speed_cap;
1619 }
1620
1621 /* return 0 means link status changed, -1 means not changed */
1622 int
1623 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1624 {
1625         struct qede_dev *qdev = eth_dev->data->dev_private;
1626         struct ecore_dev *edev = &qdev->edev;
1627         uint16_t link_duplex;
1628         struct qed_link_output link;
1629         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1630
1631         memset(&link, 0, sizeof(struct qed_link_output));
1632         qdev->ops->common->get_link(edev, &link);
1633
1634         /* Link Speed */
1635         curr->link_speed = link.speed;
1636
1637         /* Link Mode */
1638         switch (link.duplex) {
1639         case QEDE_DUPLEX_HALF:
1640                 link_duplex = ETH_LINK_HALF_DUPLEX;
1641                 break;
1642         case QEDE_DUPLEX_FULL:
1643                 link_duplex = ETH_LINK_FULL_DUPLEX;
1644                 break;
1645         case QEDE_DUPLEX_UNKNOWN:
1646         default:
1647                 link_duplex = -1;
1648         }
1649         curr->link_duplex = link_duplex;
1650
1651         /* Link Status */
1652         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1653
1654         /* AN */
1655         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1656                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1657
1658         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1659                 curr->link_speed, curr->link_duplex,
1660                 curr->link_autoneg, curr->link_status);
1661
1662         /* return 0 means link status changed, -1 means not changed */
1663         return ((curr->link_status == link.link_up) ? -1 : 0);
1664 }
1665
1666 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1667 {
1668 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1669         struct qede_dev *qdev = eth_dev->data->dev_private;
1670         struct ecore_dev *edev = &qdev->edev;
1671
1672         PMD_INIT_FUNC_TRACE(edev);
1673 #endif
1674
1675         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1676
1677         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1678                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1679
1680         qed_configure_filter_rx_mode(eth_dev, type);
1681 }
1682
1683 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1684 {
1685 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1686         struct qede_dev *qdev = eth_dev->data->dev_private;
1687         struct ecore_dev *edev = &qdev->edev;
1688
1689         PMD_INIT_FUNC_TRACE(edev);
1690 #endif
1691
1692         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1693                 qed_configure_filter_rx_mode(eth_dev,
1694                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1695         else
1696                 qed_configure_filter_rx_mode(eth_dev,
1697                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1698 }
1699
1700 static void qede_poll_sp_sb_cb(void *param)
1701 {
1702         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1703         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1704         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1705         int rc;
1706
1707         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1708         qede_interrupt_action(&edev->hwfns[1]);
1709
1710         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1711                                qede_poll_sp_sb_cb,
1712                                (void *)eth_dev);
1713         if (rc != 0) {
1714                 DP_ERR(edev, "Unable to start periodic"
1715                              " timer rc %d\n", rc);
1716                 assert(false && "Unable to start periodic timer");
1717         }
1718 }
1719
1720 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1721 {
1722         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1723         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1724         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1725
1726         PMD_INIT_FUNC_TRACE(edev);
1727
1728         /* dev_stop() shall cleanup fp resources in hw but without releasing
1729          * dma memories and sw structures so that dev_start() can be called
1730          * by the app without reconfiguration. However, in dev_close() we
1731          * can release all the resources and device can be brought up newly
1732          */
1733         if (eth_dev->data->dev_started)
1734                 qede_dev_stop(eth_dev);
1735
1736         qede_stop_vport(edev);
1737         qdev->vport_started = false;
1738         qede_fdir_dealloc_resc(eth_dev);
1739         qede_dealloc_fp_resc(eth_dev);
1740
1741         eth_dev->data->nb_rx_queues = 0;
1742         eth_dev->data->nb_tx_queues = 0;
1743
1744         /* Bring the link down */
1745         qede_dev_set_link_state(eth_dev, false);
1746         qdev->ops->common->slowpath_stop(edev);
1747         qdev->ops->common->remove(edev);
1748         rte_intr_disable(&pci_dev->intr_handle);
1749         rte_intr_callback_unregister(&pci_dev->intr_handle,
1750                                      qede_interrupt_handler, (void *)eth_dev);
1751         if (ECORE_IS_CMT(edev))
1752                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1753 }
1754
1755 static int
1756 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1757 {
1758         struct qede_dev *qdev = eth_dev->data->dev_private;
1759         struct ecore_dev *edev = &qdev->edev;
1760         struct ecore_eth_stats stats;
1761         unsigned int i = 0, j = 0, qid;
1762         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1763         struct qede_tx_queue *txq;
1764
1765         ecore_get_vport_stats(edev, &stats);
1766
1767         /* RX Stats */
1768         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1769             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1770
1771         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1772             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1773
1774         eth_stats->ierrors = stats.common.rx_crc_errors +
1775             stats.common.rx_align_errors +
1776             stats.common.rx_carrier_errors +
1777             stats.common.rx_oversize_packets +
1778             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1779
1780         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1781
1782         eth_stats->imissed = stats.common.mftag_filter_discards +
1783             stats.common.mac_filter_discards +
1784             stats.common.no_buff_discards +
1785             stats.common.brb_truncates + stats.common.brb_discards;
1786
1787         /* TX stats */
1788         eth_stats->opackets = stats.common.tx_ucast_pkts +
1789             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1790
1791         eth_stats->obytes = stats.common.tx_ucast_bytes +
1792             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1793
1794         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1795
1796         /* Queue stats */
1797         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1798                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1799         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1800                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1801         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1802             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1803                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1804                        "Not all the queue stats will be displayed. Set"
1805                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1806                        " appropriately and retry.\n");
1807
1808         for_each_rss(qid) {
1809                 eth_stats->q_ipackets[i] =
1810                         *(uint64_t *)(
1811                                 ((char *)(qdev->fp_array[qid].rxq)) +
1812                                 offsetof(struct qede_rx_queue,
1813                                 rcv_pkts));
1814                 eth_stats->q_errors[i] =
1815                         *(uint64_t *)(
1816                                 ((char *)(qdev->fp_array[qid].rxq)) +
1817                                 offsetof(struct qede_rx_queue,
1818                                 rx_hw_errors)) +
1819                         *(uint64_t *)(
1820                                 ((char *)(qdev->fp_array[qid].rxq)) +
1821                                 offsetof(struct qede_rx_queue,
1822                                 rx_alloc_errors));
1823                 i++;
1824                 if (i == rxq_stat_cntrs)
1825                         break;
1826         }
1827
1828         for_each_tss(qid) {
1829                 txq = qdev->fp_array[qid].txq;
1830                 eth_stats->q_opackets[j] =
1831                         *((uint64_t *)(uintptr_t)
1832                                 (((uint64_t)(uintptr_t)(txq)) +
1833                                  offsetof(struct qede_tx_queue,
1834                                           xmit_pkts)));
1835                 j++;
1836                 if (j == txq_stat_cntrs)
1837                         break;
1838         }
1839
1840         return 0;
1841 }
1842
1843 static unsigned
1844 qede_get_xstats_count(struct qede_dev *qdev) {
1845         if (ECORE_IS_BB(&qdev->edev))
1846                 return RTE_DIM(qede_xstats_strings) +
1847                        RTE_DIM(qede_bb_xstats_strings) +
1848                        (RTE_DIM(qede_rxq_xstats_strings) *
1849                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1850                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1851         else
1852                 return RTE_DIM(qede_xstats_strings) +
1853                        RTE_DIM(qede_ah_xstats_strings) +
1854                        (RTE_DIM(qede_rxq_xstats_strings) *
1855                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1856                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1857 }
1858
1859 static int
1860 qede_get_xstats_names(struct rte_eth_dev *dev,
1861                       struct rte_eth_xstat_name *xstats_names,
1862                       __rte_unused unsigned int limit)
1863 {
1864         struct qede_dev *qdev = dev->data->dev_private;
1865         struct ecore_dev *edev = &qdev->edev;
1866         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1867         unsigned int i, qid, stat_idx = 0;
1868         unsigned int rxq_stat_cntrs;
1869
1870         if (xstats_names != NULL) {
1871                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1872                         snprintf(xstats_names[stat_idx].name,
1873                                 sizeof(xstats_names[stat_idx].name),
1874                                 "%s",
1875                                 qede_xstats_strings[i].name);
1876                         stat_idx++;
1877                 }
1878
1879                 if (ECORE_IS_BB(edev)) {
1880                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1881                                 snprintf(xstats_names[stat_idx].name,
1882                                         sizeof(xstats_names[stat_idx].name),
1883                                         "%s",
1884                                         qede_bb_xstats_strings[i].name);
1885                                 stat_idx++;
1886                         }
1887                 } else {
1888                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1889                                 snprintf(xstats_names[stat_idx].name,
1890                                         sizeof(xstats_names[stat_idx].name),
1891                                         "%s",
1892                                         qede_ah_xstats_strings[i].name);
1893                                 stat_idx++;
1894                         }
1895                 }
1896
1897                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1898                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1899                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1900                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1901                                 snprintf(xstats_names[stat_idx].name,
1902                                         sizeof(xstats_names[stat_idx].name),
1903                                         "%.4s%d%s",
1904                                         qede_rxq_xstats_strings[i].name, qid,
1905                                         qede_rxq_xstats_strings[i].name + 4);
1906                                 stat_idx++;
1907                         }
1908                 }
1909         }
1910
1911         return stat_cnt;
1912 }
1913
1914 static int
1915 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1916                 unsigned int n)
1917 {
1918         struct qede_dev *qdev = dev->data->dev_private;
1919         struct ecore_dev *edev = &qdev->edev;
1920         struct ecore_eth_stats stats;
1921         const unsigned int num = qede_get_xstats_count(qdev);
1922         unsigned int i, qid, stat_idx = 0;
1923         unsigned int rxq_stat_cntrs;
1924
1925         if (n < num)
1926                 return num;
1927
1928         ecore_get_vport_stats(edev, &stats);
1929
1930         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1931                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1932                                              qede_xstats_strings[i].offset);
1933                 xstats[stat_idx].id = stat_idx;
1934                 stat_idx++;
1935         }
1936
1937         if (ECORE_IS_BB(edev)) {
1938                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1939                         xstats[stat_idx].value =
1940                                         *(uint64_t *)(((char *)&stats) +
1941                                         qede_bb_xstats_strings[i].offset);
1942                         xstats[stat_idx].id = stat_idx;
1943                         stat_idx++;
1944                 }
1945         } else {
1946                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1947                         xstats[stat_idx].value =
1948                                         *(uint64_t *)(((char *)&stats) +
1949                                         qede_ah_xstats_strings[i].offset);
1950                         xstats[stat_idx].id = stat_idx;
1951                         stat_idx++;
1952                 }
1953         }
1954
1955         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1956                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1957         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1958                 for_each_rss(qid) {
1959                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1960                                 xstats[stat_idx].value = *(uint64_t *)(
1961                                         ((char *)(qdev->fp_array[qid].rxq)) +
1962                                          qede_rxq_xstats_strings[i].offset);
1963                                 xstats[stat_idx].id = stat_idx;
1964                                 stat_idx++;
1965                         }
1966                 }
1967         }
1968
1969         return stat_idx;
1970 }
1971
1972 static void
1973 qede_reset_xstats(struct rte_eth_dev *dev)
1974 {
1975         struct qede_dev *qdev = dev->data->dev_private;
1976         struct ecore_dev *edev = &qdev->edev;
1977
1978         ecore_reset_vport_stats(edev);
1979         qede_reset_queue_stats(qdev, true);
1980 }
1981
1982 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1983 {
1984         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1985         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1986         struct qed_link_params link_params;
1987         int rc;
1988
1989         DP_INFO(edev, "setting link state %d\n", link_up);
1990         memset(&link_params, 0, sizeof(link_params));
1991         link_params.link_up = link_up;
1992         rc = qdev->ops->common->set_link(edev, &link_params);
1993         if (rc != ECORE_SUCCESS)
1994                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1995
1996         return rc;
1997 }
1998
1999 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
2000 {
2001         return qede_dev_set_link_state(eth_dev, true);
2002 }
2003
2004 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
2005 {
2006         return qede_dev_set_link_state(eth_dev, false);
2007 }
2008
2009 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
2010 {
2011         struct qede_dev *qdev = eth_dev->data->dev_private;
2012         struct ecore_dev *edev = &qdev->edev;
2013
2014         ecore_reset_vport_stats(edev);
2015         qede_reset_queue_stats(qdev, false);
2016 }
2017
2018 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
2019 {
2020         enum qed_filter_rx_mode_type type =
2021             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
2022
2023         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2024                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
2025
2026         qed_configure_filter_rx_mode(eth_dev, type);
2027 }
2028
2029 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
2030 {
2031         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
2032                 qed_configure_filter_rx_mode(eth_dev,
2033                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
2034         else
2035                 qed_configure_filter_rx_mode(eth_dev,
2036                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
2037 }
2038
2039 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
2040                               struct rte_eth_fc_conf *fc_conf)
2041 {
2042         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2043         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2044         struct qed_link_output current_link;
2045         struct qed_link_params params;
2046
2047         memset(&current_link, 0, sizeof(current_link));
2048         qdev->ops->common->get_link(edev, &current_link);
2049
2050         memset(&params, 0, sizeof(params));
2051         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
2052         if (fc_conf->autoneg) {
2053                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
2054                         DP_ERR(edev, "Autoneg not supported\n");
2055                         return -EINVAL;
2056                 }
2057                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
2058         }
2059
2060         /* Pause is assumed to be supported (SUPPORTED_Pause) */
2061         if (fc_conf->mode == RTE_FC_FULL)
2062                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
2063                                         QED_LINK_PAUSE_RX_ENABLE);
2064         if (fc_conf->mode == RTE_FC_TX_PAUSE)
2065                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
2066         if (fc_conf->mode == RTE_FC_RX_PAUSE)
2067                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
2068
2069         params.link_up = true;
2070         (void)qdev->ops->common->set_link(edev, &params);
2071
2072         return 0;
2073 }
2074
2075 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
2076                               struct rte_eth_fc_conf *fc_conf)
2077 {
2078         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2079         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2080         struct qed_link_output current_link;
2081
2082         memset(&current_link, 0, sizeof(current_link));
2083         qdev->ops->common->get_link(edev, &current_link);
2084
2085         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
2086                 fc_conf->autoneg = true;
2087
2088         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
2089                                          QED_LINK_PAUSE_TX_ENABLE))
2090                 fc_conf->mode = RTE_FC_FULL;
2091         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
2092                 fc_conf->mode = RTE_FC_RX_PAUSE;
2093         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
2094                 fc_conf->mode = RTE_FC_TX_PAUSE;
2095         else
2096                 fc_conf->mode = RTE_FC_NONE;
2097
2098         return 0;
2099 }
2100
2101 static const uint32_t *
2102 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
2103 {
2104         static const uint32_t ptypes[] = {
2105                 RTE_PTYPE_L2_ETHER,
2106                 RTE_PTYPE_L2_ETHER_VLAN,
2107                 RTE_PTYPE_L3_IPV4,
2108                 RTE_PTYPE_L3_IPV6,
2109                 RTE_PTYPE_L4_TCP,
2110                 RTE_PTYPE_L4_UDP,
2111                 RTE_PTYPE_TUNNEL_VXLAN,
2112                 RTE_PTYPE_L4_FRAG,
2113                 RTE_PTYPE_TUNNEL_GENEVE,
2114                 RTE_PTYPE_TUNNEL_GRE,
2115                 /* Inner */
2116                 RTE_PTYPE_INNER_L2_ETHER,
2117                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
2118                 RTE_PTYPE_INNER_L3_IPV4,
2119                 RTE_PTYPE_INNER_L3_IPV6,
2120                 RTE_PTYPE_INNER_L4_TCP,
2121                 RTE_PTYPE_INNER_L4_UDP,
2122                 RTE_PTYPE_INNER_L4_FRAG,
2123                 RTE_PTYPE_UNKNOWN
2124         };
2125
2126         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
2127                 return ptypes;
2128
2129         return NULL;
2130 }
2131
2132 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
2133 {
2134         *rss_caps = 0;
2135         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
2136         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
2137         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
2138         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
2139         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
2140         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
2141         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
2142         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
2143 }
2144
2145 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
2146                          struct rte_eth_rss_conf *rss_conf)
2147 {
2148         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2149         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2150         struct ecore_sp_vport_update_params vport_update_params;
2151         struct ecore_rss_params rss_params;
2152         struct ecore_hwfn *p_hwfn;
2153         uint32_t *key = (uint32_t *)rss_conf->rss_key;
2154         uint64_t hf = rss_conf->rss_hf;
2155         uint8_t len = rss_conf->rss_key_len;
2156         uint8_t idx;
2157         uint8_t i;
2158         int rc;
2159
2160         memset(&vport_update_params, 0, sizeof(vport_update_params));
2161         memset(&rss_params, 0, sizeof(rss_params));
2162
2163         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
2164                 (unsigned long)hf, len, key);
2165
2166         if (hf != 0) {
2167                 /* Enabling RSS */
2168                 DP_INFO(edev, "Enabling rss\n");
2169
2170                 /* RSS caps */
2171                 qede_init_rss_caps(&rss_params.rss_caps, hf);
2172                 rss_params.update_rss_capabilities = 1;
2173
2174                 /* RSS hash key */
2175                 if (key) {
2176                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
2177                                 DP_ERR(edev, "RSS key length exceeds limit\n");
2178                                 return -EINVAL;
2179                         }
2180                         DP_INFO(edev, "Applying user supplied hash key\n");
2181                         rss_params.update_rss_key = 1;
2182                         memcpy(&rss_params.rss_key, key, len);
2183                 }
2184                 rss_params.rss_enable = 1;
2185         }
2186
2187         rss_params.update_rss_config = 1;
2188         /* tbl_size has to be set with capabilities */
2189         rss_params.rss_table_size_log = 7;
2190         vport_update_params.vport_id = 0;
2191         /* pass the L2 handles instead of qids */
2192         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
2193                 idx = qdev->rss_ind_table[i];
2194                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
2195         }
2196         vport_update_params.rss_params = &rss_params;
2197
2198         for_each_hwfn(edev, i) {
2199                 p_hwfn = &edev->hwfns[i];
2200                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2201                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2202                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2203                 if (rc) {
2204                         DP_ERR(edev, "vport-update for RSS failed\n");
2205                         return rc;
2206                 }
2207         }
2208         qdev->rss_enable = rss_params.rss_enable;
2209
2210         /* Update local structure for hash query */
2211         qdev->rss_conf.rss_hf = hf;
2212         qdev->rss_conf.rss_key_len = len;
2213         if (qdev->rss_enable) {
2214                 if  (qdev->rss_conf.rss_key == NULL) {
2215                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
2216                         if (qdev->rss_conf.rss_key == NULL) {
2217                                 DP_ERR(edev, "No memory to store RSS key\n");
2218                                 return -ENOMEM;
2219                         }
2220                 }
2221                 if (key && len) {
2222                         DP_INFO(edev, "Storing RSS key\n");
2223                         memcpy(qdev->rss_conf.rss_key, key, len);
2224                 }
2225         } else if (!qdev->rss_enable && len == 0) {
2226                 if (qdev->rss_conf.rss_key) {
2227                         free(qdev->rss_conf.rss_key);
2228                         qdev->rss_conf.rss_key = NULL;
2229                         DP_INFO(edev, "Free RSS key\n");
2230                 }
2231         }
2232
2233         return 0;
2234 }
2235
2236 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
2237                            struct rte_eth_rss_conf *rss_conf)
2238 {
2239         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2240
2241         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
2242         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
2243
2244         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
2245                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
2246                        rss_conf->rss_key_len);
2247         return 0;
2248 }
2249
2250 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
2251                                     struct ecore_rss_params *rss)
2252 {
2253         int i, fn;
2254         bool rss_mode = 1; /* enable */
2255         struct ecore_queue_cid *cid;
2256         struct ecore_rss_params *t_rss;
2257
2258         /* In regular scenario, we'd simply need to take input handlers.
2259          * But in CMT, we'd have to split the handlers according to the
2260          * engine they were configured on. We'd then have to understand
2261          * whether RSS is really required, since 2-queues on CMT doesn't
2262          * require RSS.
2263          */
2264
2265         /* CMT should be round-robin */
2266         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2267                 cid = rss->rss_ind_table[i];
2268
2269                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2270                         t_rss = &rss[0];
2271                 else
2272                         t_rss = &rss[1];
2273
2274                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2275         }
2276
2277         t_rss = &rss[1];
2278         t_rss->update_rss_ind_table = 1;
2279         t_rss->rss_table_size_log = 7;
2280         t_rss->update_rss_config = 1;
2281
2282         /* Make sure RSS is actually required */
2283         for_each_hwfn(edev, fn) {
2284                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2285                      i++) {
2286                         if (rss[fn].rss_ind_table[i] !=
2287                             rss[fn].rss_ind_table[0])
2288                                 break;
2289                 }
2290
2291                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2292                         DP_INFO(edev,
2293                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2294                         rss_mode = 0;
2295                         goto out;
2296                 }
2297         }
2298
2299 out:
2300         t_rss->rss_enable = rss_mode;
2301
2302         return rss_mode;
2303 }
2304
2305 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2306                          struct rte_eth_rss_reta_entry64 *reta_conf,
2307                          uint16_t reta_size)
2308 {
2309         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2310         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2311         struct ecore_sp_vport_update_params vport_update_params;
2312         struct ecore_rss_params *params;
2313         struct ecore_hwfn *p_hwfn;
2314         uint16_t i, idx, shift;
2315         uint8_t entry;
2316         int rc = 0;
2317
2318         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2319                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2320                        reta_size);
2321                 return -EINVAL;
2322         }
2323
2324         memset(&vport_update_params, 0, sizeof(vport_update_params));
2325         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2326                              RTE_CACHE_LINE_SIZE);
2327         if (params == NULL) {
2328                 DP_ERR(edev, "failed to allocate memory\n");
2329                 return -ENOMEM;
2330         }
2331
2332         for (i = 0; i < reta_size; i++) {
2333                 idx = i / RTE_RETA_GROUP_SIZE;
2334                 shift = i % RTE_RETA_GROUP_SIZE;
2335                 if (reta_conf[idx].mask & (1ULL << shift)) {
2336                         entry = reta_conf[idx].reta[shift];
2337                         /* Pass rxq handles to ecore */
2338                         params->rss_ind_table[i] =
2339                                         qdev->fp_array[entry].rxq->handle;
2340                         /* Update the local copy for RETA query command */
2341                         qdev->rss_ind_table[i] = entry;
2342                 }
2343         }
2344
2345         params->update_rss_ind_table = 1;
2346         params->rss_table_size_log = 7;
2347         params->update_rss_config = 1;
2348
2349         /* Fix up RETA for CMT mode device */
2350         if (ECORE_IS_CMT(edev))
2351                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2352                                                             params);
2353         vport_update_params.vport_id = 0;
2354         /* Use the current value of rss_enable */
2355         params->rss_enable = qdev->rss_enable;
2356         vport_update_params.rss_params = params;
2357
2358         for_each_hwfn(edev, i) {
2359                 p_hwfn = &edev->hwfns[i];
2360                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2361                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2362                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2363                 if (rc) {
2364                         DP_ERR(edev, "vport-update for RSS failed\n");
2365                         goto out;
2366                 }
2367         }
2368
2369 out:
2370         rte_free(params);
2371         return rc;
2372 }
2373
2374 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2375                                struct rte_eth_rss_reta_entry64 *reta_conf,
2376                                uint16_t reta_size)
2377 {
2378         struct qede_dev *qdev = eth_dev->data->dev_private;
2379         struct ecore_dev *edev = &qdev->edev;
2380         uint16_t i, idx, shift;
2381         uint8_t entry;
2382
2383         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2384                 DP_ERR(edev, "reta_size %d is not supported\n",
2385                        reta_size);
2386                 return -EINVAL;
2387         }
2388
2389         for (i = 0; i < reta_size; i++) {
2390                 idx = i / RTE_RETA_GROUP_SIZE;
2391                 shift = i % RTE_RETA_GROUP_SIZE;
2392                 if (reta_conf[idx].mask & (1ULL << shift)) {
2393                         entry = qdev->rss_ind_table[i];
2394                         reta_conf[idx].reta[shift] = entry;
2395                 }
2396         }
2397
2398         return 0;
2399 }
2400
2401
2402
2403 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2404 {
2405         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2406         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2407         struct rte_eth_dev_info dev_info = {0};
2408         struct qede_fastpath *fp;
2409         uint32_t max_rx_pkt_len;
2410         uint32_t frame_size;
2411         uint16_t rx_buf_size;
2412         uint16_t bufsz;
2413         bool restart = false;
2414         int i;
2415
2416         PMD_INIT_FUNC_TRACE(edev);
2417         qede_dev_info_get(dev, &dev_info);
2418         max_rx_pkt_len = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
2419         frame_size = max_rx_pkt_len + QEDE_ETH_OVERHEAD;
2420         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2421                 DP_ERR(edev, "MTU %u out of range, %u is maximum allowable\n",
2422                        mtu, dev_info.max_rx_pktlen - ETHER_HDR_LEN -
2423                         ETHER_CRC_LEN - QEDE_ETH_OVERHEAD);
2424                 return -EINVAL;
2425         }
2426         if (!dev->data->scattered_rx &&
2427             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2428                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2429                         dev->data->min_rx_buf_size);
2430                 return -EINVAL;
2431         }
2432         /* Temporarily replace I/O functions with dummy ones. It cannot
2433          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2434          */
2435         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2436         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2437         if (dev->data->dev_started) {
2438                 dev->data->dev_started = 0;
2439                 qede_dev_stop(dev);
2440                 restart = true;
2441         }
2442         rte_delay_ms(1000);
2443         qede_start_vport(qdev, mtu); /* Recreate vport */
2444         qdev->mtu = mtu;
2445
2446         /* Fix up RX buf size for all queues of the port */
2447         for_each_rss(i) {
2448                 fp = &qdev->fp_array[i];
2449                 if (fp->rxq != NULL) {
2450                         bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2451                                 fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2452                         if (dev->data->scattered_rx)
2453                                 rx_buf_size = bufsz + ETHER_HDR_LEN +
2454                                               ETHER_CRC_LEN + QEDE_ETH_OVERHEAD;
2455                         else
2456                                 rx_buf_size = frame_size;
2457                         rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2458                         fp->rxq->rx_buf_size = rx_buf_size;
2459                         DP_INFO(edev, "RX buffer size %u\n", rx_buf_size);
2460                 }
2461         }
2462         if (max_rx_pkt_len > ETHER_MAX_LEN)
2463                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2464         else
2465                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2466
2467         /* Restore config lost due to vport stop */
2468         qede_mac_addr_set(dev, &qdev->primary_mac);
2469         if (dev->data->promiscuous)
2470                 qede_promiscuous_enable(dev);
2471         else
2472                 qede_promiscuous_disable(dev);
2473
2474         if (dev->data->all_multicast)
2475                 qede_allmulticast_enable(dev);
2476         else
2477                 qede_allmulticast_disable(dev);
2478
2479         qede_vlan_offload_set(dev, qdev->vlan_offload_mask);
2480
2481         if (!dev->data->dev_started && restart) {
2482                 qede_dev_start(dev);
2483                 dev->data->dev_started = 1;
2484         }
2485
2486         /* update max frame size */
2487         dev->data->dev_conf.rxmode.max_rx_pkt_len = max_rx_pkt_len;
2488         /* Reassign back */
2489         dev->rx_pkt_burst = qede_recv_pkts;
2490         dev->tx_pkt_burst = qede_xmit_pkts;
2491
2492         return 0;
2493 }
2494
2495 static int
2496 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2497                       struct rte_eth_udp_tunnel *tunnel_udp)
2498 {
2499         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2500         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2501         struct ecore_tunnel_info tunn; /* @DPDK */
2502         uint16_t udp_port;
2503         int rc;
2504
2505         PMD_INIT_FUNC_TRACE(edev);
2506
2507         memset(&tunn, 0, sizeof(tunn));
2508
2509         switch (tunnel_udp->prot_type) {
2510         case RTE_TUNNEL_TYPE_VXLAN:
2511                 if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2512                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2513                                 tunnel_udp->udp_port);
2514                         return ECORE_INVAL;
2515                 }
2516                 udp_port = 0;
2517
2518                 tunn.vxlan_port.b_update_port = true;
2519                 tunn.vxlan_port.port = udp_port;
2520
2521                 rc = qede_tunnel_update(qdev, &tunn);
2522                 if (rc != ECORE_SUCCESS) {
2523                         DP_ERR(edev, "Unable to config UDP port %u\n",
2524                                tunn.vxlan_port.port);
2525                         return rc;
2526                 }
2527
2528                 qdev->vxlan.udp_port = udp_port;
2529                 /* If the request is to delete UDP port and if the number of
2530                  * VXLAN filters have reached 0 then VxLAN offload can be be
2531                  * disabled.
2532                  */
2533                 if (qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2534                         return qede_vxlan_enable(eth_dev,
2535                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2536
2537                 break;
2538         case RTE_TUNNEL_TYPE_GENEVE:
2539                 if (qdev->geneve.udp_port != tunnel_udp->udp_port) {
2540                         DP_ERR(edev, "UDP port %u doesn't exist\n",
2541                                 tunnel_udp->udp_port);
2542                         return ECORE_INVAL;
2543                 }
2544
2545                 udp_port = 0;
2546
2547                 tunn.geneve_port.b_update_port = true;
2548                 tunn.geneve_port.port = udp_port;
2549
2550                 rc = qede_tunnel_update(qdev, &tunn);
2551                 if (rc != ECORE_SUCCESS) {
2552                         DP_ERR(edev, "Unable to config UDP port %u\n",
2553                                tunn.vxlan_port.port);
2554                         return rc;
2555                 }
2556
2557                 qdev->vxlan.udp_port = udp_port;
2558                 /* If the request is to delete UDP port and if the number of
2559                  * GENEVE filters have reached 0 then GENEVE offload can be be
2560                  * disabled.
2561                  */
2562                 if (qdev->geneve.enable && qdev->geneve.num_filters == 0)
2563                         return qede_geneve_enable(eth_dev,
2564                                         ECORE_TUNN_CLSS_MAC_VLAN, false);
2565
2566                 break;
2567
2568         default:
2569                 return ECORE_INVAL;
2570         }
2571
2572         return 0;
2573
2574 }
2575 static int
2576 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2577                       struct rte_eth_udp_tunnel *tunnel_udp)
2578 {
2579         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2580         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2581         struct ecore_tunnel_info tunn; /* @DPDK */
2582         uint16_t udp_port;
2583         int rc;
2584
2585         PMD_INIT_FUNC_TRACE(edev);
2586
2587         memset(&tunn, 0, sizeof(tunn));
2588
2589         switch (tunnel_udp->prot_type) {
2590         case RTE_TUNNEL_TYPE_VXLAN:
2591                 if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2592                         DP_INFO(edev,
2593                                 "UDP port %u for VXLAN was already configured\n",
2594                                 tunnel_udp->udp_port);
2595                         return ECORE_SUCCESS;
2596                 }
2597
2598                 /* Enable VxLAN tunnel with default MAC/VLAN classification if
2599                  * it was not enabled while adding VXLAN filter before UDP port
2600                  * update.
2601                  */
2602                 if (!qdev->vxlan.enable) {
2603                         rc = qede_vxlan_enable(eth_dev,
2604                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2605                         if (rc != ECORE_SUCCESS) {
2606                                 DP_ERR(edev, "Failed to enable VXLAN "
2607                                         "prior to updating UDP port\n");
2608                                 return rc;
2609                         }
2610                 }
2611                 udp_port = tunnel_udp->udp_port;
2612
2613                 tunn.vxlan_port.b_update_port = true;
2614                 tunn.vxlan_port.port = udp_port;
2615
2616                 rc = qede_tunnel_update(qdev, &tunn);
2617                 if (rc != ECORE_SUCCESS) {
2618                         DP_ERR(edev, "Unable to config UDP port %u for VXLAN\n",
2619                                udp_port);
2620                         return rc;
2621                 }
2622
2623                 DP_INFO(edev, "Updated UDP port %u for VXLAN\n", udp_port);
2624
2625                 qdev->vxlan.udp_port = udp_port;
2626                 break;
2627         case RTE_TUNNEL_TYPE_GENEVE:
2628                 if (qdev->geneve.udp_port == tunnel_udp->udp_port) {
2629                         DP_INFO(edev,
2630                                 "UDP port %u for GENEVE was already configured\n",
2631                                 tunnel_udp->udp_port);
2632                         return ECORE_SUCCESS;
2633                 }
2634
2635                 /* Enable GENEVE tunnel with default MAC/VLAN classification if
2636                  * it was not enabled while adding GENEVE filter before UDP port
2637                  * update.
2638                  */
2639                 if (!qdev->geneve.enable) {
2640                         rc = qede_geneve_enable(eth_dev,
2641                                 ECORE_TUNN_CLSS_MAC_VLAN, true);
2642                         if (rc != ECORE_SUCCESS) {
2643                                 DP_ERR(edev, "Failed to enable GENEVE "
2644                                         "prior to updating UDP port\n");
2645                                 return rc;
2646                         }
2647                 }
2648                 udp_port = tunnel_udp->udp_port;
2649
2650                 tunn.geneve_port.b_update_port = true;
2651                 tunn.geneve_port.port = udp_port;
2652
2653                 rc = qede_tunnel_update(qdev, &tunn);
2654                 if (rc != ECORE_SUCCESS) {
2655                         DP_ERR(edev, "Unable to config UDP port %u for GENEVE\n",
2656                                udp_port);
2657                         return rc;
2658                 }
2659
2660                 DP_INFO(edev, "Updated UDP port %u for GENEVE\n", udp_port);
2661
2662                 qdev->geneve.udp_port = udp_port;
2663                 break;
2664         default:
2665                 return ECORE_INVAL;
2666         }
2667
2668         return 0;
2669 }
2670
2671 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2672                                        uint32_t *clss, char *str)
2673 {
2674         uint16_t j;
2675         *clss = MAX_ECORE_TUNN_CLSS;
2676
2677         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2678                 if (filter == qede_tunn_types[j].rte_filter_type) {
2679                         *type = qede_tunn_types[j].qede_type;
2680                         *clss = qede_tunn_types[j].qede_tunn_clss;
2681                         strcpy(str, qede_tunn_types[j].string);
2682                         return;
2683                 }
2684         }
2685 }
2686
2687 static int
2688 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2689                               const struct rte_eth_tunnel_filter_conf *conf,
2690                               uint32_t type)
2691 {
2692         /* Init commmon ucast params first */
2693         qede_set_ucast_cmn_params(ucast);
2694
2695         /* Copy out the required fields based on classification type */
2696         ucast->type = type;
2697
2698         switch (type) {
2699         case ECORE_FILTER_VNI:
2700                 ucast->vni = conf->tenant_id;
2701         break;
2702         case ECORE_FILTER_INNER_VLAN:
2703                 ucast->vlan = conf->inner_vlan;
2704         break;
2705         case ECORE_FILTER_MAC:
2706                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2707                        ETHER_ADDR_LEN);
2708         break;
2709         case ECORE_FILTER_INNER_MAC:
2710                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2711                        ETHER_ADDR_LEN);
2712         break;
2713         case ECORE_FILTER_MAC_VNI_PAIR:
2714                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2715                         ETHER_ADDR_LEN);
2716                 ucast->vni = conf->tenant_id;
2717         break;
2718         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2719                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2720                         ETHER_ADDR_LEN);
2721                 ucast->vni = conf->tenant_id;
2722         break;
2723         case ECORE_FILTER_INNER_PAIR:
2724                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2725                         ETHER_ADDR_LEN);
2726                 ucast->vlan = conf->inner_vlan;
2727         break;
2728         default:
2729                 return -EINVAL;
2730         }
2731
2732         return ECORE_SUCCESS;
2733 }
2734
2735 static int
2736 _qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2737                          const struct rte_eth_tunnel_filter_conf *conf,
2738                          __attribute__((unused)) enum rte_filter_op filter_op,
2739                          enum ecore_tunn_clss *clss,
2740                          bool add)
2741 {
2742         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2743         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2744         struct ecore_filter_ucast ucast = {0};
2745         enum ecore_filter_ucast_type type;
2746         uint16_t filter_type = 0;
2747         char str[80];
2748         int rc;
2749
2750         filter_type = conf->filter_type;
2751         /* Determine if the given filter classification is supported */
2752         qede_get_ecore_tunn_params(filter_type, &type, clss, str);
2753         if (*clss == MAX_ECORE_TUNN_CLSS) {
2754                 DP_ERR(edev, "Unsupported filter type\n");
2755                 return -EINVAL;
2756         }
2757         /* Init tunnel ucast params */
2758         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2759         if (rc != ECORE_SUCCESS) {
2760                 DP_ERR(edev, "Unsupported Tunnel filter type 0x%x\n",
2761                 conf->filter_type);
2762                 return rc;
2763         }
2764         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2765                 str, filter_op, ucast.type);
2766
2767         ucast.opcode = add ? ECORE_FILTER_ADD : ECORE_FILTER_REMOVE;
2768
2769         /* Skip MAC/VLAN if filter is based on VNI */
2770         if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2771                 rc = qede_mac_int_ops(eth_dev, &ucast, add);
2772                 if ((rc == 0) && add) {
2773                         /* Enable accept anyvlan */
2774                         qede_config_accept_any_vlan(qdev, true);
2775                 }
2776         } else {
2777                 rc = qede_ucast_filter(eth_dev, &ucast, add);
2778                 if (rc == 0)
2779                         rc = ecore_filter_ucast_cmd(edev, &ucast,
2780                                             ECORE_SPQ_MODE_CB, NULL);
2781         }
2782
2783         return rc;
2784 }
2785
2786 static int
2787 qede_tunn_filter_config(struct rte_eth_dev *eth_dev,
2788                         enum rte_filter_op filter_op,
2789                         const struct rte_eth_tunnel_filter_conf *conf)
2790 {
2791         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2792         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2793         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2794         bool add;
2795         int rc;
2796
2797         PMD_INIT_FUNC_TRACE(edev);
2798
2799         switch (filter_op) {
2800         case RTE_ETH_FILTER_ADD:
2801                 add = true;
2802                 break;
2803         case RTE_ETH_FILTER_DELETE:
2804                 add = false;
2805                 break;
2806         default:
2807                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2808                 return -EINVAL;
2809         }
2810
2811         if (IS_VF(edev))
2812                 return qede_tunn_enable(eth_dev,
2813                                         ECORE_TUNN_CLSS_MAC_VLAN,
2814                                         conf->tunnel_type, add);
2815
2816         rc = _qede_tunn_filter_config(eth_dev, conf, filter_op, &clss, add);
2817         if (rc != ECORE_SUCCESS)
2818                 return rc;
2819
2820         if (add) {
2821                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN) {
2822                         qdev->vxlan.num_filters++;
2823                         qdev->vxlan.filter_type = conf->filter_type;
2824                 } else { /* GENEVE */
2825                         qdev->geneve.num_filters++;
2826                         qdev->geneve.filter_type = conf->filter_type;
2827                 }
2828
2829                 if (!qdev->vxlan.enable || !qdev->geneve.enable ||
2830                     !qdev->ipgre.enable)
2831                         return qede_tunn_enable(eth_dev, clss,
2832                                                 conf->tunnel_type,
2833                                                 true);
2834         } else {
2835                 if (conf->tunnel_type == RTE_TUNNEL_TYPE_VXLAN)
2836                         qdev->vxlan.num_filters--;
2837                 else /*GENEVE*/
2838                         qdev->geneve.num_filters--;
2839
2840                 /* Disable VXLAN if VXLAN filters become 0 */
2841                 if ((qdev->vxlan.num_filters == 0) ||
2842                     (qdev->geneve.num_filters == 0))
2843                         return qede_tunn_enable(eth_dev, clss,
2844                                                 conf->tunnel_type,
2845                                                 false);
2846         }
2847
2848         return 0;
2849 }
2850
2851 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2852                          enum rte_filter_type filter_type,
2853                          enum rte_filter_op filter_op,
2854                          void *arg)
2855 {
2856         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2857         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2858         struct rte_eth_tunnel_filter_conf *filter_conf =
2859                         (struct rte_eth_tunnel_filter_conf *)arg;
2860
2861         switch (filter_type) {
2862         case RTE_ETH_FILTER_TUNNEL:
2863                 switch (filter_conf->tunnel_type) {
2864                 case RTE_TUNNEL_TYPE_VXLAN:
2865                 case RTE_TUNNEL_TYPE_GENEVE:
2866                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2867                         DP_INFO(edev,
2868                                 "Packet steering to the specified Rx queue"
2869                                 " is not supported with UDP tunneling");
2870                         return(qede_tunn_filter_config(eth_dev, filter_op,
2871                                                       filter_conf));
2872                 case RTE_TUNNEL_TYPE_TEREDO:
2873                 case RTE_TUNNEL_TYPE_NVGRE:
2874                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2875                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2876                                 filter_conf->tunnel_type);
2877                         return -EINVAL;
2878                 case RTE_TUNNEL_TYPE_NONE:
2879                 default:
2880                         return 0;
2881                 }
2882                 break;
2883         case RTE_ETH_FILTER_FDIR:
2884                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2885         case RTE_ETH_FILTER_NTUPLE:
2886                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2887         case RTE_ETH_FILTER_MACVLAN:
2888         case RTE_ETH_FILTER_ETHERTYPE:
2889         case RTE_ETH_FILTER_FLEXIBLE:
2890         case RTE_ETH_FILTER_SYN:
2891         case RTE_ETH_FILTER_HASH:
2892         case RTE_ETH_FILTER_L2_TUNNEL:
2893         case RTE_ETH_FILTER_MAX:
2894         default:
2895                 DP_ERR(edev, "Unsupported filter type %d\n",
2896                         filter_type);
2897                 return -EINVAL;
2898         }
2899
2900         return 0;
2901 }
2902
2903 static const struct eth_dev_ops qede_eth_dev_ops = {
2904         .dev_configure = qede_dev_configure,
2905         .dev_infos_get = qede_dev_info_get,
2906         .rx_queue_setup = qede_rx_queue_setup,
2907         .rx_queue_release = qede_rx_queue_release,
2908         .tx_queue_setup = qede_tx_queue_setup,
2909         .tx_queue_release = qede_tx_queue_release,
2910         .dev_start = qede_dev_start,
2911         .dev_set_link_up = qede_dev_set_link_up,
2912         .dev_set_link_down = qede_dev_set_link_down,
2913         .link_update = qede_link_update,
2914         .promiscuous_enable = qede_promiscuous_enable,
2915         .promiscuous_disable = qede_promiscuous_disable,
2916         .allmulticast_enable = qede_allmulticast_enable,
2917         .allmulticast_disable = qede_allmulticast_disable,
2918         .dev_stop = qede_dev_stop,
2919         .dev_close = qede_dev_close,
2920         .stats_get = qede_get_stats,
2921         .stats_reset = qede_reset_stats,
2922         .xstats_get = qede_get_xstats,
2923         .xstats_reset = qede_reset_xstats,
2924         .xstats_get_names = qede_get_xstats_names,
2925         .mac_addr_add = qede_mac_addr_add,
2926         .mac_addr_remove = qede_mac_addr_remove,
2927         .mac_addr_set = qede_mac_addr_set,
2928         .vlan_offload_set = qede_vlan_offload_set,
2929         .vlan_filter_set = qede_vlan_filter_set,
2930         .flow_ctrl_set = qede_flow_ctrl_set,
2931         .flow_ctrl_get = qede_flow_ctrl_get,
2932         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2933         .rss_hash_update = qede_rss_hash_update,
2934         .rss_hash_conf_get = qede_rss_hash_conf_get,
2935         .reta_update  = qede_rss_reta_update,
2936         .reta_query  = qede_rss_reta_query,
2937         .mtu_set = qede_set_mtu,
2938         .filter_ctrl = qede_dev_filter_ctrl,
2939         .udp_tunnel_port_add = qede_udp_dst_port_add,
2940         .udp_tunnel_port_del = qede_udp_dst_port_del,
2941 };
2942
2943 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2944         .dev_configure = qede_dev_configure,
2945         .dev_infos_get = qede_dev_info_get,
2946         .rx_queue_setup = qede_rx_queue_setup,
2947         .rx_queue_release = qede_rx_queue_release,
2948         .tx_queue_setup = qede_tx_queue_setup,
2949         .tx_queue_release = qede_tx_queue_release,
2950         .dev_start = qede_dev_start,
2951         .dev_set_link_up = qede_dev_set_link_up,
2952         .dev_set_link_down = qede_dev_set_link_down,
2953         .link_update = qede_link_update,
2954         .promiscuous_enable = qede_promiscuous_enable,
2955         .promiscuous_disable = qede_promiscuous_disable,
2956         .allmulticast_enable = qede_allmulticast_enable,
2957         .allmulticast_disable = qede_allmulticast_disable,
2958         .dev_stop = qede_dev_stop,
2959         .dev_close = qede_dev_close,
2960         .stats_get = qede_get_stats,
2961         .stats_reset = qede_reset_stats,
2962         .xstats_get = qede_get_xstats,
2963         .xstats_reset = qede_reset_xstats,
2964         .xstats_get_names = qede_get_xstats_names,
2965         .vlan_offload_set = qede_vlan_offload_set,
2966         .vlan_filter_set = qede_vlan_filter_set,
2967         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2968         .rss_hash_update = qede_rss_hash_update,
2969         .rss_hash_conf_get = qede_rss_hash_conf_get,
2970         .reta_update  = qede_rss_reta_update,
2971         .reta_query  = qede_rss_reta_query,
2972         .mtu_set = qede_set_mtu,
2973         .udp_tunnel_port_add = qede_udp_dst_port_add,
2974         .udp_tunnel_port_del = qede_udp_dst_port_del,
2975 };
2976
2977 static void qede_update_pf_params(struct ecore_dev *edev)
2978 {
2979         struct ecore_pf_params pf_params;
2980
2981         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2982         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2983         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2984         qed_ops->common->update_pf_params(edev, &pf_params);
2985 }
2986
2987 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2988 {
2989         struct rte_pci_device *pci_dev;
2990         struct rte_pci_addr pci_addr;
2991         struct qede_dev *adapter;
2992         struct ecore_dev *edev;
2993         struct qed_dev_eth_info dev_info;
2994         struct qed_slowpath_params params;
2995         static bool do_once = true;
2996         uint8_t bulletin_change;
2997         uint8_t vf_mac[ETHER_ADDR_LEN];
2998         uint8_t is_mac_forced;
2999         bool is_mac_exist;
3000         /* Fix up ecore debug level */
3001         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
3002         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
3003         int rc;
3004
3005         /* Extract key data structures */
3006         adapter = eth_dev->data->dev_private;
3007         adapter->ethdev = eth_dev;
3008         edev = &adapter->edev;
3009         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
3010         pci_addr = pci_dev->addr;
3011
3012         PMD_INIT_FUNC_TRACE(edev);
3013
3014         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
3015                  pci_addr.bus, pci_addr.devid, pci_addr.function,
3016                  eth_dev->data->port_id);
3017
3018         eth_dev->rx_pkt_burst = qede_recv_pkts;
3019         eth_dev->tx_pkt_burst = qede_xmit_pkts;
3020         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
3021
3022         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
3023                 DP_ERR(edev, "Skipping device init from secondary process\n");
3024                 return 0;
3025         }
3026
3027         rte_eth_copy_pci_info(eth_dev, pci_dev);
3028
3029         /* @DPDK */
3030         edev->vendor_id = pci_dev->id.vendor_id;
3031         edev->device_id = pci_dev->id.device_id;
3032
3033         qed_ops = qed_get_eth_ops();
3034         if (!qed_ops) {
3035                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
3036                 return -EINVAL;
3037         }
3038
3039         DP_INFO(edev, "Starting qede probe\n");
3040         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
3041                                     dp_level, is_vf);
3042         if (rc != 0) {
3043                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
3044                 return -ENODEV;
3045         }
3046         qede_update_pf_params(edev);
3047         rte_intr_callback_register(&pci_dev->intr_handle,
3048                                    qede_interrupt_handler, (void *)eth_dev);
3049         if (rte_intr_enable(&pci_dev->intr_handle)) {
3050                 DP_ERR(edev, "rte_intr_enable() failed\n");
3051                 return -ENODEV;
3052         }
3053
3054         /* Start the Slowpath-process */
3055         memset(&params, 0, sizeof(struct qed_slowpath_params));
3056         params.int_mode = ECORE_INT_MODE_MSIX;
3057         params.drv_major = QEDE_PMD_VERSION_MAJOR;
3058         params.drv_minor = QEDE_PMD_VERSION_MINOR;
3059         params.drv_rev = QEDE_PMD_VERSION_REVISION;
3060         params.drv_eng = QEDE_PMD_VERSION_PATCH;
3061         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
3062                 QEDE_PMD_DRV_VER_STR_SIZE);
3063
3064         /* For CMT mode device do periodic polling for slowpath events.
3065          * This is required since uio device uses only one MSI-x
3066          * interrupt vector but we need one for each engine.
3067          */
3068         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
3069                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
3070                                        qede_poll_sp_sb_cb,
3071                                        (void *)eth_dev);
3072                 if (rc != 0) {
3073                         DP_ERR(edev, "Unable to start periodic"
3074                                      " timer rc %d\n", rc);
3075                         return -EINVAL;
3076                 }
3077         }
3078
3079         rc = qed_ops->common->slowpath_start(edev, &params);
3080         if (rc) {
3081                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
3082                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3083                                      (void *)eth_dev);
3084                 return -ENODEV;
3085         }
3086
3087         rc = qed_ops->fill_dev_info(edev, &dev_info);
3088         if (rc) {
3089                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
3090                 qed_ops->common->slowpath_stop(edev);
3091                 qed_ops->common->remove(edev);
3092                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3093                                      (void *)eth_dev);
3094                 return -ENODEV;
3095         }
3096
3097         qede_alloc_etherdev(adapter, &dev_info);
3098
3099         adapter->ops->common->set_name(edev, edev->name);
3100
3101         if (!is_vf)
3102                 adapter->dev_info.num_mac_filters =
3103                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
3104                                             ECORE_MAC);
3105         else
3106                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
3107                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
3108
3109         /* Allocate memory for storing MAC addr */
3110         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
3111                                         (ETHER_ADDR_LEN *
3112                                         adapter->dev_info.num_mac_filters),
3113                                         RTE_CACHE_LINE_SIZE);
3114
3115         if (eth_dev->data->mac_addrs == NULL) {
3116                 DP_ERR(edev, "Failed to allocate MAC address\n");
3117                 qed_ops->common->slowpath_stop(edev);
3118                 qed_ops->common->remove(edev);
3119                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
3120                                      (void *)eth_dev);
3121                 return -ENOMEM;
3122         }
3123
3124         if (!is_vf) {
3125                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
3126                                 hw_info.hw_mac_addr,
3127                                 &eth_dev->data->mac_addrs[0]);
3128                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3129                                 &adapter->primary_mac);
3130         } else {
3131                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
3132                                        &bulletin_change);
3133                 if (bulletin_change) {
3134                         is_mac_exist =
3135                             ecore_vf_bulletin_get_forced_mac(
3136                                                 ECORE_LEADING_HWFN(edev),
3137                                                 vf_mac,
3138                                                 &is_mac_forced);
3139                         if (is_mac_exist && is_mac_forced) {
3140                                 DP_INFO(edev, "VF macaddr received from PF\n");
3141                                 ether_addr_copy((struct ether_addr *)&vf_mac,
3142                                                 &eth_dev->data->mac_addrs[0]);
3143                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
3144                                                 &adapter->primary_mac);
3145                         } else {
3146                                 DP_ERR(edev, "No VF macaddr assigned\n");
3147                         }
3148                 }
3149         }
3150
3151         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
3152
3153         if (do_once) {
3154                 qede_print_adapter_info(adapter);
3155                 do_once = false;
3156         }
3157
3158         /* Bring-up the link */
3159         qede_dev_set_link_state(eth_dev, true);
3160
3161         adapter->num_tx_queues = 0;
3162         adapter->num_rx_queues = 0;
3163         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
3164         SLIST_INIT(&adapter->vlan_list_head);
3165         SLIST_INIT(&adapter->uc_list_head);
3166         adapter->mtu = ETHER_MTU;
3167         adapter->vport_started = false;
3168
3169         /* VF tunnel offloads is enabled by default in PF driver */
3170         adapter->vxlan.num_filters = 0;
3171         adapter->geneve.num_filters = 0;
3172         adapter->ipgre.num_filters = 0;
3173         if (is_vf) {
3174                 adapter->vxlan.enable = true;
3175                 adapter->vxlan.filter_type = ETH_TUNNEL_FILTER_IMAC |
3176                                              ETH_TUNNEL_FILTER_IVLAN;
3177                 adapter->vxlan.udp_port = QEDE_VXLAN_DEF_PORT;
3178                 adapter->geneve.enable = true;
3179                 adapter->geneve.filter_type = ETH_TUNNEL_FILTER_IMAC |
3180                                               ETH_TUNNEL_FILTER_IVLAN;
3181                 adapter->geneve.udp_port = QEDE_GENEVE_DEF_PORT;
3182                 adapter->ipgre.enable = true;
3183                 adapter->ipgre.filter_type = ETH_TUNNEL_FILTER_IMAC |
3184                                              ETH_TUNNEL_FILTER_IVLAN;
3185         } else {
3186                 adapter->vxlan.enable = false;
3187                 adapter->geneve.enable = false;
3188                 adapter->ipgre.enable = false;
3189         }
3190
3191         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
3192                 adapter->primary_mac.addr_bytes[0],
3193                 adapter->primary_mac.addr_bytes[1],
3194                 adapter->primary_mac.addr_bytes[2],
3195                 adapter->primary_mac.addr_bytes[3],
3196                 adapter->primary_mac.addr_bytes[4],
3197                 adapter->primary_mac.addr_bytes[5]);
3198
3199         DP_INFO(edev, "Device initialized\n");
3200
3201         return 0;
3202 }
3203
3204 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
3205 {
3206         return qede_common_dev_init(eth_dev, 1);
3207 }
3208
3209 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
3210 {
3211         return qede_common_dev_init(eth_dev, 0);
3212 }
3213
3214 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
3215 {
3216 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
3217         struct qede_dev *qdev = eth_dev->data->dev_private;
3218         struct ecore_dev *edev = &qdev->edev;
3219
3220         PMD_INIT_FUNC_TRACE(edev);
3221 #endif
3222
3223         /* only uninitialize in the primary process */
3224         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
3225                 return 0;
3226
3227         /* safe to close dev here */
3228         qede_dev_close(eth_dev);
3229
3230         eth_dev->dev_ops = NULL;
3231         eth_dev->rx_pkt_burst = NULL;
3232         eth_dev->tx_pkt_burst = NULL;
3233
3234         if (eth_dev->data->mac_addrs)
3235                 rte_free(eth_dev->data->mac_addrs);
3236
3237         eth_dev->data->mac_addrs = NULL;
3238
3239         return 0;
3240 }
3241
3242 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3243 {
3244         return qede_dev_common_uninit(eth_dev);
3245 }
3246
3247 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
3248 {
3249         return qede_dev_common_uninit(eth_dev);
3250 }
3251
3252 static const struct rte_pci_id pci_id_qedevf_map[] = {
3253 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3254         {
3255                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
3256         },
3257         {
3258                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
3259         },
3260         {
3261                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
3262         },
3263         {.vendor_id = 0,}
3264 };
3265
3266 static const struct rte_pci_id pci_id_qede_map[] = {
3267 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
3268         {
3269                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
3270         },
3271         {
3272                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
3273         },
3274         {
3275                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
3276         },
3277         {
3278                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
3279         },
3280         {
3281                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
3282         },
3283         {
3284                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
3285         },
3286         {
3287                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
3288         },
3289         {
3290                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
3291         },
3292         {
3293                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
3294         },
3295         {
3296                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
3297         },
3298         {.vendor_id = 0,}
3299 };
3300
3301 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3302         struct rte_pci_device *pci_dev)
3303 {
3304         return rte_eth_dev_pci_generic_probe(pci_dev,
3305                 sizeof(struct qede_dev), qedevf_eth_dev_init);
3306 }
3307
3308 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3309 {
3310         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
3311 }
3312
3313 static struct rte_pci_driver rte_qedevf_pmd = {
3314         .id_table = pci_id_qedevf_map,
3315         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3316         .probe = qedevf_eth_dev_pci_probe,
3317         .remove = qedevf_eth_dev_pci_remove,
3318 };
3319
3320 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3321         struct rte_pci_device *pci_dev)
3322 {
3323         return rte_eth_dev_pci_generic_probe(pci_dev,
3324                 sizeof(struct qede_dev), qede_eth_dev_init);
3325 }
3326
3327 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
3328 {
3329         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
3330 }
3331
3332 static struct rte_pci_driver rte_qede_pmd = {
3333         .id_table = pci_id_qede_map,
3334         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
3335         .probe = qede_eth_dev_pci_probe,
3336         .remove = qede_eth_dev_pci_remove,
3337 };
3338
3339 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
3340 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
3341 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
3342 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
3343 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
3344 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");
3345
3346 RTE_INIT(qede_init_log);
3347 static void
3348 qede_init_log(void)
3349 {
3350         qede_logtype_init = rte_log_register("pmd.net.qede.init");
3351         if (qede_logtype_init >= 0)
3352                 rte_log_set_level(qede_logtype_init, RTE_LOG_NOTICE);
3353         qede_logtype_driver = rte_log_register("pmd.net.qede.driver");
3354         if (qede_logtype_driver >= 0)
3355                 rte_log_set_level(qede_logtype_driver, RTE_LOG_NOTICE);
3356 }