drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes", offsetof(struct ecore_eth_stats, rx_ucast_bytes)},
 129         {"rx_multicast_bytes",
 130                 offsetof(struct ecore_eth_stats, rx_mcast_bytes)},
 131         {"rx_broadcast_bytes",
 132                 offsetof(struct ecore_eth_stats, rx_bcast_bytes)},
 133         {"rx_unicast_packets", offsetof(struct ecore_eth_stats, rx_ucast_pkts)},
 134         {"rx_multicast_packets",
 135                 offsetof(struct ecore_eth_stats, rx_mcast_pkts)},
 136         {"rx_broadcast_packets",
 137                 offsetof(struct ecore_eth_stats, rx_bcast_pkts)},
 138
 139         {"tx_unicast_bytes", offsetof(struct ecore_eth_stats, tx_ucast_bytes)},
 140         {"tx_multicast_bytes",
 141                 offsetof(struct ecore_eth_stats, tx_mcast_bytes)},
 142         {"tx_broadcast_bytes",
 143                 offsetof(struct ecore_eth_stats, tx_bcast_bytes)},
 144         {"tx_unicast_packets", offsetof(struct ecore_eth_stats, tx_ucast_pkts)},
 145         {"tx_multicast_packets",
 146                 offsetof(struct ecore_eth_stats, tx_mcast_pkts)},
 147         {"tx_broadcast_packets",
 148                 offsetof(struct ecore_eth_stats, tx_bcast_pkts)},
 149
 150         {"rx_64_byte_packets",
 151                 offsetof(struct ecore_eth_stats, rx_64_byte_packets)},
 152         {"rx_65_to_127_byte_packets",
 153                 offsetof(struct ecore_eth_stats, rx_65_to_127_byte_packets)},
 154         {"rx_128_to_255_byte_packets",
 155                 offsetof(struct ecore_eth_stats, rx_128_to_255_byte_packets)},
 156         {"rx_256_to_511_byte_packets",
 157                 offsetof(struct ecore_eth_stats, rx_256_to_511_byte_packets)},
 158         {"rx_512_to_1023_byte_packets",
 159                 offsetof(struct ecore_eth_stats, rx_512_to_1023_byte_packets)},
 160         {"rx_1024_to_1518_byte_packets",
 161                 offsetof(struct ecore_eth_stats, rx_1024_to_1518_byte_packets)},
 162         {"rx_1519_to_1522_byte_packets",
 163                 offsetof(struct ecore_eth_stats, rx_1519_to_1522_byte_packets)},
 164         {"rx_1519_to_2047_byte_packets",
 165                 offsetof(struct ecore_eth_stats, rx_1519_to_2047_byte_packets)},
 166         {"rx_2048_to_4095_byte_packets",
 167                 offsetof(struct ecore_eth_stats, rx_2048_to_4095_byte_packets)},
 168         {"rx_4096_to_9216_byte_packets",
 169                 offsetof(struct ecore_eth_stats, rx_4096_to_9216_byte_packets)},
 170         {"rx_9217_to_16383_byte_packets",
 171                 offsetof(struct ecore_eth_stats,
 172                          rx_9217_to_16383_byte_packets)},
 173         {"tx_64_byte_packets",
 174                 offsetof(struct ecore_eth_stats, tx_64_byte_packets)},
 175         {"tx_65_to_127_byte_packets",
 176                 offsetof(struct ecore_eth_stats, tx_65_to_127_byte_packets)},
 177         {"tx_128_to_255_byte_packets",
 178                 offsetof(struct ecore_eth_stats, tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats, tx_256_to_511_byte_packets)},
 181         {"tx_512_to_1023_byte_packets",
 182                 offsetof(struct ecore_eth_stats, tx_512_to_1023_byte_packets)},
 183         {"tx_1024_to_1518_byte_packets",
 184                 offsetof(struct ecore_eth_stats, tx_1024_to_1518_byte_packets)},
 185         {"trx_1519_to_1522_byte_packets",
 186                 offsetof(struct ecore_eth_stats, tx_1519_to_2047_byte_packets)},
 187         {"tx_2048_to_4095_byte_packets",
 188                 offsetof(struct ecore_eth_stats, tx_2048_to_4095_byte_packets)},
 189         {"tx_4096_to_9216_byte_packets",
 190                 offsetof(struct ecore_eth_stats, tx_4096_to_9216_byte_packets)},
 191         {"tx_9217_to_16383_byte_packets",
 192                 offsetof(struct ecore_eth_stats,
 193                          tx_9217_to_16383_byte_packets)},
 194
 195         {"rx_mac_crtl_frames",
 196                 offsetof(struct ecore_eth_stats, rx_mac_crtl_frames)},
 197         {"tx_mac_control_frames",
 198                 offsetof(struct ecore_eth_stats, tx_mac_ctrl_frames)},
 199         {"rx_pause_frames", offsetof(struct ecore_eth_stats, rx_pause_frames)},
 200         {"tx_pause_frames", offsetof(struct ecore_eth_stats, tx_pause_frames)},
 201         {"rx_priority_flow_control_frames",
 202                 offsetof(struct ecore_eth_stats, rx_pfc_frames)},
 203         {"tx_priority_flow_control_frames",
 204                 offsetof(struct ecore_eth_stats, tx_pfc_frames)},
 205
 206         {"rx_crc_errors", offsetof(struct ecore_eth_stats, rx_crc_errors)},
 207         {"rx_align_errors", offsetof(struct ecore_eth_stats, rx_align_errors)},
 208         {"rx_carrier_errors",
 209                 offsetof(struct ecore_eth_stats, rx_carrier_errors)},
 210         {"rx_oversize_packet_errors",
 211                 offsetof(struct ecore_eth_stats, rx_oversize_packets)},
 212         {"rx_jabber_errors", offsetof(struct ecore_eth_stats, rx_jabbers)},
 213         {"rx_undersize_packet_errors",
 214                 offsetof(struct ecore_eth_stats, rx_undersize_packets)},
 215         {"rx_fragments", offsetof(struct ecore_eth_stats, rx_fragments)},
 216         {"rx_host_buffer_not_available",
 217                 offsetof(struct ecore_eth_stats, no_buff_discards)},
 218         /* Number of packets discarded because they are bigger than MTU */
 219         {"rx_packet_too_big_discards",
 220                 offsetof(struct ecore_eth_stats, packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats, brb_discards)},
 231         {"tx_lpi_entry_count",
 232                 offsetof(struct ecore_eth_stats, tx_lpi_entry_count)},
 233         {"tx_total_collisions",
 234                 offsetof(struct ecore_eth_stats, tx_total_collisions)},
 235         {"tx_error_drop_packets",
 236                 offsetof(struct ecore_eth_stats, tx_err_drop_pkts)},
 237
 238         {"rx_mac_bytes", offsetof(struct ecore_eth_stats, rx_mac_bytes)},
 239         {"rx_mac_unicast_packets",
 240                 offsetof(struct ecore_eth_stats, rx_mac_uc_packets)},
 241         {"rx_mac_multicast_packets",
 242                 offsetof(struct ecore_eth_stats, rx_mac_mc_packets)},
 243         {"rx_mac_broadcast_packets",
 244                 offsetof(struct ecore_eth_stats, rx_mac_bc_packets)},
 245         {"rx_mac_frames_ok",
 246                 offsetof(struct ecore_eth_stats, rx_mac_frames_ok)},
 247         {"tx_mac_bytes", offsetof(struct ecore_eth_stats, tx_mac_bytes)},
 248         {"tx_mac_unicast_packets",
 249                 offsetof(struct ecore_eth_stats, tx_mac_uc_packets)},
 250         {"tx_mac_multicast_packets",
 251                 offsetof(struct ecore_eth_stats, tx_mac_mc_packets)},
 252         {"tx_mac_broadcast_packets",
 253                 offsetof(struct ecore_eth_stats, tx_mac_bc_packets)},
 254
 255         {"lro_coalesced_packets",
 256                 offsetof(struct ecore_eth_stats, tpa_coalesced_pkts)},
 257         {"lro_coalesced_events",
 258                 offsetof(struct ecore_eth_stats, tpa_coalesced_events)},
 259         {"lro_aborts_num",
 260                 offsetof(struct ecore_eth_stats, tpa_aborts_num)},
 261         {"lro_not_coalesced_packets",
 262                 offsetof(struct ecore_eth_stats, tpa_not_coalesced_pkts)},
 263         {"lro_coalesced_bytes",
 264                 offsetof(struct ecore_eth_stats, tpa_coalesced_bytes)},
 265 };
 266
 267 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 268         {"rx_q_segments",
 269                 offsetof(struct qede_rx_queue, rx_segs)},
 270         {"rx_q_hw_errors",
 271                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 272         {"rx_q_allocation_errors",
 273                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 274 };
 275
 276 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 277 {
 278         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 279 }
 280
 281 static void
 282 qede_interrupt_handler(void *param)
 283 {
 284         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 285         struct qede_dev *qdev = eth_dev->data->dev_private;
 286         struct ecore_dev *edev = &qdev->edev;
 287
 288         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 289         if (rte_intr_enable(eth_dev->intr_handle))
 290                 DP_ERR(edev, "rte_intr_enable failed\n");
 291 }
 292
 293 static void
 294 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 295 {
 296         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 297         qdev->ops = qed_ops;
 298 }
 299
 300 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 301 static void qede_print_adapter_info(struct qede_dev *qdev)
 302 {
 303         struct ecore_dev *edev = &qdev->edev;
 304         struct qed_dev_info *info = &qdev->dev_info.common;
 305         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 306         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 307
 308         DP_INFO(edev, "*********************************\n");
 309         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 310         DP_INFO(edev, " Chip details : %s%d\n",
 311                   ECORE_IS_BB(edev) ? "BB" : "AH",
 312                   CHIP_REV_IS_A0(edev) ? 0 : 1);
 313         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 314                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 315         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 316                  ver_str, QEDE_PMD_VERSION);
 317         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 318         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 319
 320         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 321                  "%d.%d.%d.%d",
 322                 (info->mfw_rev >> 24) & 0xff,
 323                 (info->mfw_rev >> 16) & 0xff,
 324                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 325         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 326         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 327         DP_INFO(edev, "*********************************\n");
 328 }
 329 #endif
 330
 331 static int
 332 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 333 {
 334         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 335         struct ecore_sp_vport_start_params params;
 336         struct ecore_hwfn *p_hwfn;
 337         int rc;
 338         int i;
 339
 340         memset(&params, 0, sizeof(params));
 341         params.vport_id = 0;
 342         params.mtu = mtu;
 343         /* @DPDK - Disable FW placement */
 344         params.zero_placement_offset = 1;
 345         for_each_hwfn(edev, i) {
 346                 p_hwfn = &edev->hwfns[i];
 347                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 348                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 349                 rc = ecore_sp_vport_start(p_hwfn, &params);
 350                 if (rc != ECORE_SUCCESS) {
 351                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 352                         return rc;
 353                 }
 354         }
 355         ecore_reset_vport_stats(edev);
 356         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 357
 358         return 0;
 359 }
 360
 361 static int
 362 qede_stop_vport(struct ecore_dev *edev)
 363 {
 364         struct ecore_hwfn *p_hwfn;
 365         uint8_t vport_id;
 366         int rc;
 367         int i;
 368
 369         vport_id = 0;
 370         for_each_hwfn(edev, i) {
 371                 p_hwfn = &edev->hwfns[i];
 372                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 373                                          vport_id);
 374                 if (rc != ECORE_SUCCESS) {
 375                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 376                         return rc;
 377                 }
 378         }
 379
 380         return 0;
 381 }
 382
 383 /* Activate or deactivate vport via vport-update */
 384 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 385 {
 386         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 387         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 388         struct ecore_sp_vport_update_params params;
 389         struct ecore_hwfn *p_hwfn;
 390         uint8_t i;
 391         int rc = -1;
 392
 393         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 394         params.vport_id = 0;
 395         params.update_vport_active_rx_flg = 1;
 396         params.update_vport_active_tx_flg = 1;
 397         params.vport_active_rx_flg = flg;
 398         params.vport_active_tx_flg = flg;
 399         for_each_hwfn(edev, i) {
 400                 p_hwfn = &edev->hwfns[i];
 401                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 402                 rc = ecore_sp_vport_update(p_hwfn, &params,
 403                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 404                 if (rc != ECORE_SUCCESS) {
 405                         DP_ERR(edev, "Failed to update vport\n");
 406                         break;
 407                 }
 408         }
 409         DP_INFO(edev, "vport %s\n", flg ? "activated" : "deactivated");
 410         return rc;
 411 }
 412
 413 static void
 414 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 415                            uint16_t mtu, bool enable)
 416 {
 417         /* Enable LRO in split mode */
 418         sge_tpa_params->tpa_ipv4_en_flg = enable;
 419         sge_tpa_params->tpa_ipv6_en_flg = enable;
 420         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 421         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 422         /* set if tpa enable changes */
 423         sge_tpa_params->update_tpa_en_flg = 1;
 424         /* set if tpa parameters should be handled */
 425         sge_tpa_params->update_tpa_param_flg = enable;
 426
 427         sge_tpa_params->max_buffers_per_cqe = 20;
 428         /* Enable TPA in split mode. In this mode each TPA segment
 429          * starts on the new BD, so there is one BD per segment.
 430          */
 431         sge_tpa_params->tpa_pkt_split_flg = 1;
 432         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 433         sge_tpa_params->tpa_gro_consistent_flg = 0;
 434         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 435         sge_tpa_params->tpa_max_size = 0x7FFF;
 436         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 437         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 438 }
 439
 440 /* Enable/disable LRO via vport-update */
 441 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_sge_tpa_params tpa_params;
 447         struct ecore_hwfn *p_hwfn;
 448         int rc;
 449         int i;
 450
 451         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 452         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 453         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 454         params.vport_id = 0;
 455         params.sge_tpa_params = &tpa_params;
 456         for_each_hwfn(edev, i) {
 457                 p_hwfn = &edev->hwfns[i];
 458                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 459                 rc = ecore_sp_vport_update(p_hwfn, &params,
 460                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 461                 if (rc != ECORE_SUCCESS) {
 462                         DP_ERR(edev, "Failed to update LRO\n");
 463                         return -1;
 464                 }
 465         }
 466
 467         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 468
 469         return 0;
 470 }
 471
 472 /* Update MTU via vport-update without doing port restart.
 473  * The vport must be deactivated before calling this API.
 474  */
 475 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 476 {
 477         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 478         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 479         struct ecore_sp_vport_update_params params;
 480         struct ecore_hwfn *p_hwfn;
 481         int rc;
 482         int i;
 483
 484         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 485         params.vport_id = 0;
 486         params.mtu = mtu;
 487         params.vport_id = 0;
 488         for_each_hwfn(edev, i) {
 489                 p_hwfn = &edev->hwfns[i];
 490                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 491                 rc = ecore_sp_vport_update(p_hwfn, &params,
 492                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 493                 if (rc != ECORE_SUCCESS) {
 494                         DP_ERR(edev, "Failed to update MTU\n");
 495                         return -1;
 496                 }
 497         }
 498         DP_INFO(edev, "MTU updated to %u\n", mtu);
 499
 500         return 0;
 501 }
 502
 503 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 504 {
 505         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 506         ucast->is_rx_filter = true;
 507         ucast->is_tx_filter = true;
 508         /* ucast->assert_on_error = true; - For debug */
 509 }
 510
 511 static int
 512 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 513                              enum qed_filter_rx_mode_type type)
 514 {
 515         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 516         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 517         struct ecore_filter_accept_flags flags;
 518
 519         memset(&flags, 0, sizeof(flags));
 520
 521         flags.update_rx_mode_config = 1;
 522         flags.update_tx_mode_config = 1;
 523         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 524                 ECORE_ACCEPT_MCAST_MATCHED |
 525                 ECORE_ACCEPT_BCAST;
 526
 527         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 528                 ECORE_ACCEPT_MCAST_MATCHED |
 529                 ECORE_ACCEPT_BCAST;
 530
 531         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 532                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 533                 if (IS_VF(edev)) {
 534                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 535                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 536                 }
 537         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 538                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 539         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 540                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 541                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 542                         ECORE_ACCEPT_MCAST_UNMATCHED;
 543         }
 544
 545         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 546                         ECORE_SPQ_MODE_CB, NULL);
 547 }
 548 static void qede_set_cmn_tunn_param(struct ecore_tunnel_info *p_tunn,
 549                                     uint8_t clss, bool mode, bool mask)
 550 {
 551         memset(p_tunn, 0, sizeof(struct ecore_tunnel_info));
 552         p_tunn->vxlan.b_update_mode = mode;
 553         p_tunn->vxlan.b_mode_enabled = mask;
 554         p_tunn->b_update_rx_cls = true;
 555         p_tunn->b_update_tx_cls = true;
 556         p_tunn->vxlan.tun_cls = clss;
 557 }
 558
 559 static int
 560 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 561                   bool add)
 562 {
 563         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 564         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 565         struct qede_ucast_entry *tmp = NULL;
 566         struct qede_ucast_entry *u;
 567         struct ether_addr *mac_addr;
 568
 569         mac_addr  = (struct ether_addr *)ucast->mac;
 570         if (add) {
 571                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 572                         if ((memcmp(mac_addr, &tmp->mac,
 573                                     ETHER_ADDR_LEN) == 0) &&
 574                              ucast->vlan == tmp->vlan) {
 575                                 DP_ERR(edev, "Unicast MAC is already added"
 576                                        " with vlan = %u, vni = %u\n",
 577                                        ucast->vlan,  ucast->vni);
 578                                         return -EEXIST;
 579                         }
 580                 }
 581                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 582                                RTE_CACHE_LINE_SIZE);
 583                 if (!u) {
 584                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 585                         return -ENOMEM;
 586                 }
 587                 ether_addr_copy(mac_addr, &u->mac);
 588                 u->vlan = ucast->vlan;
 589                 u->vni = ucast->vni;
 590                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 591                 qdev->num_uc_addr++;
 592         } else {
 593                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 594                         if ((memcmp(mac_addr, &tmp->mac,
 595                                     ETHER_ADDR_LEN) == 0) &&
 596                             ucast->vlan == tmp->vlan      &&
 597                             ucast->vni == tmp->vni)
 598                         break;
 599                 }
 600                 if (tmp == NULL) {
 601                         DP_INFO(edev, "Unicast MAC is not found\n");
 602                         return -EINVAL;
 603                 }
 604                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 605                 qdev->num_uc_addr--;
 606         }
 607
 608         return 0;
 609 }
 610
 611 static int
 612 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 613                   bool add)
 614 {
 615         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 616         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 617         struct ether_addr *mac_addr;
 618         struct qede_mcast_entry *tmp = NULL;
 619         struct qede_mcast_entry *m;
 620
 621         mac_addr  = (struct ether_addr *)mcast->mac;
 622         if (add) {
 623                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 624                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 625                                 DP_ERR(edev,
 626                                         "Multicast MAC is already added\n");
 627                                 return -EEXIST;
 628                         }
 629                 }
 630                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 631                         RTE_CACHE_LINE_SIZE);
 632                 if (!m) {
 633                         DP_ERR(edev,
 634                                 "Did not allocate memory for mcast\n");
 635                         return -ENOMEM;
 636                 }
 637                 ether_addr_copy(mac_addr, &m->mac);
 638                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 639                 qdev->num_mc_addr++;
 640         } else {
 641                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 642                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 643                                 break;
 644                 }
 645                 if (tmp == NULL) {
 646                         DP_INFO(edev, "Multicast mac is not found\n");
 647                         return -EINVAL;
 648                 }
 649                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 650                              qede_mcast_entry, list);
 651                 qdev->num_mc_addr--;
 652         }
 653
 654         return 0;
 655 }
 656
 657 static enum _ecore_status_t
 658 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 659                  bool add)
 660 {
 661         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 662         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 663         enum _ecore_status_t rc;
 664         struct ecore_filter_mcast mcast;
 665         struct qede_mcast_entry *tmp;
 666         uint16_t j = 0;
 667
 668         /* Multicast */
 669         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 670                 if (add) {
 671                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 672                                 DP_ERR(edev,
 673                                        "Mcast filter table limit exceeded, "
 674                                        "Please enable mcast promisc mode\n");
 675                                 return -ECORE_INVAL;
 676                         }
 677                 }
 678                 rc = qede_mcast_filter(eth_dev, ucast, add);
 679                 if (rc == 0) {
 680                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 681                         memset(&mcast, 0, sizeof(mcast));
 682                         mcast.num_mc_addrs = qdev->num_mc_addr;
 683                         mcast.opcode = ECORE_FILTER_ADD;
 684                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 685                                 ether_addr_copy(&tmp->mac,
 686                                         (struct ether_addr *)&mcast.mac[j]);
 687                                 j++;
 688                         }
 689                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 690                                                     ECORE_SPQ_MODE_CB, NULL);
 691                 }
 692                 if (rc != ECORE_SUCCESS) {
 693                         DP_ERR(edev, "Failed to add multicast filter"
 694                                " rc = %d, op = %d\n", rc, add);
 695                 }
 696         } else { /* Unicast */
 697                 if (add) {
 698                         if (qdev->num_uc_addr >=
 699                             qdev->dev_info.num_mac_filters) {
 700                                 DP_ERR(edev,
 701                                        "Ucast filter table limit exceeded,"
 702                                        " Please enable promisc mode\n");
 703                                 return -ECORE_INVAL;
 704                         }
 705                 }
 706                 rc = qede_ucast_filter(eth_dev, ucast, add);
 707                 if (rc == 0)
 708                         rc = ecore_filter_ucast_cmd(edev, ucast,
 709                                                     ECORE_SPQ_MODE_CB, NULL);
 710                 if (rc != ECORE_SUCCESS) {
 711                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 712                                rc, add);
 713                 }
 714         }
 715
 716         return rc;
 717 }
 718
 719 static int
 720 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 721                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 722 {
 723         struct ecore_filter_ucast ucast;
 724         int re;
 725
 726         qede_set_ucast_cmn_params(&ucast);
 727         ucast.type = ECORE_FILTER_MAC;
 728         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 729         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 730         return re;
 731 }
 732
 733 static void
 734 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 735 {
 736         struct qede_dev *qdev = eth_dev->data->dev_private;
 737         struct ecore_dev *edev = &qdev->edev;
 738         struct ecore_filter_ucast ucast;
 739
 740         PMD_INIT_FUNC_TRACE(edev);
 741
 742         if (index >= qdev->dev_info.num_mac_filters) {
 743                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 744                        index, qdev->dev_info.num_mac_filters);
 745                 return;
 746         }
 747
 748         qede_set_ucast_cmn_params(&ucast);
 749         ucast.opcode = ECORE_FILTER_REMOVE;
 750         ucast.type = ECORE_FILTER_MAC;
 751
 752         /* Use the index maintained by rte */
 753         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 754                         (struct ether_addr *)&ucast.mac);
 755
 756         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 757 }
 758
 759 static void
 760 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 761 {
 762         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 763         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 764
 765         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 766                                                mac_addr->addr_bytes)) {
 767                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 768                 ether_addr_copy(&qdev->primary_mac,
 769                                 &eth_dev->data->mac_addrs[0]);
 770                 return;
 771         }
 772
 773         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 774 }
 775
 776 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 777 {
 778         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 779         struct ecore_sp_vport_update_params params;
 780         struct ecore_hwfn *p_hwfn;
 781         uint8_t i;
 782         int rc;
 783
 784         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 785         params.vport_id = 0;
 786         params.update_accept_any_vlan_flg = 1;
 787         params.accept_any_vlan = flg;
 788         for_each_hwfn(edev, i) {
 789                 p_hwfn = &edev->hwfns[i];
 790                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 791                 rc = ecore_sp_vport_update(p_hwfn, &params,
 792                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 793                 if (rc != ECORE_SUCCESS) {
 794                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 795                         return;
 796                 }
 797         }
 798
 799         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 800 }
 801
 802 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 803 {
 804         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 805         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 806         struct ecore_sp_vport_update_params params;
 807         struct ecore_hwfn *p_hwfn;
 808         uint8_t i;
 809         int rc;
 810
 811         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 812         params.vport_id = 0;
 813         params.update_inner_vlan_removal_flg = 1;
 814         params.inner_vlan_removal_flg = flg;
 815         for_each_hwfn(edev, i) {
 816                 p_hwfn = &edev->hwfns[i];
 817                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 818                 rc = ecore_sp_vport_update(p_hwfn, &params,
 819                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 820                 if (rc != ECORE_SUCCESS) {
 821                         DP_ERR(edev, "Failed to update vport\n");
 822                         return -1;
 823                 }
 824         }
 825
 826         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 827         return 0;
 828 }
 829
 830 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 831                                 uint16_t vlan_id, int on)
 832 {
 833         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 834         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 835         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 836         struct qede_vlan_entry *tmp = NULL;
 837         struct qede_vlan_entry *vlan;
 838         struct ecore_filter_ucast ucast;
 839         int rc;
 840
 841         if (on) {
 842                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 843                         DP_ERR(edev, "Reached max VLAN filter limit"
 844                                       " enabling accept_any_vlan\n");
 845                         qede_config_accept_any_vlan(qdev, true);
 846                         return 0;
 847                 }
 848
 849                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 850                         if (tmp->vid == vlan_id) {
 851                                 DP_ERR(edev, "VLAN %u already configured\n",
 852                                        vlan_id);
 853                                 return -EEXIST;
 854                         }
 855                 }
 856
 857                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 858                                   RTE_CACHE_LINE_SIZE);
 859
 860                 if (!vlan) {
 861                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 862                         return -ENOMEM;
 863                 }
 864
 865                 qede_set_ucast_cmn_params(&ucast);
 866                 ucast.opcode = ECORE_FILTER_ADD;
 867                 ucast.type = ECORE_FILTER_VLAN;
 868                 ucast.vlan = vlan_id;
 869                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 870                                             NULL);
 871                 if (rc != 0) {
 872                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 873                                rc);
 874                         rte_free(vlan);
 875                 } else {
 876                         vlan->vid = vlan_id;
 877                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 878                         qdev->configured_vlans++;
 879                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 880                                 vlan_id, qdev->configured_vlans);
 881                 }
 882         } else {
 883                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 884                         if (tmp->vid == vlan_id)
 885                                 break;
 886                 }
 887
 888                 if (!tmp) {
 889                         if (qdev->configured_vlans == 0) {
 890                                 DP_INFO(edev,
 891                                         "No VLAN filters configured yet\n");
 892                                 return 0;
 893                         }
 894
 895                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 896                         return -EINVAL;
 897                 }
 898
 899                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 900
 901                 qede_set_ucast_cmn_params(&ucast);
 902                 ucast.opcode = ECORE_FILTER_REMOVE;
 903                 ucast.type = ECORE_FILTER_VLAN;
 904                 ucast.vlan = vlan_id;
 905                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 906                                             NULL);
 907                 if (rc != 0) {
 908                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
 909                                vlan_id, rc);
 910                 } else {
 911                         qdev->configured_vlans--;
 912                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
 913                                 vlan_id, qdev->configured_vlans);
 914                 }
 915         }
 916
 917         return rc;
 918 }
 919
 920 static void qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
 921 {
 922         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 923         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 924         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
 925
 926         if (mask & ETH_VLAN_STRIP_MASK) {
 927                 if (rxmode->hw_vlan_strip)
 928                         (void)qede_vlan_stripping(eth_dev, 1);
 929                 else
 930                         (void)qede_vlan_stripping(eth_dev, 0);
 931         }
 932
 933         if (mask & ETH_VLAN_FILTER_MASK) {
 934                 /* VLAN filtering kicks in when a VLAN is added */
 935                 if (rxmode->hw_vlan_filter) {
 936                         qede_vlan_filter_set(eth_dev, 0, 1);
 937                 } else {
 938                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
 939                                 DP_ERR(edev,
 940                                   " Please remove existing VLAN filters"
 941                                   " before disabling VLAN filtering\n");
 942                                 /* Signal app that VLAN filtering is still
 943                                  * enabled
 944                                  */
 945                                 rxmode->hw_vlan_filter = true;
 946                         } else {
 947                                 qede_vlan_filter_set(eth_dev, 0, 0);
 948                         }
 949                 }
 950         }
 951
 952         if (mask & ETH_VLAN_EXTEND_MASK)
 953                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
 954                         " and classification is based on outer tag only\n");
 955
 956         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
 957                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
 958 }
 959
 960 static void qede_prandom_bytes(uint32_t *buff)
 961 {
 962         uint8_t i;
 963
 964         srand((unsigned int)time(NULL));
 965         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 966                 buff[i] = rand();
 967 }
 968
 969 int qede_config_rss(struct rte_eth_dev *eth_dev)
 970 {
 971         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 972 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 973         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 974 #endif
 975         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
 976         struct rte_eth_rss_reta_entry64 reta_conf[2];
 977         struct rte_eth_rss_conf rss_conf;
 978         uint32_t i, id, pos, q;
 979
 980         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 981         if (!rss_conf.rss_key) {
 982                 DP_INFO(edev, "Applying driver default key\n");
 983                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
 984                 qede_prandom_bytes(&def_rss_key[0]);
 985                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
 986         }
 987
 988         /* Configure RSS hash */
 989         if (qede_rss_hash_update(eth_dev, &rss_conf))
 990                 return -EINVAL;
 991
 992         /* Configure default RETA */
 993         memset(reta_conf, 0, sizeof(reta_conf));
 994         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 995                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
 996
 997         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
 998                 id = i / RTE_RETA_GROUP_SIZE;
 999                 pos = i % RTE_RETA_GROUP_SIZE;
1000                 q = i % QEDE_RSS_COUNT(qdev);
1001                 reta_conf[id].reta[pos] = q;
1002         }
1003         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1004                                  ECORE_RSS_IND_TABLE_SIZE))
1005                 return -EINVAL;
1006
1007         return 0;
1008 }
1009
1010 static void qede_fastpath_start(struct ecore_dev *edev)
1011 {
1012         struct ecore_hwfn *p_hwfn;
1013         int i;
1014
1015         for_each_hwfn(edev, i) {
1016                 p_hwfn = &edev->hwfns[i];
1017                 ecore_hw_start_fastpath(p_hwfn);
1018         }
1019 }
1020
1021 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1022 {
1023         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1024         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1025
1026         PMD_INIT_FUNC_TRACE(edev);
1027
1028         /* Update MTU only if it has changed */
1029         if (qdev->mtu != qdev->new_mtu) {
1030                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1031                         goto err;
1032                 qdev->mtu = qdev->new_mtu;
1033                 /* If MTU has changed then update TPA too */
1034                 if (qdev->enable_lro)
1035                         if (qede_enable_tpa(eth_dev, true))
1036                                 goto err;
1037         }
1038
1039         /* Start queues */
1040         if (qede_start_queues(eth_dev))
1041                 goto err;
1042
1043         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1044          * enabling RSS. Hence RSS configuration is deferred upto this point.
1045          * Also, we would like to retain similar behavior in PF case, so we
1046          * don't do PF/VF specific check here.
1047          */
1048         if (eth_dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
1049                 if (qede_config_rss(eth_dev))
1050                         goto err;
1051
1052         /* Enable vport*/
1053         if (qede_activate_vport(eth_dev, true))
1054                 goto err;
1055
1056         /* Bring-up the link */
1057         qede_dev_set_link_state(eth_dev, true);
1058
1059         /* Start/resume traffic */
1060         qede_fastpath_start(edev);
1061
1062         DP_INFO(edev, "Device started\n");
1063
1064         return 0;
1065 err:
1066         DP_ERR(edev, "Device start fails\n");
1067         return -1; /* common error code is < 0 */
1068 }
1069
1070 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1071 {
1072         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1073         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1074
1075         PMD_INIT_FUNC_TRACE(edev);
1076
1077         /* Disable vport */
1078         if (qede_activate_vport(eth_dev, false))
1079                 return;
1080
1081         if (qdev->enable_lro)
1082                 qede_enable_tpa(eth_dev, false);
1083
1084         /* TODO: Do we need disable LRO or RSS */
1085         /* Stop queues */
1086         qede_stop_queues(eth_dev);
1087
1088         /* Disable traffic */
1089         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1090
1091         /* Bring the link down */
1092         qede_dev_set_link_state(eth_dev, false);
1093
1094         DP_INFO(edev, "Device is stopped\n");
1095 }
1096
1097 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1098 {
1099         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1100         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1101         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1102
1103         PMD_INIT_FUNC_TRACE(edev);
1104
1105         /* Check requirements for 100G mode */
1106         if (edev->num_hwfns > 1) {
1107                 if (eth_dev->data->nb_rx_queues < 2 ||
1108                                 eth_dev->data->nb_tx_queues < 2) {
1109                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1110                         return -EINVAL;
1111                 }
1112
1113                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1114                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1115                         DP_ERR(edev,
1116                                         "100G mode needs even no. of RX/TX queues\n");
1117                         return -EINVAL;
1118                 }
1119         }
1120
1121         /* Sanity checks and throw warnings */
1122         if (rxmode->enable_scatter)
1123                 eth_dev->data->scattered_rx = 1;
1124
1125         if (!rxmode->hw_strip_crc)
1126                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1127
1128         if (!rxmode->hw_ip_checksum)
1129                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1130                                 "in hw\n");
1131         if (rxmode->header_split)
1132                 DP_INFO(edev, "Header split enable is not supported\n");
1133         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1134                                 ETH_MQ_RX_RSS)) {
1135                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1136                 return -ENOTSUP;
1137         }
1138         /* Flow director mode check */
1139         if (qede_check_fdir_support(eth_dev))
1140                 return -ENOTSUP;
1141
1142         /* Deallocate resources if held previously. It is needed only if the
1143          * queue count has been changed from previous configuration. If its
1144          * going to change then it means RX/TX queue setup will be called
1145          * again and the fastpath pointers will be reinitialized there.
1146          */
1147         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1148             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1149                 qede_dealloc_fp_resc(eth_dev);
1150                 /* Proceed with updated queue count */
1151                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1152                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1153                 if (qede_alloc_fp_resc(qdev))
1154                         return -ENOMEM;
1155         }
1156
1157         /* VF's MTU has to be set using vport-start where as
1158          * PF's MTU can be updated via vport-update.
1159          */
1160         if (IS_VF(edev)) {
1161                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1162                         return -1;
1163         } else {
1164                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1165                         return -1;
1166         }
1167
1168         qdev->mtu = rxmode->max_rx_pkt_len;
1169         qdev->new_mtu = qdev->mtu;
1170
1171         /* Configure TPA parameters */
1172         if (rxmode->enable_lro) {
1173                 if (qede_enable_tpa(eth_dev, true))
1174                         return -EINVAL;
1175                 /* Enable scatter mode for LRO */
1176                 if (!rxmode->enable_scatter)
1177                         eth_dev->data->scattered_rx = 1;
1178         }
1179         qdev->enable_lro = rxmode->enable_lro;
1180
1181         /* Enable VLAN offloads by default */
1182         qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1183                         ETH_VLAN_FILTER_MASK |
1184                         ETH_VLAN_EXTEND_MASK);
1185
1186         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1187                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1188
1189         return 0;
1190 }
1191
1192 /* Info about HW descriptor ring limitations */
1193 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1194         .nb_max = 0x8000, /* 32K */
1195         .nb_min = 128,
1196         .nb_align = 128 /* lowest common multiple */
1197 };
1198
1199 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1200         .nb_max = 0x8000, /* 32K */
1201         .nb_min = 256,
1202         .nb_align = 256,
1203         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1204         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1205 };
1206
1207 static void
1208 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1209                   struct rte_eth_dev_info *dev_info)
1210 {
1211         struct qede_dev *qdev = eth_dev->data->dev_private;
1212         struct ecore_dev *edev = &qdev->edev;
1213         struct qed_link_output link;
1214         uint32_t speed_cap = 0;
1215
1216         PMD_INIT_FUNC_TRACE(edev);
1217
1218         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1219         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1220         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1221         dev_info->rx_desc_lim = qede_rx_desc_lim;
1222         dev_info->tx_desc_lim = qede_tx_desc_lim;
1223
1224         if (IS_PF(edev))
1225                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1226                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1227         else
1228                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1229                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1230         dev_info->max_tx_queues = dev_info->max_rx_queues;
1231
1232         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1233         dev_info->max_vfs = 0;
1234         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1235         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1236         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1237
1238         dev_info->default_txconf = (struct rte_eth_txconf) {
1239                 .txq_flags = QEDE_TXQ_FLAGS,
1240         };
1241
1242         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1243                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1244                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1245                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1246                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1247                                      DEV_RX_OFFLOAD_TCP_LRO);
1248
1249         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1250                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1251                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1252                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1253                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1254                                      DEV_TX_OFFLOAD_TCP_TSO |
1255                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1256
1257         memset(&link, 0, sizeof(struct qed_link_output));
1258         qdev->ops->common->get_link(edev, &link);
1259         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1260                 speed_cap |= ETH_LINK_SPEED_1G;
1261         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1262                 speed_cap |= ETH_LINK_SPEED_10G;
1263         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1264                 speed_cap |= ETH_LINK_SPEED_25G;
1265         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1266                 speed_cap |= ETH_LINK_SPEED_40G;
1267         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1268                 speed_cap |= ETH_LINK_SPEED_50G;
1269         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1270                 speed_cap |= ETH_LINK_SPEED_100G;
1271         dev_info->speed_capa = speed_cap;
1272 }
1273
1274 /* return 0 means link status changed, -1 means not changed */
1275 static int
1276 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1277 {
1278         struct qede_dev *qdev = eth_dev->data->dev_private;
1279         struct ecore_dev *edev = &qdev->edev;
1280         uint16_t link_duplex;
1281         struct qed_link_output link;
1282         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1283
1284         memset(&link, 0, sizeof(struct qed_link_output));
1285         qdev->ops->common->get_link(edev, &link);
1286
1287         /* Link Speed */
1288         curr->link_speed = link.speed;
1289
1290         /* Link Mode */
1291         switch (link.duplex) {
1292         case QEDE_DUPLEX_HALF:
1293                 link_duplex = ETH_LINK_HALF_DUPLEX;
1294                 break;
1295         case QEDE_DUPLEX_FULL:
1296                 link_duplex = ETH_LINK_FULL_DUPLEX;
1297                 break;
1298         case QEDE_DUPLEX_UNKNOWN:
1299         default:
1300                 link_duplex = -1;
1301         }
1302         curr->link_duplex = link_duplex;
1303
1304         /* Link Status */
1305         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1306
1307         /* AN */
1308         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1309                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1310
1311         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1312                 curr->link_speed, curr->link_duplex,
1313                 curr->link_autoneg, curr->link_status);
1314
1315         /* return 0 means link status changed, -1 means not changed */
1316         return ((curr->link_status == link.link_up) ? -1 : 0);
1317 }
1318
1319 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1320 {
1321 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1322         struct qede_dev *qdev = eth_dev->data->dev_private;
1323         struct ecore_dev *edev = &qdev->edev;
1324
1325         PMD_INIT_FUNC_TRACE(edev);
1326 #endif
1327
1328         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1329
1330         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1331                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1332
1333         qed_configure_filter_rx_mode(eth_dev, type);
1334 }
1335
1336 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1337 {
1338 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1339         struct qede_dev *qdev = eth_dev->data->dev_private;
1340         struct ecore_dev *edev = &qdev->edev;
1341
1342         PMD_INIT_FUNC_TRACE(edev);
1343 #endif
1344
1345         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1346                 qed_configure_filter_rx_mode(eth_dev,
1347                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1348         else
1349                 qed_configure_filter_rx_mode(eth_dev,
1350                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1351 }
1352
1353 static void qede_poll_sp_sb_cb(void *param)
1354 {
1355         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1356         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1357         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1358         int rc;
1359
1360         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1361         qede_interrupt_action(&edev->hwfns[1]);
1362
1363         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1364                                qede_poll_sp_sb_cb,
1365                                (void *)eth_dev);
1366         if (rc != 0) {
1367                 DP_ERR(edev, "Unable to start periodic"
1368                              " timer rc %d\n", rc);
1369                 assert(false && "Unable to start periodic timer");
1370         }
1371 }
1372
1373 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1374 {
1375         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1376         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1377         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1378
1379         PMD_INIT_FUNC_TRACE(edev);
1380
1381         /* dev_stop() shall cleanup fp resources in hw but without releasing
1382          * dma memories and sw structures so that dev_start() can be called
1383          * by the app without reconfiguration. However, in dev_close() we
1384          * can release all the resources and device can be brought up newly
1385          */
1386         if (eth_dev->data->dev_started)
1387                 qede_dev_stop(eth_dev);
1388
1389         qede_stop_vport(edev);
1390         qede_fdir_dealloc_resc(eth_dev);
1391         qede_dealloc_fp_resc(eth_dev);
1392
1393         eth_dev->data->nb_rx_queues = 0;
1394         eth_dev->data->nb_tx_queues = 0;
1395
1396         qdev->ops->common->slowpath_stop(edev);
1397         qdev->ops->common->remove(edev);
1398         rte_intr_disable(&pci_dev->intr_handle);
1399         rte_intr_callback_unregister(&pci_dev->intr_handle,
1400                                      qede_interrupt_handler, (void *)eth_dev);
1401         if (edev->num_hwfns > 1)
1402                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1403 }
1404
1405 static void
1406 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1407 {
1408         struct qede_dev *qdev = eth_dev->data->dev_private;
1409         struct ecore_dev *edev = &qdev->edev;
1410         struct ecore_eth_stats stats;
1411         unsigned int i = 0, j = 0, qid;
1412         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1413         struct qede_tx_queue *txq;
1414
1415         ecore_get_vport_stats(edev, &stats);
1416
1417         /* RX Stats */
1418         eth_stats->ipackets = stats.rx_ucast_pkts +
1419             stats.rx_mcast_pkts + stats.rx_bcast_pkts;
1420
1421         eth_stats->ibytes = stats.rx_ucast_bytes +
1422             stats.rx_mcast_bytes + stats.rx_bcast_bytes;
1423
1424         eth_stats->ierrors = stats.rx_crc_errors +
1425             stats.rx_align_errors +
1426             stats.rx_carrier_errors +
1427             stats.rx_oversize_packets +
1428             stats.rx_jabbers + stats.rx_undersize_packets;
1429
1430         eth_stats->rx_nombuf = stats.no_buff_discards;
1431
1432         eth_stats->imissed = stats.mftag_filter_discards +
1433             stats.mac_filter_discards +
1434             stats.no_buff_discards + stats.brb_truncates + stats.brb_discards;
1435
1436         /* TX stats */
1437         eth_stats->opackets = stats.tx_ucast_pkts +
1438             stats.tx_mcast_pkts + stats.tx_bcast_pkts;
1439
1440         eth_stats->obytes = stats.tx_ucast_bytes +
1441             stats.tx_mcast_bytes + stats.tx_bcast_bytes;
1442
1443         eth_stats->oerrors = stats.tx_err_drop_pkts;
1444
1445         /* Queue stats */
1446         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1447                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1448         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1449                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1450         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1451             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1452                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1453                        "Not all the queue stats will be displayed. Set"
1454                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1455                        " appropriately and retry.\n");
1456
1457         for_each_rss(qid) {
1458                 eth_stats->q_ipackets[i] =
1459                         *(uint64_t *)(
1460                                 ((char *)(qdev->fp_array[qid].rxq)) +
1461                                 offsetof(struct qede_rx_queue,
1462                                 rcv_pkts));
1463                 eth_stats->q_errors[i] =
1464                         *(uint64_t *)(
1465                                 ((char *)(qdev->fp_array[qid].rxq)) +
1466                                 offsetof(struct qede_rx_queue,
1467                                 rx_hw_errors)) +
1468                         *(uint64_t *)(
1469                                 ((char *)(qdev->fp_array[qid].rxq)) +
1470                                 offsetof(struct qede_rx_queue,
1471                                 rx_alloc_errors));
1472                 i++;
1473                 if (i == rxq_stat_cntrs)
1474                         break;
1475         }
1476
1477         for_each_tss(qid) {
1478                 txq = qdev->fp_array[qid].txq;
1479                 eth_stats->q_opackets[j] =
1480                         *((uint64_t *)(uintptr_t)
1481                                 (((uint64_t)(uintptr_t)(txq)) +
1482                                  offsetof(struct qede_tx_queue,
1483                                           xmit_pkts)));
1484                 j++;
1485                 if (j == txq_stat_cntrs)
1486                         break;
1487         }
1488 }
1489
1490 static unsigned
1491 qede_get_xstats_count(struct qede_dev *qdev) {
1492         return RTE_DIM(qede_xstats_strings) +
1493                 (RTE_DIM(qede_rxq_xstats_strings) *
1494                  RTE_MIN(QEDE_RSS_COUNT(qdev),
1495                          RTE_ETHDEV_QUEUE_STAT_CNTRS));
1496 }
1497
1498 static int
1499 qede_get_xstats_names(struct rte_eth_dev *dev,
1500                       struct rte_eth_xstat_name *xstats_names,
1501                       __rte_unused unsigned int limit)
1502 {
1503         struct qede_dev *qdev = dev->data->dev_private;
1504         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1505         unsigned int i, qid, stat_idx = 0;
1506         unsigned int rxq_stat_cntrs;
1507
1508         if (xstats_names != NULL) {
1509                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1510                         snprintf(xstats_names[stat_idx].name,
1511                                 sizeof(xstats_names[stat_idx].name),
1512                                 "%s",
1513                                 qede_xstats_strings[i].name);
1514                         stat_idx++;
1515                 }
1516
1517                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1518                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1519                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1520                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1521                                 snprintf(xstats_names[stat_idx].name,
1522                                         sizeof(xstats_names[stat_idx].name),
1523                                         "%.4s%d%s",
1524                                         qede_rxq_xstats_strings[i].name, qid,
1525                                         qede_rxq_xstats_strings[i].name + 4);
1526                                 stat_idx++;
1527                         }
1528                 }
1529         }
1530
1531         return stat_cnt;
1532 }
1533
1534 static int
1535 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1536                 unsigned int n)
1537 {
1538         struct qede_dev *qdev = dev->data->dev_private;
1539         struct ecore_dev *edev = &qdev->edev;
1540         struct ecore_eth_stats stats;
1541         const unsigned int num = qede_get_xstats_count(qdev);
1542         unsigned int i, qid, stat_idx = 0;
1543         unsigned int rxq_stat_cntrs;
1544
1545         if (n < num)
1546                 return num;
1547
1548         ecore_get_vport_stats(edev, &stats);
1549
1550         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1551                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1552                                              qede_xstats_strings[i].offset);
1553                 xstats[stat_idx].id = stat_idx;
1554                 stat_idx++;
1555         }
1556
1557         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1558                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1559         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1560                 for_each_rss(qid) {
1561                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1562                                 xstats[stat_idx].value = *(uint64_t *)(
1563                                         ((char *)(qdev->fp_array[qid].rxq)) +
1564                                          qede_rxq_xstats_strings[i].offset);
1565                                 xstats[stat_idx].id = stat_idx;
1566                                 stat_idx++;
1567                         }
1568                 }
1569         }
1570
1571         return stat_idx;
1572 }
1573
1574 static void
1575 qede_reset_xstats(struct rte_eth_dev *dev)
1576 {
1577         struct qede_dev *qdev = dev->data->dev_private;
1578         struct ecore_dev *edev = &qdev->edev;
1579
1580         ecore_reset_vport_stats(edev);
1581 }
1582
1583 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1584 {
1585         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1586         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1587         struct qed_link_params link_params;
1588         int rc;
1589
1590         DP_INFO(edev, "setting link state %d\n", link_up);
1591         memset(&link_params, 0, sizeof(link_params));
1592         link_params.link_up = link_up;
1593         rc = qdev->ops->common->set_link(edev, &link_params);
1594         if (rc != ECORE_SUCCESS)
1595                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1596
1597         return rc;
1598 }
1599
1600 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1601 {
1602         return qede_dev_set_link_state(eth_dev, true);
1603 }
1604
1605 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1606 {
1607         return qede_dev_set_link_state(eth_dev, false);
1608 }
1609
1610 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1611 {
1612         struct qede_dev *qdev = eth_dev->data->dev_private;
1613         struct ecore_dev *edev = &qdev->edev;
1614
1615         ecore_reset_vport_stats(edev);
1616 }
1617
1618 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1619 {
1620         enum qed_filter_rx_mode_type type =
1621             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1622
1623         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1624                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1625
1626         qed_configure_filter_rx_mode(eth_dev, type);
1627 }
1628
1629 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1630 {
1631         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1632                 qed_configure_filter_rx_mode(eth_dev,
1633                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1634         else
1635                 qed_configure_filter_rx_mode(eth_dev,
1636                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1637 }
1638
1639 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1640                               struct rte_eth_fc_conf *fc_conf)
1641 {
1642         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1643         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1644         struct qed_link_output current_link;
1645         struct qed_link_params params;
1646
1647         memset(&current_link, 0, sizeof(current_link));
1648         qdev->ops->common->get_link(edev, &current_link);
1649
1650         memset(&params, 0, sizeof(params));
1651         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1652         if (fc_conf->autoneg) {
1653                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1654                         DP_ERR(edev, "Autoneg not supported\n");
1655                         return -EINVAL;
1656                 }
1657                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1658         }
1659
1660         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1661         if (fc_conf->mode == RTE_FC_FULL)
1662                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1663                                         QED_LINK_PAUSE_RX_ENABLE);
1664         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1665                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1666         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1667                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1668
1669         params.link_up = true;
1670         (void)qdev->ops->common->set_link(edev, &params);
1671
1672         return 0;
1673 }
1674
1675 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1676                               struct rte_eth_fc_conf *fc_conf)
1677 {
1678         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1679         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1680         struct qed_link_output current_link;
1681
1682         memset(&current_link, 0, sizeof(current_link));
1683         qdev->ops->common->get_link(edev, &current_link);
1684
1685         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1686                 fc_conf->autoneg = true;
1687
1688         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1689                                          QED_LINK_PAUSE_TX_ENABLE))
1690                 fc_conf->mode = RTE_FC_FULL;
1691         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1692                 fc_conf->mode = RTE_FC_RX_PAUSE;
1693         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1694                 fc_conf->mode = RTE_FC_TX_PAUSE;
1695         else
1696                 fc_conf->mode = RTE_FC_NONE;
1697
1698         return 0;
1699 }
1700
1701 static const uint32_t *
1702 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1703 {
1704         static const uint32_t ptypes[] = {
1705                 RTE_PTYPE_L3_IPV4,
1706                 RTE_PTYPE_L3_IPV6,
1707                 RTE_PTYPE_UNKNOWN
1708         };
1709
1710         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1711                 return ptypes;
1712
1713         return NULL;
1714 }
1715
1716 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1717 {
1718         *rss_caps = 0;
1719         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1720         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1721         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1722         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1723         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1724         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1725         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1726         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1727 }
1728
1729 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1730                          struct rte_eth_rss_conf *rss_conf)
1731 {
1732         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1733         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1734         struct ecore_sp_vport_update_params vport_update_params;
1735         struct ecore_rss_params rss_params;
1736         struct ecore_hwfn *p_hwfn;
1737         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1738         uint64_t hf = rss_conf->rss_hf;
1739         uint8_t len = rss_conf->rss_key_len;
1740         uint8_t idx;
1741         uint8_t i;
1742         int rc;
1743
1744         memset(&vport_update_params, 0, sizeof(vport_update_params));
1745         memset(&rss_params, 0, sizeof(rss_params));
1746
1747         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1748                 (unsigned long)hf, len, key);
1749
1750         if (hf != 0) {
1751                 /* Enabling RSS */
1752                 DP_INFO(edev, "Enabling rss\n");
1753
1754                 /* RSS caps */
1755                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1756                 rss_params.update_rss_capabilities = 1;
1757
1758                 /* RSS hash key */
1759                 if (key) {
1760                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1761                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1762                                 return -EINVAL;
1763                         }
1764                         DP_INFO(edev, "Applying user supplied hash key\n");
1765                         rss_params.update_rss_key = 1;
1766                         memcpy(&rss_params.rss_key, key, len);
1767                 }
1768                 rss_params.rss_enable = 1;
1769         }
1770
1771         rss_params.update_rss_config = 1;
1772         /* tbl_size has to be set with capabilities */
1773         rss_params.rss_table_size_log = 7;
1774         vport_update_params.vport_id = 0;
1775         /* pass the L2 handles instead of qids */
1776         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1777                 idx = qdev->rss_ind_table[i];
1778                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1779         }
1780         vport_update_params.rss_params = &rss_params;
1781
1782         for_each_hwfn(edev, i) {
1783                 p_hwfn = &edev->hwfns[i];
1784                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1785                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1786                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1787                 if (rc) {
1788                         DP_ERR(edev, "vport-update for RSS failed\n");
1789                         return rc;
1790                 }
1791         }
1792         qdev->rss_enable = rss_params.rss_enable;
1793
1794         /* Update local structure for hash query */
1795         qdev->rss_conf.rss_hf = hf;
1796         qdev->rss_conf.rss_key_len = len;
1797         if (qdev->rss_enable) {
1798                 if  (qdev->rss_conf.rss_key == NULL) {
1799                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1800                         if (qdev->rss_conf.rss_key == NULL) {
1801                                 DP_ERR(edev, "No memory to store RSS key\n");
1802                                 return -ENOMEM;
1803                         }
1804                 }
1805                 if (key && len) {
1806                         DP_INFO(edev, "Storing RSS key\n");
1807                         memcpy(qdev->rss_conf.rss_key, key, len);
1808                 }
1809         } else if (!qdev->rss_enable && len == 0) {
1810                 if (qdev->rss_conf.rss_key) {
1811                         free(qdev->rss_conf.rss_key);
1812                         qdev->rss_conf.rss_key = NULL;
1813                         DP_INFO(edev, "Free RSS key\n");
1814                 }
1815         }
1816
1817         return 0;
1818 }
1819
1820 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1821                            struct rte_eth_rss_conf *rss_conf)
1822 {
1823         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1824
1825         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1826         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1827
1828         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1829                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1830                        rss_conf->rss_key_len);
1831         return 0;
1832 }
1833
1834 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1835                                     struct ecore_rss_params *rss)
1836 {
1837         int i, fn;
1838         bool rss_mode = 1; /* enable */
1839         struct ecore_queue_cid *cid;
1840         struct ecore_rss_params *t_rss;
1841
1842         /* In regular scenario, we'd simply need to take input handlers.
1843          * But in CMT, we'd have to split the handlers according to the
1844          * engine they were configured on. We'd then have to understand
1845          * whether RSS is really required, since 2-queues on CMT doesn't
1846          * require RSS.
1847          */
1848
1849         /* CMT should be round-robin */
1850         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1851                 cid = rss->rss_ind_table[i];
1852
1853                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
1854                         t_rss = &rss[0];
1855                 else
1856                         t_rss = &rss[1];
1857
1858                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
1859         }
1860
1861         t_rss = &rss[1];
1862         t_rss->update_rss_ind_table = 1;
1863         t_rss->rss_table_size_log = 7;
1864         t_rss->update_rss_config = 1;
1865
1866         /* Make sure RSS is actually required */
1867         for_each_hwfn(edev, fn) {
1868                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
1869                      i++) {
1870                         if (rss[fn].rss_ind_table[i] !=
1871                             rss[fn].rss_ind_table[0])
1872                                 break;
1873                 }
1874
1875                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
1876                         DP_INFO(edev,
1877                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
1878                         rss_mode = 0;
1879                         goto out;
1880                 }
1881         }
1882
1883 out:
1884         t_rss->rss_enable = rss_mode;
1885
1886         return rss_mode;
1887 }
1888
1889 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
1890                          struct rte_eth_rss_reta_entry64 *reta_conf,
1891                          uint16_t reta_size)
1892 {
1893         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1894         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1895         struct ecore_sp_vport_update_params vport_update_params;
1896         struct ecore_rss_params *params;
1897         struct ecore_hwfn *p_hwfn;
1898         uint16_t i, idx, shift;
1899         uint8_t entry;
1900         int rc = 0;
1901
1902         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1903                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
1904                        reta_size);
1905                 return -EINVAL;
1906         }
1907
1908         memset(&vport_update_params, 0, sizeof(vport_update_params));
1909         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
1910                              RTE_CACHE_LINE_SIZE);
1911
1912         for (i = 0; i < reta_size; i++) {
1913                 idx = i / RTE_RETA_GROUP_SIZE;
1914                 shift = i % RTE_RETA_GROUP_SIZE;
1915                 if (reta_conf[idx].mask & (1ULL << shift)) {
1916                         entry = reta_conf[idx].reta[shift];
1917                         /* Pass rxq handles to ecore */
1918                         params->rss_ind_table[i] =
1919                                         qdev->fp_array[entry].rxq->handle;
1920                         /* Update the local copy for RETA query command */
1921                         qdev->rss_ind_table[i] = entry;
1922                 }
1923         }
1924
1925         params->update_rss_ind_table = 1;
1926         params->rss_table_size_log = 7;
1927         params->update_rss_config = 1;
1928
1929         /* Fix up RETA for CMT mode device */
1930         if (edev->num_hwfns > 1)
1931                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
1932                                                             params);
1933         vport_update_params.vport_id = 0;
1934         /* Use the current value of rss_enable */
1935         params->rss_enable = qdev->rss_enable;
1936         vport_update_params.rss_params = params;
1937
1938         for_each_hwfn(edev, i) {
1939                 p_hwfn = &edev->hwfns[i];
1940                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1941                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1942                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1943                 if (rc) {
1944                         DP_ERR(edev, "vport-update for RSS failed\n");
1945                         goto out;
1946                 }
1947         }
1948
1949 out:
1950         rte_free(params);
1951         return rc;
1952 }
1953
1954 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
1955                                struct rte_eth_rss_reta_entry64 *reta_conf,
1956                                uint16_t reta_size)
1957 {
1958         struct qede_dev *qdev = eth_dev->data->dev_private;
1959         struct ecore_dev *edev = &qdev->edev;
1960         uint16_t i, idx, shift;
1961         uint8_t entry;
1962
1963         if (reta_size > ETH_RSS_RETA_SIZE_128) {
1964                 DP_ERR(edev, "reta_size %d is not supported\n",
1965                        reta_size);
1966                 return -EINVAL;
1967         }
1968
1969         for (i = 0; i < reta_size; i++) {
1970                 idx = i / RTE_RETA_GROUP_SIZE;
1971                 shift = i % RTE_RETA_GROUP_SIZE;
1972                 if (reta_conf[idx].mask & (1ULL << shift)) {
1973                         entry = qdev->rss_ind_table[i];
1974                         reta_conf[idx].reta[shift] = entry;
1975                 }
1976         }
1977
1978         return 0;
1979 }
1980
1981
1982
1983 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
1984 {
1985         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
1986         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1987         struct rte_eth_dev_info dev_info = {0};
1988         struct qede_fastpath *fp;
1989         uint32_t frame_size;
1990         uint16_t rx_buf_size;
1991         uint16_t bufsz;
1992         int i;
1993
1994         PMD_INIT_FUNC_TRACE(edev);
1995         qede_dev_info_get(dev, &dev_info);
1996         frame_size = mtu + QEDE_ETH_OVERHEAD;
1997         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
1998                 DP_ERR(edev, "MTU %u out of range\n", mtu);
1999                 return -EINVAL;
2000         }
2001         if (!dev->data->scattered_rx &&
2002             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2003                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2004                         dev->data->min_rx_buf_size);
2005                 return -EINVAL;
2006         }
2007         /* Temporarily replace I/O functions with dummy ones. It cannot
2008          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2009          */
2010         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2011         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2012         qede_dev_stop(dev);
2013         rte_delay_ms(1000);
2014         qdev->mtu = mtu;
2015         /* Fix up RX buf size for all queues of the port */
2016         for_each_rss(i) {
2017                 fp = &qdev->fp_array[i];
2018                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2019                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2020                 if (dev->data->scattered_rx)
2021                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2022                 else
2023                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2024                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2025                 fp->rxq->rx_buf_size = rx_buf_size;
2026                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2027         }
2028         qede_dev_start(dev);
2029         if (frame_size > ETHER_MAX_LEN)
2030                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2031         else
2032                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2033         /* update max frame size */
2034         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2035         /* Reassign back */
2036         dev->rx_pkt_burst = qede_recv_pkts;
2037         dev->tx_pkt_burst = qede_xmit_pkts;
2038
2039         return 0;
2040 }
2041
2042 static int
2043 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2044                        struct rte_eth_udp_tunnel *tunnel_udp,
2045                        bool add)
2046 {
2047         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2048         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2049         struct ecore_tunnel_info tunn; /* @DPDK */
2050         struct ecore_hwfn *p_hwfn;
2051         int rc, i;
2052
2053         PMD_INIT_FUNC_TRACE(edev);
2054
2055         memset(&tunn, 0, sizeof(tunn));
2056         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2057                 tunn.vxlan_port.b_update_port = true;
2058                 tunn.vxlan_port.port = (add) ? tunnel_udp->udp_port :
2059                                                   QEDE_VXLAN_DEF_PORT;
2060                 for_each_hwfn(edev, i) {
2061                         p_hwfn = &edev->hwfns[i];
2062                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2063                                                 ECORE_SPQ_MODE_CB, NULL);
2064                         if (rc != ECORE_SUCCESS) {
2065                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2066                                        tunn.vxlan_port.port);
2067                                 return rc;
2068                         }
2069                 }
2070         }
2071
2072         return 0;
2073 }
2074
2075 static int
2076 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2077                       struct rte_eth_udp_tunnel *tunnel_udp)
2078 {
2079         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2080 }
2081
2082 static int
2083 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2084                       struct rte_eth_udp_tunnel *tunnel_udp)
2085 {
2086         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2087 }
2088
2089 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2090                                        uint32_t *clss, char *str)
2091 {
2092         uint16_t j;
2093         *clss = MAX_ECORE_TUNN_CLSS;
2094
2095         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2096                 if (filter == qede_tunn_types[j].rte_filter_type) {
2097                         *type = qede_tunn_types[j].qede_type;
2098                         *clss = qede_tunn_types[j].qede_tunn_clss;
2099                         strcpy(str, qede_tunn_types[j].string);
2100                         return;
2101                 }
2102         }
2103 }
2104
2105 static int
2106 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2107                               const struct rte_eth_tunnel_filter_conf *conf,
2108                               uint32_t type)
2109 {
2110         /* Init commmon ucast params first */
2111         qede_set_ucast_cmn_params(ucast);
2112
2113         /* Copy out the required fields based on classification type */
2114         ucast->type = type;
2115
2116         switch (type) {
2117         case ECORE_FILTER_VNI:
2118                 ucast->vni = conf->tenant_id;
2119         break;
2120         case ECORE_FILTER_INNER_VLAN:
2121                 ucast->vlan = conf->inner_vlan;
2122         break;
2123         case ECORE_FILTER_MAC:
2124                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2125                        ETHER_ADDR_LEN);
2126         break;
2127         case ECORE_FILTER_INNER_MAC:
2128                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2129                        ETHER_ADDR_LEN);
2130         break;
2131         case ECORE_FILTER_MAC_VNI_PAIR:
2132                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2133                         ETHER_ADDR_LEN);
2134                 ucast->vni = conf->tenant_id;
2135         break;
2136         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2137                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2138                         ETHER_ADDR_LEN);
2139                 ucast->vni = conf->tenant_id;
2140         break;
2141         case ECORE_FILTER_INNER_PAIR:
2142                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2143                         ETHER_ADDR_LEN);
2144                 ucast->vlan = conf->inner_vlan;
2145         break;
2146         default:
2147                 return -EINVAL;
2148         }
2149
2150         return ECORE_SUCCESS;
2151 }
2152
2153 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2154                                   enum rte_filter_op filter_op,
2155                                   const struct rte_eth_tunnel_filter_conf *conf)
2156 {
2157         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2158         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2159         struct ecore_tunnel_info tunn;
2160         struct ecore_hwfn *p_hwfn;
2161         enum ecore_filter_ucast_type type;
2162         enum ecore_tunn_clss clss;
2163         struct ecore_filter_ucast ucast;
2164         char str[80];
2165         uint16_t filter_type;
2166         int rc, i;
2167
2168         PMD_INIT_FUNC_TRACE(edev);
2169
2170         filter_type = conf->filter_type | qdev->vxlan_filter_type;
2171         /* First determine if the given filter classification is supported */
2172         qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2173         if (clss == MAX_ECORE_TUNN_CLSS) {
2174                 DP_ERR(edev, "Wrong filter type\n");
2175                 return -EINVAL;
2176         }
2177         /* Init tunnel ucast params */
2178         rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2179         if (rc != ECORE_SUCCESS) {
2180                 DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2181                                 conf->filter_type);
2182                 return rc;
2183         }
2184         DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2185                 str, filter_op, ucast.type);
2186         switch (filter_op) {
2187         case RTE_ETH_FILTER_ADD:
2188                 ucast.opcode = ECORE_FILTER_ADD;
2189
2190                 /* Skip MAC/VLAN if filter is based on VNI */
2191                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2192                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2193                         if (rc == 0) {
2194                                 /* Enable accept anyvlan */
2195                                 qede_config_accept_any_vlan(qdev, true);
2196                         }
2197                 } else {
2198                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2199                         if (rc == 0)
2200                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2201                                                     ECORE_SPQ_MODE_CB, NULL);
2202                 }
2203
2204                 if (rc != ECORE_SUCCESS)
2205                         return rc;
2206
2207                 qdev->vxlan_filter_type = filter_type;
2208
2209                 DP_INFO(edev, "Enabling VXLAN tunneling\n");
2210                 qede_set_cmn_tunn_param(&tunn, clss, true, true);
2211                 for_each_hwfn(edev, i) {
2212                         p_hwfn = &edev->hwfns[i];
2213                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn,
2214                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
2215                         if (rc != ECORE_SUCCESS) {
2216                                 DP_ERR(edev, "Failed to update tunn_clss %u\n",
2217                                        tunn.vxlan.tun_cls);
2218                         }
2219                 }
2220                 qdev->num_tunn_filters++; /* Filter added successfully */
2221         break;
2222         case RTE_ETH_FILTER_DELETE:
2223                 ucast.opcode = ECORE_FILTER_REMOVE;
2224
2225                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2226                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2227                 } else {
2228                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2229                         if (rc == 0)
2230                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2231                                                     ECORE_SPQ_MODE_CB, NULL);
2232                 }
2233                 if (rc != ECORE_SUCCESS)
2234                         return rc;
2235
2236                 qdev->vxlan_filter_type = filter_type;
2237                 qdev->num_tunn_filters--;
2238
2239                 /* Disable VXLAN if VXLAN filters become 0 */
2240                 if (qdev->num_tunn_filters == 0) {
2241                         DP_INFO(edev, "Disabling VXLAN tunneling\n");
2242
2243                         /* Use 0 as tunnel mode */
2244                         qede_set_cmn_tunn_param(&tunn, clss, false, true);
2245                         for_each_hwfn(edev, i) {
2246                                 p_hwfn = &edev->hwfns[i];
2247                                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, &tunn,
2248                                         ECORE_SPQ_MODE_CB, NULL);
2249                                 if (rc != ECORE_SUCCESS) {
2250                                         DP_ERR(edev,
2251                                                 "Failed to update tunn_clss %u\n",
2252                                                 tunn.vxlan.tun_cls);
2253                                         break;
2254                                 }
2255                         }
2256                 }
2257         break;
2258         default:
2259                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2260                 return -EINVAL;
2261         }
2262         DP_INFO(edev, "Current VXLAN filters %d\n", qdev->num_tunn_filters);
2263
2264         return 0;
2265 }
2266
2267 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2268                          enum rte_filter_type filter_type,
2269                          enum rte_filter_op filter_op,
2270                          void *arg)
2271 {
2272         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2273         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2274         struct rte_eth_tunnel_filter_conf *filter_conf =
2275                         (struct rte_eth_tunnel_filter_conf *)arg;
2276
2277         switch (filter_type) {
2278         case RTE_ETH_FILTER_TUNNEL:
2279                 switch (filter_conf->tunnel_type) {
2280                 case RTE_TUNNEL_TYPE_VXLAN:
2281                         DP_INFO(edev,
2282                                 "Packet steering to the specified Rx queue"
2283                                 " is not supported with VXLAN tunneling");
2284                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2285                                                       filter_conf));
2286                 /* Place holders for future tunneling support */
2287                 case RTE_TUNNEL_TYPE_GENEVE:
2288                 case RTE_TUNNEL_TYPE_TEREDO:
2289                 case RTE_TUNNEL_TYPE_NVGRE:
2290                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2291                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2292                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2293                                 filter_conf->tunnel_type);
2294                         return -EINVAL;
2295                 case RTE_TUNNEL_TYPE_NONE:
2296                 default:
2297                         return 0;
2298                 }
2299                 break;
2300         case RTE_ETH_FILTER_FDIR:
2301                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2302         case RTE_ETH_FILTER_NTUPLE:
2303                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2304         case RTE_ETH_FILTER_MACVLAN:
2305         case RTE_ETH_FILTER_ETHERTYPE:
2306         case RTE_ETH_FILTER_FLEXIBLE:
2307         case RTE_ETH_FILTER_SYN:
2308         case RTE_ETH_FILTER_HASH:
2309         case RTE_ETH_FILTER_L2_TUNNEL:
2310         case RTE_ETH_FILTER_MAX:
2311         default:
2312                 DP_ERR(edev, "Unsupported filter type %d\n",
2313                         filter_type);
2314                 return -EINVAL;
2315         }
2316
2317         return 0;
2318 }
2319
2320 static const struct eth_dev_ops qede_eth_dev_ops = {
2321         .dev_configure = qede_dev_configure,
2322         .dev_infos_get = qede_dev_info_get,
2323         .rx_queue_setup = qede_rx_queue_setup,
2324         .rx_queue_release = qede_rx_queue_release,
2325         .tx_queue_setup = qede_tx_queue_setup,
2326         .tx_queue_release = qede_tx_queue_release,
2327         .dev_start = qede_dev_start,
2328         .dev_set_link_up = qede_dev_set_link_up,
2329         .dev_set_link_down = qede_dev_set_link_down,
2330         .link_update = qede_link_update,
2331         .promiscuous_enable = qede_promiscuous_enable,
2332         .promiscuous_disable = qede_promiscuous_disable,
2333         .allmulticast_enable = qede_allmulticast_enable,
2334         .allmulticast_disable = qede_allmulticast_disable,
2335         .dev_stop = qede_dev_stop,
2336         .dev_close = qede_dev_close,
2337         .stats_get = qede_get_stats,
2338         .stats_reset = qede_reset_stats,
2339         .xstats_get = qede_get_xstats,
2340         .xstats_reset = qede_reset_xstats,
2341         .xstats_get_names = qede_get_xstats_names,
2342         .mac_addr_add = qede_mac_addr_add,
2343         .mac_addr_remove = qede_mac_addr_remove,
2344         .mac_addr_set = qede_mac_addr_set,
2345         .vlan_offload_set = qede_vlan_offload_set,
2346         .vlan_filter_set = qede_vlan_filter_set,
2347         .flow_ctrl_set = qede_flow_ctrl_set,
2348         .flow_ctrl_get = qede_flow_ctrl_get,
2349         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2350         .rss_hash_update = qede_rss_hash_update,
2351         .rss_hash_conf_get = qede_rss_hash_conf_get,
2352         .reta_update  = qede_rss_reta_update,
2353         .reta_query  = qede_rss_reta_query,
2354         .mtu_set = qede_set_mtu,
2355         .filter_ctrl = qede_dev_filter_ctrl,
2356         .udp_tunnel_port_add = qede_udp_dst_port_add,
2357         .udp_tunnel_port_del = qede_udp_dst_port_del,
2358 };
2359
2360 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2361         .dev_configure = qede_dev_configure,
2362         .dev_infos_get = qede_dev_info_get,
2363         .rx_queue_setup = qede_rx_queue_setup,
2364         .rx_queue_release = qede_rx_queue_release,
2365         .tx_queue_setup = qede_tx_queue_setup,
2366         .tx_queue_release = qede_tx_queue_release,
2367         .dev_start = qede_dev_start,
2368         .dev_set_link_up = qede_dev_set_link_up,
2369         .dev_set_link_down = qede_dev_set_link_down,
2370         .link_update = qede_link_update,
2371         .promiscuous_enable = qede_promiscuous_enable,
2372         .promiscuous_disable = qede_promiscuous_disable,
2373         .allmulticast_enable = qede_allmulticast_enable,
2374         .allmulticast_disable = qede_allmulticast_disable,
2375         .dev_stop = qede_dev_stop,
2376         .dev_close = qede_dev_close,
2377         .stats_get = qede_get_stats,
2378         .stats_reset = qede_reset_stats,
2379         .xstats_get = qede_get_xstats,
2380         .xstats_reset = qede_reset_xstats,
2381         .xstats_get_names = qede_get_xstats_names,
2382         .vlan_offload_set = qede_vlan_offload_set,
2383         .vlan_filter_set = qede_vlan_filter_set,
2384         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2385         .rss_hash_update = qede_rss_hash_update,
2386         .rss_hash_conf_get = qede_rss_hash_conf_get,
2387         .reta_update  = qede_rss_reta_update,
2388         .reta_query  = qede_rss_reta_query,
2389         .mtu_set = qede_set_mtu,
2390 };
2391
2392 static void qede_update_pf_params(struct ecore_dev *edev)
2393 {
2394         struct ecore_pf_params pf_params;
2395
2396         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2397         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2398         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2399         qed_ops->common->update_pf_params(edev, &pf_params);
2400 }
2401
2402 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2403 {
2404         struct rte_pci_device *pci_dev;
2405         struct rte_pci_addr pci_addr;
2406         struct qede_dev *adapter;
2407         struct ecore_dev *edev;
2408         struct qed_dev_eth_info dev_info;
2409         struct qed_slowpath_params params;
2410         static bool do_once = true;
2411         uint8_t bulletin_change;
2412         uint8_t vf_mac[ETHER_ADDR_LEN];
2413         uint8_t is_mac_forced;
2414         bool is_mac_exist;
2415         /* Fix up ecore debug level */
2416         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2417         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2418         int rc;
2419
2420         /* Extract key data structures */
2421         adapter = eth_dev->data->dev_private;
2422         edev = &adapter->edev;
2423         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2424         pci_addr = pci_dev->addr;
2425
2426         PMD_INIT_FUNC_TRACE(edev);
2427
2428         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2429                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2430                  eth_dev->data->port_id);
2431
2432         eth_dev->rx_pkt_burst = qede_recv_pkts;
2433         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2434         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2435
2436         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2437                 DP_NOTICE(edev, false,
2438                           "Skipping device init from secondary process\n");
2439                 return 0;
2440         }
2441
2442         rte_eth_copy_pci_info(eth_dev, pci_dev);
2443
2444         /* @DPDK */
2445         edev->vendor_id = pci_dev->id.vendor_id;
2446         edev->device_id = pci_dev->id.device_id;
2447
2448         qed_ops = qed_get_eth_ops();
2449         if (!qed_ops) {
2450                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2451                 return -EINVAL;
2452         }
2453
2454         DP_INFO(edev, "Starting qede probe\n");
2455         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2456                                     dp_level, is_vf);
2457         if (rc != 0) {
2458                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2459                 return -ENODEV;
2460         }
2461         qede_update_pf_params(edev);
2462         rte_intr_callback_register(&pci_dev->intr_handle,
2463                                    qede_interrupt_handler, (void *)eth_dev);
2464         if (rte_intr_enable(&pci_dev->intr_handle)) {
2465                 DP_ERR(edev, "rte_intr_enable() failed\n");
2466                 return -ENODEV;
2467         }
2468
2469         /* Start the Slowpath-process */
2470         memset(&params, 0, sizeof(struct qed_slowpath_params));
2471         params.int_mode = ECORE_INT_MODE_MSIX;
2472         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2473         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2474         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2475         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2476         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2477                 QEDE_PMD_DRV_VER_STR_SIZE);
2478
2479         /* For CMT mode device do periodic polling for slowpath events.
2480          * This is required since uio device uses only one MSI-x
2481          * interrupt vector but we need one for each engine.
2482          */
2483         if (edev->num_hwfns > 1 && IS_PF(edev)) {
2484                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2485                                        qede_poll_sp_sb_cb,
2486                                        (void *)eth_dev);
2487                 if (rc != 0) {
2488                         DP_ERR(edev, "Unable to start periodic"
2489                                      " timer rc %d\n", rc);
2490                         return -EINVAL;
2491                 }
2492         }
2493
2494         rc = qed_ops->common->slowpath_start(edev, &params);
2495         if (rc) {
2496                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2497                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2498                                      (void *)eth_dev);
2499                 return -ENODEV;
2500         }
2501
2502         rc = qed_ops->fill_dev_info(edev, &dev_info);
2503         if (rc) {
2504                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2505                 qed_ops->common->slowpath_stop(edev);
2506                 qed_ops->common->remove(edev);
2507                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2508                                      (void *)eth_dev);
2509                 return -ENODEV;
2510         }
2511
2512         qede_alloc_etherdev(adapter, &dev_info);
2513
2514         adapter->ops->common->set_name(edev, edev->name);
2515
2516         if (!is_vf)
2517                 adapter->dev_info.num_mac_filters =
2518                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2519                                             ECORE_MAC);
2520         else
2521                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2522                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2523
2524         /* Allocate memory for storing MAC addr */
2525         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2526                                         (ETHER_ADDR_LEN *
2527                                         adapter->dev_info.num_mac_filters),
2528                                         RTE_CACHE_LINE_SIZE);
2529
2530         if (eth_dev->data->mac_addrs == NULL) {
2531                 DP_ERR(edev, "Failed to allocate MAC address\n");
2532                 qed_ops->common->slowpath_stop(edev);
2533                 qed_ops->common->remove(edev);
2534                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2535                                      (void *)eth_dev);
2536                 return -ENOMEM;
2537         }
2538
2539         if (!is_vf) {
2540                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2541                                 hw_info.hw_mac_addr,
2542                                 &eth_dev->data->mac_addrs[0]);
2543                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2544                                 &adapter->primary_mac);
2545         } else {
2546                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2547                                        &bulletin_change);
2548                 if (bulletin_change) {
2549                         is_mac_exist =
2550                             ecore_vf_bulletin_get_forced_mac(
2551                                                 ECORE_LEADING_HWFN(edev),
2552                                                 vf_mac,
2553                                                 &is_mac_forced);
2554                         if (is_mac_exist && is_mac_forced) {
2555                                 DP_INFO(edev, "VF macaddr received from PF\n");
2556                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2557                                                 &eth_dev->data->mac_addrs[0]);
2558                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2559                                                 &adapter->primary_mac);
2560                         } else {
2561                                 DP_NOTICE(edev, false,
2562                                           "No VF macaddr assigned\n");
2563                         }
2564                 }
2565         }
2566
2567         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2568
2569         if (do_once) {
2570 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2571                 qede_print_adapter_info(adapter);
2572 #endif
2573                 do_once = false;
2574         }
2575
2576         adapter->num_tx_queues = 0;
2577         adapter->num_rx_queues = 0;
2578         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2579         SLIST_INIT(&adapter->vlan_list_head);
2580         SLIST_INIT(&adapter->uc_list_head);
2581         adapter->mtu = ETHER_MTU;
2582         adapter->new_mtu = ETHER_MTU;
2583         if (!is_vf)
2584                 if (qede_start_vport(adapter, adapter->mtu))
2585                         return -1;
2586
2587         DP_NOTICE(edev, false, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2588                   adapter->primary_mac.addr_bytes[0],
2589                   adapter->primary_mac.addr_bytes[1],
2590                   adapter->primary_mac.addr_bytes[2],
2591                   adapter->primary_mac.addr_bytes[3],
2592                   adapter->primary_mac.addr_bytes[4],
2593                   adapter->primary_mac.addr_bytes[5]);
2594
2595         DP_INFO(edev, "Device initialized\n");
2596
2597         return 0;
2598 }
2599
2600 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2601 {
2602         return qede_common_dev_init(eth_dev, 1);
2603 }
2604
2605 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2606 {
2607         return qede_common_dev_init(eth_dev, 0);
2608 }
2609
2610 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2611 {
2612 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2613         struct qede_dev *qdev = eth_dev->data->dev_private;
2614         struct ecore_dev *edev = &qdev->edev;
2615
2616         PMD_INIT_FUNC_TRACE(edev);
2617 #endif
2618
2619         /* only uninitialize in the primary process */
2620         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2621                 return 0;
2622
2623         /* safe to close dev here */
2624         qede_dev_close(eth_dev);
2625
2626         eth_dev->dev_ops = NULL;
2627         eth_dev->rx_pkt_burst = NULL;
2628         eth_dev->tx_pkt_burst = NULL;
2629
2630         if (eth_dev->data->mac_addrs)
2631                 rte_free(eth_dev->data->mac_addrs);
2632
2633         eth_dev->data->mac_addrs = NULL;
2634
2635         return 0;
2636 }
2637
2638 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2639 {
2640         return qede_dev_common_uninit(eth_dev);
2641 }
2642
2643 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2644 {
2645         return qede_dev_common_uninit(eth_dev);
2646 }
2647
2648 static const struct rte_pci_id pci_id_qedevf_map[] = {
2649 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2650         {
2651                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2652         },
2653         {
2654                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2655         },
2656         {
2657                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2658         },
2659         {.vendor_id = 0,}
2660 };
2661
2662 static const struct rte_pci_id pci_id_qede_map[] = {
2663 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2664         {
2665                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2666         },
2667         {
2668                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2669         },
2670         {
2671                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2672         },
2673         {
2674                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2675         },
2676         {
2677                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2678         },
2679         {
2680                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2681         },
2682         {
2683                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2684         },
2685         {
2686                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2687         },
2688         {
2689                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2690         },
2691         {
2692                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2693         },
2694         {.vendor_id = 0,}
2695 };
2696
2697 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2698         struct rte_pci_device *pci_dev)
2699 {
2700         return rte_eth_dev_pci_generic_probe(pci_dev,
2701                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2702 }
2703
2704 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2705 {
2706         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2707 }
2708
2709 static struct rte_pci_driver rte_qedevf_pmd = {
2710         .id_table = pci_id_qedevf_map,
2711         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2712         .probe = qedevf_eth_dev_pci_probe,
2713         .remove = qedevf_eth_dev_pci_remove,
2714 };
2715
2716 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2717         struct rte_pci_device *pci_dev)
2718 {
2719         return rte_eth_dev_pci_generic_probe(pci_dev,
2720                 sizeof(struct qede_dev), qede_eth_dev_init);
2721 }
2722
2723 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2724 {
2725         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2726 }
2727
2728 static struct rte_pci_driver rte_qede_pmd = {
2729         .id_table = pci_id_qede_map,
2730         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2731         .probe = qede_eth_dev_pci_probe,
2732         .remove = qede_eth_dev_pci_remove,
2733 };
2734
2735 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2736 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2737 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2738 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2739 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2740 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");