drivers/net/qede/qede_ethdev.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_ethdev.h"
  10 #include <rte_alarm.h>
  11 #include <rte_version.h>
  12
  13 /* Globals */
  14 static const struct qed_eth_ops *qed_ops;
  15 static int64_t timer_period = 1;
  16
  17 /* VXLAN tunnel classification mapping */
  18 const struct _qede_vxlan_tunn_types {
  19         uint16_t rte_filter_type;
  20         enum ecore_filter_ucast_type qede_type;
  21         enum ecore_tunn_clss qede_tunn_clss;
  22         const char *string;
  23 } qede_tunn_types[] = {
  24         {
  25                 ETH_TUNNEL_FILTER_OMAC,
  26                 ECORE_FILTER_MAC,
  27                 ECORE_TUNN_CLSS_MAC_VLAN,
  28                 "outer-mac"
  29         },
  30         {
  31                 ETH_TUNNEL_FILTER_TENID,
  32                 ECORE_FILTER_VNI,
  33                 ECORE_TUNN_CLSS_MAC_VNI,
  34                 "vni"
  35         },
  36         {
  37                 ETH_TUNNEL_FILTER_IMAC,
  38                 ECORE_FILTER_INNER_MAC,
  39                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  40                 "inner-mac"
  41         },
  42         {
  43                 ETH_TUNNEL_FILTER_IVLAN,
  44                 ECORE_FILTER_INNER_VLAN,
  45                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  46                 "inner-vlan"
  47         },
  48         {
  49                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID,
  50                 ECORE_FILTER_MAC_VNI_PAIR,
  51                 ECORE_TUNN_CLSS_MAC_VNI,
  52                 "outer-mac and vni"
  53         },
  54         {
  55                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IMAC,
  56                 ECORE_FILTER_UNUSED,
  57                 MAX_ECORE_TUNN_CLSS,
  58                 "outer-mac and inner-mac"
  59         },
  60         {
  61                 ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_IVLAN,
  62                 ECORE_FILTER_UNUSED,
  63                 MAX_ECORE_TUNN_CLSS,
  64                 "outer-mac and inner-vlan"
  65         },
  66         {
  67                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IMAC,
  68                 ECORE_FILTER_INNER_MAC_VNI_PAIR,
  69                 ECORE_TUNN_CLSS_INNER_MAC_VNI,
  70                 "vni and inner-mac",
  71         },
  72         {
  73                 ETH_TUNNEL_FILTER_TENID | ETH_TUNNEL_FILTER_IVLAN,
  74                 ECORE_FILTER_UNUSED,
  75                 MAX_ECORE_TUNN_CLSS,
  76                 "vni and inner-vlan",
  77         },
  78         {
  79                 ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
  80                 ECORE_FILTER_INNER_PAIR,
  81                 ECORE_TUNN_CLSS_INNER_MAC_VLAN,
  82                 "inner-mac and inner-vlan",
  83         },
  84         {
  85                 ETH_TUNNEL_FILTER_OIP,
  86                 ECORE_FILTER_UNUSED,
  87                 MAX_ECORE_TUNN_CLSS,
  88                 "outer-IP"
  89         },
  90         {
  91                 ETH_TUNNEL_FILTER_IIP,
  92                 ECORE_FILTER_UNUSED,
  93                 MAX_ECORE_TUNN_CLSS,
  94                 "inner-IP"
  95         },
  96         {
  97                 RTE_TUNNEL_FILTER_IMAC_IVLAN,
  98                 ECORE_FILTER_UNUSED,
  99                 MAX_ECORE_TUNN_CLSS,
 100                 "IMAC_IVLAN"
 101         },
 102         {
 103                 RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID,
 104                 ECORE_FILTER_UNUSED,
 105                 MAX_ECORE_TUNN_CLSS,
 106                 "IMAC_IVLAN_TENID"
 107         },
 108         {
 109                 RTE_TUNNEL_FILTER_IMAC_TENID,
 110                 ECORE_FILTER_UNUSED,
 111                 MAX_ECORE_TUNN_CLSS,
 112                 "IMAC_TENID"
 113         },
 114         {
 115                 RTE_TUNNEL_FILTER_OMAC_TENID_IMAC,
 116                 ECORE_FILTER_UNUSED,
 117                 MAX_ECORE_TUNN_CLSS,
 118                 "OMAC_TENID_IMAC"
 119         },
 120 };
 121
 122 struct rte_qede_xstats_name_off {
 123         char name[RTE_ETH_XSTATS_NAME_SIZE];
 124         uint64_t offset;
 125 };
 126
 127 static const struct rte_qede_xstats_name_off qede_xstats_strings[] = {
 128         {"rx_unicast_bytes",
 129                 offsetof(struct ecore_eth_stats_common, rx_ucast_bytes)},
 130         {"rx_multicast_bytes",
 131                 offsetof(struct ecore_eth_stats_common, rx_mcast_bytes)},
 132         {"rx_broadcast_bytes",
 133                 offsetof(struct ecore_eth_stats_common, rx_bcast_bytes)},
 134         {"rx_unicast_packets",
 135                 offsetof(struct ecore_eth_stats_common, rx_ucast_pkts)},
 136         {"rx_multicast_packets",
 137                 offsetof(struct ecore_eth_stats_common, rx_mcast_pkts)},
 138         {"rx_broadcast_packets",
 139                 offsetof(struct ecore_eth_stats_common, rx_bcast_pkts)},
 140
 141         {"tx_unicast_bytes",
 142                 offsetof(struct ecore_eth_stats_common, tx_ucast_bytes)},
 143         {"tx_multicast_bytes",
 144                 offsetof(struct ecore_eth_stats_common, tx_mcast_bytes)},
 145         {"tx_broadcast_bytes",
 146                 offsetof(struct ecore_eth_stats_common, tx_bcast_bytes)},
 147         {"tx_unicast_packets",
 148                 offsetof(struct ecore_eth_stats_common, tx_ucast_pkts)},
 149         {"tx_multicast_packets",
 150                 offsetof(struct ecore_eth_stats_common, tx_mcast_pkts)},
 151         {"tx_broadcast_packets",
 152                 offsetof(struct ecore_eth_stats_common, tx_bcast_pkts)},
 153
 154         {"rx_64_byte_packets",
 155                 offsetof(struct ecore_eth_stats_common, rx_64_byte_packets)},
 156         {"rx_65_to_127_byte_packets",
 157                 offsetof(struct ecore_eth_stats_common,
 158                          rx_65_to_127_byte_packets)},
 159         {"rx_128_to_255_byte_packets",
 160                 offsetof(struct ecore_eth_stats_common,
 161                          rx_128_to_255_byte_packets)},
 162         {"rx_256_to_511_byte_packets",
 163                 offsetof(struct ecore_eth_stats_common,
 164                          rx_256_to_511_byte_packets)},
 165         {"rx_512_to_1023_byte_packets",
 166                 offsetof(struct ecore_eth_stats_common,
 167                          rx_512_to_1023_byte_packets)},
 168         {"rx_1024_to_1518_byte_packets",
 169                 offsetof(struct ecore_eth_stats_common,
 170                          rx_1024_to_1518_byte_packets)},
 171         {"tx_64_byte_packets",
 172                 offsetof(struct ecore_eth_stats_common, tx_64_byte_packets)},
 173         {"tx_65_to_127_byte_packets",
 174                 offsetof(struct ecore_eth_stats_common,
 175                          tx_65_to_127_byte_packets)},
 176         {"tx_128_to_255_byte_packets",
 177                 offsetof(struct ecore_eth_stats_common,
 178                          tx_128_to_255_byte_packets)},
 179         {"tx_256_to_511_byte_packets",
 180                 offsetof(struct ecore_eth_stats_common,
 181                          tx_256_to_511_byte_packets)},
 182         {"tx_512_to_1023_byte_packets",
 183                 offsetof(struct ecore_eth_stats_common,
 184                          tx_512_to_1023_byte_packets)},
 185         {"tx_1024_to_1518_byte_packets",
 186                 offsetof(struct ecore_eth_stats_common,
 187                          tx_1024_to_1518_byte_packets)},
 188
 189         {"rx_mac_crtl_frames",
 190                 offsetof(struct ecore_eth_stats_common, rx_mac_crtl_frames)},
 191         {"tx_mac_control_frames",
 192                 offsetof(struct ecore_eth_stats_common, tx_mac_ctrl_frames)},
 193         {"rx_pause_frames",
 194                 offsetof(struct ecore_eth_stats_common, rx_pause_frames)},
 195         {"tx_pause_frames",
 196                 offsetof(struct ecore_eth_stats_common, tx_pause_frames)},
 197         {"rx_priority_flow_control_frames",
 198                 offsetof(struct ecore_eth_stats_common, rx_pfc_frames)},
 199         {"tx_priority_flow_control_frames",
 200                 offsetof(struct ecore_eth_stats_common, tx_pfc_frames)},
 201
 202         {"rx_crc_errors",
 203                 offsetof(struct ecore_eth_stats_common, rx_crc_errors)},
 204         {"rx_align_errors",
 205                 offsetof(struct ecore_eth_stats_common, rx_align_errors)},
 206         {"rx_carrier_errors",
 207                 offsetof(struct ecore_eth_stats_common, rx_carrier_errors)},
 208         {"rx_oversize_packet_errors",
 209                 offsetof(struct ecore_eth_stats_common, rx_oversize_packets)},
 210         {"rx_jabber_errors",
 211                 offsetof(struct ecore_eth_stats_common, rx_jabbers)},
 212         {"rx_undersize_packet_errors",
 213                 offsetof(struct ecore_eth_stats_common, rx_undersize_packets)},
 214         {"rx_fragments", offsetof(struct ecore_eth_stats_common, rx_fragments)},
 215         {"rx_host_buffer_not_available",
 216                 offsetof(struct ecore_eth_stats_common, no_buff_discards)},
 217         /* Number of packets discarded because they are bigger than MTU */
 218         {"rx_packet_too_big_discards",
 219                 offsetof(struct ecore_eth_stats_common,
 220                          packet_too_big_discard)},
 221         {"rx_ttl_zero_discards",
 222                 offsetof(struct ecore_eth_stats_common, ttl0_discard)},
 223         {"rx_multi_function_tag_filter_discards",
 224                 offsetof(struct ecore_eth_stats_common, mftag_filter_discards)},
 225         {"rx_mac_filter_discards",
 226                 offsetof(struct ecore_eth_stats_common, mac_filter_discards)},
 227         {"rx_hw_buffer_truncates",
 228                 offsetof(struct ecore_eth_stats_common, brb_truncates)},
 229         {"rx_hw_buffer_discards",
 230                 offsetof(struct ecore_eth_stats_common, brb_discards)},
 231         {"tx_error_drop_packets",
 232                 offsetof(struct ecore_eth_stats_common, tx_err_drop_pkts)},
 233
 234         {"rx_mac_bytes", offsetof(struct ecore_eth_stats_common, rx_mac_bytes)},
 235         {"rx_mac_unicast_packets",
 236                 offsetof(struct ecore_eth_stats_common, rx_mac_uc_packets)},
 237         {"rx_mac_multicast_packets",
 238                 offsetof(struct ecore_eth_stats_common, rx_mac_mc_packets)},
 239         {"rx_mac_broadcast_packets",
 240                 offsetof(struct ecore_eth_stats_common, rx_mac_bc_packets)},
 241         {"rx_mac_frames_ok",
 242                 offsetof(struct ecore_eth_stats_common, rx_mac_frames_ok)},
 243         {"tx_mac_bytes", offsetof(struct ecore_eth_stats_common, tx_mac_bytes)},
 244         {"tx_mac_unicast_packets",
 245                 offsetof(struct ecore_eth_stats_common, tx_mac_uc_packets)},
 246         {"tx_mac_multicast_packets",
 247                 offsetof(struct ecore_eth_stats_common, tx_mac_mc_packets)},
 248         {"tx_mac_broadcast_packets",
 249                 offsetof(struct ecore_eth_stats_common, tx_mac_bc_packets)},
 250
 251         {"lro_coalesced_packets",
 252                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_pkts)},
 253         {"lro_coalesced_events",
 254                 offsetof(struct ecore_eth_stats_common, tpa_coalesced_events)},
 255         {"lro_aborts_num",
 256                 offsetof(struct ecore_eth_stats_common, tpa_aborts_num)},
 257         {"lro_not_coalesced_packets",
 258                 offsetof(struct ecore_eth_stats_common,
 259                          tpa_not_coalesced_pkts)},
 260         {"lro_coalesced_bytes",
 261                 offsetof(struct ecore_eth_stats_common,
 262                          tpa_coalesced_bytes)},
 263 };
 264
 265 static const struct rte_qede_xstats_name_off qede_bb_xstats_strings[] = {
 266         {"rx_1519_to_1522_byte_packets",
 267                 offsetof(struct ecore_eth_stats, bb) +
 268                 offsetof(struct ecore_eth_stats_bb,
 269                          rx_1519_to_1522_byte_packets)},
 270         {"rx_1519_to_2047_byte_packets",
 271                 offsetof(struct ecore_eth_stats, bb) +
 272                 offsetof(struct ecore_eth_stats_bb,
 273                          rx_1519_to_2047_byte_packets)},
 274         {"rx_2048_to_4095_byte_packets",
 275                 offsetof(struct ecore_eth_stats, bb) +
 276                 offsetof(struct ecore_eth_stats_bb,
 277                          rx_2048_to_4095_byte_packets)},
 278         {"rx_4096_to_9216_byte_packets",
 279                 offsetof(struct ecore_eth_stats, bb) +
 280                 offsetof(struct ecore_eth_stats_bb,
 281                          rx_4096_to_9216_byte_packets)},
 282         {"rx_9217_to_16383_byte_packets",
 283                 offsetof(struct ecore_eth_stats, bb) +
 284                 offsetof(struct ecore_eth_stats_bb,
 285                          rx_9217_to_16383_byte_packets)},
 286
 287         {"tx_1519_to_2047_byte_packets",
 288                 offsetof(struct ecore_eth_stats, bb) +
 289                 offsetof(struct ecore_eth_stats_bb,
 290                          tx_1519_to_2047_byte_packets)},
 291         {"tx_2048_to_4095_byte_packets",
 292                 offsetof(struct ecore_eth_stats, bb) +
 293                 offsetof(struct ecore_eth_stats_bb,
 294                          tx_2048_to_4095_byte_packets)},
 295         {"tx_4096_to_9216_byte_packets",
 296                 offsetof(struct ecore_eth_stats, bb) +
 297                 offsetof(struct ecore_eth_stats_bb,
 298                          tx_4096_to_9216_byte_packets)},
 299         {"tx_9217_to_16383_byte_packets",
 300                 offsetof(struct ecore_eth_stats, bb) +
 301                 offsetof(struct ecore_eth_stats_bb,
 302                          tx_9217_to_16383_byte_packets)},
 303
 304         {"tx_lpi_entry_count",
 305                 offsetof(struct ecore_eth_stats, bb) +
 306                 offsetof(struct ecore_eth_stats_bb, tx_lpi_entry_count)},
 307         {"tx_total_collisions",
 308                 offsetof(struct ecore_eth_stats, bb) +
 309                 offsetof(struct ecore_eth_stats_bb, tx_total_collisions)},
 310 };
 311
 312 static const struct rte_qede_xstats_name_off qede_ah_xstats_strings[] = {
 313         {"rx_1519_to_max_byte_packets",
 314                 offsetof(struct ecore_eth_stats, ah) +
 315                 offsetof(struct ecore_eth_stats_ah,
 316                          rx_1519_to_max_byte_packets)},
 317         {"tx_1519_to_max_byte_packets",
 318                 offsetof(struct ecore_eth_stats, ah) +
 319                 offsetof(struct ecore_eth_stats_ah,
 320                          tx_1519_to_max_byte_packets)},
 321 };
 322
 323 static const struct rte_qede_xstats_name_off qede_rxq_xstats_strings[] = {
 324         {"rx_q_segments",
 325                 offsetof(struct qede_rx_queue, rx_segs)},
 326         {"rx_q_hw_errors",
 327                 offsetof(struct qede_rx_queue, rx_hw_errors)},
 328         {"rx_q_allocation_errors",
 329                 offsetof(struct qede_rx_queue, rx_alloc_errors)}
 330 };
 331
 332 static void qede_interrupt_action(struct ecore_hwfn *p_hwfn)
 333 {
 334         ecore_int_sp_dpc((osal_int_ptr_t)(p_hwfn));
 335 }
 336
 337 static void
 338 qede_interrupt_handler(void *param)
 339 {
 340         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
 341         struct qede_dev *qdev = eth_dev->data->dev_private;
 342         struct ecore_dev *edev = &qdev->edev;
 343
 344         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
 345         if (rte_intr_enable(eth_dev->intr_handle))
 346                 DP_ERR(edev, "rte_intr_enable failed\n");
 347 }
 348
 349 static void
 350 qede_alloc_etherdev(struct qede_dev *qdev, struct qed_dev_eth_info *info)
 351 {
 352         rte_memcpy(&qdev->dev_info, info, sizeof(*info));
 353         qdev->ops = qed_ops;
 354 }
 355
 356 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
 357 static void qede_print_adapter_info(struct qede_dev *qdev)
 358 {
 359         struct ecore_dev *edev = &qdev->edev;
 360         struct qed_dev_info *info = &qdev->dev_info.common;
 361         static char drv_ver[QEDE_PMD_DRV_VER_STR_SIZE];
 362         static char ver_str[QEDE_PMD_DRV_VER_STR_SIZE];
 363
 364         DP_INFO(edev, "*********************************\n");
 365         DP_INFO(edev, " DPDK version:%s\n", rte_version());
 366         DP_INFO(edev, " Chip details : %s %c%d\n",
 367                   ECORE_IS_BB(edev) ? "BB" : "AH",
 368                   'A' + edev->chip_rev,
 369                   (int)edev->chip_metal);
 370         snprintf(ver_str, QEDE_PMD_DRV_VER_STR_SIZE, "%d.%d.%d.%d",
 371                  info->fw_major, info->fw_minor, info->fw_rev, info->fw_eng);
 372         snprintf(drv_ver, QEDE_PMD_DRV_VER_STR_SIZE, "%s_%s",
 373                  ver_str, QEDE_PMD_VERSION);
 374         DP_INFO(edev, " Driver version : %s\n", drv_ver);
 375         DP_INFO(edev, " Firmware version : %s\n", ver_str);
 376
 377         snprintf(ver_str, MCP_DRV_VER_STR_SIZE,
 378                  "%d.%d.%d.%d",
 379                 (info->mfw_rev >> 24) & 0xff,
 380                 (info->mfw_rev >> 16) & 0xff,
 381                 (info->mfw_rev >> 8) & 0xff, (info->mfw_rev) & 0xff);
 382         DP_INFO(edev, " Management Firmware version : %s\n", ver_str);
 383         DP_INFO(edev, " Firmware file : %s\n", fw_file);
 384         DP_INFO(edev, "*********************************\n");
 385 }
 386 #endif
 387
 388 static int
 389 qede_start_vport(struct qede_dev *qdev, uint16_t mtu)
 390 {
 391         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 392         struct ecore_sp_vport_start_params params;
 393         struct ecore_hwfn *p_hwfn;
 394         int rc;
 395         int i;
 396
 397         memset(&params, 0, sizeof(params));
 398         params.vport_id = 0;
 399         params.mtu = mtu;
 400         /* @DPDK - Disable FW placement */
 401         params.zero_placement_offset = 1;
 402         for_each_hwfn(edev, i) {
 403                 p_hwfn = &edev->hwfns[i];
 404                 params.concrete_fid = p_hwfn->hw_info.concrete_fid;
 405                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 406                 rc = ecore_sp_vport_start(p_hwfn, &params);
 407                 if (rc != ECORE_SUCCESS) {
 408                         DP_ERR(edev, "Start V-PORT failed %d\n", rc);
 409                         return rc;
 410                 }
 411         }
 412         ecore_reset_vport_stats(edev);
 413         DP_INFO(edev, "VPORT started with MTU = %u\n", mtu);
 414
 415         return 0;
 416 }
 417
 418 static int
 419 qede_stop_vport(struct ecore_dev *edev)
 420 {
 421         struct ecore_hwfn *p_hwfn;
 422         uint8_t vport_id;
 423         int rc;
 424         int i;
 425
 426         vport_id = 0;
 427         for_each_hwfn(edev, i) {
 428                 p_hwfn = &edev->hwfns[i];
 429                 rc = ecore_sp_vport_stop(p_hwfn, p_hwfn->hw_info.opaque_fid,
 430                                          vport_id);
 431                 if (rc != ECORE_SUCCESS) {
 432                         DP_ERR(edev, "Stop V-PORT failed rc = %d\n", rc);
 433                         return rc;
 434                 }
 435         }
 436
 437         return 0;
 438 }
 439
 440 /* Activate or deactivate vport via vport-update */
 441 int qede_activate_vport(struct rte_eth_dev *eth_dev, bool flg)
 442 {
 443         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 444         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 445         struct ecore_sp_vport_update_params params;
 446         struct ecore_hwfn *p_hwfn;
 447         uint8_t i;
 448         int rc = -1;
 449
 450         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 451         params.vport_id = 0;
 452         params.update_vport_active_rx_flg = 1;
 453         params.update_vport_active_tx_flg = 1;
 454         params.vport_active_rx_flg = flg;
 455         params.vport_active_tx_flg = flg;
 456 #ifndef RTE_LIBRTE_QEDE_VF_TX_SWITCH
 457         if (IS_VF(edev)) {
 458                 params.update_tx_switching_flg = 1;
 459                 params.tx_switching_flg = !flg;
 460         }
 461 #endif
 462         for_each_hwfn(edev, i) {
 463                 p_hwfn = &edev->hwfns[i];
 464                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 465                 rc = ecore_sp_vport_update(p_hwfn, &params,
 466                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 467                 if (rc != ECORE_SUCCESS) {
 468                         DP_ERR(edev, "Failed to update vport\n");
 469                         break;
 470                 }
 471         }
 472         DP_INFO(edev, "vport %s VF tx-switch %s\n", flg ? "activated" : "deactivated",
 473                         params.tx_switching_flg ? "enabled" : "disabled");
 474         return rc;
 475 }
 476
 477 static void
 478 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 479                            uint16_t mtu, bool enable)
 480 {
 481         /* Enable LRO in split mode */
 482         sge_tpa_params->tpa_ipv4_en_flg = enable;
 483         sge_tpa_params->tpa_ipv6_en_flg = enable;
 484         sge_tpa_params->tpa_ipv4_tunn_en_flg = false;
 485         sge_tpa_params->tpa_ipv6_tunn_en_flg = false;
 486         /* set if tpa enable changes */
 487         sge_tpa_params->update_tpa_en_flg = 1;
 488         /* set if tpa parameters should be handled */
 489         sge_tpa_params->update_tpa_param_flg = enable;
 490
 491         sge_tpa_params->max_buffers_per_cqe = 20;
 492         /* Enable TPA in split mode. In this mode each TPA segment
 493          * starts on the new BD, so there is one BD per segment.
 494          */
 495         sge_tpa_params->tpa_pkt_split_flg = 1;
 496         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 497         sge_tpa_params->tpa_gro_consistent_flg = 0;
 498         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 499         sge_tpa_params->tpa_max_size = 0x7FFF;
 500         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 501         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 502 }
 503
 504 /* Enable/disable LRO via vport-update */
 505 int qede_enable_tpa(struct rte_eth_dev *eth_dev, bool flg)
 506 {
 507         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 508         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 509         struct ecore_sp_vport_update_params params;
 510         struct ecore_sge_tpa_params tpa_params;
 511         struct ecore_hwfn *p_hwfn;
 512         int rc;
 513         int i;
 514
 515         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 516         memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 517         qede_update_sge_tpa_params(&tpa_params, qdev->mtu, flg);
 518         params.vport_id = 0;
 519         params.sge_tpa_params = &tpa_params;
 520         for_each_hwfn(edev, i) {
 521                 p_hwfn = &edev->hwfns[i];
 522                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 523                 rc = ecore_sp_vport_update(p_hwfn, &params,
 524                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 525                 if (rc != ECORE_SUCCESS) {
 526                         DP_ERR(edev, "Failed to update LRO\n");
 527                         return -1;
 528                 }
 529         }
 530         qdev->enable_lro = flg;
 531         DP_INFO(edev, "LRO is %s\n", flg ? "enabled" : "disabled");
 532
 533         return 0;
 534 }
 535
 536 /* Update MTU via vport-update without doing port restart.
 537  * The vport must be deactivated before calling this API.
 538  */
 539 int qede_update_mtu(struct rte_eth_dev *eth_dev, uint16_t mtu)
 540 {
 541         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 542         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 543         struct ecore_sp_vport_update_params params;
 544         struct ecore_hwfn *p_hwfn;
 545         int rc;
 546         int i;
 547
 548         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 549         params.vport_id = 0;
 550         params.mtu = mtu;
 551         params.vport_id = 0;
 552         for_each_hwfn(edev, i) {
 553                 p_hwfn = &edev->hwfns[i];
 554                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 555                 rc = ecore_sp_vport_update(p_hwfn, &params,
 556                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 557                 if (rc != ECORE_SUCCESS) {
 558                         DP_ERR(edev, "Failed to update MTU\n");
 559                         return -1;
 560                 }
 561         }
 562         DP_INFO(edev, "MTU updated to %u\n", mtu);
 563
 564         return 0;
 565 }
 566
 567 static void qede_set_ucast_cmn_params(struct ecore_filter_ucast *ucast)
 568 {
 569         memset(ucast, 0, sizeof(struct ecore_filter_ucast));
 570         ucast->is_rx_filter = true;
 571         ucast->is_tx_filter = true;
 572         /* ucast->assert_on_error = true; - For debug */
 573 }
 574
 575 static int
 576 qed_configure_filter_rx_mode(struct rte_eth_dev *eth_dev,
 577                              enum qed_filter_rx_mode_type type)
 578 {
 579         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 580         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 581         struct ecore_filter_accept_flags flags;
 582
 583         memset(&flags, 0, sizeof(flags));
 584
 585         flags.update_rx_mode_config = 1;
 586         flags.update_tx_mode_config = 1;
 587         flags.rx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 588                 ECORE_ACCEPT_MCAST_MATCHED |
 589                 ECORE_ACCEPT_BCAST;
 590
 591         flags.tx_accept_filter = ECORE_ACCEPT_UCAST_MATCHED |
 592                 ECORE_ACCEPT_MCAST_MATCHED |
 593                 ECORE_ACCEPT_BCAST;
 594
 595         if (type == QED_FILTER_RX_MODE_TYPE_PROMISC) {
 596                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 597                 if (IS_VF(edev)) {
 598                         flags.tx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED;
 599                         DP_INFO(edev, "Enabling Tx unmatched flag for VF\n");
 600                 }
 601         } else if (type == QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC) {
 602                 flags.rx_accept_filter |= ECORE_ACCEPT_MCAST_UNMATCHED;
 603         } else if (type == (QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC |
 604                                 QED_FILTER_RX_MODE_TYPE_PROMISC)) {
 605                 flags.rx_accept_filter |= ECORE_ACCEPT_UCAST_UNMATCHED |
 606                         ECORE_ACCEPT_MCAST_UNMATCHED;
 607         }
 608
 609         return ecore_filter_accept_cmd(edev, 0, flags, false, false,
 610                         ECORE_SPQ_MODE_CB, NULL);
 611 }
 612
 613 static int
 614 qede_vxlan_enable(struct rte_eth_dev *eth_dev, uint8_t clss,
 615                   bool enable, bool mask)
 616 {
 617         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 618         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 619         enum _ecore_status_t rc = ECORE_INVAL;
 620         struct ecore_ptt *p_ptt;
 621         struct ecore_tunnel_info tunn;
 622         struct ecore_hwfn *p_hwfn;
 623         int i;
 624
 625         memset(&tunn, 0, sizeof(struct ecore_tunnel_info));
 626         tunn.vxlan.b_update_mode = enable;
 627         tunn.vxlan.b_mode_enabled = mask;
 628         tunn.b_update_rx_cls = true;
 629         tunn.b_update_tx_cls = true;
 630         tunn.vxlan.tun_cls = clss;
 631
 632         for_each_hwfn(edev, i) {
 633                 p_hwfn = &edev->hwfns[i];
 634                 p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
 635                 rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt,
 636                                 &tunn, ECORE_SPQ_MODE_CB, NULL);
 637                 if (rc != ECORE_SUCCESS) {
 638                         DP_ERR(edev, "Failed to update tunn_clss %u\n",
 639                                         tunn.vxlan.tun_cls);
 640                         if (IS_PF(edev))
 641                                 ecore_ptt_release(p_hwfn, p_ptt);
 642                         break;
 643                 }
 644         }
 645
 646         if (rc == ECORE_SUCCESS) {
 647                 qdev->vxlan.enable = enable;
 648                 qdev->vxlan.udp_port = (enable) ? QEDE_VXLAN_DEF_PORT : 0;
 649                 DP_INFO(edev, "vxlan is %s\n", enable ? "enabled" : "disabled");
 650         }
 651
 652         return rc;
 653 }
 654
 655 static int
 656 qede_ucast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 657                   bool add)
 658 {
 659         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 660         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 661         struct qede_ucast_entry *tmp = NULL;
 662         struct qede_ucast_entry *u;
 663         struct ether_addr *mac_addr;
 664
 665         mac_addr  = (struct ether_addr *)ucast->mac;
 666         if (add) {
 667                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 668                         if ((memcmp(mac_addr, &tmp->mac,
 669                                     ETHER_ADDR_LEN) == 0) &&
 670                              ucast->vni == tmp->vni &&
 671                              ucast->vlan == tmp->vlan) {
 672                                 DP_ERR(edev, "Unicast MAC is already added"
 673                                        " with vlan = %u, vni = %u\n",
 674                                        ucast->vlan,  ucast->vni);
 675                                         return -EEXIST;
 676                         }
 677                 }
 678                 u = rte_malloc(NULL, sizeof(struct qede_ucast_entry),
 679                                RTE_CACHE_LINE_SIZE);
 680                 if (!u) {
 681                         DP_ERR(edev, "Did not allocate memory for ucast\n");
 682                         return -ENOMEM;
 683                 }
 684                 ether_addr_copy(mac_addr, &u->mac);
 685                 u->vlan = ucast->vlan;
 686                 u->vni = ucast->vni;
 687                 SLIST_INSERT_HEAD(&qdev->uc_list_head, u, list);
 688                 qdev->num_uc_addr++;
 689         } else {
 690                 SLIST_FOREACH(tmp, &qdev->uc_list_head, list) {
 691                         if ((memcmp(mac_addr, &tmp->mac,
 692                                     ETHER_ADDR_LEN) == 0) &&
 693                             ucast->vlan == tmp->vlan      &&
 694                             ucast->vni == tmp->vni)
 695                         break;
 696                 }
 697                 if (tmp == NULL) {
 698                         DP_INFO(edev, "Unicast MAC is not found\n");
 699                         return -EINVAL;
 700                 }
 701                 SLIST_REMOVE(&qdev->uc_list_head, tmp, qede_ucast_entry, list);
 702                 qdev->num_uc_addr--;
 703         }
 704
 705         return 0;
 706 }
 707
 708 static int
 709 qede_mcast_filter(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *mcast,
 710                   bool add)
 711 {
 712         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 713         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 714         struct ether_addr *mac_addr;
 715         struct qede_mcast_entry *tmp = NULL;
 716         struct qede_mcast_entry *m;
 717
 718         mac_addr  = (struct ether_addr *)mcast->mac;
 719         if (add) {
 720                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 721                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0) {
 722                                 DP_ERR(edev,
 723                                         "Multicast MAC is already added\n");
 724                                 return -EEXIST;
 725                         }
 726                 }
 727                 m = rte_malloc(NULL, sizeof(struct qede_mcast_entry),
 728                         RTE_CACHE_LINE_SIZE);
 729                 if (!m) {
 730                         DP_ERR(edev,
 731                                 "Did not allocate memory for mcast\n");
 732                         return -ENOMEM;
 733                 }
 734                 ether_addr_copy(mac_addr, &m->mac);
 735                 SLIST_INSERT_HEAD(&qdev->mc_list_head, m, list);
 736                 qdev->num_mc_addr++;
 737         } else {
 738                 SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 739                         if (memcmp(mac_addr, &tmp->mac, ETHER_ADDR_LEN) == 0)
 740                                 break;
 741                 }
 742                 if (tmp == NULL) {
 743                         DP_INFO(edev, "Multicast mac is not found\n");
 744                         return -EINVAL;
 745                 }
 746                 SLIST_REMOVE(&qdev->mc_list_head, tmp,
 747                              qede_mcast_entry, list);
 748                 qdev->num_mc_addr--;
 749         }
 750
 751         return 0;
 752 }
 753
 754 static enum _ecore_status_t
 755 qede_mac_int_ops(struct rte_eth_dev *eth_dev, struct ecore_filter_ucast *ucast,
 756                  bool add)
 757 {
 758         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 759         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 760         enum _ecore_status_t rc;
 761         struct ecore_filter_mcast mcast;
 762         struct qede_mcast_entry *tmp;
 763         uint16_t j = 0;
 764
 765         /* Multicast */
 766         if (is_multicast_ether_addr((struct ether_addr *)ucast->mac)) {
 767                 if (add) {
 768                         if (qdev->num_mc_addr >= ECORE_MAX_MC_ADDRS) {
 769                                 DP_ERR(edev,
 770                                        "Mcast filter table limit exceeded, "
 771                                        "Please enable mcast promisc mode\n");
 772                                 return -ECORE_INVAL;
 773                         }
 774                 }
 775                 rc = qede_mcast_filter(eth_dev, ucast, add);
 776                 if (rc == 0) {
 777                         DP_INFO(edev, "num_mc_addrs = %u\n", qdev->num_mc_addr);
 778                         memset(&mcast, 0, sizeof(mcast));
 779                         mcast.num_mc_addrs = qdev->num_mc_addr;
 780                         mcast.opcode = ECORE_FILTER_ADD;
 781                         SLIST_FOREACH(tmp, &qdev->mc_list_head, list) {
 782                                 ether_addr_copy(&tmp->mac,
 783                                         (struct ether_addr *)&mcast.mac[j]);
 784                                 j++;
 785                         }
 786                         rc = ecore_filter_mcast_cmd(edev, &mcast,
 787                                                     ECORE_SPQ_MODE_CB, NULL);
 788                 }
 789                 if (rc != ECORE_SUCCESS) {
 790                         DP_ERR(edev, "Failed to add multicast filter"
 791                                " rc = %d, op = %d\n", rc, add);
 792                 }
 793         } else { /* Unicast */
 794                 if (add) {
 795                         if (qdev->num_uc_addr >=
 796                             qdev->dev_info.num_mac_filters) {
 797                                 DP_ERR(edev,
 798                                        "Ucast filter table limit exceeded,"
 799                                        " Please enable promisc mode\n");
 800                                 return -ECORE_INVAL;
 801                         }
 802                 }
 803                 rc = qede_ucast_filter(eth_dev, ucast, add);
 804                 if (rc == 0)
 805                         rc = ecore_filter_ucast_cmd(edev, ucast,
 806                                                     ECORE_SPQ_MODE_CB, NULL);
 807                 if (rc != ECORE_SUCCESS) {
 808                         DP_ERR(edev, "MAC filter failed, rc = %d, op = %d\n",
 809                                rc, add);
 810                 }
 811         }
 812
 813         return rc;
 814 }
 815
 816 static int
 817 qede_mac_addr_add(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr,
 818                   __rte_unused uint32_t index, __rte_unused uint32_t pool)
 819 {
 820         struct ecore_filter_ucast ucast;
 821         int re;
 822
 823         qede_set_ucast_cmn_params(&ucast);
 824         ucast.type = ECORE_FILTER_MAC;
 825         ether_addr_copy(mac_addr, (struct ether_addr *)&ucast.mac);
 826         re = (int)qede_mac_int_ops(eth_dev, &ucast, 1);
 827         return re;
 828 }
 829
 830 static void
 831 qede_mac_addr_remove(struct rte_eth_dev *eth_dev, uint32_t index)
 832 {
 833         struct qede_dev *qdev = eth_dev->data->dev_private;
 834         struct ecore_dev *edev = &qdev->edev;
 835         struct ecore_filter_ucast ucast;
 836
 837         PMD_INIT_FUNC_TRACE(edev);
 838
 839         if (index >= qdev->dev_info.num_mac_filters) {
 840                 DP_ERR(edev, "Index %u is above MAC filter limit %u\n",
 841                        index, qdev->dev_info.num_mac_filters);
 842                 return;
 843         }
 844
 845         qede_set_ucast_cmn_params(&ucast);
 846         ucast.opcode = ECORE_FILTER_REMOVE;
 847         ucast.type = ECORE_FILTER_MAC;
 848
 849         /* Use the index maintained by rte */
 850         ether_addr_copy(&eth_dev->data->mac_addrs[index],
 851                         (struct ether_addr *)&ucast.mac);
 852
 853         ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB, NULL);
 854 }
 855
 856 static void
 857 qede_mac_addr_set(struct rte_eth_dev *eth_dev, struct ether_addr *mac_addr)
 858 {
 859         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 860         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 861
 862         if (IS_VF(edev) && !ecore_vf_check_mac(ECORE_LEADING_HWFN(edev),
 863                                                mac_addr->addr_bytes)) {
 864                 DP_ERR(edev, "Setting MAC address is not allowed\n");
 865                 ether_addr_copy(&qdev->primary_mac,
 866                                 &eth_dev->data->mac_addrs[0]);
 867                 return;
 868         }
 869
 870         qede_mac_addr_add(eth_dev, mac_addr, 0, 0);
 871 }
 872
 873 static void qede_config_accept_any_vlan(struct qede_dev *qdev, bool flg)
 874 {
 875         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 876         struct ecore_sp_vport_update_params params;
 877         struct ecore_hwfn *p_hwfn;
 878         uint8_t i;
 879         int rc;
 880
 881         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 882         params.vport_id = 0;
 883         params.update_accept_any_vlan_flg = 1;
 884         params.accept_any_vlan = flg;
 885         for_each_hwfn(edev, i) {
 886                 p_hwfn = &edev->hwfns[i];
 887                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 888                 rc = ecore_sp_vport_update(p_hwfn, &params,
 889                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 890                 if (rc != ECORE_SUCCESS) {
 891                         DP_ERR(edev, "Failed to configure accept-any-vlan\n");
 892                         return;
 893                 }
 894         }
 895
 896         DP_INFO(edev, "%s accept-any-vlan\n", flg ? "enabled" : "disabled");
 897 }
 898
 899 static int qede_vlan_stripping(struct rte_eth_dev *eth_dev, bool flg)
 900 {
 901         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 902         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 903         struct ecore_sp_vport_update_params params;
 904         struct ecore_hwfn *p_hwfn;
 905         uint8_t i;
 906         int rc;
 907
 908         memset(&params, 0, sizeof(struct ecore_sp_vport_update_params));
 909         params.vport_id = 0;
 910         params.update_inner_vlan_removal_flg = 1;
 911         params.inner_vlan_removal_flg = flg;
 912         for_each_hwfn(edev, i) {
 913                 p_hwfn = &edev->hwfns[i];
 914                 params.opaque_fid = p_hwfn->hw_info.opaque_fid;
 915                 rc = ecore_sp_vport_update(p_hwfn, &params,
 916                                 ECORE_SPQ_MODE_EBLOCK, NULL);
 917                 if (rc != ECORE_SUCCESS) {
 918                         DP_ERR(edev, "Failed to update vport\n");
 919                         return -1;
 920                 }
 921         }
 922
 923         DP_INFO(edev, "VLAN stripping %s\n", flg ? "enabled" : "disabled");
 924         return 0;
 925 }
 926
 927 static int qede_vlan_filter_set(struct rte_eth_dev *eth_dev,
 928                                 uint16_t vlan_id, int on)
 929 {
 930         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 931         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 932         struct qed_dev_eth_info *dev_info = &qdev->dev_info;
 933         struct qede_vlan_entry *tmp = NULL;
 934         struct qede_vlan_entry *vlan;
 935         struct ecore_filter_ucast ucast;
 936         int rc;
 937
 938         if (on) {
 939                 if (qdev->configured_vlans == dev_info->num_vlan_filters) {
 940                         DP_ERR(edev, "Reached max VLAN filter limit"
 941                                       " enabling accept_any_vlan\n");
 942                         qede_config_accept_any_vlan(qdev, true);
 943                         return 0;
 944                 }
 945
 946                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 947                         if (tmp->vid == vlan_id) {
 948                                 DP_ERR(edev, "VLAN %u already configured\n",
 949                                        vlan_id);
 950                                 return -EEXIST;
 951                         }
 952                 }
 953
 954                 vlan = rte_malloc(NULL, sizeof(struct qede_vlan_entry),
 955                                   RTE_CACHE_LINE_SIZE);
 956
 957                 if (!vlan) {
 958                         DP_ERR(edev, "Did not allocate memory for VLAN\n");
 959                         return -ENOMEM;
 960                 }
 961
 962                 qede_set_ucast_cmn_params(&ucast);
 963                 ucast.opcode = ECORE_FILTER_ADD;
 964                 ucast.type = ECORE_FILTER_VLAN;
 965                 ucast.vlan = vlan_id;
 966                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
 967                                             NULL);
 968                 if (rc != 0) {
 969                         DP_ERR(edev, "Failed to add VLAN %u rc %d\n", vlan_id,
 970                                rc);
 971                         rte_free(vlan);
 972                 } else {
 973                         vlan->vid = vlan_id;
 974                         SLIST_INSERT_HEAD(&qdev->vlan_list_head, vlan, list);
 975                         qdev->configured_vlans++;
 976                         DP_INFO(edev, "VLAN %u added, configured_vlans %u\n",
 977                                 vlan_id, qdev->configured_vlans);
 978                 }
 979         } else {
 980                 SLIST_FOREACH(tmp, &qdev->vlan_list_head, list) {
 981                         if (tmp->vid == vlan_id)
 982                                 break;
 983                 }
 984
 985                 if (!tmp) {
 986                         if (qdev->configured_vlans == 0) {
 987                                 DP_INFO(edev,
 988                                         "No VLAN filters configured yet\n");
 989                                 return 0;
 990                         }
 991
 992                         DP_ERR(edev, "VLAN %u not configured\n", vlan_id);
 993                         return -EINVAL;
 994                 }
 995
 996                 SLIST_REMOVE(&qdev->vlan_list_head, tmp, qede_vlan_entry, list);
 997
 998                 qede_set_ucast_cmn_params(&ucast);
 999                 ucast.opcode = ECORE_FILTER_REMOVE;
1000                 ucast.type = ECORE_FILTER_VLAN;
1001                 ucast.vlan = vlan_id;
1002                 rc = ecore_filter_ucast_cmd(edev, &ucast, ECORE_SPQ_MODE_CB,
1003                                             NULL);
1004                 if (rc != 0) {
1005                         DP_ERR(edev, "Failed to delete VLAN %u rc %d\n",
1006                                vlan_id, rc);
1007                 } else {
1008                         qdev->configured_vlans--;
1009                         DP_INFO(edev, "VLAN %u removed configured_vlans %u\n",
1010                                 vlan_id, qdev->configured_vlans);
1011                 }
1012         }
1013
1014         return rc;
1015 }
1016
1017 static int qede_vlan_offload_set(struct rte_eth_dev *eth_dev, int mask)
1018 {
1019         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1020         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1021         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1022
1023         if (mask & ETH_VLAN_STRIP_MASK) {
1024                 if (rxmode->hw_vlan_strip)
1025                         (void)qede_vlan_stripping(eth_dev, 1);
1026                 else
1027                         (void)qede_vlan_stripping(eth_dev, 0);
1028         }
1029
1030         if (mask & ETH_VLAN_FILTER_MASK) {
1031                 /* VLAN filtering kicks in when a VLAN is added */
1032                 if (rxmode->hw_vlan_filter) {
1033                         qede_vlan_filter_set(eth_dev, 0, 1);
1034                 } else {
1035                         if (qdev->configured_vlans > 1) { /* Excluding VLAN0 */
1036                                 DP_ERR(edev,
1037                                   " Please remove existing VLAN filters"
1038                                   " before disabling VLAN filtering\n");
1039                                 /* Signal app that VLAN filtering is still
1040                                  * enabled
1041                                  */
1042                                 rxmode->hw_vlan_filter = true;
1043                         } else {
1044                                 qede_vlan_filter_set(eth_dev, 0, 0);
1045                         }
1046                 }
1047         }
1048
1049         if (mask & ETH_VLAN_EXTEND_MASK)
1050                 DP_INFO(edev, "No offloads are supported with VLAN Q-in-Q"
1051                         " and classification is based on outer tag only\n");
1052
1053         DP_INFO(edev, "vlan offload mask %d vlan-strip %d vlan-filter %d\n",
1054                 mask, rxmode->hw_vlan_strip, rxmode->hw_vlan_filter);
1055
1056         return 0;
1057 }
1058
1059 static void qede_prandom_bytes(uint32_t *buff)
1060 {
1061         uint8_t i;
1062
1063         srand((unsigned int)time(NULL));
1064         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
1065                 buff[i] = rand();
1066 }
1067
1068 int qede_config_rss(struct rte_eth_dev *eth_dev)
1069 {
1070         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1071 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
1072         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1073 #endif
1074         uint32_t def_rss_key[ECORE_RSS_KEY_SIZE];
1075         struct rte_eth_rss_reta_entry64 reta_conf[2];
1076         struct rte_eth_rss_conf rss_conf;
1077         uint32_t i, id, pos, q;
1078
1079         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
1080         if (!rss_conf.rss_key) {
1081                 DP_INFO(edev, "Applying driver default key\n");
1082                 rss_conf.rss_key_len = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1083                 qede_prandom_bytes(&def_rss_key[0]);
1084                 rss_conf.rss_key = (uint8_t *)&def_rss_key[0];
1085         }
1086
1087         /* Configure RSS hash */
1088         if (qede_rss_hash_update(eth_dev, &rss_conf))
1089                 return -EINVAL;
1090
1091         /* Configure default RETA */
1092         memset(reta_conf, 0, sizeof(reta_conf));
1093         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
1094                 reta_conf[i / RTE_RETA_GROUP_SIZE].mask = UINT64_MAX;
1095
1096         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
1097                 id = i / RTE_RETA_GROUP_SIZE;
1098                 pos = i % RTE_RETA_GROUP_SIZE;
1099                 q = i % QEDE_RSS_COUNT(qdev);
1100                 reta_conf[id].reta[pos] = q;
1101         }
1102         if (qede_rss_reta_update(eth_dev, &reta_conf[0],
1103                                  ECORE_RSS_IND_TABLE_SIZE))
1104                 return -EINVAL;
1105
1106         return 0;
1107 }
1108
1109 static void qede_fastpath_start(struct ecore_dev *edev)
1110 {
1111         struct ecore_hwfn *p_hwfn;
1112         int i;
1113
1114         for_each_hwfn(edev, i) {
1115                 p_hwfn = &edev->hwfns[i];
1116                 ecore_hw_start_fastpath(p_hwfn);
1117         }
1118 }
1119
1120 static int qede_dev_start(struct rte_eth_dev *eth_dev)
1121 {
1122         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1123         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1124         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1125
1126         PMD_INIT_FUNC_TRACE(edev);
1127
1128         /* Update MTU only if it has changed */
1129         if (qdev->mtu != qdev->new_mtu) {
1130                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1131                         goto err;
1132                 qdev->mtu = qdev->new_mtu;
1133         }
1134
1135         /* Configure TPA parameters */
1136         if (rxmode->enable_lro) {
1137                 if (qede_enable_tpa(eth_dev, true))
1138                         return -EINVAL;
1139                 /* Enable scatter mode for LRO */
1140                 if (!rxmode->enable_scatter)
1141                         eth_dev->data->scattered_rx = 1;
1142         }
1143
1144         /* Start queues */
1145         if (qede_start_queues(eth_dev))
1146                 goto err;
1147
1148         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1149          * enabling RSS. Hence RSS configuration is deferred upto this point.
1150          * Also, we would like to retain similar behavior in PF case, so we
1151          * don't do PF/VF specific check here.
1152          */
1153         if (rxmode->mq_mode == ETH_MQ_RX_RSS)
1154                 if (qede_config_rss(eth_dev))
1155                         goto err;
1156
1157         /* Enable vport*/
1158         if (qede_activate_vport(eth_dev, true))
1159                 goto err;
1160
1161         /* Bring-up the link */
1162         qede_dev_set_link_state(eth_dev, true);
1163
1164         /* Update link status */
1165         qede_link_update(eth_dev, 0);
1166
1167         /* Start/resume traffic */
1168         qede_fastpath_start(edev);
1169
1170         DP_INFO(edev, "Device started\n");
1171
1172         return 0;
1173 err:
1174         DP_ERR(edev, "Device start fails\n");
1175         return -1; /* common error code is < 0 */
1176 }
1177
1178 static void qede_dev_stop(struct rte_eth_dev *eth_dev)
1179 {
1180         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1181         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1182
1183         PMD_INIT_FUNC_TRACE(edev);
1184
1185         /* Disable vport */
1186         if (qede_activate_vport(eth_dev, false))
1187                 return;
1188
1189         if (qdev->enable_lro)
1190                 qede_enable_tpa(eth_dev, false);
1191
1192         /* Stop queues */
1193         qede_stop_queues(eth_dev);
1194
1195         /* Disable traffic */
1196         ecore_hw_stop_fastpath(edev); /* TBD - loop */
1197
1198         /* Bring the link down */
1199         qede_dev_set_link_state(eth_dev, false);
1200
1201         DP_INFO(edev, "Device is stopped\n");
1202 }
1203
1204 static int qede_dev_configure(struct rte_eth_dev *eth_dev)
1205 {
1206         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1207         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1208         struct rte_eth_rxmode *rxmode = &eth_dev->data->dev_conf.rxmode;
1209         int ret;
1210
1211         PMD_INIT_FUNC_TRACE(edev);
1212
1213         /* Check requirements for 100G mode */
1214         if (ECORE_IS_CMT(edev)) {
1215                 if (eth_dev->data->nb_rx_queues < 2 ||
1216                                 eth_dev->data->nb_tx_queues < 2) {
1217                         DP_ERR(edev, "100G mode needs min. 2 RX/TX queues\n");
1218                         return -EINVAL;
1219                 }
1220
1221                 if ((eth_dev->data->nb_rx_queues % 2 != 0) ||
1222                                 (eth_dev->data->nb_tx_queues % 2 != 0)) {
1223                         DP_ERR(edev,
1224                                         "100G mode needs even no. of RX/TX queues\n");
1225                         return -EINVAL;
1226                 }
1227         }
1228
1229         /* Sanity checks and throw warnings */
1230         if (rxmode->enable_scatter)
1231                 eth_dev->data->scattered_rx = 1;
1232
1233         if (!rxmode->hw_strip_crc)
1234                 DP_INFO(edev, "L2 CRC stripping is always enabled in hw\n");
1235
1236         if (!rxmode->hw_ip_checksum)
1237                 DP_INFO(edev, "IP/UDP/TCP checksum offload is always enabled "
1238                                 "in hw\n");
1239         if (rxmode->header_split)
1240                 DP_INFO(edev, "Header split enable is not supported\n");
1241         if (!(rxmode->mq_mode == ETH_MQ_RX_NONE || rxmode->mq_mode ==
1242                                 ETH_MQ_RX_RSS)) {
1243                 DP_ERR(edev, "Unsupported multi-queue mode\n");
1244                 return -ENOTSUP;
1245         }
1246         /* Flow director mode check */
1247         if (qede_check_fdir_support(eth_dev))
1248                 return -ENOTSUP;
1249
1250         /* Deallocate resources if held previously. It is needed only if the
1251          * queue count has been changed from previous configuration. If its
1252          * going to change then it means RX/TX queue setup will be called
1253          * again and the fastpath pointers will be reinitialized there.
1254          */
1255         if (qdev->num_tx_queues != eth_dev->data->nb_tx_queues ||
1256             qdev->num_rx_queues != eth_dev->data->nb_rx_queues) {
1257                 qede_dealloc_fp_resc(eth_dev);
1258                 /* Proceed with updated queue count */
1259                 qdev->num_tx_queues = eth_dev->data->nb_tx_queues;
1260                 qdev->num_rx_queues = eth_dev->data->nb_rx_queues;
1261                 if (qede_alloc_fp_resc(qdev))
1262                         return -ENOMEM;
1263         }
1264
1265         /* VF's MTU has to be set using vport-start where as
1266          * PF's MTU can be updated via vport-update.
1267          */
1268         if (IS_VF(edev)) {
1269                 if (qede_start_vport(qdev, rxmode->max_rx_pkt_len))
1270                         return -1;
1271         } else {
1272                 if (qede_update_mtu(eth_dev, rxmode->max_rx_pkt_len))
1273                         return -1;
1274         }
1275
1276         qdev->mtu = rxmode->max_rx_pkt_len;
1277         qdev->new_mtu = qdev->mtu;
1278
1279         /* Enable VLAN offloads by default */
1280         ret = qede_vlan_offload_set(eth_dev, ETH_VLAN_STRIP_MASK  |
1281                         ETH_VLAN_FILTER_MASK |
1282                         ETH_VLAN_EXTEND_MASK);
1283         if (ret)
1284                 return ret;
1285
1286         DP_INFO(edev, "Device configured with RSS=%d TSS=%d\n",
1287                         QEDE_RSS_COUNT(qdev), QEDE_TSS_COUNT(qdev));
1288
1289         return 0;
1290 }
1291
1292 /* Info about HW descriptor ring limitations */
1293 static const struct rte_eth_desc_lim qede_rx_desc_lim = {
1294         .nb_max = 0x8000, /* 32K */
1295         .nb_min = 128,
1296         .nb_align = 128 /* lowest common multiple */
1297 };
1298
1299 static const struct rte_eth_desc_lim qede_tx_desc_lim = {
1300         .nb_max = 0x8000, /* 32K */
1301         .nb_min = 256,
1302         .nb_align = 256,
1303         .nb_seg_max = ETH_TX_MAX_BDS_PER_LSO_PACKET,
1304         .nb_mtu_seg_max = ETH_TX_MAX_BDS_PER_NON_LSO_PACKET
1305 };
1306
1307 static void
1308 qede_dev_info_get(struct rte_eth_dev *eth_dev,
1309                   struct rte_eth_dev_info *dev_info)
1310 {
1311         struct qede_dev *qdev = eth_dev->data->dev_private;
1312         struct ecore_dev *edev = &qdev->edev;
1313         struct qed_link_output link;
1314         uint32_t speed_cap = 0;
1315
1316         PMD_INIT_FUNC_TRACE(edev);
1317
1318         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1319         dev_info->min_rx_bufsize = (uint32_t)QEDE_MIN_RX_BUFF_SIZE;
1320         dev_info->max_rx_pktlen = (uint32_t)ETH_TX_MAX_NON_LSO_PKT_LEN;
1321         dev_info->rx_desc_lim = qede_rx_desc_lim;
1322         dev_info->tx_desc_lim = qede_tx_desc_lim;
1323
1324         if (IS_PF(edev))
1325                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1326                         QEDE_MAX_RSS_CNT(qdev), QEDE_PF_NUM_CONNS / 2);
1327         else
1328                 dev_info->max_rx_queues = (uint16_t)RTE_MIN(
1329                         QEDE_MAX_RSS_CNT(qdev), ECORE_MAX_VF_CHAINS_PER_PF);
1330         dev_info->max_tx_queues = dev_info->max_rx_queues;
1331
1332         dev_info->max_mac_addrs = qdev->dev_info.num_mac_filters;
1333         dev_info->max_vfs = 0;
1334         dev_info->reta_size = ECORE_RSS_IND_TABLE_SIZE;
1335         dev_info->hash_key_size = ECORE_RSS_KEY_SIZE * sizeof(uint32_t);
1336         dev_info->flow_type_rss_offloads = (uint64_t)QEDE_RSS_OFFLOAD_ALL;
1337
1338         dev_info->default_txconf = (struct rte_eth_txconf) {
1339                 .txq_flags = QEDE_TXQ_FLAGS,
1340         };
1341
1342         dev_info->rx_offload_capa = (DEV_RX_OFFLOAD_VLAN_STRIP  |
1343                                      DEV_RX_OFFLOAD_IPV4_CKSUM  |
1344                                      DEV_RX_OFFLOAD_UDP_CKSUM   |
1345                                      DEV_RX_OFFLOAD_TCP_CKSUM   |
1346                                      DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
1347                                      DEV_RX_OFFLOAD_TCP_LRO);
1348
1349         dev_info->tx_offload_capa = (DEV_TX_OFFLOAD_VLAN_INSERT |
1350                                      DEV_TX_OFFLOAD_IPV4_CKSUM  |
1351                                      DEV_TX_OFFLOAD_UDP_CKSUM   |
1352                                      DEV_TX_OFFLOAD_TCP_CKSUM   |
1353                                      DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1354                                      DEV_TX_OFFLOAD_TCP_TSO |
1355                                      DEV_TX_OFFLOAD_VXLAN_TNL_TSO);
1356
1357         memset(&link, 0, sizeof(struct qed_link_output));
1358         qdev->ops->common->get_link(edev, &link);
1359         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
1360                 speed_cap |= ETH_LINK_SPEED_1G;
1361         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
1362                 speed_cap |= ETH_LINK_SPEED_10G;
1363         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
1364                 speed_cap |= ETH_LINK_SPEED_25G;
1365         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
1366                 speed_cap |= ETH_LINK_SPEED_40G;
1367         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
1368                 speed_cap |= ETH_LINK_SPEED_50G;
1369         if (link.adv_speed & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
1370                 speed_cap |= ETH_LINK_SPEED_100G;
1371         dev_info->speed_capa = speed_cap;
1372 }
1373
1374 /* return 0 means link status changed, -1 means not changed */
1375 int
1376 qede_link_update(struct rte_eth_dev *eth_dev, __rte_unused int wait_to_complete)
1377 {
1378         struct qede_dev *qdev = eth_dev->data->dev_private;
1379         struct ecore_dev *edev = &qdev->edev;
1380         uint16_t link_duplex;
1381         struct qed_link_output link;
1382         struct rte_eth_link *curr = &eth_dev->data->dev_link;
1383
1384         memset(&link, 0, sizeof(struct qed_link_output));
1385         qdev->ops->common->get_link(edev, &link);
1386
1387         /* Link Speed */
1388         curr->link_speed = link.speed;
1389
1390         /* Link Mode */
1391         switch (link.duplex) {
1392         case QEDE_DUPLEX_HALF:
1393                 link_duplex = ETH_LINK_HALF_DUPLEX;
1394                 break;
1395         case QEDE_DUPLEX_FULL:
1396                 link_duplex = ETH_LINK_FULL_DUPLEX;
1397                 break;
1398         case QEDE_DUPLEX_UNKNOWN:
1399         default:
1400                 link_duplex = -1;
1401         }
1402         curr->link_duplex = link_duplex;
1403
1404         /* Link Status */
1405         curr->link_status = (link.link_up) ? ETH_LINK_UP : ETH_LINK_DOWN;
1406
1407         /* AN */
1408         curr->link_autoneg = (link.supported_caps & QEDE_SUPPORTED_AUTONEG) ?
1409                              ETH_LINK_AUTONEG : ETH_LINK_FIXED;
1410
1411         DP_INFO(edev, "Link - Speed %u Mode %u AN %u Status %u\n",
1412                 curr->link_speed, curr->link_duplex,
1413                 curr->link_autoneg, curr->link_status);
1414
1415         /* return 0 means link status changed, -1 means not changed */
1416         return ((curr->link_status == link.link_up) ? -1 : 0);
1417 }
1418
1419 static void qede_promiscuous_enable(struct rte_eth_dev *eth_dev)
1420 {
1421 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1422         struct qede_dev *qdev = eth_dev->data->dev_private;
1423         struct ecore_dev *edev = &qdev->edev;
1424
1425         PMD_INIT_FUNC_TRACE(edev);
1426 #endif
1427
1428         enum qed_filter_rx_mode_type type = QED_FILTER_RX_MODE_TYPE_PROMISC;
1429
1430         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1431                 type |= QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1432
1433         qed_configure_filter_rx_mode(eth_dev, type);
1434 }
1435
1436 static void qede_promiscuous_disable(struct rte_eth_dev *eth_dev)
1437 {
1438 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
1439         struct qede_dev *qdev = eth_dev->data->dev_private;
1440         struct ecore_dev *edev = &qdev->edev;
1441
1442         PMD_INIT_FUNC_TRACE(edev);
1443 #endif
1444
1445         if (rte_eth_allmulticast_get(eth_dev->data->port_id) == 1)
1446                 qed_configure_filter_rx_mode(eth_dev,
1447                                 QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC);
1448         else
1449                 qed_configure_filter_rx_mode(eth_dev,
1450                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1451 }
1452
1453 static void qede_poll_sp_sb_cb(void *param)
1454 {
1455         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)param;
1456         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1457         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1458         int rc;
1459
1460         qede_interrupt_action(ECORE_LEADING_HWFN(edev));
1461         qede_interrupt_action(&edev->hwfns[1]);
1462
1463         rc = rte_eal_alarm_set(timer_period * US_PER_S,
1464                                qede_poll_sp_sb_cb,
1465                                (void *)eth_dev);
1466         if (rc != 0) {
1467                 DP_ERR(edev, "Unable to start periodic"
1468                              " timer rc %d\n", rc);
1469                 assert(false && "Unable to start periodic timer");
1470         }
1471 }
1472
1473 static void qede_dev_close(struct rte_eth_dev *eth_dev)
1474 {
1475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1476         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1477         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1478
1479         PMD_INIT_FUNC_TRACE(edev);
1480
1481         /* dev_stop() shall cleanup fp resources in hw but without releasing
1482          * dma memories and sw structures so that dev_start() can be called
1483          * by the app without reconfiguration. However, in dev_close() we
1484          * can release all the resources and device can be brought up newly
1485          */
1486         if (eth_dev->data->dev_started)
1487                 qede_dev_stop(eth_dev);
1488
1489         qede_stop_vport(edev);
1490         qede_fdir_dealloc_resc(eth_dev);
1491         qede_dealloc_fp_resc(eth_dev);
1492
1493         eth_dev->data->nb_rx_queues = 0;
1494         eth_dev->data->nb_tx_queues = 0;
1495
1496         qdev->ops->common->slowpath_stop(edev);
1497         qdev->ops->common->remove(edev);
1498         rte_intr_disable(&pci_dev->intr_handle);
1499         rte_intr_callback_unregister(&pci_dev->intr_handle,
1500                                      qede_interrupt_handler, (void *)eth_dev);
1501         if (ECORE_IS_CMT(edev))
1502                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb, (void *)eth_dev);
1503 }
1504
1505 static int
1506 qede_get_stats(struct rte_eth_dev *eth_dev, struct rte_eth_stats *eth_stats)
1507 {
1508         struct qede_dev *qdev = eth_dev->data->dev_private;
1509         struct ecore_dev *edev = &qdev->edev;
1510         struct ecore_eth_stats stats;
1511         unsigned int i = 0, j = 0, qid;
1512         unsigned int rxq_stat_cntrs, txq_stat_cntrs;
1513         struct qede_tx_queue *txq;
1514
1515         ecore_get_vport_stats(edev, &stats);
1516
1517         /* RX Stats */
1518         eth_stats->ipackets = stats.common.rx_ucast_pkts +
1519             stats.common.rx_mcast_pkts + stats.common.rx_bcast_pkts;
1520
1521         eth_stats->ibytes = stats.common.rx_ucast_bytes +
1522             stats.common.rx_mcast_bytes + stats.common.rx_bcast_bytes;
1523
1524         eth_stats->ierrors = stats.common.rx_crc_errors +
1525             stats.common.rx_align_errors +
1526             stats.common.rx_carrier_errors +
1527             stats.common.rx_oversize_packets +
1528             stats.common.rx_jabbers + stats.common.rx_undersize_packets;
1529
1530         eth_stats->rx_nombuf = stats.common.no_buff_discards;
1531
1532         eth_stats->imissed = stats.common.mftag_filter_discards +
1533             stats.common.mac_filter_discards +
1534             stats.common.no_buff_discards +
1535             stats.common.brb_truncates + stats.common.brb_discards;
1536
1537         /* TX stats */
1538         eth_stats->opackets = stats.common.tx_ucast_pkts +
1539             stats.common.tx_mcast_pkts + stats.common.tx_bcast_pkts;
1540
1541         eth_stats->obytes = stats.common.tx_ucast_bytes +
1542             stats.common.tx_mcast_bytes + stats.common.tx_bcast_bytes;
1543
1544         eth_stats->oerrors = stats.common.tx_err_drop_pkts;
1545
1546         /* Queue stats */
1547         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1548                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1549         txq_stat_cntrs = RTE_MIN(QEDE_TSS_COUNT(qdev),
1550                                RTE_ETHDEV_QUEUE_STAT_CNTRS);
1551         if ((rxq_stat_cntrs != (unsigned int)QEDE_RSS_COUNT(qdev)) ||
1552             (txq_stat_cntrs != (unsigned int)QEDE_TSS_COUNT(qdev)))
1553                 DP_VERBOSE(edev, ECORE_MSG_DEBUG,
1554                        "Not all the queue stats will be displayed. Set"
1555                        " RTE_ETHDEV_QUEUE_STAT_CNTRS config param"
1556                        " appropriately and retry.\n");
1557
1558         for_each_rss(qid) {
1559                 eth_stats->q_ipackets[i] =
1560                         *(uint64_t *)(
1561                                 ((char *)(qdev->fp_array[qid].rxq)) +
1562                                 offsetof(struct qede_rx_queue,
1563                                 rcv_pkts));
1564                 eth_stats->q_errors[i] =
1565                         *(uint64_t *)(
1566                                 ((char *)(qdev->fp_array[qid].rxq)) +
1567                                 offsetof(struct qede_rx_queue,
1568                                 rx_hw_errors)) +
1569                         *(uint64_t *)(
1570                                 ((char *)(qdev->fp_array[qid].rxq)) +
1571                                 offsetof(struct qede_rx_queue,
1572                                 rx_alloc_errors));
1573                 i++;
1574                 if (i == rxq_stat_cntrs)
1575                         break;
1576         }
1577
1578         for_each_tss(qid) {
1579                 txq = qdev->fp_array[qid].txq;
1580                 eth_stats->q_opackets[j] =
1581                         *((uint64_t *)(uintptr_t)
1582                                 (((uint64_t)(uintptr_t)(txq)) +
1583                                  offsetof(struct qede_tx_queue,
1584                                           xmit_pkts)));
1585                 j++;
1586                 if (j == txq_stat_cntrs)
1587                         break;
1588         }
1589
1590         return 0;
1591 }
1592
1593 static unsigned
1594 qede_get_xstats_count(struct qede_dev *qdev) {
1595         if (ECORE_IS_BB(&qdev->edev))
1596                 return RTE_DIM(qede_xstats_strings) +
1597                        RTE_DIM(qede_bb_xstats_strings) +
1598                        (RTE_DIM(qede_rxq_xstats_strings) *
1599                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1600                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1601         else
1602                 return RTE_DIM(qede_xstats_strings) +
1603                        RTE_DIM(qede_ah_xstats_strings) +
1604                        (RTE_DIM(qede_rxq_xstats_strings) *
1605                         RTE_MIN(QEDE_RSS_COUNT(qdev),
1606                                 RTE_ETHDEV_QUEUE_STAT_CNTRS));
1607 }
1608
1609 static int
1610 qede_get_xstats_names(struct rte_eth_dev *dev,
1611                       struct rte_eth_xstat_name *xstats_names,
1612                       __rte_unused unsigned int limit)
1613 {
1614         struct qede_dev *qdev = dev->data->dev_private;
1615         struct ecore_dev *edev = &qdev->edev;
1616         const unsigned int stat_cnt = qede_get_xstats_count(qdev);
1617         unsigned int i, qid, stat_idx = 0;
1618         unsigned int rxq_stat_cntrs;
1619
1620         if (xstats_names != NULL) {
1621                 for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1622                         snprintf(xstats_names[stat_idx].name,
1623                                 sizeof(xstats_names[stat_idx].name),
1624                                 "%s",
1625                                 qede_xstats_strings[i].name);
1626                         stat_idx++;
1627                 }
1628
1629                 if (ECORE_IS_BB(edev)) {
1630                         for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1631                                 snprintf(xstats_names[stat_idx].name,
1632                                         sizeof(xstats_names[stat_idx].name),
1633                                         "%s",
1634                                         qede_bb_xstats_strings[i].name);
1635                                 stat_idx++;
1636                         }
1637                 } else {
1638                         for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1639                                 snprintf(xstats_names[stat_idx].name,
1640                                         sizeof(xstats_names[stat_idx].name),
1641                                         "%s",
1642                                         qede_ah_xstats_strings[i].name);
1643                                 stat_idx++;
1644                         }
1645                 }
1646
1647                 rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1648                                          RTE_ETHDEV_QUEUE_STAT_CNTRS);
1649                 for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1650                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1651                                 snprintf(xstats_names[stat_idx].name,
1652                                         sizeof(xstats_names[stat_idx].name),
1653                                         "%.4s%d%s",
1654                                         qede_rxq_xstats_strings[i].name, qid,
1655                                         qede_rxq_xstats_strings[i].name + 4);
1656                                 stat_idx++;
1657                         }
1658                 }
1659         }
1660
1661         return stat_cnt;
1662 }
1663
1664 static int
1665 qede_get_xstats(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
1666                 unsigned int n)
1667 {
1668         struct qede_dev *qdev = dev->data->dev_private;
1669         struct ecore_dev *edev = &qdev->edev;
1670         struct ecore_eth_stats stats;
1671         const unsigned int num = qede_get_xstats_count(qdev);
1672         unsigned int i, qid, stat_idx = 0;
1673         unsigned int rxq_stat_cntrs;
1674
1675         if (n < num)
1676                 return num;
1677
1678         ecore_get_vport_stats(edev, &stats);
1679
1680         for (i = 0; i < RTE_DIM(qede_xstats_strings); i++) {
1681                 xstats[stat_idx].value = *(uint64_t *)(((char *)&stats) +
1682                                              qede_xstats_strings[i].offset);
1683                 xstats[stat_idx].id = stat_idx;
1684                 stat_idx++;
1685         }
1686
1687         if (ECORE_IS_BB(edev)) {
1688                 for (i = 0; i < RTE_DIM(qede_bb_xstats_strings); i++) {
1689                         xstats[stat_idx].value =
1690                                         *(uint64_t *)(((char *)&stats) +
1691                                         qede_bb_xstats_strings[i].offset);
1692                         xstats[stat_idx].id = stat_idx;
1693                         stat_idx++;
1694                 }
1695         } else {
1696                 for (i = 0; i < RTE_DIM(qede_ah_xstats_strings); i++) {
1697                         xstats[stat_idx].value =
1698                                         *(uint64_t *)(((char *)&stats) +
1699                                         qede_ah_xstats_strings[i].offset);
1700                         xstats[stat_idx].id = stat_idx;
1701                         stat_idx++;
1702                 }
1703         }
1704
1705         rxq_stat_cntrs = RTE_MIN(QEDE_RSS_COUNT(qdev),
1706                                  RTE_ETHDEV_QUEUE_STAT_CNTRS);
1707         for (qid = 0; qid < rxq_stat_cntrs; qid++) {
1708                 for_each_rss(qid) {
1709                         for (i = 0; i < RTE_DIM(qede_rxq_xstats_strings); i++) {
1710                                 xstats[stat_idx].value = *(uint64_t *)(
1711                                         ((char *)(qdev->fp_array[qid].rxq)) +
1712                                          qede_rxq_xstats_strings[i].offset);
1713                                 xstats[stat_idx].id = stat_idx;
1714                                 stat_idx++;
1715                         }
1716                 }
1717         }
1718
1719         return stat_idx;
1720 }
1721
1722 static void
1723 qede_reset_xstats(struct rte_eth_dev *dev)
1724 {
1725         struct qede_dev *qdev = dev->data->dev_private;
1726         struct ecore_dev *edev = &qdev->edev;
1727
1728         ecore_reset_vport_stats(edev);
1729 }
1730
1731 int qede_dev_set_link_state(struct rte_eth_dev *eth_dev, bool link_up)
1732 {
1733         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1734         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1735         struct qed_link_params link_params;
1736         int rc;
1737
1738         DP_INFO(edev, "setting link state %d\n", link_up);
1739         memset(&link_params, 0, sizeof(link_params));
1740         link_params.link_up = link_up;
1741         rc = qdev->ops->common->set_link(edev, &link_params);
1742         if (rc != ECORE_SUCCESS)
1743                 DP_ERR(edev, "Unable to set link state %d\n", link_up);
1744
1745         return rc;
1746 }
1747
1748 static int qede_dev_set_link_up(struct rte_eth_dev *eth_dev)
1749 {
1750         return qede_dev_set_link_state(eth_dev, true);
1751 }
1752
1753 static int qede_dev_set_link_down(struct rte_eth_dev *eth_dev)
1754 {
1755         return qede_dev_set_link_state(eth_dev, false);
1756 }
1757
1758 static void qede_reset_stats(struct rte_eth_dev *eth_dev)
1759 {
1760         struct qede_dev *qdev = eth_dev->data->dev_private;
1761         struct ecore_dev *edev = &qdev->edev;
1762
1763         ecore_reset_vport_stats(edev);
1764 }
1765
1766 static void qede_allmulticast_enable(struct rte_eth_dev *eth_dev)
1767 {
1768         enum qed_filter_rx_mode_type type =
1769             QED_FILTER_RX_MODE_TYPE_MULTI_PROMISC;
1770
1771         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1772                 type |= QED_FILTER_RX_MODE_TYPE_PROMISC;
1773
1774         qed_configure_filter_rx_mode(eth_dev, type);
1775 }
1776
1777 static void qede_allmulticast_disable(struct rte_eth_dev *eth_dev)
1778 {
1779         if (rte_eth_promiscuous_get(eth_dev->data->port_id) == 1)
1780                 qed_configure_filter_rx_mode(eth_dev,
1781                                 QED_FILTER_RX_MODE_TYPE_PROMISC);
1782         else
1783                 qed_configure_filter_rx_mode(eth_dev,
1784                                 QED_FILTER_RX_MODE_TYPE_REGULAR);
1785 }
1786
1787 static int qede_flow_ctrl_set(struct rte_eth_dev *eth_dev,
1788                               struct rte_eth_fc_conf *fc_conf)
1789 {
1790         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1791         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1792         struct qed_link_output current_link;
1793         struct qed_link_params params;
1794
1795         memset(&current_link, 0, sizeof(current_link));
1796         qdev->ops->common->get_link(edev, &current_link);
1797
1798         memset(&params, 0, sizeof(params));
1799         params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
1800         if (fc_conf->autoneg) {
1801                 if (!(current_link.supported_caps & QEDE_SUPPORTED_AUTONEG)) {
1802                         DP_ERR(edev, "Autoneg not supported\n");
1803                         return -EINVAL;
1804                 }
1805                 params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
1806         }
1807
1808         /* Pause is assumed to be supported (SUPPORTED_Pause) */
1809         if (fc_conf->mode == RTE_FC_FULL)
1810                 params.pause_config |= (QED_LINK_PAUSE_TX_ENABLE |
1811                                         QED_LINK_PAUSE_RX_ENABLE);
1812         if (fc_conf->mode == RTE_FC_TX_PAUSE)
1813                 params.pause_config |= QED_LINK_PAUSE_TX_ENABLE;
1814         if (fc_conf->mode == RTE_FC_RX_PAUSE)
1815                 params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
1816
1817         params.link_up = true;
1818         (void)qdev->ops->common->set_link(edev, &params);
1819
1820         return 0;
1821 }
1822
1823 static int qede_flow_ctrl_get(struct rte_eth_dev *eth_dev,
1824                               struct rte_eth_fc_conf *fc_conf)
1825 {
1826         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1827         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1828         struct qed_link_output current_link;
1829
1830         memset(&current_link, 0, sizeof(current_link));
1831         qdev->ops->common->get_link(edev, &current_link);
1832
1833         if (current_link.pause_config & QED_LINK_PAUSE_AUTONEG_ENABLE)
1834                 fc_conf->autoneg = true;
1835
1836         if (current_link.pause_config & (QED_LINK_PAUSE_RX_ENABLE |
1837                                          QED_LINK_PAUSE_TX_ENABLE))
1838                 fc_conf->mode = RTE_FC_FULL;
1839         else if (current_link.pause_config & QED_LINK_PAUSE_RX_ENABLE)
1840                 fc_conf->mode = RTE_FC_RX_PAUSE;
1841         else if (current_link.pause_config & QED_LINK_PAUSE_TX_ENABLE)
1842                 fc_conf->mode = RTE_FC_TX_PAUSE;
1843         else
1844                 fc_conf->mode = RTE_FC_NONE;
1845
1846         return 0;
1847 }
1848
1849 static const uint32_t *
1850 qede_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev)
1851 {
1852         static const uint32_t ptypes[] = {
1853                 RTE_PTYPE_L2_ETHER,
1854                 RTE_PTYPE_L2_ETHER_VLAN,
1855                 RTE_PTYPE_L3_IPV4,
1856                 RTE_PTYPE_L3_IPV6,
1857                 RTE_PTYPE_L4_TCP,
1858                 RTE_PTYPE_L4_UDP,
1859                 RTE_PTYPE_TUNNEL_VXLAN,
1860                 RTE_PTYPE_L4_FRAG,
1861                 /* Inner */
1862                 RTE_PTYPE_INNER_L2_ETHER,
1863                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1864                 RTE_PTYPE_INNER_L3_IPV4,
1865                 RTE_PTYPE_INNER_L3_IPV6,
1866                 RTE_PTYPE_INNER_L4_TCP,
1867                 RTE_PTYPE_INNER_L4_UDP,
1868                 RTE_PTYPE_INNER_L4_FRAG,
1869                 RTE_PTYPE_UNKNOWN
1870         };
1871
1872         if (eth_dev->rx_pkt_burst == qede_recv_pkts)
1873                 return ptypes;
1874
1875         return NULL;
1876 }
1877
1878 static void qede_init_rss_caps(uint8_t *rss_caps, uint64_t hf)
1879 {
1880         *rss_caps = 0;
1881         *rss_caps |= (hf & ETH_RSS_IPV4)              ? ECORE_RSS_IPV4 : 0;
1882         *rss_caps |= (hf & ETH_RSS_IPV6)              ? ECORE_RSS_IPV6 : 0;
1883         *rss_caps |= (hf & ETH_RSS_IPV6_EX)           ? ECORE_RSS_IPV6 : 0;
1884         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_TCP)  ? ECORE_RSS_IPV4_TCP : 0;
1885         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_TCP)  ? ECORE_RSS_IPV6_TCP : 0;
1886         *rss_caps |= (hf & ETH_RSS_IPV6_TCP_EX)       ? ECORE_RSS_IPV6_TCP : 0;
1887         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV4_UDP)  ? ECORE_RSS_IPV4_UDP : 0;
1888         *rss_caps |= (hf & ETH_RSS_NONFRAG_IPV6_UDP)  ? ECORE_RSS_IPV6_UDP : 0;
1889 }
1890
1891 int qede_rss_hash_update(struct rte_eth_dev *eth_dev,
1892                          struct rte_eth_rss_conf *rss_conf)
1893 {
1894         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1895         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
1896         struct ecore_sp_vport_update_params vport_update_params;
1897         struct ecore_rss_params rss_params;
1898         struct ecore_hwfn *p_hwfn;
1899         uint32_t *key = (uint32_t *)rss_conf->rss_key;
1900         uint64_t hf = rss_conf->rss_hf;
1901         uint8_t len = rss_conf->rss_key_len;
1902         uint8_t idx;
1903         uint8_t i;
1904         int rc;
1905
1906         memset(&vport_update_params, 0, sizeof(vport_update_params));
1907         memset(&rss_params, 0, sizeof(rss_params));
1908
1909         DP_INFO(edev, "RSS hf = 0x%lx len = %u key = %p\n",
1910                 (unsigned long)hf, len, key);
1911
1912         if (hf != 0) {
1913                 /* Enabling RSS */
1914                 DP_INFO(edev, "Enabling rss\n");
1915
1916                 /* RSS caps */
1917                 qede_init_rss_caps(&rss_params.rss_caps, hf);
1918                 rss_params.update_rss_capabilities = 1;
1919
1920                 /* RSS hash key */
1921                 if (key) {
1922                         if (len > (ECORE_RSS_KEY_SIZE * sizeof(uint32_t))) {
1923                                 DP_ERR(edev, "RSS key length exceeds limit\n");
1924                                 return -EINVAL;
1925                         }
1926                         DP_INFO(edev, "Applying user supplied hash key\n");
1927                         rss_params.update_rss_key = 1;
1928                         memcpy(&rss_params.rss_key, key, len);
1929                 }
1930                 rss_params.rss_enable = 1;
1931         }
1932
1933         rss_params.update_rss_config = 1;
1934         /* tbl_size has to be set with capabilities */
1935         rss_params.rss_table_size_log = 7;
1936         vport_update_params.vport_id = 0;
1937         /* pass the L2 handles instead of qids */
1938         for (i = 0 ; i < ECORE_RSS_IND_TABLE_SIZE ; i++) {
1939                 idx = qdev->rss_ind_table[i];
1940                 rss_params.rss_ind_table[i] = qdev->fp_array[idx].rxq->handle;
1941         }
1942         vport_update_params.rss_params = &rss_params;
1943
1944         for_each_hwfn(edev, i) {
1945                 p_hwfn = &edev->hwfns[i];
1946                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
1947                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
1948                                            ECORE_SPQ_MODE_EBLOCK, NULL);
1949                 if (rc) {
1950                         DP_ERR(edev, "vport-update for RSS failed\n");
1951                         return rc;
1952                 }
1953         }
1954         qdev->rss_enable = rss_params.rss_enable;
1955
1956         /* Update local structure for hash query */
1957         qdev->rss_conf.rss_hf = hf;
1958         qdev->rss_conf.rss_key_len = len;
1959         if (qdev->rss_enable) {
1960                 if  (qdev->rss_conf.rss_key == NULL) {
1961                         qdev->rss_conf.rss_key = (uint8_t *)malloc(len);
1962                         if (qdev->rss_conf.rss_key == NULL) {
1963                                 DP_ERR(edev, "No memory to store RSS key\n");
1964                                 return -ENOMEM;
1965                         }
1966                 }
1967                 if (key && len) {
1968                         DP_INFO(edev, "Storing RSS key\n");
1969                         memcpy(qdev->rss_conf.rss_key, key, len);
1970                 }
1971         } else if (!qdev->rss_enable && len == 0) {
1972                 if (qdev->rss_conf.rss_key) {
1973                         free(qdev->rss_conf.rss_key);
1974                         qdev->rss_conf.rss_key = NULL;
1975                         DP_INFO(edev, "Free RSS key\n");
1976                 }
1977         }
1978
1979         return 0;
1980 }
1981
1982 static int qede_rss_hash_conf_get(struct rte_eth_dev *eth_dev,
1983                            struct rte_eth_rss_conf *rss_conf)
1984 {
1985         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1986
1987         rss_conf->rss_hf = qdev->rss_conf.rss_hf;
1988         rss_conf->rss_key_len = qdev->rss_conf.rss_key_len;
1989
1990         if (rss_conf->rss_key && qdev->rss_conf.rss_key)
1991                 memcpy(rss_conf->rss_key, qdev->rss_conf.rss_key,
1992                        rss_conf->rss_key_len);
1993         return 0;
1994 }
1995
1996 static bool qede_update_rss_parm_cmt(struct ecore_dev *edev,
1997                                     struct ecore_rss_params *rss)
1998 {
1999         int i, fn;
2000         bool rss_mode = 1; /* enable */
2001         struct ecore_queue_cid *cid;
2002         struct ecore_rss_params *t_rss;
2003
2004         /* In regular scenario, we'd simply need to take input handlers.
2005          * But in CMT, we'd have to split the handlers according to the
2006          * engine they were configured on. We'd then have to understand
2007          * whether RSS is really required, since 2-queues on CMT doesn't
2008          * require RSS.
2009          */
2010
2011         /* CMT should be round-robin */
2012         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++) {
2013                 cid = rss->rss_ind_table[i];
2014
2015                 if (cid->p_owner == ECORE_LEADING_HWFN(edev))
2016                         t_rss = &rss[0];
2017                 else
2018                         t_rss = &rss[1];
2019
2020                 t_rss->rss_ind_table[i / edev->num_hwfns] = cid;
2021         }
2022
2023         t_rss = &rss[1];
2024         t_rss->update_rss_ind_table = 1;
2025         t_rss->rss_table_size_log = 7;
2026         t_rss->update_rss_config = 1;
2027
2028         /* Make sure RSS is actually required */
2029         for_each_hwfn(edev, fn) {
2030                 for (i = 1; i < ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns;
2031                      i++) {
2032                         if (rss[fn].rss_ind_table[i] !=
2033                             rss[fn].rss_ind_table[0])
2034                                 break;
2035                 }
2036
2037                 if (i == ECORE_RSS_IND_TABLE_SIZE / edev->num_hwfns) {
2038                         DP_INFO(edev,
2039                                 "CMT - 1 queue per-hwfn; Disabling RSS\n");
2040                         rss_mode = 0;
2041                         goto out;
2042                 }
2043         }
2044
2045 out:
2046         t_rss->rss_enable = rss_mode;
2047
2048         return rss_mode;
2049 }
2050
2051 int qede_rss_reta_update(struct rte_eth_dev *eth_dev,
2052                          struct rte_eth_rss_reta_entry64 *reta_conf,
2053                          uint16_t reta_size)
2054 {
2055         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2056         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2057         struct ecore_sp_vport_update_params vport_update_params;
2058         struct ecore_rss_params *params;
2059         struct ecore_hwfn *p_hwfn;
2060         uint16_t i, idx, shift;
2061         uint8_t entry;
2062         int rc = 0;
2063
2064         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2065                 DP_ERR(edev, "reta_size %d is not supported by hardware\n",
2066                        reta_size);
2067                 return -EINVAL;
2068         }
2069
2070         memset(&vport_update_params, 0, sizeof(vport_update_params));
2071         params = rte_zmalloc("qede_rss", sizeof(*params) * edev->num_hwfns,
2072                              RTE_CACHE_LINE_SIZE);
2073         if (params == NULL) {
2074                 DP_ERR(edev, "failed to allocate memory\n");
2075                 return -ENOMEM;
2076         }
2077
2078         for (i = 0; i < reta_size; i++) {
2079                 idx = i / RTE_RETA_GROUP_SIZE;
2080                 shift = i % RTE_RETA_GROUP_SIZE;
2081                 if (reta_conf[idx].mask & (1ULL << shift)) {
2082                         entry = reta_conf[idx].reta[shift];
2083                         /* Pass rxq handles to ecore */
2084                         params->rss_ind_table[i] =
2085                                         qdev->fp_array[entry].rxq->handle;
2086                         /* Update the local copy for RETA query command */
2087                         qdev->rss_ind_table[i] = entry;
2088                 }
2089         }
2090
2091         params->update_rss_ind_table = 1;
2092         params->rss_table_size_log = 7;
2093         params->update_rss_config = 1;
2094
2095         /* Fix up RETA for CMT mode device */
2096         if (ECORE_IS_CMT(edev))
2097                 qdev->rss_enable = qede_update_rss_parm_cmt(edev,
2098                                                             params);
2099         vport_update_params.vport_id = 0;
2100         /* Use the current value of rss_enable */
2101         params->rss_enable = qdev->rss_enable;
2102         vport_update_params.rss_params = params;
2103
2104         for_each_hwfn(edev, i) {
2105                 p_hwfn = &edev->hwfns[i];
2106                 vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
2107                 rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
2108                                            ECORE_SPQ_MODE_EBLOCK, NULL);
2109                 if (rc) {
2110                         DP_ERR(edev, "vport-update for RSS failed\n");
2111                         goto out;
2112                 }
2113         }
2114
2115 out:
2116         rte_free(params);
2117         return rc;
2118 }
2119
2120 static int qede_rss_reta_query(struct rte_eth_dev *eth_dev,
2121                                struct rte_eth_rss_reta_entry64 *reta_conf,
2122                                uint16_t reta_size)
2123 {
2124         struct qede_dev *qdev = eth_dev->data->dev_private;
2125         struct ecore_dev *edev = &qdev->edev;
2126         uint16_t i, idx, shift;
2127         uint8_t entry;
2128
2129         if (reta_size > ETH_RSS_RETA_SIZE_128) {
2130                 DP_ERR(edev, "reta_size %d is not supported\n",
2131                        reta_size);
2132                 return -EINVAL;
2133         }
2134
2135         for (i = 0; i < reta_size; i++) {
2136                 idx = i / RTE_RETA_GROUP_SIZE;
2137                 shift = i % RTE_RETA_GROUP_SIZE;
2138                 if (reta_conf[idx].mask & (1ULL << shift)) {
2139                         entry = qdev->rss_ind_table[i];
2140                         reta_conf[idx].reta[shift] = entry;
2141                 }
2142         }
2143
2144         return 0;
2145 }
2146
2147
2148
2149 static int qede_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
2150 {
2151         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
2152         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2153         struct rte_eth_dev_info dev_info = {0};
2154         struct qede_fastpath *fp;
2155         uint32_t frame_size;
2156         uint16_t rx_buf_size;
2157         uint16_t bufsz;
2158         int i;
2159
2160         PMD_INIT_FUNC_TRACE(edev);
2161         qede_dev_info_get(dev, &dev_info);
2162         frame_size = mtu + QEDE_ETH_OVERHEAD;
2163         if ((mtu < ETHER_MIN_MTU) || (frame_size > dev_info.max_rx_pktlen)) {
2164                 DP_ERR(edev, "MTU %u out of range\n", mtu);
2165                 return -EINVAL;
2166         }
2167         if (!dev->data->scattered_rx &&
2168             frame_size > dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM) {
2169                 DP_INFO(edev, "MTU greater than minimum RX buffer size of %u\n",
2170                         dev->data->min_rx_buf_size);
2171                 return -EINVAL;
2172         }
2173         /* Temporarily replace I/O functions with dummy ones. It cannot
2174          * be set to NULL because rte_eth_rx_burst() doesn't check for NULL.
2175          */
2176         dev->rx_pkt_burst = qede_rxtx_pkts_dummy;
2177         dev->tx_pkt_burst = qede_rxtx_pkts_dummy;
2178         qede_dev_stop(dev);
2179         rte_delay_ms(1000);
2180         qdev->mtu = mtu;
2181         /* Fix up RX buf size for all queues of the port */
2182         for_each_rss(i) {
2183                 fp = &qdev->fp_array[i];
2184                 bufsz = (uint16_t)rte_pktmbuf_data_room_size(
2185                         fp->rxq->mb_pool) - RTE_PKTMBUF_HEADROOM;
2186                 if (dev->data->scattered_rx)
2187                         rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
2188                 else
2189                         rx_buf_size = mtu + QEDE_ETH_OVERHEAD;
2190                 rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rx_buf_size);
2191                 fp->rxq->rx_buf_size = rx_buf_size;
2192                 DP_INFO(edev, "buf_size adjusted to %u\n", rx_buf_size);
2193         }
2194         qede_dev_start(dev);
2195         if (frame_size > ETHER_MAX_LEN)
2196                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
2197         else
2198                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
2199         /* update max frame size */
2200         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2201         /* Reassign back */
2202         dev->rx_pkt_burst = qede_recv_pkts;
2203         dev->tx_pkt_burst = qede_xmit_pkts;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 qede_conf_udp_dst_port(struct rte_eth_dev *eth_dev,
2210                        struct rte_eth_udp_tunnel *tunnel_udp,
2211                        bool add)
2212 {
2213         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2214         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2215         struct ecore_tunnel_info tunn; /* @DPDK */
2216         struct ecore_hwfn *p_hwfn;
2217         struct ecore_ptt *p_ptt;
2218         uint16_t udp_port;
2219         int rc, i;
2220
2221         PMD_INIT_FUNC_TRACE(edev);
2222
2223         memset(&tunn, 0, sizeof(tunn));
2224         if (tunnel_udp->prot_type == RTE_TUNNEL_TYPE_VXLAN) {
2225                 /* Enable VxLAN tunnel if needed before UDP port update using
2226                  * default MAC/VLAN classification.
2227                  */
2228                 if (add) {
2229                         if (qdev->vxlan.udp_port == tunnel_udp->udp_port) {
2230                                 DP_INFO(edev,
2231                                         "UDP port %u was already configured\n",
2232                                         tunnel_udp->udp_port);
2233                                 return ECORE_SUCCESS;
2234                         }
2235                         /* Enable VXLAN if it was not enabled while adding
2236                          * VXLAN filter.
2237                          */
2238                         if (!qdev->vxlan.enable) {
2239                                 rc = qede_vxlan_enable(eth_dev,
2240                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2241                                 if (rc != ECORE_SUCCESS) {
2242                                         DP_ERR(edev, "Failed to enable VXLAN "
2243                                                 "prior to updating UDP port\n");
2244                                         return rc;
2245                                 }
2246                         }
2247                         udp_port = tunnel_udp->udp_port;
2248                 } else {
2249                         if (qdev->vxlan.udp_port != tunnel_udp->udp_port) {
2250                                 DP_ERR(edev, "UDP port %u doesn't exist\n",
2251                                         tunnel_udp->udp_port);
2252                                 return ECORE_INVAL;
2253                         }
2254                         udp_port = 0;
2255                 }
2256
2257                 tunn.vxlan_port.b_update_port = true;
2258                 tunn.vxlan_port.port = udp_port;
2259                 for_each_hwfn(edev, i) {
2260                         p_hwfn = &edev->hwfns[i];
2261                         p_ptt = IS_PF(edev) ? ecore_ptt_acquire(p_hwfn) : NULL;
2262                         rc = ecore_sp_pf_update_tunn_cfg(p_hwfn, p_ptt, &tunn,
2263                                                 ECORE_SPQ_MODE_CB, NULL);
2264                         if (rc != ECORE_SUCCESS) {
2265                                 DP_ERR(edev, "Unable to config UDP port %u\n",
2266                                        tunn.vxlan_port.port);
2267                                 if (IS_PF(edev))
2268                                         ecore_ptt_release(p_hwfn, p_ptt);
2269                                 return rc;
2270                         }
2271                 }
2272
2273                 qdev->vxlan.udp_port = udp_port;
2274                 /* If the request is to delete UDP port and if the number of
2275                  * VXLAN filters have reached 0 then VxLAN offload can be be
2276                  * disabled.
2277                  */
2278                 if (!add && qdev->vxlan.enable && qdev->vxlan.num_filters == 0)
2279                         return qede_vxlan_enable(eth_dev,
2280                                         ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2281         }
2282
2283         return 0;
2284 }
2285
2286 static int
2287 qede_udp_dst_port_del(struct rte_eth_dev *eth_dev,
2288                       struct rte_eth_udp_tunnel *tunnel_udp)
2289 {
2290         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, false);
2291 }
2292
2293 static int
2294 qede_udp_dst_port_add(struct rte_eth_dev *eth_dev,
2295                       struct rte_eth_udp_tunnel *tunnel_udp)
2296 {
2297         return qede_conf_udp_dst_port(eth_dev, tunnel_udp, true);
2298 }
2299
2300 static void qede_get_ecore_tunn_params(uint32_t filter, uint32_t *type,
2301                                        uint32_t *clss, char *str)
2302 {
2303         uint16_t j;
2304         *clss = MAX_ECORE_TUNN_CLSS;
2305
2306         for (j = 0; j < RTE_DIM(qede_tunn_types); j++) {
2307                 if (filter == qede_tunn_types[j].rte_filter_type) {
2308                         *type = qede_tunn_types[j].qede_type;
2309                         *clss = qede_tunn_types[j].qede_tunn_clss;
2310                         strcpy(str, qede_tunn_types[j].string);
2311                         return;
2312                 }
2313         }
2314 }
2315
2316 static int
2317 qede_set_ucast_tunn_cmn_param(struct ecore_filter_ucast *ucast,
2318                               const struct rte_eth_tunnel_filter_conf *conf,
2319                               uint32_t type)
2320 {
2321         /* Init commmon ucast params first */
2322         qede_set_ucast_cmn_params(ucast);
2323
2324         /* Copy out the required fields based on classification type */
2325         ucast->type = type;
2326
2327         switch (type) {
2328         case ECORE_FILTER_VNI:
2329                 ucast->vni = conf->tenant_id;
2330         break;
2331         case ECORE_FILTER_INNER_VLAN:
2332                 ucast->vlan = conf->inner_vlan;
2333         break;
2334         case ECORE_FILTER_MAC:
2335                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2336                        ETHER_ADDR_LEN);
2337         break;
2338         case ECORE_FILTER_INNER_MAC:
2339                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2340                        ETHER_ADDR_LEN);
2341         break;
2342         case ECORE_FILTER_MAC_VNI_PAIR:
2343                 memcpy(ucast->mac, conf->outer_mac.addr_bytes,
2344                         ETHER_ADDR_LEN);
2345                 ucast->vni = conf->tenant_id;
2346         break;
2347         case ECORE_FILTER_INNER_MAC_VNI_PAIR:
2348                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2349                         ETHER_ADDR_LEN);
2350                 ucast->vni = conf->tenant_id;
2351         break;
2352         case ECORE_FILTER_INNER_PAIR:
2353                 memcpy(ucast->mac, conf->inner_mac.addr_bytes,
2354                         ETHER_ADDR_LEN);
2355                 ucast->vlan = conf->inner_vlan;
2356         break;
2357         default:
2358                 return -EINVAL;
2359         }
2360
2361         return ECORE_SUCCESS;
2362 }
2363
2364 static int qede_vxlan_tunn_config(struct rte_eth_dev *eth_dev,
2365                                   enum rte_filter_op filter_op,
2366                                   const struct rte_eth_tunnel_filter_conf *conf)
2367 {
2368         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2369         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2370         enum ecore_filter_ucast_type type;
2371         enum ecore_tunn_clss clss = MAX_ECORE_TUNN_CLSS;
2372         struct ecore_filter_ucast ucast = {0};
2373         char str[80];
2374         uint16_t filter_type = 0;
2375         int rc;
2376
2377         PMD_INIT_FUNC_TRACE(edev);
2378
2379         switch (filter_op) {
2380         case RTE_ETH_FILTER_ADD:
2381                 if (IS_VF(edev))
2382                         return qede_vxlan_enable(eth_dev,
2383                                         ECORE_TUNN_CLSS_MAC_VLAN, true, true);
2384
2385                 filter_type = conf->filter_type;
2386                 /* Determine if the given filter classification is supported */
2387                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2388                 if (clss == MAX_ECORE_TUNN_CLSS) {
2389                         DP_ERR(edev, "Unsupported filter type\n");
2390                         return -EINVAL;
2391                 }
2392                 /* Init tunnel ucast params */
2393                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2394                 if (rc != ECORE_SUCCESS) {
2395                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2396                         conf->filter_type);
2397                         return rc;
2398                 }
2399                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2400                         str, filter_op, ucast.type);
2401
2402                 ucast.opcode = ECORE_FILTER_ADD;
2403
2404                 /* Skip MAC/VLAN if filter is based on VNI */
2405                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2406                         rc = qede_mac_int_ops(eth_dev, &ucast, 1);
2407                         if (rc == 0) {
2408                                 /* Enable accept anyvlan */
2409                                 qede_config_accept_any_vlan(qdev, true);
2410                         }
2411                 } else {
2412                         rc = qede_ucast_filter(eth_dev, &ucast, 1);
2413                         if (rc == 0)
2414                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2415                                                     ECORE_SPQ_MODE_CB, NULL);
2416                 }
2417
2418                 if (rc != ECORE_SUCCESS)
2419                         return rc;
2420
2421                 qdev->vxlan.num_filters++;
2422                 qdev->vxlan.filter_type = filter_type;
2423                 if (!qdev->vxlan.enable)
2424                         return qede_vxlan_enable(eth_dev, clss, true, true);
2425
2426         break;
2427         case RTE_ETH_FILTER_DELETE:
2428                 if (IS_VF(edev))
2429                         return qede_vxlan_enable(eth_dev,
2430                                 ECORE_TUNN_CLSS_MAC_VLAN, false, true);
2431
2432                 filter_type = conf->filter_type;
2433                 /* Determine if the given filter classification is supported */
2434                 qede_get_ecore_tunn_params(filter_type, &type, &clss, str);
2435                 if (clss == MAX_ECORE_TUNN_CLSS) {
2436                         DP_ERR(edev, "Unsupported filter type\n");
2437                         return -EINVAL;
2438                 }
2439                 /* Init tunnel ucast params */
2440                 rc = qede_set_ucast_tunn_cmn_param(&ucast, conf, type);
2441                 if (rc != ECORE_SUCCESS) {
2442                         DP_ERR(edev, "Unsupported VxLAN filter type 0x%x\n",
2443                         conf->filter_type);
2444                         return rc;
2445                 }
2446                 DP_INFO(edev, "Rule: \"%s\", op %d, type 0x%x\n",
2447                         str, filter_op, ucast.type);
2448
2449                 ucast.opcode = ECORE_FILTER_REMOVE;
2450
2451                 if (!(filter_type & ETH_TUNNEL_FILTER_TENID)) {
2452                         rc = qede_mac_int_ops(eth_dev, &ucast, 0);
2453                 } else {
2454                         rc = qede_ucast_filter(eth_dev, &ucast, 0);
2455                         if (rc == 0)
2456                                 rc = ecore_filter_ucast_cmd(edev, &ucast,
2457                                                     ECORE_SPQ_MODE_CB, NULL);
2458                 }
2459                 if (rc != ECORE_SUCCESS)
2460                         return rc;
2461
2462                 qdev->vxlan.num_filters--;
2463
2464                 /* Disable VXLAN if VXLAN filters become 0 */
2465                 if (qdev->vxlan.num_filters == 0)
2466                         return qede_vxlan_enable(eth_dev, clss, false, true);
2467         break;
2468         default:
2469                 DP_ERR(edev, "Unsupported operation %d\n", filter_op);
2470                 return -EINVAL;
2471         }
2472
2473         return 0;
2474 }
2475
2476 int qede_dev_filter_ctrl(struct rte_eth_dev *eth_dev,
2477                          enum rte_filter_type filter_type,
2478                          enum rte_filter_op filter_op,
2479                          void *arg)
2480 {
2481         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
2482         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
2483         struct rte_eth_tunnel_filter_conf *filter_conf =
2484                         (struct rte_eth_tunnel_filter_conf *)arg;
2485
2486         switch (filter_type) {
2487         case RTE_ETH_FILTER_TUNNEL:
2488                 switch (filter_conf->tunnel_type) {
2489                 case RTE_TUNNEL_TYPE_VXLAN:
2490                         DP_INFO(edev,
2491                                 "Packet steering to the specified Rx queue"
2492                                 " is not supported with VXLAN tunneling");
2493                         return(qede_vxlan_tunn_config(eth_dev, filter_op,
2494                                                       filter_conf));
2495                 /* Place holders for future tunneling support */
2496                 case RTE_TUNNEL_TYPE_GENEVE:
2497                 case RTE_TUNNEL_TYPE_TEREDO:
2498                 case RTE_TUNNEL_TYPE_NVGRE:
2499                 case RTE_TUNNEL_TYPE_IP_IN_GRE:
2500                 case RTE_L2_TUNNEL_TYPE_E_TAG:
2501                         DP_ERR(edev, "Unsupported tunnel type %d\n",
2502                                 filter_conf->tunnel_type);
2503                         return -EINVAL;
2504                 case RTE_TUNNEL_TYPE_NONE:
2505                 default:
2506                         return 0;
2507                 }
2508                 break;
2509         case RTE_ETH_FILTER_FDIR:
2510                 return qede_fdir_filter_conf(eth_dev, filter_op, arg);
2511         case RTE_ETH_FILTER_NTUPLE:
2512                 return qede_ntuple_filter_conf(eth_dev, filter_op, arg);
2513         case RTE_ETH_FILTER_MACVLAN:
2514         case RTE_ETH_FILTER_ETHERTYPE:
2515         case RTE_ETH_FILTER_FLEXIBLE:
2516         case RTE_ETH_FILTER_SYN:
2517         case RTE_ETH_FILTER_HASH:
2518         case RTE_ETH_FILTER_L2_TUNNEL:
2519         case RTE_ETH_FILTER_MAX:
2520         default:
2521                 DP_ERR(edev, "Unsupported filter type %d\n",
2522                         filter_type);
2523                 return -EINVAL;
2524         }
2525
2526         return 0;
2527 }
2528
2529 static const struct eth_dev_ops qede_eth_dev_ops = {
2530         .dev_configure = qede_dev_configure,
2531         .dev_infos_get = qede_dev_info_get,
2532         .rx_queue_setup = qede_rx_queue_setup,
2533         .rx_queue_release = qede_rx_queue_release,
2534         .tx_queue_setup = qede_tx_queue_setup,
2535         .tx_queue_release = qede_tx_queue_release,
2536         .dev_start = qede_dev_start,
2537         .dev_set_link_up = qede_dev_set_link_up,
2538         .dev_set_link_down = qede_dev_set_link_down,
2539         .link_update = qede_link_update,
2540         .promiscuous_enable = qede_promiscuous_enable,
2541         .promiscuous_disable = qede_promiscuous_disable,
2542         .allmulticast_enable = qede_allmulticast_enable,
2543         .allmulticast_disable = qede_allmulticast_disable,
2544         .dev_stop = qede_dev_stop,
2545         .dev_close = qede_dev_close,
2546         .stats_get = qede_get_stats,
2547         .stats_reset = qede_reset_stats,
2548         .xstats_get = qede_get_xstats,
2549         .xstats_reset = qede_reset_xstats,
2550         .xstats_get_names = qede_get_xstats_names,
2551         .mac_addr_add = qede_mac_addr_add,
2552         .mac_addr_remove = qede_mac_addr_remove,
2553         .mac_addr_set = qede_mac_addr_set,
2554         .vlan_offload_set = qede_vlan_offload_set,
2555         .vlan_filter_set = qede_vlan_filter_set,
2556         .flow_ctrl_set = qede_flow_ctrl_set,
2557         .flow_ctrl_get = qede_flow_ctrl_get,
2558         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2559         .rss_hash_update = qede_rss_hash_update,
2560         .rss_hash_conf_get = qede_rss_hash_conf_get,
2561         .reta_update  = qede_rss_reta_update,
2562         .reta_query  = qede_rss_reta_query,
2563         .mtu_set = qede_set_mtu,
2564         .filter_ctrl = qede_dev_filter_ctrl,
2565         .udp_tunnel_port_add = qede_udp_dst_port_add,
2566         .udp_tunnel_port_del = qede_udp_dst_port_del,
2567 };
2568
2569 static const struct eth_dev_ops qede_eth_vf_dev_ops = {
2570         .dev_configure = qede_dev_configure,
2571         .dev_infos_get = qede_dev_info_get,
2572         .rx_queue_setup = qede_rx_queue_setup,
2573         .rx_queue_release = qede_rx_queue_release,
2574         .tx_queue_setup = qede_tx_queue_setup,
2575         .tx_queue_release = qede_tx_queue_release,
2576         .dev_start = qede_dev_start,
2577         .dev_set_link_up = qede_dev_set_link_up,
2578         .dev_set_link_down = qede_dev_set_link_down,
2579         .link_update = qede_link_update,
2580         .promiscuous_enable = qede_promiscuous_enable,
2581         .promiscuous_disable = qede_promiscuous_disable,
2582         .allmulticast_enable = qede_allmulticast_enable,
2583         .allmulticast_disable = qede_allmulticast_disable,
2584         .dev_stop = qede_dev_stop,
2585         .dev_close = qede_dev_close,
2586         .stats_get = qede_get_stats,
2587         .stats_reset = qede_reset_stats,
2588         .xstats_get = qede_get_xstats,
2589         .xstats_reset = qede_reset_xstats,
2590         .xstats_get_names = qede_get_xstats_names,
2591         .vlan_offload_set = qede_vlan_offload_set,
2592         .vlan_filter_set = qede_vlan_filter_set,
2593         .dev_supported_ptypes_get = qede_dev_supported_ptypes_get,
2594         .rss_hash_update = qede_rss_hash_update,
2595         .rss_hash_conf_get = qede_rss_hash_conf_get,
2596         .reta_update  = qede_rss_reta_update,
2597         .reta_query  = qede_rss_reta_query,
2598         .mtu_set = qede_set_mtu,
2599         .udp_tunnel_port_add = qede_udp_dst_port_add,
2600         .udp_tunnel_port_del = qede_udp_dst_port_del,
2601 };
2602
2603 static void qede_update_pf_params(struct ecore_dev *edev)
2604 {
2605         struct ecore_pf_params pf_params;
2606
2607         memset(&pf_params, 0, sizeof(struct ecore_pf_params));
2608         pf_params.eth_pf_params.num_cons = QEDE_PF_NUM_CONNS;
2609         pf_params.eth_pf_params.num_arfs_filters = QEDE_RFS_MAX_FLTR;
2610         qed_ops->common->update_pf_params(edev, &pf_params);
2611 }
2612
2613 static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf)
2614 {
2615         struct rte_pci_device *pci_dev;
2616         struct rte_pci_addr pci_addr;
2617         struct qede_dev *adapter;
2618         struct ecore_dev *edev;
2619         struct qed_dev_eth_info dev_info;
2620         struct qed_slowpath_params params;
2621         static bool do_once = true;
2622         uint8_t bulletin_change;
2623         uint8_t vf_mac[ETHER_ADDR_LEN];
2624         uint8_t is_mac_forced;
2625         bool is_mac_exist;
2626         /* Fix up ecore debug level */
2627         uint32_t dp_module = ~0 & ~ECORE_MSG_HW;
2628         uint8_t dp_level = ECORE_LEVEL_VERBOSE;
2629         int rc;
2630
2631         /* Extract key data structures */
2632         adapter = eth_dev->data->dev_private;
2633         adapter->ethdev = eth_dev;
2634         edev = &adapter->edev;
2635         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2636         pci_addr = pci_dev->addr;
2637
2638         PMD_INIT_FUNC_TRACE(edev);
2639
2640         snprintf(edev->name, NAME_SIZE, PCI_SHORT_PRI_FMT ":dpdk-port-%u",
2641                  pci_addr.bus, pci_addr.devid, pci_addr.function,
2642                  eth_dev->data->port_id);
2643
2644         eth_dev->rx_pkt_burst = qede_recv_pkts;
2645         eth_dev->tx_pkt_burst = qede_xmit_pkts;
2646         eth_dev->tx_pkt_prepare = qede_xmit_prep_pkts;
2647
2648         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2649                 DP_ERR(edev, "Skipping device init from secondary process\n");
2650                 return 0;
2651         }
2652
2653         rte_eth_copy_pci_info(eth_dev, pci_dev);
2654
2655         /* @DPDK */
2656         edev->vendor_id = pci_dev->id.vendor_id;
2657         edev->device_id = pci_dev->id.device_id;
2658
2659         qed_ops = qed_get_eth_ops();
2660         if (!qed_ops) {
2661                 DP_ERR(edev, "Failed to get qed_eth_ops_pass\n");
2662                 return -EINVAL;
2663         }
2664
2665         DP_INFO(edev, "Starting qede probe\n");
2666         rc = qed_ops->common->probe(edev, pci_dev, dp_module,
2667                                     dp_level, is_vf);
2668         if (rc != 0) {
2669                 DP_ERR(edev, "qede probe failed rc %d\n", rc);
2670                 return -ENODEV;
2671         }
2672         qede_update_pf_params(edev);
2673         rte_intr_callback_register(&pci_dev->intr_handle,
2674                                    qede_interrupt_handler, (void *)eth_dev);
2675         if (rte_intr_enable(&pci_dev->intr_handle)) {
2676                 DP_ERR(edev, "rte_intr_enable() failed\n");
2677                 return -ENODEV;
2678         }
2679
2680         /* Start the Slowpath-process */
2681         memset(&params, 0, sizeof(struct qed_slowpath_params));
2682         params.int_mode = ECORE_INT_MODE_MSIX;
2683         params.drv_major = QEDE_PMD_VERSION_MAJOR;
2684         params.drv_minor = QEDE_PMD_VERSION_MINOR;
2685         params.drv_rev = QEDE_PMD_VERSION_REVISION;
2686         params.drv_eng = QEDE_PMD_VERSION_PATCH;
2687         strncpy((char *)params.name, QEDE_PMD_VER_PREFIX,
2688                 QEDE_PMD_DRV_VER_STR_SIZE);
2689
2690         /* For CMT mode device do periodic polling for slowpath events.
2691          * This is required since uio device uses only one MSI-x
2692          * interrupt vector but we need one for each engine.
2693          */
2694         if (ECORE_IS_CMT(edev) && IS_PF(edev)) {
2695                 rc = rte_eal_alarm_set(timer_period * US_PER_S,
2696                                        qede_poll_sp_sb_cb,
2697                                        (void *)eth_dev);
2698                 if (rc != 0) {
2699                         DP_ERR(edev, "Unable to start periodic"
2700                                      " timer rc %d\n", rc);
2701                         return -EINVAL;
2702                 }
2703         }
2704
2705         rc = qed_ops->common->slowpath_start(edev, &params);
2706         if (rc) {
2707                 DP_ERR(edev, "Cannot start slowpath rc = %d\n", rc);
2708                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2709                                      (void *)eth_dev);
2710                 return -ENODEV;
2711         }
2712
2713         rc = qed_ops->fill_dev_info(edev, &dev_info);
2714         if (rc) {
2715                 DP_ERR(edev, "Cannot get device_info rc %d\n", rc);
2716                 qed_ops->common->slowpath_stop(edev);
2717                 qed_ops->common->remove(edev);
2718                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2719                                      (void *)eth_dev);
2720                 return -ENODEV;
2721         }
2722
2723         qede_alloc_etherdev(adapter, &dev_info);
2724
2725         adapter->ops->common->set_name(edev, edev->name);
2726
2727         if (!is_vf)
2728                 adapter->dev_info.num_mac_filters =
2729                         (uint32_t)RESC_NUM(ECORE_LEADING_HWFN(edev),
2730                                             ECORE_MAC);
2731         else
2732                 ecore_vf_get_num_mac_filters(ECORE_LEADING_HWFN(edev),
2733                                 (uint32_t *)&adapter->dev_info.num_mac_filters);
2734
2735         /* Allocate memory for storing MAC addr */
2736         eth_dev->data->mac_addrs = rte_zmalloc(edev->name,
2737                                         (ETHER_ADDR_LEN *
2738                                         adapter->dev_info.num_mac_filters),
2739                                         RTE_CACHE_LINE_SIZE);
2740
2741         if (eth_dev->data->mac_addrs == NULL) {
2742                 DP_ERR(edev, "Failed to allocate MAC address\n");
2743                 qed_ops->common->slowpath_stop(edev);
2744                 qed_ops->common->remove(edev);
2745                 rte_eal_alarm_cancel(qede_poll_sp_sb_cb,
2746                                      (void *)eth_dev);
2747                 return -ENOMEM;
2748         }
2749
2750         if (!is_vf) {
2751                 ether_addr_copy((struct ether_addr *)edev->hwfns[0].
2752                                 hw_info.hw_mac_addr,
2753                                 &eth_dev->data->mac_addrs[0]);
2754                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2755                                 &adapter->primary_mac);
2756         } else {
2757                 ecore_vf_read_bulletin(ECORE_LEADING_HWFN(edev),
2758                                        &bulletin_change);
2759                 if (bulletin_change) {
2760                         is_mac_exist =
2761                             ecore_vf_bulletin_get_forced_mac(
2762                                                 ECORE_LEADING_HWFN(edev),
2763                                                 vf_mac,
2764                                                 &is_mac_forced);
2765                         if (is_mac_exist && is_mac_forced) {
2766                                 DP_INFO(edev, "VF macaddr received from PF\n");
2767                                 ether_addr_copy((struct ether_addr *)&vf_mac,
2768                                                 &eth_dev->data->mac_addrs[0]);
2769                                 ether_addr_copy(&eth_dev->data->mac_addrs[0],
2770                                                 &adapter->primary_mac);
2771                         } else {
2772                                 DP_ERR(edev, "No VF macaddr assigned\n");
2773                         }
2774                 }
2775         }
2776
2777         eth_dev->dev_ops = (is_vf) ? &qede_eth_vf_dev_ops : &qede_eth_dev_ops;
2778
2779         if (do_once) {
2780 #ifdef RTE_LIBRTE_QEDE_DEBUG_INFO
2781                 qede_print_adapter_info(adapter);
2782 #endif
2783                 do_once = false;
2784         }
2785
2786         adapter->num_tx_queues = 0;
2787         adapter->num_rx_queues = 0;
2788         SLIST_INIT(&adapter->fdir_info.fdir_list_head);
2789         SLIST_INIT(&adapter->vlan_list_head);
2790         SLIST_INIT(&adapter->uc_list_head);
2791         adapter->mtu = ETHER_MTU;
2792         adapter->new_mtu = ETHER_MTU;
2793         if (!is_vf)
2794                 if (qede_start_vport(adapter, adapter->mtu))
2795                         return -1;
2796
2797         DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n",
2798                 adapter->primary_mac.addr_bytes[0],
2799                 adapter->primary_mac.addr_bytes[1],
2800                 adapter->primary_mac.addr_bytes[2],
2801                 adapter->primary_mac.addr_bytes[3],
2802                 adapter->primary_mac.addr_bytes[4],
2803                 adapter->primary_mac.addr_bytes[5]);
2804
2805         DP_INFO(edev, "Device initialized\n");
2806
2807         return 0;
2808 }
2809
2810 static int qedevf_eth_dev_init(struct rte_eth_dev *eth_dev)
2811 {
2812         return qede_common_dev_init(eth_dev, 1);
2813 }
2814
2815 static int qede_eth_dev_init(struct rte_eth_dev *eth_dev)
2816 {
2817         return qede_common_dev_init(eth_dev, 0);
2818 }
2819
2820 static int qede_dev_common_uninit(struct rte_eth_dev *eth_dev)
2821 {
2822 #ifdef RTE_LIBRTE_QEDE_DEBUG_INIT
2823         struct qede_dev *qdev = eth_dev->data->dev_private;
2824         struct ecore_dev *edev = &qdev->edev;
2825
2826         PMD_INIT_FUNC_TRACE(edev);
2827 #endif
2828
2829         /* only uninitialize in the primary process */
2830         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2831                 return 0;
2832
2833         /* safe to close dev here */
2834         qede_dev_close(eth_dev);
2835
2836         eth_dev->dev_ops = NULL;
2837         eth_dev->rx_pkt_burst = NULL;
2838         eth_dev->tx_pkt_burst = NULL;
2839
2840         if (eth_dev->data->mac_addrs)
2841                 rte_free(eth_dev->data->mac_addrs);
2842
2843         eth_dev->data->mac_addrs = NULL;
2844
2845         return 0;
2846 }
2847
2848 static int qede_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2849 {
2850         return qede_dev_common_uninit(eth_dev);
2851 }
2852
2853 static int qedevf_eth_dev_uninit(struct rte_eth_dev *eth_dev)
2854 {
2855         return qede_dev_common_uninit(eth_dev);
2856 }
2857
2858 static const struct rte_pci_id pci_id_qedevf_map[] = {
2859 #define QEDEVF_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2860         {
2861                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_VF)
2862         },
2863         {
2864                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_IOV)
2865         },
2866         {
2867                 QEDEVF_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_IOV)
2868         },
2869         {.vendor_id = 0,}
2870 };
2871
2872 static const struct rte_pci_id pci_id_qede_map[] = {
2873 #define QEDE_RTE_PCI_DEVICE(dev) RTE_PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, dev)
2874         {
2875                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980E)
2876         },
2877         {
2878                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_NX2_57980S)
2879         },
2880         {
2881                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_40)
2882         },
2883         {
2884                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_25)
2885         },
2886         {
2887                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_100)
2888         },
2889         {
2890                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_57980S_50)
2891         },
2892         {
2893                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_50G)
2894         },
2895         {
2896                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_10G)
2897         },
2898         {
2899                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_40G)
2900         },
2901         {
2902                 QEDE_RTE_PCI_DEVICE(PCI_DEVICE_ID_QLOGIC_AH_25G)
2903         },
2904         {.vendor_id = 0,}
2905 };
2906
2907 static int qedevf_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2908         struct rte_pci_device *pci_dev)
2909 {
2910         return rte_eth_dev_pci_generic_probe(pci_dev,
2911                 sizeof(struct qede_dev), qedevf_eth_dev_init);
2912 }
2913
2914 static int qedevf_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2915 {
2916         return rte_eth_dev_pci_generic_remove(pci_dev, qedevf_eth_dev_uninit);
2917 }
2918
2919 static struct rte_pci_driver rte_qedevf_pmd = {
2920         .id_table = pci_id_qedevf_map,
2921         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2922         .probe = qedevf_eth_dev_pci_probe,
2923         .remove = qedevf_eth_dev_pci_remove,
2924 };
2925
2926 static int qede_eth_dev_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2927         struct rte_pci_device *pci_dev)
2928 {
2929         return rte_eth_dev_pci_generic_probe(pci_dev,
2930                 sizeof(struct qede_dev), qede_eth_dev_init);
2931 }
2932
2933 static int qede_eth_dev_pci_remove(struct rte_pci_device *pci_dev)
2934 {
2935         return rte_eth_dev_pci_generic_remove(pci_dev, qede_eth_dev_uninit);
2936 }
2937
2938 static struct rte_pci_driver rte_qede_pmd = {
2939         .id_table = pci_id_qede_map,
2940         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
2941         .probe = qede_eth_dev_pci_probe,
2942         .remove = qede_eth_dev_pci_remove,
2943 };
2944
2945 RTE_PMD_REGISTER_PCI(net_qede, rte_qede_pmd);
2946 RTE_PMD_REGISTER_PCI_TABLE(net_qede, pci_id_qede_map);
2947 RTE_PMD_REGISTER_KMOD_DEP(net_qede, "* igb_uio | uio_pci_generic | vfio-pci");
2948 RTE_PMD_REGISTER_PCI(net_qede_vf, rte_qedevf_pmd);
2949 RTE_PMD_REGISTER_PCI_TABLE(net_qede_vf, pci_id_qedevf_map);
2950 RTE_PMD_REGISTER_KMOD_DEP(net_qede_vf, "* igb_uio | vfio-pci");