drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_iova_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 int
  41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  42                     uint16_t nb_desc, unsigned int socket_id,
  43                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  44                     struct rte_mempool *mp)
  45 {
  46         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
  47         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
  48         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  49         struct qede_rx_queue *rxq;
  50         uint16_t max_rx_pkt_len;
  51         uint16_t bufsz;
  52         size_t size;
  53         int rc;
  54
  55         PMD_INIT_FUNC_TRACE(edev);
  56
  57         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
  58         if (!rte_is_power_of_2(nb_desc)) {
  59                 DP_ERR(edev, "Ring size %u is not power of 2\n",
  60                           nb_desc);
  61                 return -EINVAL;
  62         }
  63
  64         /* Free memory prior to re-allocation if needed... */
  65         if (dev->data->rx_queues[queue_idx] != NULL) {
  66                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
  67                 dev->data->rx_queues[queue_idx] = NULL;
  68         }
  69
  70         /* First allocate the rx queue data structure */
  71         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
  72                                  RTE_CACHE_LINE_SIZE, socket_id);
  73
  74         if (!rxq) {
  75                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
  76                           socket_id);
  77                 return -ENOMEM;
  78         }
  79
  80         rxq->qdev = qdev;
  81         rxq->mb_pool = mp;
  82         rxq->nb_rx_desc = nb_desc;
  83         rxq->queue_id = queue_idx;
  84         rxq->port_id = dev->data->port_id;
  85
  86         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
  87         qdev->mtu = max_rx_pkt_len;
  88
  89         /* Fix up RX buffer size */
  90         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
  91         if ((rxmode->enable_scatter)                    ||
  92             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
  93                 if (!dev->data->scattered_rx) {
  94                         DP_INFO(edev, "Forcing scatter-gather mode\n");
  95                         dev->data->scattered_rx = 1;
  96                 }
  97         }
  98
  99         if (dev->data->scattered_rx)
 100                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 101         else
 102                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 103         /* Align to cache-line size if needed */
 104         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 105
 106         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 107                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 108
 109         /* Allocate the parallel driver ring for Rx buffers */
 110         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 111         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 112                                              RTE_CACHE_LINE_SIZE, socket_id);
 113         if (!rxq->sw_rx_ring) {
 114                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 115                        " socket %u\n", socket_id);
 116                 rte_free(rxq);
 117                 return -ENOMEM;
 118         }
 119
 120         /* Allocate FW Rx ring  */
 121         rc = qdev->ops->common->chain_alloc(edev,
 122                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 123                                             ECORE_CHAIN_MODE_NEXT_PTR,
 124                                             ECORE_CHAIN_CNT_TYPE_U16,
 125                                             rxq->nb_rx_desc,
 126                                             sizeof(struct eth_rx_bd),
 127                                             &rxq->rx_bd_ring,
 128                                             NULL);
 129
 130         if (rc != ECORE_SUCCESS) {
 131                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 132                        " on socket %u\n", socket_id);
 133                 rte_free(rxq->sw_rx_ring);
 134                 rte_free(rxq);
 135                 return -ENOMEM;
 136         }
 137
 138         /* Allocate FW completion ring */
 139         rc = qdev->ops->common->chain_alloc(edev,
 140                                             ECORE_CHAIN_USE_TO_CONSUME,
 141                                             ECORE_CHAIN_MODE_PBL,
 142                                             ECORE_CHAIN_CNT_TYPE_U16,
 143                                             rxq->nb_rx_desc,
 144                                             sizeof(union eth_rx_cqe),
 145                                             &rxq->rx_comp_ring,
 146                                             NULL);
 147
 148         if (rc != ECORE_SUCCESS) {
 149                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 150                        " on socket %u\n", socket_id);
 151                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 152                 rte_free(rxq->sw_rx_ring);
 153                 rte_free(rxq);
 154                 return -ENOMEM;
 155         }
 156
 157         dev->data->rx_queues[queue_idx] = rxq;
 158         qdev->fp_array[queue_idx].rxq = rxq;
 159
 160         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 161                   queue_idx, nb_desc, qdev->mtu, socket_id);
 162
 163         return 0;
 164 }
 165
 166 static void
 167 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 168                     struct qede_rx_queue *rxq)
 169 {
 170         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 171         ecore_chain_reset(&rxq->rx_bd_ring);
 172         ecore_chain_reset(&rxq->rx_comp_ring);
 173         rxq->sw_rx_prod = 0;
 174         rxq->sw_rx_cons = 0;
 175         *rxq->hw_cons_ptr = 0;
 176 }
 177
 178 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 179 {
 180         uint16_t i;
 181
 182         if (rxq->sw_rx_ring) {
 183                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 184                         if (rxq->sw_rx_ring[i].mbuf) {
 185                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 186                                 rxq->sw_rx_ring[i].mbuf = NULL;
 187                         }
 188                 }
 189         }
 190 }
 191
 192 void qede_rx_queue_release(void *rx_queue)
 193 {
 194         struct qede_rx_queue *rxq = rx_queue;
 195
 196         if (rxq) {
 197                 qede_rx_queue_release_mbufs(rxq);
 198                 rte_free(rxq->sw_rx_ring);
 199                 rte_free(rxq);
 200         }
 201 }
 202
 203 /* Stops a given RX queue in the HW */
 204 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 205 {
 206         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 207         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 208         struct ecore_hwfn *p_hwfn;
 209         struct qede_rx_queue *rxq;
 210         int hwfn_index;
 211         int rc;
 212
 213         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 214                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 215                 hwfn_index = rx_queue_id % edev->num_hwfns;
 216                 p_hwfn = &edev->hwfns[hwfn_index];
 217                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 218                                 true, false);
 219                 if (rc != ECORE_SUCCESS) {
 220                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 221                         return -1;
 222                 }
 223                 qede_rx_queue_release_mbufs(rxq);
 224                 qede_rx_queue_reset(qdev, rxq);
 225                 eth_dev->data->rx_queue_state[rx_queue_id] =
 226                         RTE_ETH_QUEUE_STATE_STOPPED;
 227                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 228         } else {
 229                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 230                 rc = -EINVAL;
 231         }
 232
 233         return rc;
 234 }
 235
 236 int
 237 qede_tx_queue_setup(struct rte_eth_dev *dev,
 238                     uint16_t queue_idx,
 239                     uint16_t nb_desc,
 240                     unsigned int socket_id,
 241                     const struct rte_eth_txconf *tx_conf)
 242 {
 243         struct qede_dev *qdev = dev->data->dev_private;
 244         struct ecore_dev *edev = &qdev->edev;
 245         struct qede_tx_queue *txq;
 246         int rc;
 247
 248         PMD_INIT_FUNC_TRACE(edev);
 249
 250         if (!rte_is_power_of_2(nb_desc)) {
 251                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 252                        nb_desc);
 253                 return -EINVAL;
 254         }
 255
 256         /* Free memory prior to re-allocation if needed... */
 257         if (dev->data->tx_queues[queue_idx] != NULL) {
 258                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 259                 dev->data->tx_queues[queue_idx] = NULL;
 260         }
 261
 262         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 263                                  RTE_CACHE_LINE_SIZE, socket_id);
 264
 265         if (txq == NULL) {
 266                 DP_ERR(edev,
 267                        "Unable to allocate memory for txq on socket %u",
 268                        socket_id);
 269                 return -ENOMEM;
 270         }
 271
 272         txq->nb_tx_desc = nb_desc;
 273         txq->qdev = qdev;
 274         txq->port_id = dev->data->port_id;
 275
 276         rc = qdev->ops->common->chain_alloc(edev,
 277                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 278                                             ECORE_CHAIN_MODE_PBL,
 279                                             ECORE_CHAIN_CNT_TYPE_U16,
 280                                             txq->nb_tx_desc,
 281                                             sizeof(union eth_tx_bd_types),
 282                                             &txq->tx_pbl,
 283                                             NULL);
 284         if (rc != ECORE_SUCCESS) {
 285                 DP_ERR(edev,
 286                        "Unable to allocate memory for txbd ring on socket %u",
 287                        socket_id);
 288                 qede_tx_queue_release(txq);
 289                 return -ENOMEM;
 290         }
 291
 292         /* Allocate software ring */
 293         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 294                                              (sizeof(struct qede_tx_entry) *
 295                                               txq->nb_tx_desc),
 296                                              RTE_CACHE_LINE_SIZE, socket_id);
 297
 298         if (!txq->sw_tx_ring) {
 299                 DP_ERR(edev,
 300                        "Unable to allocate memory for txbd ring on socket %u",
 301                        socket_id);
 302                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 303                 qede_tx_queue_release(txq);
 304                 return -ENOMEM;
 305         }
 306
 307         txq->queue_id = queue_idx;
 308
 309         txq->nb_tx_avail = txq->nb_tx_desc;
 310
 311         txq->tx_free_thresh =
 312             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 313             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 314
 315         dev->data->tx_queues[queue_idx] = txq;
 316         qdev->fp_array[queue_idx].txq = txq;
 317
 318         DP_INFO(edev,
 319                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 320                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 321
 322         return 0;
 323 }
 324
 325 static void
 326 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 327                     struct qede_tx_queue *txq)
 328 {
 329         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 330         ecore_chain_reset(&txq->tx_pbl);
 331         txq->sw_tx_cons = 0;
 332         txq->sw_tx_prod = 0;
 333         *txq->hw_cons_ptr = 0;
 334 }
 335
 336 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 337 {
 338         uint16_t i;
 339
 340         if (txq->sw_tx_ring) {
 341                 for (i = 0; i < txq->nb_tx_desc; i++) {
 342                         if (txq->sw_tx_ring[i].mbuf) {
 343                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
 344                                 txq->sw_tx_ring[i].mbuf = NULL;
 345                         }
 346                 }
 347         }
 348 }
 349
 350 void qede_tx_queue_release(void *tx_queue)
 351 {
 352         struct qede_tx_queue *txq = tx_queue;
 353
 354         if (txq) {
 355                 qede_tx_queue_release_mbufs(txq);
 356                 rte_free(txq->sw_tx_ring);
 357                 rte_free(txq);
 358         }
 359 }
 360
 361 /* This function allocates fast-path status block memory */
 362 static int
 363 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 364                   uint16_t sb_id)
 365 {
 366         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 367         struct status_block_e4 *sb_virt;
 368         dma_addr_t sb_phys;
 369         int rc;
 370
 371         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 372                                           sizeof(struct status_block_e4));
 373         if (!sb_virt) {
 374                 DP_ERR(edev, "Status block allocation failed\n");
 375                 return -ENOMEM;
 376         }
 377         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 378                                         sb_phys, sb_id);
 379         if (rc) {
 380                 DP_ERR(edev, "Status block initialization failed\n");
 381                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 382                                        sizeof(struct status_block_e4));
 383                 return rc;
 384         }
 385
 386         return 0;
 387 }
 388
 389 int qede_alloc_fp_resc(struct qede_dev *qdev)
 390 {
 391         struct ecore_dev *edev = &qdev->edev;
 392         struct qede_fastpath *fp;
 393         uint32_t num_sbs;
 394         uint16_t sb_idx;
 395
 396         if (IS_VF(edev))
 397                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 398         else
 399                 num_sbs = ecore_cxt_get_proto_cid_count
 400                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 401
 402         if (num_sbs == 0) {
 403                 DP_ERR(edev, "No status blocks available\n");
 404                 return -EINVAL;
 405         }
 406
 407         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 408                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 409
 410         if (!qdev->fp_array) {
 411                 DP_ERR(edev, "fp array allocation failed\n");
 412                 return -ENOMEM;
 413         }
 414
 415         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 416                         sizeof(*qdev->fp_array));
 417
 418         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 419                 fp = &qdev->fp_array[sb_idx];
 420                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 421                                 RTE_CACHE_LINE_SIZE);
 422                 if (!fp->sb_info) {
 423                         DP_ERR(edev, "FP sb_info allocation fails\n");
 424                         return -1;
 425                 }
 426                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 427                         DP_ERR(edev, "FP status block allocation fails\n");
 428                         return -1;
 429                 }
 430                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 431                                 fp->sb_info->igu_sb_id);
 432         }
 433
 434         return 0;
 435 }
 436
 437 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 438 {
 439         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 440         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 441         struct qede_fastpath *fp;
 442         struct qede_rx_queue *rxq;
 443         struct qede_tx_queue *txq;
 444         uint16_t sb_idx;
 445         uint8_t i;
 446
 447         PMD_INIT_FUNC_TRACE(edev);
 448
 449         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 450                 fp = &qdev->fp_array[sb_idx];
 451                 DP_INFO(edev, "Free sb_info index 0x%x\n",
 452                                 fp->sb_info->igu_sb_id);
 453                 if (fp->sb_info) {
 454                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 455                                 fp->sb_info->sb_phys,
 456                                 sizeof(struct status_block_e4));
 457                         rte_free(fp->sb_info);
 458                         fp->sb_info = NULL;
 459                 }
 460         }
 461
 462         /* Free packet buffers and ring memories */
 463         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 464                 if (eth_dev->data->rx_queues[i]) {
 465                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 466                         rxq = eth_dev->data->rx_queues[i];
 467                         qdev->ops->common->chain_free(edev,
 468                                                       &rxq->rx_bd_ring);
 469                         qdev->ops->common->chain_free(edev,
 470                                                       &rxq->rx_comp_ring);
 471                         eth_dev->data->rx_queues[i] = NULL;
 472                 }
 473         }
 474
 475         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 476                 if (eth_dev->data->tx_queues[i]) {
 477                         txq = eth_dev->data->tx_queues[i];
 478                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 479                         qdev->ops->common->chain_free(edev,
 480                                                       &txq->tx_pbl);
 481                         eth_dev->data->tx_queues[i] = NULL;
 482                 }
 483         }
 484
 485         if (qdev->fp_array)
 486                 rte_free(qdev->fp_array);
 487         qdev->fp_array = NULL;
 488 }
 489
 490 static inline void
 491 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 492                     struct qede_rx_queue *rxq)
 493 {
 494         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 495         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 496         struct eth_rx_prod_data rx_prods = { 0 };
 497
 498         /* Update producers */
 499         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 500         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 501
 502         /* Make sure that the BD and SGE data is updated before updating the
 503          * producers since FW might read the BD/SGE right after the producer
 504          * is updated.
 505          */
 506         rte_wmb();
 507
 508         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 509                         (uint32_t *)&rx_prods);
 510
 511         /* mmiowb is needed to synchronize doorbell writes from more than one
 512          * processor. It guarantees that the write arrives to the device before
 513          * the napi lock is released and another qede_poll is called (possibly
 514          * on another CPU). Without this barrier, the next doorbell can bypass
 515          * this doorbell. This is applicable to IA64/Altix systems.
 516          */
 517         rte_wmb();
 518
 519         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 520 }
 521
 522 /* Starts a given RX queue in HW */
 523 static int
 524 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 525 {
 526         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 527         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 528         struct ecore_queue_start_common_params params;
 529         struct ecore_rxq_start_ret_params ret_params;
 530         struct qede_rx_queue *rxq;
 531         struct qede_fastpath *fp;
 532         struct ecore_hwfn *p_hwfn;
 533         dma_addr_t p_phys_table;
 534         uint16_t page_cnt;
 535         uint16_t j;
 536         int hwfn_index;
 537         int rc;
 538
 539         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 540                 fp = &qdev->fp_array[rx_queue_id];
 541                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 542                 /* Allocate buffers for the Rx ring */
 543                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 544                         rc = qede_alloc_rx_buffer(rxq);
 545                         if (rc) {
 546                                 DP_ERR(edev, "RX buffer allocation failed"
 547                                                 " for rxq = %u\n", rx_queue_id);
 548                                 return -ENOMEM;
 549                         }
 550                 }
 551                 /* disable interrupts */
 552                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 553                 /* Prepare ramrod */
 554                 memset(&params, 0, sizeof(params));
 555                 params.queue_id = rx_queue_id / edev->num_hwfns;
 556                 params.vport_id = 0;
 557                 params.stats_id = params.vport_id;
 558                 params.p_sb = fp->sb_info;
 559                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 560                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 561                 params.sb_idx = RX_PI;
 562                 hwfn_index = rx_queue_id % edev->num_hwfns;
 563                 p_hwfn = &edev->hwfns[hwfn_index];
 564                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 565                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 566                 memset(&ret_params, 0, sizeof(ret_params));
 567                 rc = ecore_eth_rx_queue_start(p_hwfn,
 568                                 p_hwfn->hw_info.opaque_fid,
 569                                 &params, fp->rxq->rx_buf_size,
 570                                 fp->rxq->rx_bd_ring.p_phys_addr,
 571                                 p_phys_table, page_cnt,
 572                                 &ret_params);
 573                 if (rc) {
 574                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 575                                         rx_queue_id, rc);
 576                         return -1;
 577                 }
 578                 /* Update with the returned parameters */
 579                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 580                 fp->rxq->handle = ret_params.p_handle;
 581
 582                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
 583                 qede_update_rx_prod(qdev, fp->rxq);
 584                 eth_dev->data->rx_queue_state[rx_queue_id] =
 585                         RTE_ETH_QUEUE_STATE_STARTED;
 586                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 587         } else {
 588                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 589                 rc = -EINVAL;
 590         }
 591
 592         return rc;
 593 }
 594
 595 static int
 596 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 597 {
 598         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 599         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 600         struct ecore_queue_start_common_params params;
 601         struct ecore_txq_start_ret_params ret_params;
 602         struct ecore_hwfn *p_hwfn;
 603         dma_addr_t p_phys_table;
 604         struct qede_tx_queue *txq;
 605         struct qede_fastpath *fp;
 606         uint16_t page_cnt;
 607         int hwfn_index;
 608         int rc;
 609
 610         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 611                 txq = eth_dev->data->tx_queues[tx_queue_id];
 612                 fp = &qdev->fp_array[tx_queue_id];
 613                 memset(&params, 0, sizeof(params));
 614                 params.queue_id = tx_queue_id / edev->num_hwfns;
 615                 params.vport_id = 0;
 616                 params.stats_id = params.vport_id;
 617                 params.p_sb = fp->sb_info;
 618                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 619                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 620                 params.sb_idx = TX_PI(0); /* tc = 0 */
 621                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 622                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 623                 hwfn_index = tx_queue_id % edev->num_hwfns;
 624                 p_hwfn = &edev->hwfns[hwfn_index];
 625                 if (qdev->dev_info.is_legacy)
 626                         fp->txq->is_legacy = true;
 627                 rc = ecore_eth_tx_queue_start(p_hwfn,
 628                                 p_hwfn->hw_info.opaque_fid,
 629                                 &params, 0 /* tc */,
 630                                 p_phys_table, page_cnt,
 631                                 &ret_params);
 632                 if (rc != ECORE_SUCCESS) {
 633                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 634                                         tx_queue_id, rc);
 635                         return -1;
 636                 }
 637                 txq->doorbell_addr = ret_params.p_doorbell;
 638                 txq->handle = ret_params.p_handle;
 639
 640                 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
 641                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 642                                 DB_DEST_XCM);
 643                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 644                                 DB_AGG_CMD_SET);
 645                 SET_FIELD(txq->tx_db.data.params,
 646                                 ETH_DB_DATA_AGG_VAL_SEL,
 647                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 648                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 649                 eth_dev->data->tx_queue_state[tx_queue_id] =
 650                         RTE_ETH_QUEUE_STATE_STARTED;
 651                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 652         } else {
 653                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 654                 rc = -EINVAL;
 655         }
 656
 657         return rc;
 658 }
 659
 660 static inline void
 661 qede_free_tx_pkt(struct qede_tx_queue *txq)
 662 {
 663         struct rte_mbuf *mbuf;
 664         uint16_t nb_segs;
 665         uint16_t idx;
 666
 667         idx = TX_CONS(txq);
 668         mbuf = txq->sw_tx_ring[idx].mbuf;
 669         if (mbuf) {
 670                 nb_segs = mbuf->nb_segs;
 671                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 672                 while (nb_segs) {
 673                         /* It's like consuming rxbuf in recv() */
 674                         ecore_chain_consume(&txq->tx_pbl);
 675                         txq->nb_tx_avail++;
 676                         nb_segs--;
 677                 }
 678                 rte_pktmbuf_free(mbuf);
 679                 txq->sw_tx_ring[idx].mbuf = NULL;
 680                 txq->sw_tx_cons++;
 681                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 682         } else {
 683                 ecore_chain_consume(&txq->tx_pbl);
 684                 txq->nb_tx_avail++;
 685         }
 686 }
 687
 688 static inline void
 689 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 690                       struct qede_tx_queue *txq)
 691 {
 692         uint16_t hw_bd_cons;
 693 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 694         uint16_t sw_tx_cons;
 695 #endif
 696
 697         rte_compiler_barrier();
 698         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 699 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 700         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 701         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 702                    abs(hw_bd_cons - sw_tx_cons));
 703 #endif
 704         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
 705                 qede_free_tx_pkt(txq);
 706 }
 707
 708 static int qede_drain_txq(struct qede_dev *qdev,
 709                           struct qede_tx_queue *txq, bool allow_drain)
 710 {
 711         struct ecore_dev *edev = &qdev->edev;
 712         int rc, cnt = 1000;
 713
 714         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 715                 qede_process_tx_compl(edev, txq);
 716                 if (!cnt) {
 717                         if (allow_drain) {
 718                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 719                                           "requesting MCP to drain\n",
 720                                           txq->queue_id);
 721                                 rc = qdev->ops->common->drain(edev);
 722                                 if (rc)
 723                                         return rc;
 724                                 return qede_drain_txq(qdev, txq, false);
 725                         }
 726                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 727                                   "PROD=%d, CONS=%d\n",
 728                                   txq->queue_id, txq->sw_tx_prod,
 729                                   txq->sw_tx_cons);
 730                         return -1;
 731                 }
 732                 cnt--;
 733                 DELAY(1000);
 734                 rte_compiler_barrier();
 735         }
 736
 737         /* FW finished processing, wait for HW to transmit all tx packets */
 738         DELAY(2000);
 739
 740         return 0;
 741 }
 742
 743 /* Stops a given TX queue in the HW */
 744 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 745 {
 746         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 747         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 748         struct ecore_hwfn *p_hwfn;
 749         struct qede_tx_queue *txq;
 750         int hwfn_index;
 751         int rc;
 752
 753         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 754                 txq = eth_dev->data->tx_queues[tx_queue_id];
 755                 /* Drain txq */
 756                 if (qede_drain_txq(qdev, txq, true))
 757                         return -1; /* For the lack of retcodes */
 758                 /* Stop txq */
 759                 hwfn_index = tx_queue_id % edev->num_hwfns;
 760                 p_hwfn = &edev->hwfns[hwfn_index];
 761                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 762                 if (rc != ECORE_SUCCESS) {
 763                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 764                         return -1;
 765                 }
 766                 qede_tx_queue_release_mbufs(txq);
 767                 qede_tx_queue_reset(qdev, txq);
 768                 eth_dev->data->tx_queue_state[tx_queue_id] =
 769                         RTE_ETH_QUEUE_STATE_STOPPED;
 770                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 771         } else {
 772                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 773                 rc = -EINVAL;
 774         }
 775
 776         return rc;
 777 }
 778
 779 int qede_start_queues(struct rte_eth_dev *eth_dev)
 780 {
 781         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 782         uint8_t id;
 783         int rc = -1;
 784
 785         for_each_rss(id) {
 786                 rc = qede_rx_queue_start(eth_dev, id);
 787                 if (rc != ECORE_SUCCESS)
 788                         return -1;
 789         }
 790
 791         for_each_tss(id) {
 792                 rc = qede_tx_queue_start(eth_dev, id);
 793                 if (rc != ECORE_SUCCESS)
 794                         return -1;
 795         }
 796
 797         return rc;
 798 }
 799
 800 void qede_stop_queues(struct rte_eth_dev *eth_dev)
 801 {
 802         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 803         uint8_t id;
 804
 805         /* Stopping RX/TX queues */
 806         for_each_tss(id) {
 807                 qede_tx_queue_stop(eth_dev, id);
 808         }
 809
 810         for_each_rss(id) {
 811                 qede_rx_queue_stop(eth_dev, id);
 812         }
 813 }
 814
 815 static bool qede_tunn_exist(uint16_t flag)
 816 {
 817         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 818                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 819 }
 820
 821 /*
 822  * qede_check_tunn_csum_l4:
 823  * Returns:
 824  * 1 : If L4 csum is enabled AND if the validation has failed.
 825  * 0 : Otherwise
 826  */
 827 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 828 {
 829         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 830              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 831                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 832                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 833
 834         return 0;
 835 }
 836
 837 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 838 {
 839         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 840              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 841                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 842                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 843
 844         return 0;
 845 }
 846
 847 /* Returns outer L3 and L4 packet_type for tunneled packets */
 848 static inline uint32_t qede_rx_cqe_to_pkt_type_outer(struct rte_mbuf *m)
 849 {
 850         uint32_t packet_type = RTE_PTYPE_UNKNOWN;
 851         struct ether_hdr *eth_hdr;
 852         struct ipv4_hdr *ipv4_hdr;
 853         struct ipv6_hdr *ipv6_hdr;
 854
 855         eth_hdr = rte_pktmbuf_mtod(m, struct ether_hdr *);
 856         if (eth_hdr->ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv4)) {
 857                 packet_type |= RTE_PTYPE_L3_IPV4;
 858                 ipv4_hdr = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 859                                                    sizeof(struct ether_hdr));
 860                 if (ipv4_hdr->next_proto_id == IPPROTO_TCP)
 861                         packet_type |= RTE_PTYPE_L4_TCP;
 862                 else if (ipv4_hdr->next_proto_id == IPPROTO_UDP)
 863                         packet_type |= RTE_PTYPE_L4_UDP;
 864         } else if (eth_hdr->ether_type == rte_cpu_to_be_16(ETHER_TYPE_IPv6)) {
 865                 packet_type |= RTE_PTYPE_L3_IPV6;
 866                 ipv6_hdr = rte_pktmbuf_mtod_offset(m, struct ipv6_hdr *,
 867                                                    sizeof(struct ether_hdr));
 868                 if (ipv6_hdr->proto == IPPROTO_TCP)
 869                         packet_type |= RTE_PTYPE_L4_TCP;
 870                 else if (ipv6_hdr->proto == IPPROTO_UDP)
 871                         packet_type |= RTE_PTYPE_L4_UDP;
 872         }
 873
 874         return packet_type;
 875 }
 876
 877 static inline uint32_t qede_rx_cqe_to_pkt_type_inner(uint16_t flags)
 878 {
 879         uint16_t val;
 880
 881         /* Lookup table */
 882         static const uint32_t
 883         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 884                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_INNER_L3_IPV4          |
 885                                        RTE_PTYPE_INNER_L2_ETHER,
 886                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_INNER_L3_IPV6          |
 887                                        RTE_PTYPE_INNER_L2_ETHER,
 888                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_INNER_L3_IPV4      |
 889                                            RTE_PTYPE_INNER_L4_TCP       |
 890                                            RTE_PTYPE_INNER_L2_ETHER,
 891                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_INNER_L3_IPV6      |
 892                                            RTE_PTYPE_INNER_L4_TCP       |
 893                                            RTE_PTYPE_INNER_L2_ETHER,
 894                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_INNER_L3_IPV4      |
 895                                            RTE_PTYPE_INNER_L4_UDP       |
 896                                            RTE_PTYPE_INNER_L2_ETHER,
 897                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_INNER_L3_IPV6      |
 898                                            RTE_PTYPE_INNER_L4_UDP       |
 899                                            RTE_PTYPE_INNER_L2_ETHER,
 900                 /* Frags with no VLAN */
 901                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_INNER_L3_IPV4     |
 902                                             RTE_PTYPE_INNER_L4_FRAG     |
 903                                             RTE_PTYPE_INNER_L2_ETHER,
 904                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_INNER_L3_IPV6     |
 905                                             RTE_PTYPE_INNER_L4_FRAG     |
 906                                             RTE_PTYPE_INNER_L2_ETHER,
 907                 /* VLANs */
 908                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_INNER_L3_IPV4     |
 909                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 910                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_INNER_L3_IPV6     |
 911                                             RTE_PTYPE_INNER_L2_ETHER_VLAN,
 912                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 913                                                 RTE_PTYPE_INNER_L4_TCP  |
 914                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 915                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 916                                                 RTE_PTYPE_INNER_L4_TCP  |
 917                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 918                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV4 |
 919                                                 RTE_PTYPE_INNER_L4_UDP  |
 920                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 921                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_INNER_L3_IPV6 |
 922                                                 RTE_PTYPE_INNER_L4_UDP  |
 923                                                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
 924                 /* Frags with VLAN */
 925                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV4 |
 926                                                  RTE_PTYPE_INNER_L4_FRAG |
 927                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 928                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_INNER_L3_IPV6 |
 929                                                  RTE_PTYPE_INNER_L4_FRAG |
 930                                                  RTE_PTYPE_INNER_L2_ETHER_VLAN,
 931         };
 932
 933         /* Bits (0..3) provides L3/L4 protocol type */
 934         /* Bits (4,5) provides frag and VLAN info */
 935         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 936                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 937                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 938                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
 939                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
 940                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
 941                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
 942                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
 943
 944         if (val < QEDE_PKT_TYPE_MAX)
 945                 return ptype_lkup_tbl[val];
 946
 947         return RTE_PTYPE_UNKNOWN;
 948 }
 949
 950 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 951 {
 952         uint16_t val;
 953
 954         /* Lookup table */
 955         static const uint32_t
 956         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 957                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L2_ETHER,
 958                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L2_ETHER,
 959                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4    |
 960                                            RTE_PTYPE_L4_TCP     |
 961                                            RTE_PTYPE_L2_ETHER,
 962                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6    |
 963                                            RTE_PTYPE_L4_TCP     |
 964                                            RTE_PTYPE_L2_ETHER,
 965                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4    |
 966                                            RTE_PTYPE_L4_UDP     |
 967                                            RTE_PTYPE_L2_ETHER,
 968                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6    |
 969                                            RTE_PTYPE_L4_UDP     |
 970                                            RTE_PTYPE_L2_ETHER,
 971                 /* Frags with no VLAN */
 972                 [QEDE_PKT_TYPE_IPV4_FRAG] = RTE_PTYPE_L3_IPV4   |
 973                                             RTE_PTYPE_L4_FRAG   |
 974                                             RTE_PTYPE_L2_ETHER,
 975                 [QEDE_PKT_TYPE_IPV6_FRAG] = RTE_PTYPE_L3_IPV6   |
 976                                             RTE_PTYPE_L4_FRAG   |
 977                                             RTE_PTYPE_L2_ETHER,
 978                 /* VLANs */
 979                 [QEDE_PKT_TYPE_IPV4_VLAN] = RTE_PTYPE_L3_IPV4           |
 980                                             RTE_PTYPE_L2_ETHER_VLAN,
 981                 [QEDE_PKT_TYPE_IPV6_VLAN] = RTE_PTYPE_L3_IPV6           |
 982                                             RTE_PTYPE_L2_ETHER_VLAN,
 983                 [QEDE_PKT_TYPE_IPV4_TCP_VLAN] = RTE_PTYPE_L3_IPV4       |
 984                                                 RTE_PTYPE_L4_TCP        |
 985                                                 RTE_PTYPE_L2_ETHER_VLAN,
 986                 [QEDE_PKT_TYPE_IPV6_TCP_VLAN] = RTE_PTYPE_L3_IPV6       |
 987                                                 RTE_PTYPE_L4_TCP        |
 988                                                 RTE_PTYPE_L2_ETHER_VLAN,
 989                 [QEDE_PKT_TYPE_IPV4_UDP_VLAN] = RTE_PTYPE_L3_IPV4       |
 990                                                 RTE_PTYPE_L4_UDP        |
 991                                                 RTE_PTYPE_L2_ETHER_VLAN,
 992                 [QEDE_PKT_TYPE_IPV6_UDP_VLAN] = RTE_PTYPE_L3_IPV6       |
 993                                                 RTE_PTYPE_L4_UDP        |
 994                                                 RTE_PTYPE_L2_ETHER_VLAN,
 995                 /* Frags with VLAN */
 996                 [QEDE_PKT_TYPE_IPV4_VLAN_FRAG] = RTE_PTYPE_L3_IPV4      |
 997                                                  RTE_PTYPE_L4_FRAG      |
 998                                                  RTE_PTYPE_L2_ETHER_VLAN,
 999                 [QEDE_PKT_TYPE_IPV6_VLAN_FRAG] = RTE_PTYPE_L3_IPV6      |
1000                                                  RTE_PTYPE_L4_FRAG      |
1001                                                  RTE_PTYPE_L2_ETHER_VLAN,
1002         };
1003
1004         /* Bits (0..3) provides L3/L4 protocol type */
1005         /* Bits (4,5) provides frag and VLAN info */
1006         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
1007                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
1008                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
1009                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT) |
1010                (PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK <<
1011                 PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT) |
1012                 (PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK <<
1013                  PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT)) & flags;
1014
1015         if (val < QEDE_PKT_TYPE_MAX)
1016                 return ptype_lkup_tbl[val];
1017
1018         return RTE_PTYPE_UNKNOWN;
1019 }
1020
1021 static inline uint8_t
1022 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
1023 {
1024         struct ipv4_hdr *ip;
1025         uint16_t pkt_csum;
1026         uint16_t calc_csum;
1027         uint16_t val;
1028
1029         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
1030                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
1031
1032         if (unlikely(val)) {
1033                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
1034                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
1035                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
1036                                            sizeof(struct ether_hdr));
1037                         pkt_csum = ip->hdr_checksum;
1038                         ip->hdr_checksum = 0;
1039                         calc_csum = rte_ipv4_cksum(ip);
1040                         ip->hdr_checksum = pkt_csum;
1041                         return (calc_csum != pkt_csum);
1042                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
1043                         return 1;
1044                 }
1045         }
1046         return 0;
1047 }
1048
1049 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
1050 {
1051         ecore_chain_consume(&rxq->rx_bd_ring);
1052         rxq->sw_rx_cons++;
1053 }
1054
1055 static inline void
1056 qede_reuse_page(__rte_unused struct qede_dev *qdev,
1057                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
1058 {
1059         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
1060         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1061         struct qede_rx_entry *curr_prod;
1062         dma_addr_t new_mapping;
1063
1064         curr_prod = &rxq->sw_rx_ring[idx];
1065         *curr_prod = *curr_cons;
1066
1067         new_mapping = rte_mbuf_data_iova_default(curr_prod->mbuf) +
1068                       curr_prod->page_offset;
1069
1070         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
1071         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
1072
1073         rxq->sw_rx_prod++;
1074 }
1075
1076 static inline void
1077 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
1078                         struct qede_dev *qdev, uint8_t count)
1079 {
1080         struct qede_rx_entry *curr_cons;
1081
1082         for (; count > 0; count--) {
1083                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
1084                 qede_reuse_page(qdev, rxq, curr_cons);
1085                 qede_rx_bd_ring_consume(rxq);
1086         }
1087 }
1088
1089 static inline void
1090 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
1091                                      struct qede_rx_queue *rxq,
1092                                      uint8_t agg_index, uint16_t len)
1093 {
1094         struct qede_agg_info *tpa_info;
1095         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
1096         uint16_t cons_idx;
1097
1098         /* Under certain conditions it is possible that FW may not consume
1099          * additional or new BD. So decision to consume the BD must be made
1100          * based on len_list[0].
1101          */
1102         if (rte_le_to_cpu_16(len)) {
1103                 tpa_info = &rxq->tpa_info[agg_index];
1104                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1105                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
1106                 assert(curr_frag);
1107                 curr_frag->nb_segs = 1;
1108                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
1109                 curr_frag->data_len = curr_frag->pkt_len;
1110                 tpa_info->tpa_tail->next = curr_frag;
1111                 tpa_info->tpa_tail = curr_frag;
1112                 qede_rx_bd_ring_consume(rxq);
1113                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1114                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
1115                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
1116                         rxq->rx_alloc_errors++;
1117                 }
1118         }
1119 }
1120
1121 static inline void
1122 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
1123                              struct qede_rx_queue *rxq,
1124                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
1125 {
1126         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
1127                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
1128         /* only len_list[0] will have value */
1129         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1130                                              cqe->len_list[0]);
1131 }
1132
1133 static inline void
1134 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
1135                             struct qede_rx_queue *rxq,
1136                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
1137 {
1138         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
1139
1140         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
1141                                              cqe->len_list[0]);
1142         /* Update total length and frags based on end TPA */
1143         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
1144         /* TODO:  Add Sanity Checks */
1145         rx_mb->nb_segs = cqe->num_of_bds;
1146         rx_mb->pkt_len = cqe->total_packet_len;
1147
1148         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1149                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1150                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1151                    rx_mb->pkt_len);
1152 }
1153
1154 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1155 {
1156         uint32_t val;
1157
1158         /* Lookup table */
1159         static const uint32_t
1160         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1161                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1162                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1163                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1164                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1165                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1166                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1167                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1168                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1169                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1170                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1171                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1172                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1173                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1174                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1175                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1176                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1177                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1178                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1179                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1180                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1181                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1182                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1183                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1184                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1185                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1186                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1187                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1188                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1189                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1190                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1191                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1192                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1193                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1194                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1195                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1196                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1197                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1198                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1199                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1200                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1201         };
1202
1203         /* Cover bits[4-0] to include tunn_type and next protocol */
1204         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1205                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1206                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1207                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1208
1209         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1210                 return ptype_tunn_lkup_tbl[val];
1211         else
1212                 return RTE_PTYPE_UNKNOWN;
1213 }
1214
1215 static inline int
1216 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1217                      uint8_t num_segs, uint16_t pkt_len)
1218 {
1219         struct qede_rx_queue *rxq = p_rxq;
1220         struct qede_dev *qdev = rxq->qdev;
1221         register struct rte_mbuf *seg1 = NULL;
1222         register struct rte_mbuf *seg2 = NULL;
1223         uint16_t sw_rx_index;
1224         uint16_t cur_size;
1225
1226         seg1 = rx_mb;
1227         while (num_segs) {
1228                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1229                                                         pkt_len;
1230                 if (unlikely(!cur_size)) {
1231                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1232                                    " left for mapping jumbo\n", num_segs);
1233                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1234                         return -EINVAL;
1235                 }
1236                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1237                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1238                 qede_rx_bd_ring_consume(rxq);
1239                 pkt_len -= cur_size;
1240                 seg2->data_len = cur_size;
1241                 seg1->next = seg2;
1242                 seg1 = seg1->next;
1243                 num_segs--;
1244                 rxq->rx_segs++;
1245         }
1246
1247         return 0;
1248 }
1249
1250 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1251 static inline void
1252 print_rx_bd_info(struct rte_mbuf *m, struct qede_rx_queue *rxq,
1253                  uint8_t bitfield)
1254 {
1255         PMD_RX_LOG(INFO, rxq,
1256                 "len 0x%x bf 0x%x hash_val 0x%x"
1257                 " ol_flags 0x%04lx l2=%s l3=%s l4=%s tunn=%s"
1258                 " inner_l2=%s inner_l3=%s inner_l4=%s\n",
1259                 m->data_len, bitfield, m->hash.rss,
1260                 (unsigned long)m->ol_flags,
1261                 rte_get_ptype_l2_name(m->packet_type),
1262                 rte_get_ptype_l3_name(m->packet_type),
1263                 rte_get_ptype_l4_name(m->packet_type),
1264                 rte_get_ptype_tunnel_name(m->packet_type),
1265                 rte_get_ptype_inner_l2_name(m->packet_type),
1266                 rte_get_ptype_inner_l3_name(m->packet_type),
1267                 rte_get_ptype_inner_l4_name(m->packet_type));
1268 }
1269 #endif
1270
1271 uint16_t
1272 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1273 {
1274         struct qede_rx_queue *rxq = p_rxq;
1275         struct qede_dev *qdev = rxq->qdev;
1276         struct ecore_dev *edev = &qdev->edev;
1277         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1278         uint16_t rx_pkt = 0;
1279         union eth_rx_cqe *cqe;
1280         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1281         register struct rte_mbuf *rx_mb = NULL;
1282         register struct rte_mbuf *seg1 = NULL;
1283         enum eth_rx_cqe_type cqe_type;
1284         uint16_t pkt_len = 0; /* Sum of all BD segments */
1285         uint16_t len; /* Length of first BD */
1286         uint8_t num_segs = 1;
1287         uint16_t preload_idx;
1288         uint16_t parse_flag;
1289 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1290         uint8_t bitfield_val;
1291 #endif
1292         uint8_t tunn_parse_flag;
1293         uint8_t j;
1294         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1295         uint64_t ol_flags;
1296         uint32_t packet_type;
1297         uint16_t vlan_tci;
1298         bool tpa_start_flg;
1299         uint8_t offset, tpa_agg_idx, flags;
1300         struct qede_agg_info *tpa_info = NULL;
1301         uint32_t rss_hash;
1302
1303         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1304         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1305
1306         rte_rmb();
1307
1308         if (hw_comp_cons == sw_comp_cons)
1309                 return 0;
1310
1311         while (sw_comp_cons != hw_comp_cons) {
1312                 ol_flags = 0;
1313                 packet_type = RTE_PTYPE_UNKNOWN;
1314                 vlan_tci = 0;
1315                 tpa_start_flg = false;
1316                 rss_hash = 0;
1317
1318                 /* Get the CQE from the completion ring */
1319                 cqe =
1320                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1321                 cqe_type = cqe->fast_path_regular.type;
1322                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1323
1324                 switch (cqe_type) {
1325                 case ETH_RX_CQE_TYPE_REGULAR:
1326                         fp_cqe = &cqe->fast_path_regular;
1327                 break;
1328                 case ETH_RX_CQE_TYPE_TPA_START:
1329                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1330                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1331                         tpa_start_flg = true;
1332                         /* Mark it as LRO packet */
1333                         ol_flags |= PKT_RX_LRO;
1334                         /* In split mode,  seg_len is same as len_on_first_bd
1335                          * and ext_bd_len_list will be empty since there are
1336                          * no additional buffers
1337                          */
1338                         PMD_RX_LOG(INFO, rxq,
1339                             "TPA start[%d] - len_on_first_bd %d header %d"
1340                             " [bd_list[0] %d], [seg_len %d]\n",
1341                             cqe_start_tpa->tpa_agg_index,
1342                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1343                             cqe_start_tpa->header_len,
1344                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1345                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1346
1347                 break;
1348                 case ETH_RX_CQE_TYPE_TPA_CONT:
1349                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1350                                                      &cqe->fast_path_tpa_cont);
1351                         goto next_cqe;
1352                 case ETH_RX_CQE_TYPE_TPA_END:
1353                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1354                                                     &cqe->fast_path_tpa_end);
1355                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1356                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1357                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1358                         goto tpa_end;
1359                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1360                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1361                         ecore_eth_cqe_completion(
1362                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1363                                 (struct eth_slow_path_rx_cqe *)cqe);
1364                         /* fall-thru */
1365                 default:
1366                         goto next_cqe;
1367                 }
1368
1369                 /* Get the data from the SW ring */
1370                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1371                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1372                 assert(rx_mb != NULL);
1373
1374                 /* Handle regular CQE or TPA start CQE */
1375                 if (!tpa_start_flg) {
1376                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1377                         offset = fp_cqe->placement_offset;
1378                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1379                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1380                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1381                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1382 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1383                         bitfield_val = fp_cqe->bitfields;
1384 #endif
1385                 } else {
1386                         parse_flag =
1387                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1388                         offset = cqe_start_tpa->placement_offset;
1389                         /* seg_len = len_on_first_bd */
1390                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1391                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1392 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1393                         bitfield_val = cqe_start_tpa->bitfields;
1394 #endif
1395                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1396                 }
1397                 if (qede_tunn_exist(parse_flag)) {
1398                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1399                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1400                                 PMD_RX_LOG(ERR, rxq,
1401                                             "L4 csum failed, flags = 0x%x\n",
1402                                             parse_flag);
1403                                 rxq->rx_hw_errors++;
1404                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1405                         } else {
1406                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1407                                 if (tpa_start_flg)
1408                                         flags =
1409                                          cqe_start_tpa->tunnel_pars_flags.flags;
1410                                 else
1411                                         flags = fp_cqe->tunnel_pars_flags.flags;
1412                                 tunn_parse_flag = flags;
1413                                 /* Tunnel_type */
1414                                 packet_type =
1415                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1416
1417                                 /* Inner header */
1418                                 packet_type |=
1419                                       qede_rx_cqe_to_pkt_type_inner(parse_flag);
1420
1421                                 /* Outer L3/L4 types is not available in CQE */
1422                                 packet_type |=
1423                                       qede_rx_cqe_to_pkt_type_outer(rx_mb);
1424                         }
1425                 } else {
1426                         PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1427                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1428                                 PMD_RX_LOG(ERR, rxq,
1429                                             "L4 csum failed, flags = 0x%x\n",
1430                                             parse_flag);
1431                                 rxq->rx_hw_errors++;
1432                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1433                         } else {
1434                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1435                         }
1436                         if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1437                                                         parse_flag))) {
1438                                 PMD_RX_LOG(ERR, rxq,
1439                                            "IP csum failed, flags = 0x%x\n",
1440                                            parse_flag);
1441                                 rxq->rx_hw_errors++;
1442                                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1443                         } else {
1444                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1445                                 packet_type =
1446                                         qede_rx_cqe_to_pkt_type(parse_flag);
1447                         }
1448                 }
1449
1450                 if (CQE_HAS_VLAN(parse_flag) ||
1451                     CQE_HAS_OUTER_VLAN(parse_flag)) {
1452                         /* Note: FW doesn't indicate Q-in-Q packet */
1453                         ol_flags |= PKT_RX_VLAN;
1454                         if (qdev->vlan_strip_flg) {
1455                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1456                                 rx_mb->vlan_tci = vlan_tci;
1457                         }
1458                 }
1459
1460                 /* RSS Hash */
1461                 if (qdev->rss_enable) {
1462                         ol_flags |= PKT_RX_RSS_HASH;
1463                         rx_mb->hash.rss = rss_hash;
1464                 }
1465
1466                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1467                         PMD_RX_LOG(ERR, rxq,
1468                                    "New buffer allocation failed,"
1469                                    "dropping incoming packet\n");
1470                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1471                         rte_eth_devices[rxq->port_id].
1472                             data->rx_mbuf_alloc_failed++;
1473                         rxq->rx_alloc_errors++;
1474                         break;
1475                 }
1476                 qede_rx_bd_ring_consume(rxq);
1477
1478                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1479                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1480                                    " len on first: %04x Total Len: %04x",
1481                                    fp_cqe->bd_num, len, pkt_len);
1482                         num_segs = fp_cqe->bd_num - 1;
1483                         seg1 = rx_mb;
1484                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1485                                                  pkt_len - len))
1486                                 goto next_cqe;
1487                         for (j = 0; j < num_segs; j++) {
1488                                 if (qede_alloc_rx_buffer(rxq)) {
1489                                         PMD_RX_LOG(ERR, rxq,
1490                                                 "Buffer allocation failed");
1491                                         rte_eth_devices[rxq->port_id].
1492                                                 data->rx_mbuf_alloc_failed++;
1493                                         rxq->rx_alloc_errors++;
1494                                         break;
1495                                 }
1496                                 rxq->rx_segs++;
1497                         }
1498                 }
1499                 rxq->rx_segs++; /* for the first segment */
1500
1501                 /* Prefetch next mbuf while processing current one. */
1502                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1503                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1504
1505                 /* Update rest of the MBUF fields */
1506                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1507                 rx_mb->port = rxq->port_id;
1508                 rx_mb->ol_flags = ol_flags;
1509                 rx_mb->data_len = len;
1510                 rx_mb->packet_type = packet_type;
1511 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1512                 print_rx_bd_info(rx_mb, rxq, bitfield_val);
1513 #endif
1514                 if (!tpa_start_flg) {
1515                         rx_mb->nb_segs = fp_cqe->bd_num;
1516                         rx_mb->pkt_len = pkt_len;
1517                 } else {
1518                         /* store ref to the updated mbuf */
1519                         tpa_info->tpa_head = rx_mb;
1520                         tpa_info->tpa_tail = tpa_info->tpa_head;
1521                 }
1522                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1523 tpa_end:
1524                 if (!tpa_start_flg) {
1525                         rx_pkts[rx_pkt] = rx_mb;
1526                         rx_pkt++;
1527                 }
1528 next_cqe:
1529                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1530                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1531                 if (rx_pkt == nb_pkts) {
1532                         PMD_RX_LOG(DEBUG, rxq,
1533                                    "Budget reached nb_pkts=%u received=%u",
1534                                    rx_pkt, nb_pkts);
1535                         break;
1536                 }
1537         }
1538
1539         qede_update_rx_prod(qdev, rxq);
1540
1541         rxq->rcv_pkts += rx_pkt;
1542
1543         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1544
1545         return rx_pkt;
1546 }
1547
1548
1549 /* Populate scatter gather buffer descriptor fields */
1550 static inline uint16_t
1551 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1552                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1553 {
1554         struct qede_tx_queue *txq = p_txq;
1555         struct eth_tx_bd *tx_bd = NULL;
1556         dma_addr_t mapping;
1557         uint16_t nb_segs = 0;
1558
1559         /* Check for scattered buffers */
1560         while (m_seg) {
1561                 if (nb_segs == 0) {
1562                         if (!*bd2) {
1563                                 *bd2 = (struct eth_tx_2nd_bd *)
1564                                         ecore_chain_produce(&txq->tx_pbl);
1565                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1566                                 nb_segs++;
1567                         }
1568                         mapping = rte_mbuf_data_iova(m_seg);
1569                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1570                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1571                 } else if (nb_segs == 1) {
1572                         if (!*bd3) {
1573                                 *bd3 = (struct eth_tx_3rd_bd *)
1574                                         ecore_chain_produce(&txq->tx_pbl);
1575                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1576                                 nb_segs++;
1577                         }
1578                         mapping = rte_mbuf_data_iova(m_seg);
1579                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1580                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1581                 } else {
1582                         tx_bd = (struct eth_tx_bd *)
1583                                 ecore_chain_produce(&txq->tx_pbl);
1584                         memset(tx_bd, 0, sizeof(*tx_bd));
1585                         nb_segs++;
1586                         mapping = rte_mbuf_data_iova(m_seg);
1587                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1588                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1589                 }
1590                 m_seg = m_seg->next;
1591         }
1592
1593         /* Return total scattered buffers */
1594         return nb_segs;
1595 }
1596
1597 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1598 static inline void
1599 print_tx_bd_info(struct qede_tx_queue *txq,
1600                  struct eth_tx_1st_bd *bd1,
1601                  struct eth_tx_2nd_bd *bd2,
1602                  struct eth_tx_3rd_bd *bd3,
1603                  uint64_t tx_ol_flags)
1604 {
1605         char ol_buf[256] = { 0 }; /* for verbose prints */
1606
1607         if (bd1)
1608                 PMD_TX_LOG(INFO, txq,
1609                            "BD1: nbytes=%u nbds=%u bd_flags=%04x bf=%04x",
1610                            rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1611                            bd1->data.bd_flags.bitfields,
1612                            rte_cpu_to_le_16(bd1->data.bitfields));
1613         if (bd2)
1614                 PMD_TX_LOG(INFO, txq,
1615                            "BD2: nbytes=%u bf=%04x\n",
1616                            rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1617         if (bd3)
1618                 PMD_TX_LOG(INFO, txq,
1619                            "BD3: nbytes=%u bf=%04x mss=%u\n",
1620                            rte_cpu_to_le_16(bd3->nbytes),
1621                            rte_cpu_to_le_16(bd3->data.bitfields),
1622                            rte_cpu_to_le_16(bd3->data.lso_mss));
1623
1624         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1625         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1626 }
1627 #endif
1628
1629 /* TX prepare to check packets meets TX conditions */
1630 uint16_t
1631 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1632 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1633                     uint16_t nb_pkts)
1634 {
1635         struct qede_tx_queue *txq = p_txq;
1636 #else
1637 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1638                     uint16_t nb_pkts)
1639 {
1640 #endif
1641         uint64_t ol_flags;
1642         struct rte_mbuf *m;
1643         uint16_t i;
1644 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1645         int ret;
1646 #endif
1647
1648         for (i = 0; i < nb_pkts; i++) {
1649                 m = tx_pkts[i];
1650                 ol_flags = m->ol_flags;
1651                 if (ol_flags & PKT_TX_TCP_SEG) {
1652                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1653                                 rte_errno = -EINVAL;
1654                                 break;
1655                         }
1656                         /* TBD: confirm its ~9700B for both ? */
1657                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1658                                 rte_errno = -EINVAL;
1659                                 break;
1660                         }
1661                 } else {
1662                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1663                                 rte_errno = -EINVAL;
1664                                 break;
1665                         }
1666                 }
1667                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1668                         rte_errno = -ENOTSUP;
1669                         break;
1670                 }
1671
1672 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1673                 ret = rte_validate_tx_offload(m);
1674                 if (ret != 0) {
1675                         rte_errno = ret;
1676                         break;
1677                 }
1678 #endif
1679         }
1680
1681 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1682         if (unlikely(i != nb_pkts))
1683                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1684                            nb_pkts - i);
1685 #endif
1686         return i;
1687 }
1688
1689 #define MPLSINUDP_HDR_SIZE                      (12)
1690
1691 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1692 static inline void
1693 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1694                                struct qede_tx_queue *txq)
1695 {
1696         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1697                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1698         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1699                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1700                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1701         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1702                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1703                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1704         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1705                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1706                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1707 }
1708 #endif
1709
1710 uint16_t
1711 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1712 {
1713         struct qede_tx_queue *txq = p_txq;
1714         struct qede_dev *qdev = txq->qdev;
1715         struct ecore_dev *edev = &qdev->edev;
1716         struct rte_mbuf *mbuf;
1717         struct rte_mbuf *m_seg = NULL;
1718         uint16_t nb_tx_pkts;
1719         uint16_t bd_prod;
1720         uint16_t idx;
1721         uint16_t nb_frags;
1722         uint16_t nb_pkt_sent = 0;
1723         uint8_t nbds;
1724         bool lso_flg;
1725         bool mplsoudp_flg;
1726         __rte_unused bool tunn_flg;
1727         bool tunn_ipv6_ext_flg;
1728         struct eth_tx_1st_bd *bd1;
1729         struct eth_tx_2nd_bd *bd2;
1730         struct eth_tx_3rd_bd *bd3;
1731         uint64_t tx_ol_flags;
1732         uint16_t hdr_size;
1733         /* BD1 */
1734         uint16_t bd1_bf;
1735         uint8_t bd1_bd_flags_bf;
1736         uint16_t vlan;
1737         /* BD2 */
1738         uint16_t bd2_bf1;
1739         uint16_t bd2_bf2;
1740         /* BD3 */
1741         uint16_t mss;
1742         uint16_t bd3_bf;
1743
1744         uint8_t tunn_l4_hdr_start_offset;
1745         uint8_t tunn_hdr_size;
1746         uint8_t inner_l2_hdr_size;
1747         uint16_t inner_l4_hdr_offset;
1748
1749         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1750                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1751                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1752                 qede_process_tx_compl(edev, txq);
1753         }
1754
1755         nb_tx_pkts  = nb_pkts;
1756         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1757         while (nb_tx_pkts--) {
1758                 /* Init flags/values */
1759                 tunn_flg = false;
1760                 lso_flg = false;
1761                 nbds = 0;
1762                 vlan = 0;
1763                 bd1 = NULL;
1764                 bd2 = NULL;
1765                 bd3 = NULL;
1766                 hdr_size = 0;
1767                 bd1_bf = 0;
1768                 bd1_bd_flags_bf = 0;
1769                 bd2_bf1 = 0;
1770                 bd2_bf2 = 0;
1771                 mss = 0;
1772                 bd3_bf = 0;
1773                 mplsoudp_flg = false;
1774                 tunn_ipv6_ext_flg = false;
1775                 tunn_hdr_size = 0;
1776                 tunn_l4_hdr_start_offset = 0;
1777
1778                 mbuf = *tx_pkts++;
1779                 assert(mbuf);
1780
1781                 /* Check minimum TX BDS availability against available BDs */
1782                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1783                         break;
1784
1785                 tx_ol_flags = mbuf->ol_flags;
1786                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1787
1788                 /* TX prepare would have already checked supported tunnel Tx
1789                  * offloads. Don't rely on pkt_type marked by Rx, instead use
1790                  * tx_ol_flags to decide.
1791                  */
1792                 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1793                                                 PKT_TX_TUNNEL_VXLAN) ||
1794                     ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1795                                                 PKT_TX_TUNNEL_MPLSINUDP)) {
1796                         /* Check against max which is Tunnel IPv6 + ext */
1797                         if (unlikely(txq->nb_tx_avail <
1798                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1799                                         break;
1800                         tunn_flg = true;
1801                         /* First indicate its a tunnel pkt */
1802                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1803                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1804                         /* Legacy FW had flipped behavior in regard to this bit
1805                          * i.e. it needed to set to prevent FW from touching
1806                          * encapsulated packets when it didn't need to.
1807                          */
1808                         if (unlikely(txq->is_legacy)) {
1809                                 bd1_bf ^= 1 <<
1810                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1811                         }
1812
1813                         /* Outer IP checksum offload */
1814                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1815                                            PKT_TX_OUTER_IPV4)) {
1816                                 bd1_bd_flags_bf |=
1817                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1818                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1819                         }
1820
1821                         /**
1822                          * Currently, only inner checksum offload in MPLS-in-UDP
1823                          * tunnel with one MPLS label is supported. Both outer
1824                          * and inner layers  lengths need to be provided in
1825                          * mbuf.
1826                          */
1827                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1828                                                 PKT_TX_TUNNEL_MPLSINUDP) {
1829                                 mplsoudp_flg = true;
1830 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1831                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1832 #endif
1833                                 /* Outer L4 offset in two byte words */
1834                                 tunn_l4_hdr_start_offset =
1835                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1836                                 /* Tunnel header size in two byte words */
1837                                 tunn_hdr_size = (mbuf->outer_l2_len +
1838                                                 mbuf->outer_l3_len +
1839                                                 MPLSINUDP_HDR_SIZE) / 2;
1840                                 /* Inner L2 header size in two byte words */
1841                                 inner_l2_hdr_size = (mbuf->l2_len -
1842                                                 MPLSINUDP_HDR_SIZE) / 2;
1843                                 /* Inner L4 header offset from the beggining
1844                                  * of inner packet in two byte words
1845                                  */
1846                                 inner_l4_hdr_offset = (mbuf->l2_len -
1847                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1848
1849                                 /* Inner L2 size and address type */
1850                                 bd2_bf1 |= (inner_l2_hdr_size &
1851                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1852                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1853                                 bd2_bf1 |= (UNICAST_ADDRESS &
1854                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1855                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1856                                 /* Treated as IPv6+Ext */
1857                                 bd2_bf1 |=
1858                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1859
1860                                 /* Mark inner IPv6 if present */
1861                                 if (tx_ol_flags & PKT_TX_IPV6)
1862                                         bd2_bf1 |=
1863                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1864
1865                                 /* Inner L4 offsets */
1866                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1867                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1868                                                         PKT_TX_TCP_CKSUM))) {
1869                                         /* Determines if BD3 is needed */
1870                                         tunn_ipv6_ext_flg = true;
1871                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1872                                                         PKT_TX_UDP_CKSUM) {
1873                                                 bd2_bf1 |=
1874                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1875                                         }
1876
1877                                         /* TODO other pseudo checksum modes are
1878                                          * not supported
1879                                          */
1880                                         bd2_bf1 |=
1881                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1882                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1883                                         bd2_bf2 |= (inner_l4_hdr_offset &
1884                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1885                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1886                                 }
1887                         } /* End MPLSoUDP */
1888                 } /* End Tunnel handling */
1889
1890                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1891                         lso_flg = true;
1892                         if (unlikely(txq->nb_tx_avail <
1893                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1894                                 break;
1895                         /* For LSO, packet header and payload must reside on
1896                          * buffers pointed by different BDs. Using BD1 for HDR
1897                          * and BD2 onwards for data.
1898                          */
1899                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1900                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1901                         bd1_bd_flags_bf |=
1902                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1903                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1904                         bd1_bd_flags_bf |=
1905                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1906                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1907                         /* Using one header BD */
1908                         bd3_bf |= rte_cpu_to_le_16(1 <<
1909                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1910                 } else {
1911                         if (unlikely(txq->nb_tx_avail <
1912                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1913                                 break;
1914                         bd1_bf |=
1915                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1916                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1917                 }
1918
1919                 /* Descriptor based VLAN insertion */
1920                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1921                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1922                         bd1_bd_flags_bf |=
1923                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1924                 }
1925
1926                 /* Offload the IP checksum in the hardware */
1927                 if (tx_ol_flags & PKT_TX_IP_CKSUM) {
1928                         bd1_bd_flags_bf |=
1929                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1930                         /* There's no DPDK flag to request outer-L4 csum
1931                          * offload. But in the case of tunnel if inner L3 or L4
1932                          * csum offload is requested then we need to force
1933                          * recalculation of L4 tunnel header csum also.
1934                          */
1935                         if (tunn_flg) {
1936                                 bd1_bd_flags_bf |=
1937                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1938                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1939                         }
1940                 }
1941
1942                 /* L4 checksum offload (tcp or udp) */
1943                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1944                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
1945                         bd1_bd_flags_bf |=
1946                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1947                         /* There's no DPDK flag to request outer-L4 csum
1948                          * offload. But in the case of tunnel if inner L3 or L4
1949                          * csum offload is requested then we need to force
1950                          * recalculation of L4 tunnel header csum also.
1951                          */
1952                         if (tunn_flg) {
1953                                 bd1_bd_flags_bf |=
1954                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1955                                         ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1956                         }
1957                 }
1958
1959                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1960                 idx = TX_PROD(txq);
1961                 txq->sw_tx_ring[idx].mbuf = mbuf;
1962
1963                 /* BD1 */
1964                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1965                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1966                 nbds++;
1967
1968                 /* Map MBUF linear data for DMA and set in the BD1 */
1969                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
1970                                      mbuf->data_len);
1971                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
1972                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
1973                 bd1->data.vlan = vlan;
1974
1975                 if (lso_flg || mplsoudp_flg) {
1976                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1977                                                         (&txq->tx_pbl);
1978                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1979                         nbds++;
1980
1981                         /* BD1 */
1982                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_iova(mbuf),
1983                                              hdr_size);
1984                         /* BD2 */
1985                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
1986                                              rte_mbuf_data_iova(mbuf)),
1987                                              mbuf->data_len - hdr_size);
1988                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
1989                         if (mplsoudp_flg) {
1990                                 bd2->data.bitfields2 =
1991                                         rte_cpu_to_le_16(bd2_bf2);
1992                                 /* Outer L3 size */
1993                                 bd2->data.tunn_ip_size =
1994                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
1995                         }
1996                         /* BD3 */
1997                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
1998                                 bd3 = (struct eth_tx_3rd_bd *)
1999                                         ecore_chain_produce(&txq->tx_pbl);
2000                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
2001                                 nbds++;
2002                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
2003                                 if (lso_flg)
2004                                         bd3->data.lso_mss = mss;
2005                                 if (mplsoudp_flg) {
2006                                         bd3->data.tunn_l4_hdr_start_offset_w =
2007                                                 tunn_l4_hdr_start_offset;
2008                                         bd3->data.tunn_hdr_size_w =
2009                                                 tunn_hdr_size;
2010                                 }
2011                         }
2012                 }
2013
2014                 /* Handle fragmented MBUF */
2015                 m_seg = mbuf->next;
2016                 /* Encode scatter gather buffer descriptors if required */
2017                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
2018                 bd1->data.nbds = nbds + nb_frags;
2019                 txq->nb_tx_avail -= bd1->data.nbds;
2020                 txq->sw_tx_prod++;
2021                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
2022                 bd_prod =
2023                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
2024 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
2025                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
2026                 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d", lso_flg, tunn_flg);
2027 #endif
2028                 nb_pkt_sent++;
2029                 txq->xmit_pkts++;
2030         }
2031
2032         /* Write value of prod idx into bd_prod */
2033         txq->tx_db.data.bd_prod = bd_prod;
2034         rte_wmb();
2035         rte_compiler_barrier();
2036         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
2037         rte_wmb();
2038
2039         /* Check again for Tx completions */
2040         qede_process_tx_compl(edev, txq);
2041
2042         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
2043                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
2044
2045         return nb_pkt_sent;
2046 }
2047
2048 uint16_t
2049 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
2050                      __rte_unused struct rte_mbuf **pkts,
2051                      __rte_unused uint16_t nb_pkts)
2052 {
2053         return 0;
2054 }