drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  14 {
  15         struct rte_mbuf *new_mb = NULL;
  16         struct eth_rx_bd *rx_bd;
  17         dma_addr_t mapping;
  18         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  19
  20         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  21         if (unlikely(!new_mb)) {
  22                 PMD_RX_LOG(ERR, rxq,
  23                            "Failed to allocate rx buffer "
  24                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  25                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  26                            rte_mempool_avail_count(rxq->mb_pool),
  27                            rte_mempool_in_use_count(rxq->mb_pool));
  28                 return -ENOMEM;
  29         }
  30         rxq->sw_rx_ring[idx].mbuf = new_mb;
  31         rxq->sw_rx_ring[idx].page_offset = 0;
  32         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  33         /* Advance PROD and get BD pointer */
  34         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  35         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  36         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  37         rxq->sw_rx_prod++;
  38         return 0;
  39 }
  40
  41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  42 {
  43         uint16_t i;
  44
  45         if (rxq->sw_rx_ring != NULL) {
  46                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  47                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  48                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  49                                 rxq->sw_rx_ring[i].mbuf = NULL;
  50                         }
  51                 }
  52         }
  53 }
  54
  55 void qede_rx_queue_release(void *rx_queue)
  56 {
  57         struct qede_rx_queue *rxq = rx_queue;
  58
  59         if (rxq != NULL) {
  60                 qede_rx_queue_release_mbufs(rxq);
  61                 rte_free(rxq->sw_rx_ring);
  62                 rxq->sw_rx_ring = NULL;
  63                 rte_free(rxq);
  64                 rxq = NULL;
  65         }
  66 }
  67
  68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  69 {
  70         unsigned int i;
  71
  72         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
  73
  74         if (txq->sw_tx_ring) {
  75                 for (i = 0; i < txq->nb_tx_desc; i++) {
  76                         if (txq->sw_tx_ring[i].mbuf) {
  77                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  78                                 txq->sw_tx_ring[i].mbuf = NULL;
  79                         }
  80                 }
  81         }
  82 }
  83
  84 int
  85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  86                     uint16_t nb_desc, unsigned int socket_id,
  87                     const struct rte_eth_rxconf *rx_conf,
  88                     struct rte_mempool *mp)
  89 {
  90         struct qede_dev *qdev = dev->data->dev_private;
  91         struct ecore_dev *edev = &qdev->edev;
  92         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  93         struct qede_rx_queue *rxq;
  94         uint16_t max_rx_pkt_len;
  95         uint16_t bufsz;
  96         size_t size;
  97         int rc;
  98         int i;
  99
 100         PMD_INIT_FUNC_TRACE(edev);
 101
 102         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 103         if (!rte_is_power_of_2(nb_desc)) {
 104                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 105                           nb_desc);
 106                 return -EINVAL;
 107         }
 108
 109         /* Free memory prior to re-allocation if needed... */
 110         if (dev->data->rx_queues[queue_idx] != NULL) {
 111                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 112                 dev->data->rx_queues[queue_idx] = NULL;
 113         }
 114
 115         /* First allocate the rx queue data structure */
 116         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 117                                  RTE_CACHE_LINE_SIZE, socket_id);
 118
 119         if (!rxq) {
 120                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 121                           socket_id);
 122                 return -ENOMEM;
 123         }
 124
 125         rxq->qdev = qdev;
 126         rxq->mb_pool = mp;
 127         rxq->nb_rx_desc = nb_desc;
 128         rxq->queue_id = queue_idx;
 129         rxq->port_id = dev->data->port_id;
 130         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 131         qdev->mtu = max_rx_pkt_len;
 132
 133         /* Fix up RX buffer size */
 134         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 135         if ((rxmode->enable_scatter)                    ||
 136             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 137                 if (!dev->data->scattered_rx) {
 138                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 139                         dev->data->scattered_rx = 1;
 140                 }
 141         }
 142         if (dev->data->scattered_rx)
 143                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 144         else
 145                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 146         /* Align to cache-line size if needed */
 147         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 148
 149         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 150                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 151
 152         /* Allocate the parallel driver ring for Rx buffers */
 153         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 154         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 155                                              RTE_CACHE_LINE_SIZE, socket_id);
 156         if (!rxq->sw_rx_ring) {
 157                 DP_NOTICE(edev, false,
 158                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 159                           socket_id);
 160                 rte_free(rxq);
 161                 rxq = NULL;
 162                 return -ENOMEM;
 163         }
 164
 165         /* Allocate FW Rx ring  */
 166         rc = qdev->ops->common->chain_alloc(edev,
 167                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 168                                             ECORE_CHAIN_MODE_NEXT_PTR,
 169                                             ECORE_CHAIN_CNT_TYPE_U16,
 170                                             rxq->nb_rx_desc,
 171                                             sizeof(struct eth_rx_bd),
 172                                             &rxq->rx_bd_ring,
 173                                             NULL);
 174
 175         if (rc != ECORE_SUCCESS) {
 176                 DP_NOTICE(edev, false,
 177                           "Unable to alloc memory for rxbd ring on socket %u\n",
 178                           socket_id);
 179                 rte_free(rxq->sw_rx_ring);
 180                 rxq->sw_rx_ring = NULL;
 181                 rte_free(rxq);
 182                 rxq = NULL;
 183                 return -ENOMEM;
 184         }
 185
 186         /* Allocate FW completion ring */
 187         rc = qdev->ops->common->chain_alloc(edev,
 188                                             ECORE_CHAIN_USE_TO_CONSUME,
 189                                             ECORE_CHAIN_MODE_PBL,
 190                                             ECORE_CHAIN_CNT_TYPE_U16,
 191                                             rxq->nb_rx_desc,
 192                                             sizeof(union eth_rx_cqe),
 193                                             &rxq->rx_comp_ring,
 194                                             NULL);
 195
 196         if (rc != ECORE_SUCCESS) {
 197                 DP_NOTICE(edev, false,
 198                           "Unable to alloc memory for cqe ring on socket %u\n",
 199                           socket_id);
 200                 /* TBD: Freeing RX BD ring */
 201                 rte_free(rxq->sw_rx_ring);
 202                 rxq->sw_rx_ring = NULL;
 203                 rte_free(rxq);
 204                 return -ENOMEM;
 205         }
 206
 207         /* Allocate buffers for the Rx ring */
 208         for (i = 0; i < rxq->nb_rx_desc; i++) {
 209                 rc = qede_alloc_rx_buffer(rxq);
 210                 if (rc) {
 211                         DP_NOTICE(edev, false,
 212                                   "RX buffer allocation failed at idx=%d\n", i);
 213                         goto err4;
 214                 }
 215         }
 216
 217         dev->data->rx_queues[queue_idx] = rxq;
 218
 219         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 220                   queue_idx, nb_desc, qdev->mtu, socket_id);
 221
 222         return 0;
 223 err4:
 224         qede_rx_queue_release(rxq);
 225         return -ENOMEM;
 226 }
 227
 228 void qede_tx_queue_release(void *tx_queue)
 229 {
 230         struct qede_tx_queue *txq = tx_queue;
 231
 232         if (txq != NULL) {
 233                 qede_tx_queue_release_mbufs(txq);
 234                 if (txq->sw_tx_ring) {
 235                         rte_free(txq->sw_tx_ring);
 236                         txq->sw_tx_ring = NULL;
 237                 }
 238                 rte_free(txq);
 239         }
 240         txq = NULL;
 241 }
 242
 243 int
 244 qede_tx_queue_setup(struct rte_eth_dev *dev,
 245                     uint16_t queue_idx,
 246                     uint16_t nb_desc,
 247                     unsigned int socket_id,
 248                     const struct rte_eth_txconf *tx_conf)
 249 {
 250         struct qede_dev *qdev = dev->data->dev_private;
 251         struct ecore_dev *edev = &qdev->edev;
 252         struct qede_tx_queue *txq;
 253         int rc;
 254
 255         PMD_INIT_FUNC_TRACE(edev);
 256
 257         if (!rte_is_power_of_2(nb_desc)) {
 258                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 259                        nb_desc);
 260                 return -EINVAL;
 261         }
 262
 263         /* Free memory prior to re-allocation if needed... */
 264         if (dev->data->tx_queues[queue_idx] != NULL) {
 265                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 266                 dev->data->tx_queues[queue_idx] = NULL;
 267         }
 268
 269         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 270                                  RTE_CACHE_LINE_SIZE, socket_id);
 271
 272         if (txq == NULL) {
 273                 DP_ERR(edev,
 274                        "Unable to allocate memory for txq on socket %u",
 275                        socket_id);
 276                 return -ENOMEM;
 277         }
 278
 279         txq->nb_tx_desc = nb_desc;
 280         txq->qdev = qdev;
 281         txq->port_id = dev->data->port_id;
 282
 283         rc = qdev->ops->common->chain_alloc(edev,
 284                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 285                                             ECORE_CHAIN_MODE_PBL,
 286                                             ECORE_CHAIN_CNT_TYPE_U16,
 287                                             txq->nb_tx_desc,
 288                                             sizeof(union eth_tx_bd_types),
 289                                             &txq->tx_pbl,
 290                                             NULL);
 291         if (rc != ECORE_SUCCESS) {
 292                 DP_ERR(edev,
 293                        "Unable to allocate memory for txbd ring on socket %u",
 294                        socket_id);
 295                 qede_tx_queue_release(txq);
 296                 return -ENOMEM;
 297         }
 298
 299         /* Allocate software ring */
 300         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 301                                              (sizeof(struct qede_tx_entry) *
 302                                               txq->nb_tx_desc),
 303                                              RTE_CACHE_LINE_SIZE, socket_id);
 304
 305         if (!txq->sw_tx_ring) {
 306                 DP_ERR(edev,
 307                        "Unable to allocate memory for txbd ring on socket %u",
 308                        socket_id);
 309                 qede_tx_queue_release(txq);
 310                 return -ENOMEM;
 311         }
 312
 313         txq->queue_id = queue_idx;
 314
 315         txq->nb_tx_avail = txq->nb_tx_desc;
 316
 317         txq->tx_free_thresh =
 318             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 319             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 320
 321         dev->data->tx_queues[queue_idx] = txq;
 322
 323         DP_INFO(edev,
 324                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 325                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 326
 327         return 0;
 328 }
 329
 330 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 331 static void qede_init_fp(struct qede_dev *qdev)
 332 {
 333         struct qede_fastpath *fp;
 334         uint8_t i, rss_id, tc;
 335         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 336
 337         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 338                                            sizeof(*qdev->fp_array)));
 339         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 340                                            sizeof(*qdev->sb_array)));
 341         for_each_queue(i) {
 342                 fp = &qdev->fp_array[i];
 343                 if (fp_rx) {
 344                         fp->type = QEDE_FASTPATH_RX;
 345                         fp_rx--;
 346                 } else{
 347                         fp->type = QEDE_FASTPATH_TX;
 348                 }
 349                 fp->qdev = qdev;
 350                 fp->id = i;
 351                 fp->sb_info = &qdev->sb_array[i];
 352                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 353         }
 354
 355         qdev->gro_disable = gro_disable;
 356 }
 357
 358 void qede_free_fp_arrays(struct qede_dev *qdev)
 359 {
 360         /* It asseumes qede_free_mem_load() is called before */
 361         if (qdev->fp_array != NULL) {
 362                 rte_free(qdev->fp_array);
 363                 qdev->fp_array = NULL;
 364         }
 365
 366         if (qdev->sb_array != NULL) {
 367                 rte_free(qdev->sb_array);
 368                 qdev->sb_array = NULL;
 369         }
 370 }
 371
 372 int qede_alloc_fp_array(struct qede_dev *qdev)
 373 {
 374         struct qede_fastpath *fp;
 375         struct ecore_dev *edev = &qdev->edev;
 376         int i;
 377
 378         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 379                                     sizeof(*qdev->fp_array),
 380                                     RTE_CACHE_LINE_SIZE);
 381
 382         if (!qdev->fp_array) {
 383                 DP_ERR(edev, "fp array allocation failed\n");
 384                 return -ENOMEM;
 385         }
 386
 387         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 388                                     sizeof(*qdev->sb_array),
 389                                     RTE_CACHE_LINE_SIZE);
 390
 391         if (!qdev->sb_array) {
 392                 DP_ERR(edev, "sb array allocation failed\n");
 393                 rte_free(qdev->fp_array);
 394                 return -ENOMEM;
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* This function allocates fast-path status block memory */
 401 static int
 402 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 403                   uint16_t sb_id)
 404 {
 405         struct ecore_dev *edev = &qdev->edev;
 406         struct status_block *sb_virt;
 407         dma_addr_t sb_phys;
 408         int rc;
 409
 410         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 411
 412         if (!sb_virt) {
 413                 DP_ERR(edev, "Status block allocation failed\n");
 414                 return -ENOMEM;
 415         }
 416
 417         rc = qdev->ops->common->sb_init(edev, sb_info,
 418                                         sb_virt, sb_phys, sb_id,
 419                                         QED_SB_TYPE_L2_QUEUE);
 420         if (rc) {
 421                 DP_ERR(edev, "Status block initialization failed\n");
 422                 /* TBD: No dma_free_coherent possible */
 423                 return rc;
 424         }
 425
 426         return 0;
 427 }
 428
 429 int qede_alloc_fp_resc(struct qede_dev *qdev)
 430 {
 431         struct ecore_dev *edev = &qdev->edev;
 432         struct qede_fastpath *fp;
 433         uint32_t num_sbs;
 434         int rc, i;
 435
 436         if (IS_VF(edev))
 437                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 438         else
 439                 num_sbs = (ecore_cxt_get_proto_cid_count
 440                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL)) / 2;
 441
 442         if (num_sbs == 0) {
 443                 DP_ERR(edev, "No status blocks available\n");
 444                 return -EINVAL;
 445         }
 446
 447         if (qdev->fp_array)
 448                 qede_free_fp_arrays(qdev);
 449
 450         rc = qede_alloc_fp_array(qdev);
 451         if (rc != 0)
 452                 return rc;
 453
 454         qede_init_fp(qdev);
 455
 456         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 457                 fp = &qdev->fp_array[i];
 458                 if (qede_alloc_mem_sb(qdev, fp->sb_info, i % num_sbs)) {
 459                         qede_free_fp_arrays(qdev);
 460                         return -ENOMEM;
 461                 }
 462         }
 463
 464         return 0;
 465 }
 466
 467 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 468 {
 469         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 470
 471         qede_free_mem_load(eth_dev);
 472         qede_free_fp_arrays(qdev);
 473 }
 474
 475 static inline void
 476 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 477 {
 478         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 479         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 480         struct eth_rx_prod_data rx_prods = { 0 };
 481
 482         /* Update producers */
 483         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 484         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 485
 486         /* Make sure that the BD and SGE data is updated before updating the
 487          * producers since FW might read the BD/SGE right after the producer
 488          * is updated.
 489          */
 490         rte_wmb();
 491
 492         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 493                         (uint32_t *)&rx_prods);
 494
 495         /* mmiowb is needed to synchronize doorbell writes from more than one
 496          * processor. It guarantees that the write arrives to the device before
 497          * the napi lock is released and another qede_poll is called (possibly
 498          * on another CPU). Without this barrier, the next doorbell can bypass
 499          * this doorbell. This is applicable to IA64/Altix systems.
 500          */
 501         rte_wmb();
 502
 503         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u\n", bd_prod, cqe_prod);
 504 }
 505
 506 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 507 {
 508         struct qede_dev *qdev = eth_dev->data->dev_private;
 509         struct ecore_dev *edev = &qdev->edev;
 510         struct ecore_queue_start_common_params q_params;
 511         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 512         struct qed_update_vport_params vport_update_params;
 513         struct qede_tx_queue *txq;
 514         struct qede_fastpath *fp;
 515         dma_addr_t p_phys_table;
 516         int txq_index;
 517         uint16_t page_cnt;
 518         int vlan_removal_en = 1;
 519         int rc, tc, i;
 520
 521         for_each_queue(i) {
 522                 fp = &qdev->fp_array[i];
 523                 if (fp->type & QEDE_FASTPATH_RX) {
 524                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 525                                                                 rx_comp_ring);
 526                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 527                                                                 rx_comp_ring);
 528
 529                         memset(&q_params, 0, sizeof(q_params));
 530                         q_params.queue_id = i;
 531                         q_params.vport_id = 0;
 532                         q_params.sb = fp->sb_info->igu_sb_id;
 533                         q_params.sb_idx = RX_PI;
 534
 535                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 536
 537                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 538                                            fp->rxq->rx_buf_size,
 539                                            fp->rxq->rx_bd_ring.p_phys_addr,
 540                                            p_phys_table,
 541                                            page_cnt,
 542                                            &fp->rxq->hw_rxq_prod_addr);
 543                         if (rc) {
 544                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 545                                        fp->rxq->queue_id, rc);
 546                                 return rc;
 547                         }
 548
 549                         fp->rxq->hw_cons_ptr =
 550                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 551
 552                         qede_update_rx_prod(qdev, fp->rxq);
 553                 }
 554
 555                 if (!(fp->type & QEDE_FASTPATH_TX))
 556                         continue;
 557                 for (tc = 0; tc < qdev->num_tc; tc++) {
 558                         txq = fp->txqs[tc];
 559                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 560
 561                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 562                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 563
 564                         memset(&q_params, 0, sizeof(q_params));
 565                         q_params.queue_id = txq->queue_id;
 566                         q_params.vport_id = 0;
 567                         q_params.sb = fp->sb_info->igu_sb_id;
 568                         q_params.sb_idx = TX_PI(tc);
 569
 570                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 571                                                    p_phys_table,
 572                                                    page_cnt, /* **pp_doorbell */
 573                                                    &txq->doorbell_addr);
 574                         if (rc) {
 575                                 DP_ERR(edev, "Start txq %u failed %d\n",
 576                                        txq_index, rc);
 577                                 return rc;
 578                         }
 579
 580                         txq->hw_cons_ptr =
 581                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 582                         SET_FIELD(txq->tx_db.data.params,
 583                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 584                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 585                                   DB_AGG_CMD_SET);
 586                         SET_FIELD(txq->tx_db.data.params,
 587                                   ETH_DB_DATA_AGG_VAL_SEL,
 588                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 589
 590                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 591                 }
 592         }
 593
 594         /* Prepare and send the vport enable */
 595         memset(&vport_update_params, 0, sizeof(vport_update_params));
 596         /* Update MTU via vport update */
 597         vport_update_params.mtu = qdev->mtu;
 598         vport_update_params.vport_id = 0;
 599         vport_update_params.update_vport_active_flg = 1;
 600         vport_update_params.vport_active_flg = 1;
 601
 602         /* @DPDK */
 603         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 604                 /* TBD: Check SRIOV enabled for VF */
 605                 vport_update_params.update_tx_switching_flg = 1;
 606                 vport_update_params.tx_switching_flg = 1;
 607         }
 608
 609         rc = qdev->ops->vport_update(edev, &vport_update_params);
 610         if (rc) {
 611                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 612                 return rc;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static bool qede_tunn_exist(uint16_t flag)
 619 {
 620         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 621                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 622 }
 623
 624 /*
 625  * qede_check_tunn_csum_l4:
 626  * Returns:
 627  * 1 : If L4 csum is enabled AND if the validation has failed.
 628  * 0 : Otherwise
 629  */
 630 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 631 {
 632         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 633              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 634                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 635                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 636
 637         return 0;
 638 }
 639
 640 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 641 {
 642         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 643              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 644                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 645                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 646
 647         return 0;
 648 }
 649
 650 static inline uint8_t
 651 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 652 {
 653         struct ipv4_hdr *ip;
 654         uint16_t pkt_csum;
 655         uint16_t calc_csum;
 656         uint16_t val;
 657
 658         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 659                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 660
 661         if (unlikely(val)) {
 662                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 663                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 664                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 665                                            sizeof(struct ether_hdr));
 666                         pkt_csum = ip->hdr_checksum;
 667                         ip->hdr_checksum = 0;
 668                         calc_csum = rte_ipv4_cksum(ip);
 669                         ip->hdr_checksum = pkt_csum;
 670                         return (calc_csum != pkt_csum);
 671                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 672                         return 1;
 673                 }
 674         }
 675         return 0;
 676 }
 677
 678 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 679 {
 680         ecore_chain_consume(&rxq->rx_bd_ring);
 681         rxq->sw_rx_cons++;
 682 }
 683
 684 static inline void
 685 qede_reuse_page(struct qede_dev *qdev,
 686                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 687 {
 688         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 689         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 690         struct qede_rx_entry *curr_prod;
 691         dma_addr_t new_mapping;
 692
 693         curr_prod = &rxq->sw_rx_ring[idx];
 694         *curr_prod = *curr_cons;
 695
 696         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 697                       curr_prod->page_offset;
 698
 699         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 700         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 701
 702         rxq->sw_rx_prod++;
 703 }
 704
 705 static inline void
 706 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 707                         struct qede_dev *qdev, uint8_t count)
 708 {
 709         struct qede_rx_entry *curr_cons;
 710
 711         for (; count > 0; count--) {
 712                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 713                 qede_reuse_page(qdev, rxq, curr_cons);
 714                 qede_rx_bd_ring_consume(rxq);
 715         }
 716 }
 717
 718 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 719 {
 720         uint16_t val;
 721
 722         /* Lookup table */
 723         static const uint32_t
 724         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 725                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 726                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 727                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 728                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 729                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 730                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 731         };
 732
 733         /* Bits (0..3) provides L3/L4 protocol type */
 734         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 735                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 736                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 737                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 738
 739         if (val < QEDE_PKT_TYPE_MAX)
 740                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 741         else
 742                 return RTE_PTYPE_UNKNOWN;
 743 }
 744
 745 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 746 {
 747         uint32_t val;
 748
 749         /* Lookup table */
 750         static const uint32_t
 751         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 752                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 753                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 754                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 755                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 756                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 757                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 758                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 759                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 760                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 761                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 762                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 763                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 764                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 765                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 766                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 767                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 768                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 769                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 770                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 771                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 772                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 773                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 774                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 775                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 776                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 777                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 778                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 779                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 780                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 781                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 782                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 783                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 784                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 785                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 786                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 787                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 788                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 789                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 790                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 791                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 792         };
 793
 794         /* Cover bits[4-0] to include tunn_type and next protocol */
 795         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 796                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 797                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 798                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 799
 800         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 801                 return ptype_tunn_lkup_tbl[val];
 802         else
 803                 return RTE_PTYPE_UNKNOWN;
 804 }
 805
 806 static inline int
 807 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 808                      uint8_t num_segs, uint16_t pkt_len)
 809 {
 810         struct qede_rx_queue *rxq = p_rxq;
 811         struct qede_dev *qdev = rxq->qdev;
 812         struct ecore_dev *edev = &qdev->edev;
 813         register struct rte_mbuf *seg1 = NULL;
 814         register struct rte_mbuf *seg2 = NULL;
 815         uint16_t sw_rx_index;
 816         uint16_t cur_size;
 817
 818         seg1 = rx_mb;
 819         while (num_segs) {
 820                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
 821                                                         pkt_len;
 822                 if (unlikely(!cur_size)) {
 823                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
 824                                    " left for mapping jumbo\n", num_segs);
 825                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 826                         return -EINVAL;
 827                 }
 828                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 829                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 830                 qede_rx_bd_ring_consume(rxq);
 831                 pkt_len -= cur_size;
 832                 seg2->data_len = cur_size;
 833                 seg1->next = seg2;
 834                 seg1 = seg1->next;
 835                 num_segs--;
 836                 rxq->rx_segs++;
 837         }
 838
 839         return 0;
 840 }
 841
 842 uint16_t
 843 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 844 {
 845         struct qede_rx_queue *rxq = p_rxq;
 846         struct qede_dev *qdev = rxq->qdev;
 847         struct ecore_dev *edev = &qdev->edev;
 848         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 849         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 850         uint16_t rx_pkt = 0;
 851         union eth_rx_cqe *cqe;
 852         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 853         register struct rte_mbuf *rx_mb = NULL;
 854         register struct rte_mbuf *seg1 = NULL;
 855         enum eth_rx_cqe_type cqe_type;
 856         uint16_t pkt_len; /* Sum of all BD segments */
 857         uint16_t len; /* Length of first BD */
 858         uint8_t num_segs = 1;
 859         uint16_t pad;
 860         uint16_t preload_idx;
 861         uint8_t csum_flag;
 862         uint16_t parse_flag;
 863         enum rss_hash_type htype;
 864         uint8_t tunn_parse_flag;
 865         uint8_t j;
 866
 867         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 868         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 869
 870         rte_rmb();
 871
 872         if (hw_comp_cons == sw_comp_cons)
 873                 return 0;
 874
 875         while (sw_comp_cons != hw_comp_cons) {
 876                 /* Get the CQE from the completion ring */
 877                 cqe =
 878                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 879                 cqe_type = cqe->fast_path_regular.type;
 880
 881                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 882                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
 883
 884                         qdev->ops->eth_cqe_completion(edev, fp->id,
 885                                 (struct eth_slow_path_rx_cqe *)cqe);
 886                         goto next_cqe;
 887                 }
 888
 889                 /* Get the data from the SW ring */
 890                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 891                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 892                 assert(rx_mb != NULL);
 893
 894                 /* non GRO */
 895                 fp_cqe = &cqe->fast_path_regular;
 896
 897                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 898                 pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 899                 pad = fp_cqe->placement_offset;
 900                 assert((len + pad) <= rx_mb->buf_len);
 901
 902                 PMD_RX_LOG(DEBUG, rxq,
 903                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 904                            " len = %u, parsing_flags = %d\n",
 905                            cqe_type, fp_cqe->bitfields,
 906                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 907                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 908
 909                 /* If this is an error packet then drop it */
 910                 parse_flag =
 911                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 912
 913                 rx_mb->ol_flags = 0;
 914
 915                 if (qede_tunn_exist(parse_flag)) {
 916                         PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet\n");
 917                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
 918                                 PMD_RX_LOG(ERR, rxq,
 919                                             "L4 csum failed, flags = 0x%x\n",
 920                                             parse_flag);
 921                                 rxq->rx_hw_errors++;
 922                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 923                         } else {
 924                                 tunn_parse_flag =
 925                                                 fp_cqe->tunnel_pars_flags.flags;
 926                                 rx_mb->packet_type =
 927                                         qede_rx_cqe_to_tunn_pkt_type(
 928                                                         tunn_parse_flag);
 929                         }
 930                 } else {
 931                         PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet\n");
 932                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
 933                                 PMD_RX_LOG(ERR, rxq,
 934                                             "L4 csum failed, flags = 0x%x\n",
 935                                             parse_flag);
 936                                 rxq->rx_hw_errors++;
 937                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 938                         } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
 939                                                         parse_flag))) {
 940                                 PMD_RX_LOG(ERR, rxq,
 941                                            "IP csum failed, flags = 0x%x\n",
 942                                            parse_flag);
 943                                 rxq->rx_hw_errors++;
 944                                 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 945                         } else {
 946                                 rx_mb->packet_type =
 947                                         qede_rx_cqe_to_pkt_type(parse_flag);
 948                         }
 949                 }
 950
 951                 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x\n", rx_mb->packet_type);
 952
 953                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 954                         PMD_RX_LOG(ERR, rxq,
 955                                    "New buffer allocation failed,"
 956                                    "dropping incoming packet\n");
 957                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 958                         rte_eth_devices[rxq->port_id].
 959                             data->rx_mbuf_alloc_failed++;
 960                         rxq->rx_alloc_errors++;
 961                         break;
 962                 }
 963                 qede_rx_bd_ring_consume(rxq);
 964                 if (fp_cqe->bd_num > 1) {
 965                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
 966                                    " len on first: %04x Total Len: %04x\n",
 967                                    fp_cqe->bd_num, len, pkt_len);
 968                         num_segs = fp_cqe->bd_num - 1;
 969                         seg1 = rx_mb;
 970                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
 971                                                  pkt_len - len))
 972                                 goto next_cqe;
 973                         for (j = 0; j < num_segs; j++) {
 974                                 if (qede_alloc_rx_buffer(rxq)) {
 975                                         PMD_RX_LOG(ERR, rxq,
 976                                                 "Buffer allocation failed\n");
 977                                         rte_eth_devices[rxq->port_id].
 978                                                 data->rx_mbuf_alloc_failed++;
 979                                         rxq->rx_alloc_errors++;
 980                                         break;
 981                                 }
 982                                 rxq->rx_segs++;
 983                         }
 984                 }
 985                 rxq->rx_segs++; /* for the first segment */
 986
 987                 /* Prefetch next mbuf while processing current one. */
 988                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 989                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
 990
 991                 /* Update rest of the MBUF fields */
 992                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
 993                 rx_mb->nb_segs = fp_cqe->bd_num;
 994                 rx_mb->data_len = len;
 995                 rx_mb->pkt_len = pkt_len;
 996                 rx_mb->port = rxq->port_id;
 997
 998                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
 999                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1000                 if (qdev->rss_enable && htype) {
1001                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1002                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1003                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1004                                    rx_mb->hash.rss);
1005                 }
1006
1007                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1008
1009                 if (CQE_HAS_VLAN(parse_flag)) {
1010                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1011                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1012                 }
1013
1014                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1015                         /* FW does not provide indication of Outer VLAN tag,
1016                          * which is always stripped, so vlan_tci_outer is set
1017                          * to 0. Here vlan_tag represents inner VLAN tag.
1018                          */
1019                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1020                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1021                         rx_mb->vlan_tci_outer = 0;
1022                 }
1023
1024                 rx_pkts[rx_pkt] = rx_mb;
1025                 rx_pkt++;
1026 next_cqe:
1027                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1028                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1029                 if (rx_pkt == nb_pkts) {
1030                         PMD_RX_LOG(DEBUG, rxq,
1031                                    "Budget reached nb_pkts=%u received=%u\n",
1032                                    rx_pkt, nb_pkts);
1033                         break;
1034                 }
1035         }
1036
1037         qede_update_rx_prod(qdev, rxq);
1038
1039         rxq->rcv_pkts += rx_pkt;
1040
1041         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1042
1043         return rx_pkt;
1044 }
1045
1046 static inline int
1047 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1048 {
1049         uint16_t nb_segs, idx = TX_CONS(txq);
1050         struct eth_tx_bd *tx_data_bd;
1051         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1052
1053         if (unlikely(!mbuf)) {
1054                 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1055                 PMD_TX_LOG(ERR, txq,
1056                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1057                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1058                            TX_PROD(txq));
1059                 return -1;
1060         }
1061
1062         nb_segs = mbuf->nb_segs;
1063         while (nb_segs) {
1064                 /* It's like consuming rxbuf in recv() */
1065                 ecore_chain_consume(&txq->tx_pbl);
1066                 txq->nb_tx_avail++;
1067                 nb_segs--;
1068         }
1069         rte_pktmbuf_free(mbuf);
1070         txq->sw_tx_ring[idx].mbuf = NULL;
1071
1072         return 0;
1073 }
1074
1075 static inline uint16_t
1076 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1077 {
1078         uint16_t tx_compl = 0;
1079         uint16_t hw_bd_cons;
1080
1081         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1082         rte_compiler_barrier();
1083
1084         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1085                 if (qede_free_tx_pkt(edev, txq)) {
1086                         PMD_TX_LOG(ERR, txq,
1087                                    "hw_bd_cons = %u, chain_cons = %u\n",
1088                                    hw_bd_cons,
1089                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1090                         break;
1091                 }
1092                 txq->sw_tx_cons++;      /* Making TXD available */
1093                 tx_compl++;
1094         }
1095
1096         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1097                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1098         return tx_compl;
1099 }
1100
1101 /* Populate scatter gather buffer descriptor fields */
1102 static inline uint8_t
1103 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1104                   struct eth_tx_1st_bd *bd1)
1105 {
1106         struct qede_tx_queue *txq = p_txq;
1107         struct eth_tx_2nd_bd *bd2 = NULL;
1108         struct eth_tx_3rd_bd *bd3 = NULL;
1109         struct eth_tx_bd *tx_bd = NULL;
1110         dma_addr_t mapping;
1111         uint8_t nb_segs = 1; /* min one segment per packet */
1112
1113         /* Check for scattered buffers */
1114         while (m_seg) {
1115                 if (nb_segs == 1) {
1116                         bd2 = (struct eth_tx_2nd_bd *)
1117                                 ecore_chain_produce(&txq->tx_pbl);
1118                         memset(bd2, 0, sizeof(*bd2));
1119                         mapping = rte_mbuf_data_dma_addr(m_seg);
1120                         QEDE_BD_SET_ADDR_LEN(bd2, mapping, m_seg->data_len);
1121                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x\n",
1122                                    m_seg->data_len);
1123                 } else if (nb_segs == 2) {
1124                         bd3 = (struct eth_tx_3rd_bd *)
1125                                 ecore_chain_produce(&txq->tx_pbl);
1126                         memset(bd3, 0, sizeof(*bd3));
1127                         mapping = rte_mbuf_data_dma_addr(m_seg);
1128                         QEDE_BD_SET_ADDR_LEN(bd3, mapping, m_seg->data_len);
1129                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x\n",
1130                                    m_seg->data_len);
1131                 } else {
1132                         tx_bd = (struct eth_tx_bd *)
1133                                 ecore_chain_produce(&txq->tx_pbl);
1134                         memset(tx_bd, 0, sizeof(*tx_bd));
1135                         mapping = rte_mbuf_data_dma_addr(m_seg);
1136                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1137                         PMD_TX_LOG(DEBUG, txq, "BD len %04x\n",
1138                                    m_seg->data_len);
1139                 }
1140                 nb_segs++;
1141                 m_seg = m_seg->next;
1142         }
1143
1144         /* Return total scattered buffers */
1145         return nb_segs;
1146 }
1147
1148 uint16_t
1149 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1150 {
1151         struct qede_tx_queue *txq = p_txq;
1152         struct qede_dev *qdev = txq->qdev;
1153         struct ecore_dev *edev = &qdev->edev;
1154         struct qede_fastpath *fp;
1155         struct eth_tx_1st_bd *bd1;
1156         struct rte_mbuf *mbuf;
1157         struct rte_mbuf *m_seg = NULL;
1158         uint16_t nb_tx_pkts;
1159         uint16_t bd_prod;
1160         uint16_t idx;
1161         uint16_t tx_count;
1162         uint16_t nb_frags;
1163         uint16_t nb_pkt_sent = 0;
1164
1165         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1166
1167         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1168                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1169                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1170                 (void)qede_process_tx_compl(edev, txq);
1171         }
1172
1173         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1174                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1175         if (unlikely(nb_tx_pkts == 0)) {
1176                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1177                            nb_pkts, txq->nb_tx_avail);
1178                 return 0;
1179         }
1180
1181         tx_count = nb_tx_pkts;
1182         while (nb_tx_pkts--) {
1183                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1184                 idx = TX_PROD(txq);
1185                 mbuf = *tx_pkts++;
1186                 txq->sw_tx_ring[idx].mbuf = mbuf;
1187                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1188                 bd1->data.bd_flags.bitfields =
1189                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1190                 /* FW 8.10.x specific change */
1191                 bd1->data.bitfields =
1192                         (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1193                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1194                 /* Map MBUF linear data for DMA and set in the first BD */
1195                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1196                                      mbuf->data_len);
1197                 PMD_TX_LOG(INFO, txq, "BD1 len %04x\n", mbuf->data_len);
1198
1199                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1200                         PMD_TX_LOG(INFO, txq, "Tx tunnel packet\n");
1201                         /* First indicate its a tunnel pkt */
1202                         bd1->data.bd_flags.bitfields |=
1203                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1204                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1205
1206                         /* Legacy FW had flipped behavior in regard to this bit
1207                          * i.e. it needed to set to prevent FW from touching
1208                          * encapsulated packets when it didn't need to.
1209                          */
1210                         if (unlikely(txq->is_legacy))
1211                                 bd1->data.bitfields ^=
1212                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1213
1214                         /* Outer IP checksum offload */
1215                         if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1216                                 PMD_TX_LOG(INFO, txq, "OuterIP csum offload\n");
1217                                 bd1->data.bd_flags.bitfields |=
1218                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1219                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1220                         }
1221
1222                         /* Outer UDP checksum offload */
1223                         bd1->data.bd_flags.bitfields |=
1224                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1225                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1226                 }
1227
1228                 /* Descriptor based VLAN insertion */
1229                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1230                         PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x\n",
1231                                    mbuf->vlan_tci);
1232                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1233                         bd1->data.bd_flags.bitfields |=
1234                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1235                 }
1236
1237                 /* Offload the IP checksum in the hardware */
1238                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1239                         PMD_TX_LOG(INFO, txq, "IP csum offload\n");
1240                         bd1->data.bd_flags.bitfields |=
1241                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1242                 }
1243
1244                 /* L4 checksum offload (tcp or udp) */
1245                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1246                         PMD_TX_LOG(INFO, txq, "L4 csum offload\n");
1247                         bd1->data.bd_flags.bitfields |=
1248                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1249                         /* IPv6 + extn. -> later */
1250                 }
1251
1252                 /* Handle fragmented MBUF */
1253                 m_seg = mbuf->next;
1254                 /* Encode scatter gather buffer descriptors if required */
1255                 nb_frags = qede_encode_sg_bd(txq, m_seg, bd1);
1256                 bd1->data.nbds = nb_frags;
1257                 txq->nb_tx_avail -= nb_frags;
1258                 txq->sw_tx_prod++;
1259                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1260                 bd_prod =
1261                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1262                 nb_pkt_sent++;
1263                 txq->xmit_pkts++;
1264                 PMD_TX_LOG(INFO, txq, "nbds = %d pkt_len = %04x\n",
1265                            bd1->data.nbds, mbuf->pkt_len);
1266         }
1267
1268         /* Write value of prod idx into bd_prod */
1269         txq->tx_db.data.bd_prod = bd_prod;
1270         rte_wmb();
1271         rte_compiler_barrier();
1272         DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1273         rte_wmb();
1274
1275         /* Check again for Tx completions */
1276         (void)qede_process_tx_compl(edev, txq);
1277
1278         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1279                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1280
1281         return nb_pkt_sent;
1282 }
1283
1284 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1285 {
1286         struct qede_dev *qdev = eth_dev->data->dev_private;
1287         struct qede_fastpath *fp;
1288         uint8_t i, rss_id, txq_index, tc;
1289         int rxq = 0, txq = 0;
1290
1291         for_each_queue(i) {
1292                 fp = &qdev->fp_array[i];
1293                 if (fp->type & QEDE_FASTPATH_RX) {
1294                         fp->rxq = eth_dev->data->rx_queues[i];
1295                         fp->rxq->queue_id = rxq++;
1296                 }
1297
1298                 if (fp->type & QEDE_FASTPATH_TX) {
1299                         for (tc = 0; tc < qdev->num_tc; tc++) {
1300                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1301                                 fp->txqs[tc] =
1302                                         eth_dev->data->tx_queues[txq_index];
1303                                 fp->txqs[tc]->queue_id = txq_index;
1304                                 if (qdev->dev_info.is_legacy)
1305                                         fp->txqs[tc]->is_legacy = true;
1306                         }
1307                         txq++;
1308                 }
1309         }
1310 }
1311
1312 int qede_dev_start(struct rte_eth_dev *eth_dev)
1313 {
1314         struct qede_dev *qdev = eth_dev->data->dev_private;
1315         struct ecore_dev *edev = &qdev->edev;
1316         struct qed_link_output link_output;
1317         struct qede_fastpath *fp;
1318         int rc;
1319
1320         DP_INFO(edev, "Device state is %d\n", qdev->state);
1321
1322         if (qdev->state == QEDE_DEV_START) {
1323                 DP_INFO(edev, "Port is already started\n");
1324                 return 0;
1325         }
1326
1327         if (qdev->state == QEDE_DEV_CONFIG)
1328                 qede_init_fp_queue(eth_dev);
1329
1330         rc = qede_start_queues(eth_dev, true);
1331         if (rc) {
1332                 DP_ERR(edev, "Failed to start queues\n");
1333                 /* TBD: free */
1334                 return rc;
1335         }
1336
1337         /* Bring-up the link */
1338         qede_dev_set_link_state(eth_dev, true);
1339
1340         /* Reset ring */
1341         if (qede_reset_fp_rings(qdev))
1342                 return -ENOMEM;
1343
1344         /* Start/resume traffic */
1345         qdev->ops->fastpath_start(edev);
1346
1347         qdev->state = QEDE_DEV_START;
1348
1349         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1350
1351         return 0;
1352 }
1353
1354 static int qede_drain_txq(struct qede_dev *qdev,
1355                           struct qede_tx_queue *txq, bool allow_drain)
1356 {
1357         struct ecore_dev *edev = &qdev->edev;
1358         int rc, cnt = 1000;
1359
1360         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1361                 qede_process_tx_compl(edev, txq);
1362                 if (!cnt) {
1363                         if (allow_drain) {
1364                                 DP_NOTICE(edev, false,
1365                                           "Tx queue[%u] is stuck,"
1366                                           "requesting MCP to drain\n",
1367                                           txq->queue_id);
1368                                 rc = qdev->ops->common->drain(edev);
1369                                 if (rc)
1370                                         return rc;
1371                                 return qede_drain_txq(qdev, txq, false);
1372                         }
1373
1374                         DP_NOTICE(edev, false,
1375                                   "Timeout waiting for tx queue[%d]:"
1376                                   "PROD=%d, CONS=%d\n",
1377                                   txq->queue_id, txq->sw_tx_prod,
1378                                   txq->sw_tx_cons);
1379                         return -ENODEV;
1380                 }
1381                 cnt--;
1382                 DELAY(1000);
1383                 rte_compiler_barrier();
1384         }
1385
1386         /* FW finished processing, wait for HW to transmit all tx packets */
1387         DELAY(2000);
1388
1389         return 0;
1390 }
1391
1392 static int qede_stop_queues(struct qede_dev *qdev)
1393 {
1394         struct qed_update_vport_params vport_update_params;
1395         struct ecore_dev *edev = &qdev->edev;
1396         int rc, tc, i;
1397
1398         /* Disable the vport */
1399         memset(&vport_update_params, 0, sizeof(vport_update_params));
1400         vport_update_params.vport_id = 0;
1401         vport_update_params.update_vport_active_flg = 1;
1402         vport_update_params.vport_active_flg = 0;
1403         vport_update_params.update_rss_flg = 0;
1404
1405         DP_INFO(edev, "Deactivate vport\n");
1406
1407         rc = qdev->ops->vport_update(edev, &vport_update_params);
1408         if (rc) {
1409                 DP_ERR(edev, "Failed to update vport\n");
1410                 return rc;
1411         }
1412
1413         DP_INFO(edev, "Flushing tx queues\n");
1414
1415         /* Flush Tx queues. If needed, request drain from MCP */
1416         for_each_queue(i) {
1417                 struct qede_fastpath *fp = &qdev->fp_array[i];
1418
1419                 if (fp->type & QEDE_FASTPATH_TX) {
1420                         for (tc = 0; tc < qdev->num_tc; tc++) {
1421                                 struct qede_tx_queue *txq = fp->txqs[tc];
1422
1423                                 rc = qede_drain_txq(qdev, txq, true);
1424                                 if (rc)
1425                                         return rc;
1426                         }
1427                 }
1428         }
1429
1430         /* Stop all Queues in reverse order */
1431         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1432                 struct qed_stop_rxq_params rx_params;
1433
1434                 /* Stop the Tx Queue(s) */
1435                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1436                         for (tc = 0; tc < qdev->num_tc; tc++) {
1437                                 struct qed_stop_txq_params tx_params;
1438                                 u8 val;
1439
1440                                 tx_params.rss_id = i;
1441                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1442                                 tx_params.tx_queue_id = val;
1443
1444                                 DP_INFO(edev, "Stopping tx queues\n");
1445                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1446                                 if (rc) {
1447                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1448                                                tx_params.tx_queue_id);
1449                                         return rc;
1450                                 }
1451                         }
1452                 }
1453
1454                 /* Stop the Rx Queue */
1455                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1456                         memset(&rx_params, 0, sizeof(rx_params));
1457                         rx_params.rss_id = i;
1458                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1459                         rx_params.eq_completion_only = 1;
1460
1461                         DP_INFO(edev, "Stopping rx queues\n");
1462
1463                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1464                         if (rc) {
1465                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1466                                 return rc;
1467                         }
1468                 }
1469         }
1470
1471         return 0;
1472 }
1473
1474 int qede_reset_fp_rings(struct qede_dev *qdev)
1475 {
1476         struct qede_fastpath *fp;
1477         struct qede_tx_queue *txq;
1478         uint8_t tc;
1479         uint16_t id, i;
1480
1481         for_each_queue(id) {
1482                 fp = &qdev->fp_array[id];
1483
1484                 if (fp->type & QEDE_FASTPATH_RX) {
1485                         DP_INFO(&qdev->edev,
1486                                 "Reset FP chain for RSS %u\n", id);
1487                         qede_rx_queue_release_mbufs(fp->rxq);
1488                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1489                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1490                         fp->rxq->sw_rx_prod = 0;
1491                         fp->rxq->sw_rx_cons = 0;
1492                         *fp->rxq->hw_cons_ptr = 0;
1493                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1494                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1495                                         DP_ERR(&qdev->edev,
1496                                                "RX buffer allocation failed\n");
1497                                         return -ENOMEM;
1498                                 }
1499                         }
1500                 }
1501                 if (fp->type & QEDE_FASTPATH_TX) {
1502                         for (tc = 0; tc < qdev->num_tc; tc++) {
1503                                 txq = fp->txqs[tc];
1504                                 qede_tx_queue_release_mbufs(txq);
1505                                 ecore_chain_reset(&txq->tx_pbl);
1506                                 txq->sw_tx_cons = 0;
1507                                 txq->sw_tx_prod = 0;
1508                                 *txq->hw_cons_ptr = 0;
1509                         }
1510                 }
1511         }
1512
1513         return 0;
1514 }
1515
1516 /* This function frees all memory of a single fp */
1517 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1518 {
1519         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1520         struct qede_fastpath *fp;
1521         uint16_t txq_idx;
1522         uint8_t id;
1523         uint8_t tc;
1524
1525         for_each_queue(id) {
1526                 fp = &qdev->fp_array[id];
1527                 if (fp->type & QEDE_FASTPATH_RX) {
1528                         if (!fp->rxq)
1529                                 continue;
1530                         qede_rx_queue_release(fp->rxq);
1531                         eth_dev->data->rx_queues[id] = NULL;
1532                 } else {
1533                         for (tc = 0; tc < qdev->num_tc; tc++) {
1534                                 if (!fp->txqs[tc])
1535                                         continue;
1536                                 txq_idx = fp->txqs[tc]->queue_id;
1537                                 qede_tx_queue_release(fp->txqs[tc]);
1538                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1539                         }
1540                 }
1541         }
1542 }
1543
1544 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1545 {
1546         struct qede_dev *qdev = eth_dev->data->dev_private;
1547         struct ecore_dev *edev = &qdev->edev;
1548
1549         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1550
1551         if (qdev->state != QEDE_DEV_START) {
1552                 DP_INFO(edev, "Device not yet started\n");
1553                 return;
1554         }
1555
1556         if (qede_stop_queues(qdev))
1557                 DP_ERR(edev, "Didn't succeed to close queues\n");
1558
1559         DP_INFO(edev, "Stopped queues\n");
1560
1561         qdev->ops->fastpath_stop(edev);
1562
1563         /* Bring the link down */
1564         qede_dev_set_link_state(eth_dev, false);
1565
1566         qdev->state = QEDE_DEV_STOP;
1567
1568         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1569 }