drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  41 {
  42         uint16_t i;
  43
  44         if (rxq->sw_rx_ring != NULL) {
  45                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  46                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  47                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  48                                 rxq->sw_rx_ring[i].mbuf = NULL;
  49                         }
  50                 }
  51         }
  52 }
  53
  54 void qede_rx_queue_release(void *rx_queue)
  55 {
  56         struct qede_rx_queue *rxq = rx_queue;
  57
  58         if (rxq != NULL) {
  59                 qede_rx_queue_release_mbufs(rxq);
  60                 rte_free(rxq->sw_rx_ring);
  61                 rxq->sw_rx_ring = NULL;
  62                 rte_free(rxq);
  63                 rxq = NULL;
  64         }
  65 }
  66
  67 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  68 {
  69         unsigned int i;
  70
  71         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs", txq->nb_tx_desc);
  72
  73         if (txq->sw_tx_ring) {
  74                 for (i = 0; i < txq->nb_tx_desc; i++) {
  75                         if (txq->sw_tx_ring[i].mbuf) {
  76                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  77                                 txq->sw_tx_ring[i].mbuf = NULL;
  78                         }
  79                 }
  80         }
  81 }
  82
  83 int
  84 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  85                     uint16_t nb_desc, unsigned int socket_id,
  86                     const struct rte_eth_rxconf *rx_conf,
  87                     struct rte_mempool *mp)
  88 {
  89         struct qede_dev *qdev = dev->data->dev_private;
  90         struct ecore_dev *edev = &qdev->edev;
  91         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  92         struct qede_rx_queue *rxq;
  93         uint16_t max_rx_pkt_len;
  94         uint16_t bufsz;
  95         size_t size;
  96         int rc;
  97         int i;
  98
  99         PMD_INIT_FUNC_TRACE(edev);
 100
 101         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 102         if (!rte_is_power_of_2(nb_desc)) {
 103                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 104                           nb_desc);
 105                 return -EINVAL;
 106         }
 107
 108         /* Free memory prior to re-allocation if needed... */
 109         if (dev->data->rx_queues[queue_idx] != NULL) {
 110                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 111                 dev->data->rx_queues[queue_idx] = NULL;
 112         }
 113
 114         /* First allocate the rx queue data structure */
 115         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 116                                  RTE_CACHE_LINE_SIZE, socket_id);
 117
 118         if (!rxq) {
 119                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 120                           socket_id);
 121                 return -ENOMEM;
 122         }
 123
 124         rxq->qdev = qdev;
 125         rxq->mb_pool = mp;
 126         rxq->nb_rx_desc = nb_desc;
 127         rxq->queue_id = queue_idx;
 128         rxq->port_id = dev->data->port_id;
 129         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 130         qdev->mtu = max_rx_pkt_len;
 131
 132         /* Fix up RX buffer size */
 133         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 134         if ((rxmode->enable_scatter)                    ||
 135             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 136                 if (!dev->data->scattered_rx) {
 137                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 138                         dev->data->scattered_rx = 1;
 139                 }
 140         }
 141         if (dev->data->scattered_rx)
 142                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 143         else
 144                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 145         /* Align to cache-line size if needed */
 146         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 147
 148         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 149                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 150
 151         /* Allocate the parallel driver ring for Rx buffers */
 152         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 153         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 154                                              RTE_CACHE_LINE_SIZE, socket_id);
 155         if (!rxq->sw_rx_ring) {
 156                 DP_NOTICE(edev, false,
 157                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 158                           socket_id);
 159                 rte_free(rxq);
 160                 rxq = NULL;
 161                 return -ENOMEM;
 162         }
 163
 164         /* Allocate FW Rx ring  */
 165         rc = qdev->ops->common->chain_alloc(edev,
 166                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 167                                             ECORE_CHAIN_MODE_NEXT_PTR,
 168                                             ECORE_CHAIN_CNT_TYPE_U16,
 169                                             rxq->nb_rx_desc,
 170                                             sizeof(struct eth_rx_bd),
 171                                             &rxq->rx_bd_ring,
 172                                             NULL);
 173
 174         if (rc != ECORE_SUCCESS) {
 175                 DP_NOTICE(edev, false,
 176                           "Unable to alloc memory for rxbd ring on socket %u\n",
 177                           socket_id);
 178                 rte_free(rxq->sw_rx_ring);
 179                 rxq->sw_rx_ring = NULL;
 180                 rte_free(rxq);
 181                 rxq = NULL;
 182                 return -ENOMEM;
 183         }
 184
 185         /* Allocate FW completion ring */
 186         rc = qdev->ops->common->chain_alloc(edev,
 187                                             ECORE_CHAIN_USE_TO_CONSUME,
 188                                             ECORE_CHAIN_MODE_PBL,
 189                                             ECORE_CHAIN_CNT_TYPE_U16,
 190                                             rxq->nb_rx_desc,
 191                                             sizeof(union eth_rx_cqe),
 192                                             &rxq->rx_comp_ring,
 193                                             NULL);
 194
 195         if (rc != ECORE_SUCCESS) {
 196                 DP_NOTICE(edev, false,
 197                           "Unable to alloc memory for cqe ring on socket %u\n",
 198                           socket_id);
 199                 /* TBD: Freeing RX BD ring */
 200                 rte_free(rxq->sw_rx_ring);
 201                 rxq->sw_rx_ring = NULL;
 202                 rte_free(rxq);
 203                 return -ENOMEM;
 204         }
 205
 206         /* Allocate buffers for the Rx ring */
 207         for (i = 0; i < rxq->nb_rx_desc; i++) {
 208                 rc = qede_alloc_rx_buffer(rxq);
 209                 if (rc) {
 210                         DP_NOTICE(edev, false,
 211                                   "RX buffer allocation failed at idx=%d\n", i);
 212                         goto err4;
 213                 }
 214         }
 215
 216         dev->data->rx_queues[queue_idx] = rxq;
 217
 218         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 219                   queue_idx, nb_desc, qdev->mtu, socket_id);
 220
 221         return 0;
 222 err4:
 223         qede_rx_queue_release(rxq);
 224         return -ENOMEM;
 225 }
 226
 227 void qede_tx_queue_release(void *tx_queue)
 228 {
 229         struct qede_tx_queue *txq = tx_queue;
 230
 231         if (txq != NULL) {
 232                 qede_tx_queue_release_mbufs(txq);
 233                 if (txq->sw_tx_ring) {
 234                         rte_free(txq->sw_tx_ring);
 235                         txq->sw_tx_ring = NULL;
 236                 }
 237                 rte_free(txq);
 238         }
 239         txq = NULL;
 240 }
 241
 242 int
 243 qede_tx_queue_setup(struct rte_eth_dev *dev,
 244                     uint16_t queue_idx,
 245                     uint16_t nb_desc,
 246                     unsigned int socket_id,
 247                     const struct rte_eth_txconf *tx_conf)
 248 {
 249         struct qede_dev *qdev = dev->data->dev_private;
 250         struct ecore_dev *edev = &qdev->edev;
 251         struct qede_tx_queue *txq;
 252         int rc;
 253
 254         PMD_INIT_FUNC_TRACE(edev);
 255
 256         if (!rte_is_power_of_2(nb_desc)) {
 257                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 258                        nb_desc);
 259                 return -EINVAL;
 260         }
 261
 262         /* Free memory prior to re-allocation if needed... */
 263         if (dev->data->tx_queues[queue_idx] != NULL) {
 264                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 265                 dev->data->tx_queues[queue_idx] = NULL;
 266         }
 267
 268         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 269                                  RTE_CACHE_LINE_SIZE, socket_id);
 270
 271         if (txq == NULL) {
 272                 DP_ERR(edev,
 273                        "Unable to allocate memory for txq on socket %u",
 274                        socket_id);
 275                 return -ENOMEM;
 276         }
 277
 278         txq->nb_tx_desc = nb_desc;
 279         txq->qdev = qdev;
 280         txq->port_id = dev->data->port_id;
 281
 282         rc = qdev->ops->common->chain_alloc(edev,
 283                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 284                                             ECORE_CHAIN_MODE_PBL,
 285                                             ECORE_CHAIN_CNT_TYPE_U16,
 286                                             txq->nb_tx_desc,
 287                                             sizeof(union eth_tx_bd_types),
 288                                             &txq->tx_pbl,
 289                                             NULL);
 290         if (rc != ECORE_SUCCESS) {
 291                 DP_ERR(edev,
 292                        "Unable to allocate memory for txbd ring on socket %u",
 293                        socket_id);
 294                 qede_tx_queue_release(txq);
 295                 return -ENOMEM;
 296         }
 297
 298         /* Allocate software ring */
 299         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 300                                              (sizeof(struct qede_tx_entry) *
 301                                               txq->nb_tx_desc),
 302                                              RTE_CACHE_LINE_SIZE, socket_id);
 303
 304         if (!txq->sw_tx_ring) {
 305                 DP_ERR(edev,
 306                        "Unable to allocate memory for txbd ring on socket %u",
 307                        socket_id);
 308                 qede_tx_queue_release(txq);
 309                 return -ENOMEM;
 310         }
 311
 312         txq->queue_id = queue_idx;
 313
 314         txq->nb_tx_avail = txq->nb_tx_desc;
 315
 316         txq->tx_free_thresh =
 317             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 318             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 319
 320         dev->data->tx_queues[queue_idx] = txq;
 321
 322         DP_INFO(edev,
 323                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 324                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 325
 326         return 0;
 327 }
 328
 329 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 330 static void qede_init_fp(struct qede_dev *qdev)
 331 {
 332         struct qede_fastpath *fp;
 333         uint8_t i, rss_id, tc;
 334         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 335
 336         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 337                                            sizeof(*qdev->fp_array)));
 338         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 339                                            sizeof(*qdev->sb_array)));
 340         for_each_queue(i) {
 341                 fp = &qdev->fp_array[i];
 342                 if (fp_rx) {
 343                         fp->type = QEDE_FASTPATH_RX;
 344                         fp_rx--;
 345                 } else{
 346                         fp->type = QEDE_FASTPATH_TX;
 347                 }
 348                 fp->qdev = qdev;
 349                 fp->id = i;
 350                 fp->sb_info = &qdev->sb_array[i];
 351                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 352         }
 353
 354 }
 355
 356 void qede_free_fp_arrays(struct qede_dev *qdev)
 357 {
 358         /* It asseumes qede_free_mem_load() is called before */
 359         if (qdev->fp_array != NULL) {
 360                 rte_free(qdev->fp_array);
 361                 qdev->fp_array = NULL;
 362         }
 363
 364         if (qdev->sb_array != NULL) {
 365                 rte_free(qdev->sb_array);
 366                 qdev->sb_array = NULL;
 367         }
 368 }
 369
 370 int qede_alloc_fp_array(struct qede_dev *qdev)
 371 {
 372         struct qede_fastpath *fp;
 373         struct ecore_dev *edev = &qdev->edev;
 374         int i;
 375
 376         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 377                                     sizeof(*qdev->fp_array),
 378                                     RTE_CACHE_LINE_SIZE);
 379
 380         if (!qdev->fp_array) {
 381                 DP_ERR(edev, "fp array allocation failed\n");
 382                 return -ENOMEM;
 383         }
 384
 385         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 386                                     sizeof(*qdev->sb_array),
 387                                     RTE_CACHE_LINE_SIZE);
 388
 389         if (!qdev->sb_array) {
 390                 DP_ERR(edev, "sb array allocation failed\n");
 391                 rte_free(qdev->fp_array);
 392                 return -ENOMEM;
 393         }
 394
 395         return 0;
 396 }
 397
 398 /* This function allocates fast-path status block memory */
 399 static int
 400 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 401                   uint16_t sb_id)
 402 {
 403         struct ecore_dev *edev = &qdev->edev;
 404         struct status_block *sb_virt;
 405         dma_addr_t sb_phys;
 406         int rc;
 407
 408         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 409
 410         if (!sb_virt) {
 411                 DP_ERR(edev, "Status block allocation failed\n");
 412                 return -ENOMEM;
 413         }
 414
 415         rc = qdev->ops->common->sb_init(edev, sb_info,
 416                                         sb_virt, sb_phys, sb_id,
 417                                         QED_SB_TYPE_L2_QUEUE);
 418         if (rc) {
 419                 DP_ERR(edev, "Status block initialization failed\n");
 420                 /* TBD: No dma_free_coherent possible */
 421                 return rc;
 422         }
 423
 424         return 0;
 425 }
 426
 427 int qede_alloc_fp_resc(struct qede_dev *qdev)
 428 {
 429         struct ecore_dev *edev = &qdev->edev;
 430         struct qede_fastpath *fp;
 431         uint32_t num_sbs;
 432         uint16_t i;
 433         uint16_t sb_idx;
 434         int rc;
 435
 436         if (IS_VF(edev))
 437                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 438         else
 439                 num_sbs = ecore_cxt_get_proto_cid_count
 440                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 441
 442         if (num_sbs == 0) {
 443                 DP_ERR(edev, "No status blocks available\n");
 444                 return -EINVAL;
 445         }
 446
 447         if (qdev->fp_array)
 448                 qede_free_fp_arrays(qdev);
 449
 450         rc = qede_alloc_fp_array(qdev);
 451         if (rc != 0)
 452                 return rc;
 453
 454         qede_init_fp(qdev);
 455
 456         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 457                 fp = &qdev->fp_array[i];
 458                 if (IS_VF(edev))
 459                         sb_idx = i % num_sbs;
 460                 else
 461                         sb_idx = i;
 462                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 463                         qede_free_fp_arrays(qdev);
 464                         return -ENOMEM;
 465                 }
 466         }
 467
 468         return 0;
 469 }
 470
 471 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 472 {
 473         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 474
 475         qede_free_mem_load(eth_dev);
 476         qede_free_fp_arrays(qdev);
 477 }
 478
 479 static inline void
 480 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 481 {
 482         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 483         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 484         struct eth_rx_prod_data rx_prods = { 0 };
 485
 486         /* Update producers */
 487         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 488         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 489
 490         /* Make sure that the BD and SGE data is updated before updating the
 491          * producers since FW might read the BD/SGE right after the producer
 492          * is updated.
 493          */
 494         rte_wmb();
 495
 496         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 497                         (uint32_t *)&rx_prods);
 498
 499         /* mmiowb is needed to synchronize doorbell writes from more than one
 500          * processor. It guarantees that the write arrives to the device before
 501          * the napi lock is released and another qede_poll is called (possibly
 502          * on another CPU). Without this barrier, the next doorbell can bypass
 503          * this doorbell. This is applicable to IA64/Altix systems.
 504          */
 505         rte_wmb();
 506
 507         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 508 }
 509
 510 static void
 511 qede_update_sge_tpa_params(struct ecore_sge_tpa_params *sge_tpa_params,
 512                            uint16_t mtu, bool enable)
 513 {
 514         /* Enable LRO in split mode */
 515         sge_tpa_params->tpa_ipv4_en_flg = enable;
 516         sge_tpa_params->tpa_ipv6_en_flg = enable;
 517         sge_tpa_params->tpa_ipv4_tunn_en_flg = enable;
 518         sge_tpa_params->tpa_ipv6_tunn_en_flg = enable;
 519         /* set if tpa enable changes */
 520         sge_tpa_params->update_tpa_en_flg = 1;
 521         /* set if tpa parameters should be handled */
 522         sge_tpa_params->update_tpa_param_flg = enable;
 523
 524         sge_tpa_params->max_buffers_per_cqe = 20;
 525         sge_tpa_params->tpa_pkt_split_flg = 1;
 526         sge_tpa_params->tpa_hdr_data_split_flg = 0;
 527         sge_tpa_params->tpa_gro_consistent_flg = 0;
 528         sge_tpa_params->tpa_max_aggs_num = ETH_TPA_MAX_AGGS_NUM;
 529         sge_tpa_params->tpa_max_size = 0x7FFF;
 530         sge_tpa_params->tpa_min_size_to_start = mtu / 2;
 531         sge_tpa_params->tpa_min_size_to_cont = mtu / 2;
 532 }
 533
 534 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 535 {
 536         struct qede_dev *qdev = eth_dev->data->dev_private;
 537         struct ecore_dev *edev = &qdev->edev;
 538         struct ecore_queue_start_common_params q_params;
 539         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 540         struct qed_update_vport_params vport_update_params;
 541         struct ecore_sge_tpa_params tpa_params;
 542         struct qede_tx_queue *txq;
 543         struct qede_fastpath *fp;
 544         dma_addr_t p_phys_table;
 545         int txq_index;
 546         uint16_t page_cnt;
 547         int vlan_removal_en = 1;
 548         int rc, tc, i;
 549
 550         for_each_queue(i) {
 551                 fp = &qdev->fp_array[i];
 552                 if (fp->type & QEDE_FASTPATH_RX) {
 553                         struct ecore_rxq_start_ret_params ret_params;
 554
 555                         p_phys_table =
 556                             ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 557                         page_cnt =
 558                             ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 559
 560                         memset(&ret_params, 0, sizeof(ret_params));
 561                         memset(&q_params, 0, sizeof(q_params));
 562                         q_params.queue_id = i;
 563                         q_params.vport_id = 0;
 564                         q_params.sb = fp->sb_info->igu_sb_id;
 565                         q_params.sb_idx = RX_PI;
 566
 567                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 568
 569                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 570                                            fp->rxq->rx_buf_size,
 571                                            fp->rxq->rx_bd_ring.p_phys_addr,
 572                                            p_phys_table,
 573                                            page_cnt,
 574                                            &ret_params);
 575                         if (rc) {
 576                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 577                                        fp->rxq->queue_id, rc);
 578                                 return rc;
 579                         }
 580
 581                         /* Use the return parameters */
 582                         fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 583                         fp->rxq->handle = ret_params.p_handle;
 584
 585                         fp->rxq->hw_cons_ptr =
 586                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 587
 588                         qede_update_rx_prod(qdev, fp->rxq);
 589                 }
 590
 591                 if (!(fp->type & QEDE_FASTPATH_TX))
 592                         continue;
 593                 for (tc = 0; tc < qdev->num_tc; tc++) {
 594                         struct ecore_txq_start_ret_params ret_params;
 595
 596                         txq = fp->txqs[tc];
 597                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 598
 599                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 600                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 601
 602                         memset(&q_params, 0, sizeof(q_params));
 603                         memset(&ret_params, 0, sizeof(ret_params));
 604                         q_params.queue_id = txq->queue_id;
 605                         q_params.vport_id = 0;
 606                         q_params.sb = fp->sb_info->igu_sb_id;
 607                         q_params.sb_idx = TX_PI(tc);
 608
 609                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 610                                                    p_phys_table,
 611                                                    page_cnt, /* **pp_doorbell */
 612                                                    &ret_params);
 613                         if (rc) {
 614                                 DP_ERR(edev, "Start txq %u failed %d\n",
 615                                        txq_index, rc);
 616                                 return rc;
 617                         }
 618
 619                         txq->doorbell_addr = ret_params.p_doorbell;
 620                         txq->handle = ret_params.p_handle;
 621
 622                         txq->hw_cons_ptr =
 623                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 624                         SET_FIELD(txq->tx_db.data.params,
 625                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 626                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 627                                   DB_AGG_CMD_SET);
 628                         SET_FIELD(txq->tx_db.data.params,
 629                                   ETH_DB_DATA_AGG_VAL_SEL,
 630                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 631
 632                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 633                 }
 634         }
 635
 636         /* Prepare and send the vport enable */
 637         memset(&vport_update_params, 0, sizeof(vport_update_params));
 638         /* Update MTU via vport update */
 639         vport_update_params.mtu = qdev->mtu;
 640         vport_update_params.vport_id = 0;
 641         vport_update_params.update_vport_active_flg = 1;
 642         vport_update_params.vport_active_flg = 1;
 643
 644         /* @DPDK */
 645         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 646                 /* TBD: Check SRIOV enabled for VF */
 647                 vport_update_params.update_tx_switching_flg = 1;
 648                 vport_update_params.tx_switching_flg = 1;
 649         }
 650
 651         /* TPA */
 652         if (qdev->enable_lro) {
 653                 DP_INFO(edev, "Enabling LRO\n");
 654                 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
 655                 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, true);
 656                 vport_update_params.sge_tpa_params = &tpa_params;
 657         }
 658
 659         rc = qdev->ops->vport_update(edev, &vport_update_params);
 660         if (rc) {
 661                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 662                 return rc;
 663         }
 664
 665         return 0;
 666 }
 667
 668 static bool qede_tunn_exist(uint16_t flag)
 669 {
 670         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 671                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 672 }
 673
 674 /*
 675  * qede_check_tunn_csum_l4:
 676  * Returns:
 677  * 1 : If L4 csum is enabled AND if the validation has failed.
 678  * 0 : Otherwise
 679  */
 680 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 681 {
 682         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 683              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 684                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 685                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 686
 687         return 0;
 688 }
 689
 690 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 691 {
 692         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 693              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 694                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 695                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 696
 697         return 0;
 698 }
 699
 700 static inline uint8_t
 701 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 702 {
 703         struct ipv4_hdr *ip;
 704         uint16_t pkt_csum;
 705         uint16_t calc_csum;
 706         uint16_t val;
 707
 708         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 709                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 710
 711         if (unlikely(val)) {
 712                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 713                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 714                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 715                                            sizeof(struct ether_hdr));
 716                         pkt_csum = ip->hdr_checksum;
 717                         ip->hdr_checksum = 0;
 718                         calc_csum = rte_ipv4_cksum(ip);
 719                         ip->hdr_checksum = pkt_csum;
 720                         return (calc_csum != pkt_csum);
 721                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 722                         return 1;
 723                 }
 724         }
 725         return 0;
 726 }
 727
 728 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 729 {
 730         ecore_chain_consume(&rxq->rx_bd_ring);
 731         rxq->sw_rx_cons++;
 732 }
 733
 734 static inline void
 735 qede_reuse_page(struct qede_dev *qdev,
 736                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 737 {
 738         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 739         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 740         struct qede_rx_entry *curr_prod;
 741         dma_addr_t new_mapping;
 742
 743         curr_prod = &rxq->sw_rx_ring[idx];
 744         *curr_prod = *curr_cons;
 745
 746         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 747                       curr_prod->page_offset;
 748
 749         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 750         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 751
 752         rxq->sw_rx_prod++;
 753 }
 754
 755 static inline void
 756 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 757                         struct qede_dev *qdev, uint8_t count)
 758 {
 759         struct qede_rx_entry *curr_cons;
 760
 761         for (; count > 0; count--) {
 762                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 763                 qede_reuse_page(qdev, rxq, curr_cons);
 764                 qede_rx_bd_ring_consume(rxq);
 765         }
 766 }
 767
 768 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 769 {
 770         uint16_t val;
 771
 772         /* Lookup table */
 773         static const uint32_t
 774         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 775                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 776                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 777                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 778                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 779                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 780                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 781         };
 782
 783         /* Bits (0..3) provides L3/L4 protocol type */
 784         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 785                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 786                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 787                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 788
 789         if (val < QEDE_PKT_TYPE_MAX)
 790                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 791         else
 792                 return RTE_PTYPE_UNKNOWN;
 793 }
 794
 795 static inline void
 796 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
 797                              struct qede_rx_queue *rxq,
 798                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
 799 {
 800         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 801         struct qede_agg_info *tpa_info;
 802         struct rte_mbuf *temp_frag; /* Pointer to mbuf chain head */
 803         struct rte_mbuf *curr_frag;
 804         uint8_t list_count = 0;
 805         uint16_t cons_idx;
 806         uint8_t i;
 807
 808         PMD_RX_LOG(INFO, rxq, "TPA cont[%02x] - len_list [%04x %04x]\n",
 809                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]),
 810                    rte_le_to_cpu_16(cqe->len_list[1]));
 811
 812         tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
 813         temp_frag = tpa_info->mbuf;
 814         assert(temp_frag);
 815
 816         for (i = 0; cqe->len_list[i]; i++) {
 817                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 818                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
 819                 qede_rx_bd_ring_consume(rxq);
 820                 curr_frag->data_len = rte_le_to_cpu_16(cqe->len_list[i]);
 821                 temp_frag->next = curr_frag;
 822                 temp_frag = curr_frag;
 823                 list_count++;
 824         }
 825
 826         /* Allocate RX mbuf on the RX BD ring for those many consumed  */
 827         for (i = 0 ; i < list_count ; i++) {
 828                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 829                         DP_ERR(edev, "Failed to allocate mbuf for LRO cont\n");
 830                         tpa_info->state = QEDE_AGG_STATE_ERROR;
 831                 }
 832         }
 833 }
 834
 835 static inline void
 836 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
 837                             struct qede_rx_queue *rxq,
 838                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
 839 {
 840         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 841         struct qede_agg_info *tpa_info;
 842         struct rte_mbuf *temp_frag; /* Pointer to mbuf chain head */
 843         struct rte_mbuf *curr_frag;
 844         struct rte_mbuf *rx_mb;
 845         uint8_t list_count = 0;
 846         uint16_t cons_idx;
 847         uint8_t i;
 848
 849         PMD_RX_LOG(INFO, rxq, "TPA End[%02x] - len_list [%04x %04x]\n",
 850                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]),
 851                    rte_le_to_cpu_16(cqe->len_list[1]));
 852
 853         tpa_info = &rxq->tpa_info[cqe->tpa_agg_index];
 854         temp_frag = tpa_info->mbuf;
 855         assert(temp_frag);
 856
 857         for (i = 0; cqe->len_list[i]; i++) {
 858                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 859                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
 860                 qede_rx_bd_ring_consume(rxq);
 861                 curr_frag->data_len = rte_le_to_cpu_16(cqe->len_list[i]);
 862                 temp_frag->next = curr_frag;
 863                 temp_frag = curr_frag;
 864                 list_count++;
 865         }
 866
 867         /* Allocate RX mbuf on the RX BD ring for those many consumed */
 868         for (i = 0 ; i < list_count ; i++) {
 869                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 870                         DP_ERR(edev, "Failed to allocate mbuf for lro end\n");
 871                         tpa_info->state = QEDE_AGG_STATE_ERROR;
 872                 }
 873         }
 874
 875         /* Update total length and frags based on end TPA */
 876         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].mbuf;
 877         /* TBD: Add sanity checks here */
 878         rx_mb->nb_segs = cqe->num_of_bds;
 879         rx_mb->pkt_len = cqe->total_packet_len;
 880         tpa_info->state = QEDE_AGG_STATE_NONE;
 881 }
 882
 883 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 884 {
 885         uint32_t val;
 886
 887         /* Lookup table */
 888         static const uint32_t
 889         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 890                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 891                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 892                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 893                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 894                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 895                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 896                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 897                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 898                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 899                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 900                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 901                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 902                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 903                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 904                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 905                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 906                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 907                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 908                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 909                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 910                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 911                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 912                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 913                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 914                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 915                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 916                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 917                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 918                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 919                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 920                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 921                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 922                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 923                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 924                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 925                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 926                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 927                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 928                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 929                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 930         };
 931
 932         /* Cover bits[4-0] to include tunn_type and next protocol */
 933         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 934                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 935                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 936                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 937
 938         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 939                 return ptype_tunn_lkup_tbl[val];
 940         else
 941                 return RTE_PTYPE_UNKNOWN;
 942 }
 943
 944 static inline int
 945 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 946                      uint8_t num_segs, uint16_t pkt_len)
 947 {
 948         struct qede_rx_queue *rxq = p_rxq;
 949         struct qede_dev *qdev = rxq->qdev;
 950         struct ecore_dev *edev = &qdev->edev;
 951         register struct rte_mbuf *seg1 = NULL;
 952         register struct rte_mbuf *seg2 = NULL;
 953         uint16_t sw_rx_index;
 954         uint16_t cur_size;
 955
 956         seg1 = rx_mb;
 957         while (num_segs) {
 958                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
 959                                                         pkt_len;
 960                 if (unlikely(!cur_size)) {
 961                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
 962                                    " left for mapping jumbo", num_segs);
 963                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 964                         return -EINVAL;
 965                 }
 966                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 967                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 968                 qede_rx_bd_ring_consume(rxq);
 969                 pkt_len -= cur_size;
 970                 seg2->data_len = cur_size;
 971                 seg1->next = seg2;
 972                 seg1 = seg1->next;
 973                 num_segs--;
 974                 rxq->rx_segs++;
 975         }
 976
 977         return 0;
 978 }
 979
 980 uint16_t
 981 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 982 {
 983         struct qede_rx_queue *rxq = p_rxq;
 984         struct qede_dev *qdev = rxq->qdev;
 985         struct ecore_dev *edev = &qdev->edev;
 986         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 987         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 988         uint16_t rx_pkt = 0;
 989         union eth_rx_cqe *cqe;
 990         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 991         register struct rte_mbuf *rx_mb = NULL;
 992         register struct rte_mbuf *seg1 = NULL;
 993         enum eth_rx_cqe_type cqe_type;
 994         uint16_t pkt_len; /* Sum of all BD segments */
 995         uint16_t len; /* Length of first BD */
 996         uint8_t num_segs = 1;
 997         uint16_t preload_idx;
 998         uint8_t csum_flag;
 999         uint16_t parse_flag;
1000         enum rss_hash_type htype;
1001         uint8_t tunn_parse_flag;
1002         uint8_t j;
1003         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1004         uint64_t ol_flags;
1005         uint32_t packet_type;
1006         uint16_t vlan_tci;
1007         bool tpa_start_flg;
1008         uint8_t bitfield_val;
1009         uint8_t offset, tpa_agg_idx, flags;
1010         struct qede_agg_info *tpa_info;
1011
1012         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1013         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1014
1015         rte_rmb();
1016
1017         if (hw_comp_cons == sw_comp_cons)
1018                 return 0;
1019
1020         while (sw_comp_cons != hw_comp_cons) {
1021                 ol_flags = 0;
1022                 packet_type = RTE_PTYPE_UNKNOWN;
1023                 vlan_tci = 0;
1024                 tpa_start_flg = false;
1025
1026                 /* Get the CQE from the completion ring */
1027                 cqe =
1028                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1029                 cqe_type = cqe->fast_path_regular.type;
1030                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1031
1032                 switch (cqe_type) {
1033                 case ETH_RX_CQE_TYPE_REGULAR:
1034                         fp_cqe = &cqe->fast_path_regular;
1035                 break;
1036                 case ETH_RX_CQE_TYPE_TPA_START:
1037                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1038                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1039                         tpa_start_flg = true;
1040                         PMD_RX_LOG(INFO, rxq,
1041                             "TPA start[%u] - len %04x [header %02x]"
1042                             " [bd_list[0] %04x], [seg_len %04x]\n",
1043                             cqe_start_tpa->tpa_agg_index,
1044                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1045                             cqe_start_tpa->header_len,
1046                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1047                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1048
1049                 break;
1050                 case ETH_RX_CQE_TYPE_TPA_CONT:
1051                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1052                                                      &cqe->fast_path_tpa_cont);
1053                         continue;
1054                 case ETH_RX_CQE_TYPE_TPA_END:
1055                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1056                                                     &cqe->fast_path_tpa_end);
1057                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1058                         rx_mb = rxq->tpa_info[tpa_agg_idx].mbuf;
1059                         PMD_RX_LOG(INFO, rxq, "TPA end reason %d\n",
1060                                    cqe->fast_path_tpa_end.end_reason);
1061                         goto tpa_end;
1062                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1063                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1064                         qdev->ops->eth_cqe_completion(edev, fp->id,
1065                                 (struct eth_slow_path_rx_cqe *)cqe);
1066                         /* fall-thru */
1067                 default:
1068                         goto next_cqe;
1069                 }
1070
1071                 /* Get the data from the SW ring */
1072                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1073                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1074                 assert(rx_mb != NULL);
1075
1076                 /* Handle regular CQE or TPA start CQE */
1077                 if (!tpa_start_flg) {
1078                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1079                         bitfield_val = fp_cqe->bitfields;
1080                         offset = fp_cqe->placement_offset;
1081                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1082                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1083                 } else {
1084                         parse_flag =
1085                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1086                         bitfield_val = cqe_start_tpa->bitfields;
1087                         offset = cqe_start_tpa->placement_offset;
1088                         /* seg_len = len_on_first_bd */
1089                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1090                         tpa_info->start_cqe_bd_len = len +
1091                                                 cqe_start_tpa->header_len;
1092                         tpa_info->mbuf = rx_mb;
1093                 }
1094                 if (qede_tunn_exist(parse_flag)) {
1095                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1096                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1097                                 PMD_RX_LOG(ERR, rxq,
1098                                             "L4 csum failed, flags = 0x%x\n",
1099                                             parse_flag);
1100                                 rxq->rx_hw_errors++;
1101                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1102                         } else {
1103                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1104                                 if (tpa_start_flg)
1105                                         flags =
1106                                          cqe_start_tpa->tunnel_pars_flags.flags;
1107                                 else
1108                                         flags = fp_cqe->tunnel_pars_flags.flags;
1109                                 tunn_parse_flag = flags;
1110                                 packet_type =
1111                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1112                         }
1113                 } else {
1114                         PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1115                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1116                                 PMD_RX_LOG(ERR, rxq,
1117                                             "L4 csum failed, flags = 0x%x\n",
1118                                             parse_flag);
1119                                 rxq->rx_hw_errors++;
1120                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1121                         } else {
1122                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1123                         }
1124                         if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1125                                                         parse_flag))) {
1126                                 PMD_RX_LOG(ERR, rxq,
1127                                            "IP csum failed, flags = 0x%x\n",
1128                                            parse_flag);
1129                                 rxq->rx_hw_errors++;
1130                                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1131                         } else {
1132                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1133                                 packet_type =
1134                                         qede_rx_cqe_to_pkt_type(parse_flag);
1135                         }
1136                 }
1137
1138                 if (CQE_HAS_VLAN(parse_flag)) {
1139                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1140                         ol_flags |= PKT_RX_VLAN_PKT;
1141                 }
1142
1143                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1144                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1145                         ol_flags |= PKT_RX_QINQ_PKT;
1146                         rx_mb->vlan_tci_outer = 0;
1147                 }
1148
1149                 /* RSS Hash */
1150                 htype = (uint8_t)GET_FIELD(bitfield_val,
1151                                         ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1152                 if (qdev->rss_enable && htype) {
1153                         ol_flags |= PKT_RX_RSS_HASH;
1154                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1155                         PMD_RX_LOG(INFO, rxq, "Hash result 0x%x\n",
1156                                    rx_mb->hash.rss);
1157                 }
1158
1159                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1160                         PMD_RX_LOG(ERR, rxq,
1161                                    "New buffer allocation failed,"
1162                                    "dropping incoming packet\n");
1163                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1164                         rte_eth_devices[rxq->port_id].
1165                             data->rx_mbuf_alloc_failed++;
1166                         rxq->rx_alloc_errors++;
1167                         break;
1168                 }
1169                 qede_rx_bd_ring_consume(rxq);
1170
1171                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1172                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1173                                    " len on first: %04x Total Len: %04x",
1174                                    fp_cqe->bd_num, len, pkt_len);
1175                         num_segs = fp_cqe->bd_num - 1;
1176                         seg1 = rx_mb;
1177                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1178                                                  pkt_len - len))
1179                                 goto next_cqe;
1180                         for (j = 0; j < num_segs; j++) {
1181                                 if (qede_alloc_rx_buffer(rxq)) {
1182                                         PMD_RX_LOG(ERR, rxq,
1183                                                 "Buffer allocation failed");
1184                                         rte_eth_devices[rxq->port_id].
1185                                                 data->rx_mbuf_alloc_failed++;
1186                                         rxq->rx_alloc_errors++;
1187                                         break;
1188                                 }
1189                                 rxq->rx_segs++;
1190                         }
1191                 }
1192                 rxq->rx_segs++; /* for the first segment */
1193
1194                 /* Prefetch next mbuf while processing current one. */
1195                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1196                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1197
1198                 /* Update rest of the MBUF fields */
1199                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1200                 rx_mb->port = rxq->port_id;
1201                 rx_mb->ol_flags = ol_flags;
1202                 rx_mb->data_len = len;
1203                 rx_mb->vlan_tci = vlan_tci;
1204                 rx_mb->packet_type = packet_type;
1205                 PMD_RX_LOG(INFO, rxq, "pkt_type %04x len %04x flags %04lx\n",
1206                            packet_type, len, (unsigned long)ol_flags);
1207                 if (!tpa_start_flg) {
1208                         rx_mb->nb_segs = fp_cqe->bd_num;
1209                         rx_mb->pkt_len = pkt_len;
1210                 }
1211                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1212 tpa_end:
1213                 if (!tpa_start_flg) {
1214                         rx_pkts[rx_pkt] = rx_mb;
1215                         rx_pkt++;
1216                 }
1217 next_cqe:
1218                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1219                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1220                 if (rx_pkt == nb_pkts) {
1221                         PMD_RX_LOG(DEBUG, rxq,
1222                                    "Budget reached nb_pkts=%u received=%u",
1223                                    rx_pkt, nb_pkts);
1224                         break;
1225                 }
1226         }
1227
1228         qede_update_rx_prod(qdev, rxq);
1229
1230         rxq->rcv_pkts += rx_pkt;
1231
1232         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1233
1234         return rx_pkt;
1235 }
1236
1237 static inline void
1238 qede_free_tx_pkt(struct qede_tx_queue *txq)
1239 {
1240         struct rte_mbuf *mbuf;
1241         uint16_t nb_segs;
1242         uint16_t idx;
1243         uint8_t nbds;
1244
1245         idx = TX_CONS(txq);
1246         mbuf = txq->sw_tx_ring[idx].mbuf;
1247         if (mbuf) {
1248                 nb_segs = mbuf->nb_segs;
1249                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
1250                 while (nb_segs) {
1251                         /* It's like consuming rxbuf in recv() */
1252                         ecore_chain_consume(&txq->tx_pbl);
1253                         txq->nb_tx_avail++;
1254                         nb_segs--;
1255                 }
1256                 rte_pktmbuf_free(mbuf);
1257                 txq->sw_tx_ring[idx].mbuf = NULL;
1258                 txq->sw_tx_cons++;
1259                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
1260         } else {
1261                 ecore_chain_consume(&txq->tx_pbl);
1262                 txq->nb_tx_avail++;
1263         }
1264 }
1265
1266 static inline void
1267 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1268 {
1269         uint16_t hw_bd_cons;
1270         uint16_t sw_tx_cons;
1271
1272         rte_compiler_barrier();
1273         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1274         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
1275         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
1276                    abs(hw_bd_cons - sw_tx_cons));
1277         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
1278                 qede_free_tx_pkt(txq);
1279 }
1280
1281 /* Populate scatter gather buffer descriptor fields */
1282 static inline uint8_t
1283 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1284                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1285 {
1286         struct qede_tx_queue *txq = p_txq;
1287         struct eth_tx_bd *tx_bd = NULL;
1288         dma_addr_t mapping;
1289         uint8_t nb_segs = 0;
1290
1291         /* Check for scattered buffers */
1292         while (m_seg) {
1293                 if (nb_segs == 0) {
1294                         if (!*bd2) {
1295                                 *bd2 = (struct eth_tx_2nd_bd *)
1296                                         ecore_chain_produce(&txq->tx_pbl);
1297                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1298                                 nb_segs++;
1299                         }
1300                         mapping = rte_mbuf_data_dma_addr(m_seg);
1301                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1302                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1303                 } else if (nb_segs == 1) {
1304                         if (!*bd3) {
1305                                 *bd3 = (struct eth_tx_3rd_bd *)
1306                                         ecore_chain_produce(&txq->tx_pbl);
1307                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1308                                 nb_segs++;
1309                         }
1310                         mapping = rte_mbuf_data_dma_addr(m_seg);
1311                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1312                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1313                 } else {
1314                         tx_bd = (struct eth_tx_bd *)
1315                                 ecore_chain_produce(&txq->tx_pbl);
1316                         memset(tx_bd, 0, sizeof(*tx_bd));
1317                         nb_segs++;
1318                         mapping = rte_mbuf_data_dma_addr(m_seg);
1319                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1320                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1321                 }
1322                 m_seg = m_seg->next;
1323         }
1324
1325         /* Return total scattered buffers */
1326         return nb_segs;
1327 }
1328
1329 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1330 static inline void
1331 print_tx_bd_info(struct qede_tx_queue *txq,
1332                  struct eth_tx_1st_bd *bd1,
1333                  struct eth_tx_2nd_bd *bd2,
1334                  struct eth_tx_3rd_bd *bd3,
1335                  uint64_t tx_ol_flags)
1336 {
1337         char ol_buf[256] = { 0 }; /* for verbose prints */
1338
1339         if (bd1)
1340                 PMD_TX_LOG(INFO, txq,
1341                            "BD1: nbytes=%u nbds=%u bd_flags=04%x bf=%04x",
1342                            rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1343                            bd1->data.bd_flags.bitfields,
1344                            rte_cpu_to_le_16(bd1->data.bitfields));
1345         if (bd2)
1346                 PMD_TX_LOG(INFO, txq,
1347                            "BD2: nbytes=%u bf=%04x\n",
1348                            rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1349         if (bd3)
1350                 PMD_TX_LOG(INFO, txq,
1351                            "BD3: nbytes=%u bf=%04x mss=%u\n",
1352                            rte_cpu_to_le_16(bd3->nbytes),
1353                            rte_cpu_to_le_16(bd3->data.bitfields),
1354                            rte_cpu_to_le_16(bd3->data.lso_mss));
1355
1356         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1357         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1358 }
1359 #endif
1360
1361 /* TX prepare to check packets meets TX conditions */
1362 uint16_t
1363 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1364                     uint16_t nb_pkts)
1365 {
1366         struct qede_tx_queue *txq = p_txq;
1367         uint64_t ol_flags;
1368         struct rte_mbuf *m;
1369         uint16_t i;
1370         int ret;
1371
1372         for (i = 0; i < nb_pkts; i++) {
1373                 m = tx_pkts[i];
1374                 ol_flags = m->ol_flags;
1375                 if (ol_flags & PKT_TX_TCP_SEG) {
1376                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1377                                 rte_errno = -EINVAL;
1378                                 break;
1379                         }
1380                         /* TBD: confirm its ~9700B for both ? */
1381                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1382                                 rte_errno = -EINVAL;
1383                                 break;
1384                         }
1385                 } else {
1386                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1387                                 rte_errno = -EINVAL;
1388                                 break;
1389                         }
1390                 }
1391                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1392                         rte_errno = -ENOTSUP;
1393                         break;
1394                 }
1395
1396 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1397                 ret = rte_validate_tx_offload(m);
1398                 if (ret != 0) {
1399                         rte_errno = ret;
1400                         break;
1401                 }
1402 #endif
1403                 /* TBD: pseudo csum calcuation required iff
1404                  * ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE not set?
1405                  */
1406                 ret = rte_net_intel_cksum_prepare(m);
1407                 if (ret != 0) {
1408                         rte_errno = ret;
1409                         break;
1410                 }
1411         }
1412
1413         if (unlikely(i != nb_pkts))
1414                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1415                            nb_pkts - i);
1416         return i;
1417 }
1418
1419 uint16_t
1420 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1421 {
1422         struct qede_tx_queue *txq = p_txq;
1423         struct qede_dev *qdev = txq->qdev;
1424         struct ecore_dev *edev = &qdev->edev;
1425         struct rte_mbuf *mbuf;
1426         struct rte_mbuf *m_seg = NULL;
1427         uint16_t nb_tx_pkts;
1428         uint16_t bd_prod;
1429         uint16_t idx;
1430         uint16_t nb_frags;
1431         uint16_t nb_pkt_sent = 0;
1432         uint8_t nbds;
1433         bool ipv6_ext_flg;
1434         bool lso_flg;
1435         bool tunn_flg;
1436         struct eth_tx_1st_bd *bd1;
1437         struct eth_tx_2nd_bd *bd2;
1438         struct eth_tx_3rd_bd *bd3;
1439         uint64_t tx_ol_flags;
1440         uint16_t hdr_size;
1441
1442         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1443                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1444                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1445                 qede_process_tx_compl(edev, txq);
1446         }
1447
1448         nb_tx_pkts  = nb_pkts;
1449         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1450         while (nb_tx_pkts--) {
1451                 /* Init flags/values */
1452                 ipv6_ext_flg = false;
1453                 tunn_flg = false;
1454                 lso_flg = false;
1455                 nbds = 0;
1456                 bd1 = NULL;
1457                 bd2 = NULL;
1458                 bd3 = NULL;
1459                 hdr_size = 0;
1460
1461                 mbuf = *tx_pkts;
1462                 assert(mbuf);
1463
1464                 /* Check minimum TX BDS availability against available BDs */
1465                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1466                         break;
1467
1468                 tx_ol_flags = mbuf->ol_flags;
1469
1470 #define RTE_ETH_IS_IPV6_HDR_EXT(ptype) ((ptype) & RTE_PTYPE_L3_IPV6_EXT)
1471                 if (RTE_ETH_IS_IPV6_HDR_EXT(mbuf->packet_type))
1472                         ipv6_ext_flg = true;
1473
1474                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type))
1475                         tunn_flg = true;
1476
1477                 if (tx_ol_flags & PKT_TX_TCP_SEG)
1478                         lso_flg = true;
1479
1480                 if (lso_flg) {
1481                         if (unlikely(txq->nb_tx_avail <
1482                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1483                                 break;
1484                 } else {
1485                         if (unlikely(txq->nb_tx_avail <
1486                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1487                                 break;
1488                 }
1489
1490                 if (tunn_flg && ipv6_ext_flg) {
1491                         if (unlikely(txq->nb_tx_avail <
1492                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1493                                 break;
1494                 }
1495                 if (ipv6_ext_flg) {
1496                         if (unlikely(txq->nb_tx_avail <
1497                                         ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT))
1498                                 break;
1499                 }
1500
1501                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1502                 idx = TX_PROD(txq);
1503                 *tx_pkts++;
1504                 txq->sw_tx_ring[idx].mbuf = mbuf;
1505
1506                 /* BD1 */
1507                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1508                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1509                 nbds++;
1510
1511                 bd1->data.bd_flags.bitfields |=
1512                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1513                 /* FW 8.10.x specific change */
1514                 if (!lso_flg) {
1515                         bd1->data.bitfields |=
1516                         (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1517                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1518                         /* Map MBUF linear data for DMA and set in the BD1 */
1519                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1520                                              mbuf->data_len);
1521                 } else {
1522                         /* For LSO, packet header and payload must reside on
1523                          * buffers pointed by different BDs. Using BD1 for HDR
1524                          * and BD2 onwards for data.
1525                          */
1526                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1527                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1528                                              hdr_size);
1529                 }
1530
1531                 if (tunn_flg) {
1532                         /* First indicate its a tunnel pkt */
1533                         bd1->data.bd_flags.bitfields |=
1534                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1535                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1536
1537                         /* Legacy FW had flipped behavior in regard to this bit
1538                          * i.e. it needed to set to prevent FW from touching
1539                          * encapsulated packets when it didn't need to.
1540                          */
1541                         if (unlikely(txq->is_legacy))
1542                                 bd1->data.bitfields ^=
1543                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1544
1545                         /* Outer IP checksum offload */
1546                         if (tx_ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1547                                 bd1->data.bd_flags.bitfields |=
1548                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1549                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1550                         }
1551
1552                         /* Outer UDP checksum offload */
1553                         bd1->data.bd_flags.bitfields |=
1554                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1555                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1556                 }
1557
1558                 /* Descriptor based VLAN insertion */
1559                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1560                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1561                         bd1->data.bd_flags.bitfields |=
1562                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1563                 }
1564
1565                 if (lso_flg)
1566                         bd1->data.bd_flags.bitfields |=
1567                                 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1568
1569                 /* Offload the IP checksum in the hardware */
1570                 if ((lso_flg) || (tx_ol_flags & PKT_TX_IP_CKSUM))
1571                         bd1->data.bd_flags.bitfields |=
1572                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1573
1574                 /* L4 checksum offload (tcp or udp) */
1575                 if ((lso_flg) || (tx_ol_flags & (PKT_TX_TCP_CKSUM |
1576                                                 PKT_TX_UDP_CKSUM)))
1577                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1578                         bd1->data.bd_flags.bitfields |=
1579                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1580
1581                 /* BD2 */
1582                 if (lso_flg || ipv6_ext_flg) {
1583                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1584                                                         (&txq->tx_pbl);
1585                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1586                         nbds++;
1587                         QEDE_BD_SET_ADDR_LEN(bd2,
1588                                             (hdr_size +
1589                                             rte_mbuf_data_dma_addr(mbuf)),
1590                                             mbuf->data_len - hdr_size);
1591                         /* TBD: check pseudo csum iff tx_prepare not called? */
1592                         if (ipv6_ext_flg) {
1593                                 bd2->data.bitfields1 |=
1594                                 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH <<
1595                                 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1596                         }
1597                 }
1598
1599                 /* BD3 */
1600                 if (lso_flg || ipv6_ext_flg) {
1601                         bd3 = (struct eth_tx_3rd_bd *)ecore_chain_produce
1602                                                         (&txq->tx_pbl);
1603                         memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
1604                         nbds++;
1605                         if (lso_flg) {
1606                                 bd3->data.lso_mss =
1607                                         rte_cpu_to_le_16(mbuf->tso_segsz);
1608                                 /* Using one header BD */
1609                                 bd3->data.bitfields |=
1610                                         rte_cpu_to_le_16(1 <<
1611                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1612                         }
1613                 }
1614
1615                 /* Handle fragmented MBUF */
1616                 m_seg = mbuf->next;
1617                 /* Encode scatter gather buffer descriptors if required */
1618                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
1619                 bd1->data.nbds = nbds + nb_frags;
1620                 txq->nb_tx_avail -= bd1->data.nbds;
1621                 txq->sw_tx_prod++;
1622                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1623                 bd_prod =
1624                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1625 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1626                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
1627                 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d ipv6_ext=%d\n",
1628                            lso_flg, tunn_flg, ipv6_ext_flg);
1629 #endif
1630                 nb_pkt_sent++;
1631                 txq->xmit_pkts++;
1632         }
1633
1634         /* Write value of prod idx into bd_prod */
1635         txq->tx_db.data.bd_prod = bd_prod;
1636         rte_wmb();
1637         rte_compiler_barrier();
1638         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1639         rte_wmb();
1640
1641         /* Check again for Tx completions */
1642         qede_process_tx_compl(edev, txq);
1643
1644         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
1645                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
1646
1647         return nb_pkt_sent;
1648 }
1649
1650 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1651 {
1652         struct qede_dev *qdev = eth_dev->data->dev_private;
1653         struct qede_fastpath *fp;
1654         uint8_t i, rss_id, txq_index, tc;
1655         int rxq = 0, txq = 0;
1656
1657         for_each_queue(i) {
1658                 fp = &qdev->fp_array[i];
1659                 if (fp->type & QEDE_FASTPATH_RX) {
1660                         fp->rxq = eth_dev->data->rx_queues[i];
1661                         fp->rxq->queue_id = rxq++;
1662                 }
1663
1664                 if (fp->type & QEDE_FASTPATH_TX) {
1665                         for (tc = 0; tc < qdev->num_tc; tc++) {
1666                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1667                                 fp->txqs[tc] =
1668                                         eth_dev->data->tx_queues[txq_index];
1669                                 fp->txqs[tc]->queue_id = txq_index;
1670                                 if (qdev->dev_info.is_legacy)
1671                                         fp->txqs[tc]->is_legacy = true;
1672                         }
1673                         txq++;
1674                 }
1675         }
1676 }
1677
1678 int qede_dev_start(struct rte_eth_dev *eth_dev)
1679 {
1680         struct qede_dev *qdev = eth_dev->data->dev_private;
1681         struct ecore_dev *edev = &qdev->edev;
1682         struct qed_link_output link_output;
1683         struct qede_fastpath *fp;
1684         int rc;
1685
1686         DP_INFO(edev, "Device state is %d\n", qdev->state);
1687
1688         if (qdev->state == QEDE_DEV_START) {
1689                 DP_INFO(edev, "Port is already started\n");
1690                 return 0;
1691         }
1692
1693         if (qdev->state == QEDE_DEV_CONFIG)
1694                 qede_init_fp_queue(eth_dev);
1695
1696         rc = qede_start_queues(eth_dev, true);
1697         if (rc) {
1698                 DP_ERR(edev, "Failed to start queues\n");
1699                 /* TBD: free */
1700                 return rc;
1701         }
1702
1703         /* Bring-up the link */
1704         qede_dev_set_link_state(eth_dev, true);
1705
1706         /* Reset ring */
1707         if (qede_reset_fp_rings(qdev))
1708                 return -ENOMEM;
1709
1710         /* Start/resume traffic */
1711         qdev->ops->fastpath_start(edev);
1712
1713         qdev->state = QEDE_DEV_START;
1714
1715         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1716
1717         return 0;
1718 }
1719
1720 static int qede_drain_txq(struct qede_dev *qdev,
1721                           struct qede_tx_queue *txq, bool allow_drain)
1722 {
1723         struct ecore_dev *edev = &qdev->edev;
1724         int rc, cnt = 1000;
1725
1726         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1727                 qede_process_tx_compl(edev, txq);
1728                 if (!cnt) {
1729                         if (allow_drain) {
1730                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
1731                                           "requesting MCP to drain\n",
1732                                           txq->queue_id);
1733                                 rc = qdev->ops->common->drain(edev);
1734                                 if (rc)
1735                                         return rc;
1736                                 return qede_drain_txq(qdev, txq, false);
1737                         }
1738                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
1739                                   "PROD=%d, CONS=%d\n",
1740                                   txq->queue_id, txq->sw_tx_prod,
1741                                   txq->sw_tx_cons);
1742                         return -1;
1743                 }
1744                 cnt--;
1745                 DELAY(1000);
1746                 rte_compiler_barrier();
1747         }
1748
1749         /* FW finished processing, wait for HW to transmit all tx packets */
1750         DELAY(2000);
1751
1752         return 0;
1753 }
1754
1755 static int qede_stop_queues(struct qede_dev *qdev)
1756 {
1757         struct qed_update_vport_params vport_update_params;
1758         struct ecore_dev *edev = &qdev->edev;
1759         struct ecore_sge_tpa_params tpa_params;
1760         struct qede_fastpath *fp;
1761         int rc, tc, i;
1762
1763         /* Disable the vport */
1764         memset(&vport_update_params, 0, sizeof(vport_update_params));
1765         vport_update_params.vport_id = 0;
1766         vport_update_params.update_vport_active_flg = 1;
1767         vport_update_params.vport_active_flg = 0;
1768         vport_update_params.update_rss_flg = 0;
1769         /* Disable TPA */
1770         if (qdev->enable_lro) {
1771                 DP_INFO(edev, "Disabling LRO\n");
1772                 memset(&tpa_params, 0, sizeof(struct ecore_sge_tpa_params));
1773                 qede_update_sge_tpa_params(&tpa_params, qdev->mtu, false);
1774                 vport_update_params.sge_tpa_params = &tpa_params;
1775         }
1776
1777         DP_INFO(edev, "Deactivate vport\n");
1778         rc = qdev->ops->vport_update(edev, &vport_update_params);
1779         if (rc) {
1780                 DP_ERR(edev, "Failed to update vport\n");
1781                 return rc;
1782         }
1783
1784         DP_INFO(edev, "Flushing tx queues\n");
1785
1786         /* Flush Tx queues. If needed, request drain from MCP */
1787         for_each_queue(i) {
1788                 fp = &qdev->fp_array[i];
1789
1790                 if (fp->type & QEDE_FASTPATH_TX) {
1791                         for (tc = 0; tc < qdev->num_tc; tc++) {
1792                                 struct qede_tx_queue *txq = fp->txqs[tc];
1793
1794                                 rc = qede_drain_txq(qdev, txq, true);
1795                                 if (rc)
1796                                         return rc;
1797                         }
1798                 }
1799         }
1800
1801         /* Stop all Queues in reverse order */
1802         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1803                 fp = &qdev->fp_array[i];
1804
1805                 /* Stop the Tx Queue(s) */
1806                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1807                         for (tc = 0; tc < qdev->num_tc; tc++) {
1808                                 struct qede_tx_queue *txq = fp->txqs[tc];
1809                                 DP_INFO(edev, "Stopping tx queues\n");
1810                                 rc = qdev->ops->q_tx_stop(edev, i, txq->handle);
1811                                 if (rc) {
1812                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1813                                                i);
1814                                         return rc;
1815                                 }
1816                         }
1817                 }
1818
1819                 /* Stop the Rx Queue */
1820                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1821                         DP_INFO(edev, "Stopping rx queues\n");
1822                         rc = qdev->ops->q_rx_stop(edev, i, fp->rxq->handle);
1823                         if (rc) {
1824                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1825                                 return rc;
1826                         }
1827                 }
1828         }
1829
1830         return 0;
1831 }
1832
1833 int qede_reset_fp_rings(struct qede_dev *qdev)
1834 {
1835         struct qede_fastpath *fp;
1836         struct qede_tx_queue *txq;
1837         uint8_t tc;
1838         uint16_t id, i;
1839
1840         for_each_queue(id) {
1841                 fp = &qdev->fp_array[id];
1842
1843                 if (fp->type & QEDE_FASTPATH_RX) {
1844                         DP_INFO(&qdev->edev,
1845                                 "Reset FP chain for RSS %u\n", id);
1846                         qede_rx_queue_release_mbufs(fp->rxq);
1847                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1848                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1849                         fp->rxq->sw_rx_prod = 0;
1850                         fp->rxq->sw_rx_cons = 0;
1851                         *fp->rxq->hw_cons_ptr = 0;
1852                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1853                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1854                                         DP_ERR(&qdev->edev,
1855                                                "RX buffer allocation failed\n");
1856                                         return -ENOMEM;
1857                                 }
1858                         }
1859                 }
1860                 if (fp->type & QEDE_FASTPATH_TX) {
1861                         for (tc = 0; tc < qdev->num_tc; tc++) {
1862                                 txq = fp->txqs[tc];
1863                                 qede_tx_queue_release_mbufs(txq);
1864                                 ecore_chain_reset(&txq->tx_pbl);
1865                                 txq->sw_tx_cons = 0;
1866                                 txq->sw_tx_prod = 0;
1867                                 *txq->hw_cons_ptr = 0;
1868                         }
1869                 }
1870         }
1871
1872         return 0;
1873 }
1874
1875 /* This function frees all memory of a single fp */
1876 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1877 {
1878         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1879         struct qede_fastpath *fp;
1880         uint16_t txq_idx;
1881         uint8_t id;
1882         uint8_t tc;
1883
1884         for_each_queue(id) {
1885                 fp = &qdev->fp_array[id];
1886                 if (fp->type & QEDE_FASTPATH_RX) {
1887                         if (!fp->rxq)
1888                                 continue;
1889                         qede_rx_queue_release(fp->rxq);
1890                         eth_dev->data->rx_queues[id] = NULL;
1891                 } else {
1892                         for (tc = 0; tc < qdev->num_tc; tc++) {
1893                                 if (!fp->txqs[tc])
1894                                         continue;
1895                                 txq_idx = fp->txqs[tc]->queue_id;
1896                                 qede_tx_queue_release(fp->txqs[tc]);
1897                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1898                         }
1899                 }
1900         }
1901 }
1902
1903 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1904 {
1905         struct qede_dev *qdev = eth_dev->data->dev_private;
1906         struct ecore_dev *edev = &qdev->edev;
1907
1908         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1909
1910         if (qdev->state != QEDE_DEV_START) {
1911                 DP_INFO(edev, "Device not yet started\n");
1912                 return;
1913         }
1914
1915         if (qede_stop_queues(qdev))
1916                 DP_ERR(edev, "Didn't succeed to close queues\n");
1917
1918         DP_INFO(edev, "Stopped queues\n");
1919
1920         qdev->ops->fastpath_stop(edev);
1921
1922         /* Bring the link down */
1923         qede_dev_set_link_state(eth_dev, false);
1924
1925         qdev->state = QEDE_DEV_STOP;
1926
1927         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1928 }