drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 int
  41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  42                     uint16_t nb_desc, unsigned int socket_id,
  43                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  44                     struct rte_mempool *mp)
  45 {
  46         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
  47         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
  48         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  49         struct qede_rx_queue *rxq;
  50         uint16_t max_rx_pkt_len;
  51         uint16_t bufsz;
  52         size_t size;
  53         int rc;
  54
  55         PMD_INIT_FUNC_TRACE(edev);
  56
  57         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
  58         if (!rte_is_power_of_2(nb_desc)) {
  59                 DP_ERR(edev, "Ring size %u is not power of 2\n",
  60                           nb_desc);
  61                 return -EINVAL;
  62         }
  63
  64         /* Free memory prior to re-allocation if needed... */
  65         if (dev->data->rx_queues[queue_idx] != NULL) {
  66                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
  67                 dev->data->rx_queues[queue_idx] = NULL;
  68         }
  69
  70         /* First allocate the rx queue data structure */
  71         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
  72                                  RTE_CACHE_LINE_SIZE, socket_id);
  73
  74         if (!rxq) {
  75                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
  76                           socket_id);
  77                 return -ENOMEM;
  78         }
  79
  80         rxq->qdev = qdev;
  81         rxq->mb_pool = mp;
  82         rxq->nb_rx_desc = nb_desc;
  83         rxq->queue_id = queue_idx;
  84         rxq->port_id = dev->data->port_id;
  85
  86         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
  87         qdev->mtu = max_rx_pkt_len;
  88
  89         /* Fix up RX buffer size */
  90         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
  91         if ((rxmode->enable_scatter)                    ||
  92             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
  93                 if (!dev->data->scattered_rx) {
  94                         DP_INFO(edev, "Forcing scatter-gather mode\n");
  95                         dev->data->scattered_rx = 1;
  96                 }
  97         }
  98
  99         if (dev->data->scattered_rx)
 100                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 101         else
 102                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 103         /* Align to cache-line size if needed */
 104         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 105
 106         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 107                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 108
 109         /* Allocate the parallel driver ring for Rx buffers */
 110         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 111         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 112                                              RTE_CACHE_LINE_SIZE, socket_id);
 113         if (!rxq->sw_rx_ring) {
 114                 DP_ERR(edev, "Memory allocation fails for sw_rx_ring on"
 115                        " socket %u\n", socket_id);
 116                 rte_free(rxq);
 117                 return -ENOMEM;
 118         }
 119
 120         /* Allocate FW Rx ring  */
 121         rc = qdev->ops->common->chain_alloc(edev,
 122                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 123                                             ECORE_CHAIN_MODE_NEXT_PTR,
 124                                             ECORE_CHAIN_CNT_TYPE_U16,
 125                                             rxq->nb_rx_desc,
 126                                             sizeof(struct eth_rx_bd),
 127                                             &rxq->rx_bd_ring,
 128                                             NULL);
 129
 130         if (rc != ECORE_SUCCESS) {
 131                 DP_ERR(edev, "Memory allocation fails for RX BD ring"
 132                        " on socket %u\n", socket_id);
 133                 rte_free(rxq->sw_rx_ring);
 134                 rte_free(rxq);
 135                 return -ENOMEM;
 136         }
 137
 138         /* Allocate FW completion ring */
 139         rc = qdev->ops->common->chain_alloc(edev,
 140                                             ECORE_CHAIN_USE_TO_CONSUME,
 141                                             ECORE_CHAIN_MODE_PBL,
 142                                             ECORE_CHAIN_CNT_TYPE_U16,
 143                                             rxq->nb_rx_desc,
 144                                             sizeof(union eth_rx_cqe),
 145                                             &rxq->rx_comp_ring,
 146                                             NULL);
 147
 148         if (rc != ECORE_SUCCESS) {
 149                 DP_ERR(edev, "Memory allocation fails for RX CQE ring"
 150                        " on socket %u\n", socket_id);
 151                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 152                 rte_free(rxq->sw_rx_ring);
 153                 rte_free(rxq);
 154                 return -ENOMEM;
 155         }
 156
 157         dev->data->rx_queues[queue_idx] = rxq;
 158         qdev->fp_array[queue_idx].rxq = rxq;
 159
 160         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 161                   queue_idx, nb_desc, qdev->mtu, socket_id);
 162
 163         return 0;
 164 }
 165
 166 static void
 167 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 168                     struct qede_rx_queue *rxq)
 169 {
 170         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 171         ecore_chain_reset(&rxq->rx_bd_ring);
 172         ecore_chain_reset(&rxq->rx_comp_ring);
 173         rxq->sw_rx_prod = 0;
 174         rxq->sw_rx_cons = 0;
 175         *rxq->hw_cons_ptr = 0;
 176 }
 177
 178 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 179 {
 180         uint16_t i;
 181
 182         if (rxq->sw_rx_ring) {
 183                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 184                         if (rxq->sw_rx_ring[i].mbuf) {
 185                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 186                                 rxq->sw_rx_ring[i].mbuf = NULL;
 187                         }
 188                 }
 189         }
 190 }
 191
 192 void qede_rx_queue_release(void *rx_queue)
 193 {
 194         struct qede_rx_queue *rxq = rx_queue;
 195
 196         if (rxq) {
 197                 qede_rx_queue_release_mbufs(rxq);
 198                 rte_free(rxq->sw_rx_ring);
 199                 rte_free(rxq);
 200         }
 201 }
 202
 203 /* Stops a given RX queue in the HW */
 204 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 205 {
 206         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 207         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 208         struct ecore_hwfn *p_hwfn;
 209         struct qede_rx_queue *rxq;
 210         int hwfn_index;
 211         int rc;
 212
 213         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 214                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 215                 hwfn_index = rx_queue_id % edev->num_hwfns;
 216                 p_hwfn = &edev->hwfns[hwfn_index];
 217                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 218                                 true, false);
 219                 if (rc != ECORE_SUCCESS) {
 220                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 221                         return -1;
 222                 }
 223                 qede_rx_queue_release_mbufs(rxq);
 224                 qede_rx_queue_reset(qdev, rxq);
 225                 eth_dev->data->rx_queue_state[rx_queue_id] =
 226                         RTE_ETH_QUEUE_STATE_STOPPED;
 227                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 228         } else {
 229                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 230                 rc = -EINVAL;
 231         }
 232
 233         return rc;
 234 }
 235
 236 int
 237 qede_tx_queue_setup(struct rte_eth_dev *dev,
 238                     uint16_t queue_idx,
 239                     uint16_t nb_desc,
 240                     unsigned int socket_id,
 241                     const struct rte_eth_txconf *tx_conf)
 242 {
 243         struct qede_dev *qdev = dev->data->dev_private;
 244         struct ecore_dev *edev = &qdev->edev;
 245         struct qede_tx_queue *txq;
 246         int rc;
 247
 248         PMD_INIT_FUNC_TRACE(edev);
 249
 250         if (!rte_is_power_of_2(nb_desc)) {
 251                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 252                        nb_desc);
 253                 return -EINVAL;
 254         }
 255
 256         /* Free memory prior to re-allocation if needed... */
 257         if (dev->data->tx_queues[queue_idx] != NULL) {
 258                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 259                 dev->data->tx_queues[queue_idx] = NULL;
 260         }
 261
 262         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 263                                  RTE_CACHE_LINE_SIZE, socket_id);
 264
 265         if (txq == NULL) {
 266                 DP_ERR(edev,
 267                        "Unable to allocate memory for txq on socket %u",
 268                        socket_id);
 269                 return -ENOMEM;
 270         }
 271
 272         txq->nb_tx_desc = nb_desc;
 273         txq->qdev = qdev;
 274         txq->port_id = dev->data->port_id;
 275
 276         rc = qdev->ops->common->chain_alloc(edev,
 277                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 278                                             ECORE_CHAIN_MODE_PBL,
 279                                             ECORE_CHAIN_CNT_TYPE_U16,
 280                                             txq->nb_tx_desc,
 281                                             sizeof(union eth_tx_bd_types),
 282                                             &txq->tx_pbl,
 283                                             NULL);
 284         if (rc != ECORE_SUCCESS) {
 285                 DP_ERR(edev,
 286                        "Unable to allocate memory for txbd ring on socket %u",
 287                        socket_id);
 288                 qede_tx_queue_release(txq);
 289                 return -ENOMEM;
 290         }
 291
 292         /* Allocate software ring */
 293         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 294                                              (sizeof(struct qede_tx_entry) *
 295                                               txq->nb_tx_desc),
 296                                              RTE_CACHE_LINE_SIZE, socket_id);
 297
 298         if (!txq->sw_tx_ring) {
 299                 DP_ERR(edev,
 300                        "Unable to allocate memory for txbd ring on socket %u",
 301                        socket_id);
 302                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 303                 qede_tx_queue_release(txq);
 304                 return -ENOMEM;
 305         }
 306
 307         txq->queue_id = queue_idx;
 308
 309         txq->nb_tx_avail = txq->nb_tx_desc;
 310
 311         txq->tx_free_thresh =
 312             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 313             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 314
 315         dev->data->tx_queues[queue_idx] = txq;
 316         qdev->fp_array[queue_idx].txq = txq;
 317
 318         DP_INFO(edev,
 319                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 320                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 321
 322         return 0;
 323 }
 324
 325 static void
 326 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 327                     struct qede_tx_queue *txq)
 328 {
 329         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 330         ecore_chain_reset(&txq->tx_pbl);
 331         txq->sw_tx_cons = 0;
 332         txq->sw_tx_prod = 0;
 333         *txq->hw_cons_ptr = 0;
 334 }
 335
 336 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 337 {
 338         uint16_t i;
 339
 340         if (txq->sw_tx_ring) {
 341                 for (i = 0; i < txq->nb_tx_desc; i++) {
 342                         if (txq->sw_tx_ring[i].mbuf) {
 343                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
 344                                 txq->sw_tx_ring[i].mbuf = NULL;
 345                         }
 346                 }
 347         }
 348 }
 349
 350 void qede_tx_queue_release(void *tx_queue)
 351 {
 352         struct qede_tx_queue *txq = tx_queue;
 353
 354         if (txq) {
 355                 qede_tx_queue_release_mbufs(txq);
 356                 rte_free(txq->sw_tx_ring);
 357                 rte_free(txq);
 358         }
 359 }
 360
 361 /* This function allocates fast-path status block memory */
 362 static int
 363 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 364                   uint16_t sb_id)
 365 {
 366         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 367         struct status_block *sb_virt;
 368         dma_addr_t sb_phys;
 369         int rc;
 370
 371         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 372                                           sizeof(struct status_block));
 373         if (!sb_virt) {
 374                 DP_ERR(edev, "Status block allocation failed\n");
 375                 return -ENOMEM;
 376         }
 377         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 378                                         sb_phys, sb_id);
 379         if (rc) {
 380                 DP_ERR(edev, "Status block initialization failed\n");
 381                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 382                                        sizeof(struct status_block));
 383                 return rc;
 384         }
 385
 386         return 0;
 387 }
 388
 389 int qede_alloc_fp_resc(struct qede_dev *qdev)
 390 {
 391         struct ecore_dev *edev = &qdev->edev;
 392         struct qede_fastpath *fp;
 393         uint32_t num_sbs;
 394         uint16_t sb_idx;
 395
 396         if (IS_VF(edev))
 397                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 398         else
 399                 num_sbs = ecore_cxt_get_proto_cid_count
 400                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 401
 402         if (num_sbs == 0) {
 403                 DP_ERR(edev, "No status blocks available\n");
 404                 return -EINVAL;
 405         }
 406
 407         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 408                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 409
 410         if (!qdev->fp_array) {
 411                 DP_ERR(edev, "fp array allocation failed\n");
 412                 return -ENOMEM;
 413         }
 414
 415         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 416                         sizeof(*qdev->fp_array));
 417
 418         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 419                 fp = &qdev->fp_array[sb_idx];
 420                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 421                                 RTE_CACHE_LINE_SIZE);
 422                 if (!fp->sb_info) {
 423                         DP_ERR(edev, "FP sb_info allocation fails\n");
 424                         return -1;
 425                 }
 426                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 427                         DP_ERR(edev, "FP status block allocation fails\n");
 428                         return -1;
 429                 }
 430                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 431                                 fp->sb_info->igu_sb_id);
 432         }
 433
 434         return 0;
 435 }
 436
 437 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 438 {
 439         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 440         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 441         struct qede_fastpath *fp;
 442         struct qede_rx_queue *rxq;
 443         struct qede_tx_queue *txq;
 444         uint16_t sb_idx;
 445         uint8_t i;
 446
 447         PMD_INIT_FUNC_TRACE(edev);
 448
 449         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 450                 fp = &qdev->fp_array[sb_idx];
 451                 DP_INFO(edev, "Free sb_info index 0x%x\n",
 452                                 fp->sb_info->igu_sb_id);
 453                 if (fp->sb_info) {
 454                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 455                                 fp->sb_info->sb_phys,
 456                                 sizeof(struct status_block));
 457                         rte_free(fp->sb_info);
 458                         fp->sb_info = NULL;
 459                 }
 460         }
 461
 462         /* Free packet buffers and ring memories */
 463         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 464                 if (eth_dev->data->rx_queues[i]) {
 465                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 466                         rxq = eth_dev->data->rx_queues[i];
 467                         qdev->ops->common->chain_free(edev,
 468                                                       &rxq->rx_bd_ring);
 469                         qdev->ops->common->chain_free(edev,
 470                                                       &rxq->rx_comp_ring);
 471                         eth_dev->data->rx_queues[i] = NULL;
 472                 }
 473         }
 474
 475         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 476                 if (eth_dev->data->tx_queues[i]) {
 477                         txq = eth_dev->data->tx_queues[i];
 478                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 479                         qdev->ops->common->chain_free(edev,
 480                                                       &txq->tx_pbl);
 481                         eth_dev->data->tx_queues[i] = NULL;
 482                 }
 483         }
 484
 485         if (qdev->fp_array)
 486                 rte_free(qdev->fp_array);
 487         qdev->fp_array = NULL;
 488 }
 489
 490 static inline void
 491 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 492                     struct qede_rx_queue *rxq)
 493 {
 494         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 495         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 496         struct eth_rx_prod_data rx_prods = { 0 };
 497
 498         /* Update producers */
 499         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 500         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 501
 502         /* Make sure that the BD and SGE data is updated before updating the
 503          * producers since FW might read the BD/SGE right after the producer
 504          * is updated.
 505          */
 506         rte_wmb();
 507
 508         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 509                         (uint32_t *)&rx_prods);
 510
 511         /* mmiowb is needed to synchronize doorbell writes from more than one
 512          * processor. It guarantees that the write arrives to the device before
 513          * the napi lock is released and another qede_poll is called (possibly
 514          * on another CPU). Without this barrier, the next doorbell can bypass
 515          * this doorbell. This is applicable to IA64/Altix systems.
 516          */
 517         rte_wmb();
 518
 519         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 520 }
 521
 522 /* Starts a given RX queue in HW */
 523 static int
 524 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 525 {
 526         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 527         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 528         struct ecore_queue_start_common_params params;
 529         struct ecore_rxq_start_ret_params ret_params;
 530         struct qede_rx_queue *rxq;
 531         struct qede_fastpath *fp;
 532         struct ecore_hwfn *p_hwfn;
 533         dma_addr_t p_phys_table;
 534         uint16_t page_cnt;
 535         uint16_t j;
 536         int hwfn_index;
 537         int rc;
 538
 539         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 540                 fp = &qdev->fp_array[rx_queue_id];
 541                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 542                 /* Allocate buffers for the Rx ring */
 543                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 544                         rc = qede_alloc_rx_buffer(rxq);
 545                         if (rc) {
 546                                 DP_ERR(edev, "RX buffer allocation failed"
 547                                                 " for rxq = %u\n", rx_queue_id);
 548                                 return -ENOMEM;
 549                         }
 550                 }
 551                 /* disable interrupts */
 552                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 553                 /* Prepare ramrod */
 554                 memset(&params, 0, sizeof(params));
 555                 params.queue_id = rx_queue_id;
 556                 params.vport_id = 0;
 557                 params.sb = fp->sb_info->igu_sb_id;
 558                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 559                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 560                 params.sb_idx = RX_PI;
 561                 hwfn_index = rx_queue_id % edev->num_hwfns;
 562                 p_hwfn = &edev->hwfns[hwfn_index];
 563                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 564                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 565                 memset(&ret_params, 0, sizeof(ret_params));
 566                 rc = ecore_eth_rx_queue_start(p_hwfn,
 567                                 p_hwfn->hw_info.opaque_fid,
 568                                 &params, fp->rxq->rx_buf_size,
 569                                 fp->rxq->rx_bd_ring.p_phys_addr,
 570                                 p_phys_table, page_cnt,
 571                                 &ret_params);
 572                 if (rc) {
 573                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 574                                         rx_queue_id, rc);
 575                         return -1;
 576                 }
 577                 /* Update with the returned parameters */
 578                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 579                 fp->rxq->handle = ret_params.p_handle;
 580
 581                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
 582                 qede_update_rx_prod(qdev, fp->rxq);
 583                 eth_dev->data->rx_queue_state[rx_queue_id] =
 584                         RTE_ETH_QUEUE_STATE_STARTED;
 585                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 586         } else {
 587                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 588                 rc = -EINVAL;
 589         }
 590
 591         return rc;
 592 }
 593
 594 static int
 595 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 596 {
 597         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 598         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 599         struct ecore_queue_start_common_params params;
 600         struct ecore_txq_start_ret_params ret_params;
 601         struct ecore_hwfn *p_hwfn;
 602         dma_addr_t p_phys_table;
 603         struct qede_tx_queue *txq;
 604         struct qede_fastpath *fp;
 605         uint16_t page_cnt;
 606         int hwfn_index;
 607         int rc;
 608
 609         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 610                 txq = eth_dev->data->tx_queues[tx_queue_id];
 611                 fp = &qdev->fp_array[tx_queue_id];
 612                 memset(&params, 0, sizeof(params));
 613                 params.queue_id = tx_queue_id;
 614                 params.vport_id = 0;
 615                 params.sb = fp->sb_info->igu_sb_id;
 616                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 617                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 618                 params.sb_idx = TX_PI(0); /* tc = 0 */
 619                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 620                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 621                 hwfn_index = tx_queue_id % edev->num_hwfns;
 622                 p_hwfn = &edev->hwfns[hwfn_index];
 623                 if (qdev->dev_info.is_legacy)
 624                         fp->txq->is_legacy = true;
 625                 rc = ecore_eth_tx_queue_start(p_hwfn,
 626                                 p_hwfn->hw_info.opaque_fid,
 627                                 &params, 0 /* tc */,
 628                                 p_phys_table, page_cnt,
 629                                 &ret_params);
 630                 if (rc != ECORE_SUCCESS) {
 631                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 632                                         tx_queue_id, rc);
 633                         return -1;
 634                 }
 635                 txq->doorbell_addr = ret_params.p_doorbell;
 636                 txq->handle = ret_params.p_handle;
 637
 638                 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
 639                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 640                                 DB_DEST_XCM);
 641                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 642                                 DB_AGG_CMD_SET);
 643                 SET_FIELD(txq->tx_db.data.params,
 644                                 ETH_DB_DATA_AGG_VAL_SEL,
 645                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 646                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 647                 eth_dev->data->tx_queue_state[tx_queue_id] =
 648                         RTE_ETH_QUEUE_STATE_STARTED;
 649                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 650         } else {
 651                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 652                 rc = -EINVAL;
 653         }
 654
 655         return rc;
 656 }
 657
 658 static inline void
 659 qede_free_tx_pkt(struct qede_tx_queue *txq)
 660 {
 661         struct rte_mbuf *mbuf;
 662         uint16_t nb_segs;
 663         uint16_t idx;
 664
 665         idx = TX_CONS(txq);
 666         mbuf = txq->sw_tx_ring[idx].mbuf;
 667         if (mbuf) {
 668                 nb_segs = mbuf->nb_segs;
 669                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 670                 while (nb_segs) {
 671                         /* It's like consuming rxbuf in recv() */
 672                         ecore_chain_consume(&txq->tx_pbl);
 673                         txq->nb_tx_avail++;
 674                         nb_segs--;
 675                 }
 676                 rte_pktmbuf_free(mbuf);
 677                 txq->sw_tx_ring[idx].mbuf = NULL;
 678                 txq->sw_tx_cons++;
 679                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 680         } else {
 681                 ecore_chain_consume(&txq->tx_pbl);
 682                 txq->nb_tx_avail++;
 683         }
 684 }
 685
 686 static inline void
 687 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 688                       struct qede_tx_queue *txq)
 689 {
 690         uint16_t hw_bd_cons;
 691 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 692         uint16_t sw_tx_cons;
 693 #endif
 694
 695         rte_compiler_barrier();
 696         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 697 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 698         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 699         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 700                    abs(hw_bd_cons - sw_tx_cons));
 701 #endif
 702         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
 703                 qede_free_tx_pkt(txq);
 704 }
 705
 706 static int qede_drain_txq(struct qede_dev *qdev,
 707                           struct qede_tx_queue *txq, bool allow_drain)
 708 {
 709         struct ecore_dev *edev = &qdev->edev;
 710         int rc, cnt = 1000;
 711
 712         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 713                 qede_process_tx_compl(edev, txq);
 714                 if (!cnt) {
 715                         if (allow_drain) {
 716                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 717                                           "requesting MCP to drain\n",
 718                                           txq->queue_id);
 719                                 rc = qdev->ops->common->drain(edev);
 720                                 if (rc)
 721                                         return rc;
 722                                 return qede_drain_txq(qdev, txq, false);
 723                         }
 724                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 725                                   "PROD=%d, CONS=%d\n",
 726                                   txq->queue_id, txq->sw_tx_prod,
 727                                   txq->sw_tx_cons);
 728                         return -1;
 729                 }
 730                 cnt--;
 731                 DELAY(1000);
 732                 rte_compiler_barrier();
 733         }
 734
 735         /* FW finished processing, wait for HW to transmit all tx packets */
 736         DELAY(2000);
 737
 738         return 0;
 739 }
 740
 741 /* Stops a given TX queue in the HW */
 742 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 743 {
 744         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 745         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 746         struct ecore_hwfn *p_hwfn;
 747         struct qede_tx_queue *txq;
 748         int hwfn_index;
 749         int rc;
 750
 751         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 752                 txq = eth_dev->data->tx_queues[tx_queue_id];
 753                 /* Drain txq */
 754                 if (qede_drain_txq(qdev, txq, true))
 755                         return -1; /* For the lack of retcodes */
 756                 /* Stop txq */
 757                 hwfn_index = tx_queue_id % edev->num_hwfns;
 758                 p_hwfn = &edev->hwfns[hwfn_index];
 759                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 760                 if (rc != ECORE_SUCCESS) {
 761                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 762                         return -1;
 763                 }
 764                 qede_tx_queue_release_mbufs(txq);
 765                 qede_tx_queue_reset(qdev, txq);
 766                 eth_dev->data->tx_queue_state[tx_queue_id] =
 767                         RTE_ETH_QUEUE_STATE_STOPPED;
 768                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 769         } else {
 770                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 771                 rc = -EINVAL;
 772         }
 773
 774         return rc;
 775 }
 776
 777 int qede_start_queues(struct rte_eth_dev *eth_dev)
 778 {
 779         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 780         uint8_t id;
 781         int rc;
 782
 783         for_each_rss(id) {
 784                 rc = qede_rx_queue_start(eth_dev, id);
 785                 if (rc != ECORE_SUCCESS)
 786                         return -1;
 787         }
 788
 789         for_each_tss(id) {
 790                 rc = qede_tx_queue_start(eth_dev, id);
 791                 if (rc != ECORE_SUCCESS)
 792                         return -1;
 793         }
 794
 795         return rc;
 796 }
 797
 798 void qede_stop_queues(struct rte_eth_dev *eth_dev)
 799 {
 800         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 801         uint8_t id;
 802
 803         /* Stopping RX/TX queues */
 804         for_each_tss(id) {
 805                 qede_tx_queue_stop(eth_dev, id);
 806         }
 807
 808         for_each_rss(id) {
 809                 qede_rx_queue_stop(eth_dev, id);
 810         }
 811 }
 812
 813 static bool qede_tunn_exist(uint16_t flag)
 814 {
 815         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 816                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 817 }
 818
 819 /*
 820  * qede_check_tunn_csum_l4:
 821  * Returns:
 822  * 1 : If L4 csum is enabled AND if the validation has failed.
 823  * 0 : Otherwise
 824  */
 825 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 826 {
 827         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 828              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 829                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 830                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 831
 832         return 0;
 833 }
 834
 835 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 836 {
 837         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 838              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 839                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 840                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 841
 842         return 0;
 843 }
 844
 845 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 846 {
 847         uint16_t val;
 848
 849         /* Lookup table */
 850         static const uint32_t
 851         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 852                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 853                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 854                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 855                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 856                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 857                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 858         };
 859
 860         /* Bits (0..3) provides L3/L4 protocol type */
 861         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 862                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 863                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 864                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 865
 866         if (val < QEDE_PKT_TYPE_MAX)
 867                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 868         else
 869                 return RTE_PTYPE_UNKNOWN;
 870 }
 871
 872 static inline uint8_t
 873 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 874 {
 875         struct ipv4_hdr *ip;
 876         uint16_t pkt_csum;
 877         uint16_t calc_csum;
 878         uint16_t val;
 879
 880         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 881                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 882
 883         if (unlikely(val)) {
 884                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 885                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 886                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 887                                            sizeof(struct ether_hdr));
 888                         pkt_csum = ip->hdr_checksum;
 889                         ip->hdr_checksum = 0;
 890                         calc_csum = rte_ipv4_cksum(ip);
 891                         ip->hdr_checksum = pkt_csum;
 892                         return (calc_csum != pkt_csum);
 893                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 894                         return 1;
 895                 }
 896         }
 897         return 0;
 898 }
 899
 900 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 901 {
 902         ecore_chain_consume(&rxq->rx_bd_ring);
 903         rxq->sw_rx_cons++;
 904 }
 905
 906 static inline void
 907 qede_reuse_page(__rte_unused struct qede_dev *qdev,
 908                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 909 {
 910         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 911         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 912         struct qede_rx_entry *curr_prod;
 913         dma_addr_t new_mapping;
 914
 915         curr_prod = &rxq->sw_rx_ring[idx];
 916         *curr_prod = *curr_cons;
 917
 918         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 919                       curr_prod->page_offset;
 920
 921         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 922         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 923
 924         rxq->sw_rx_prod++;
 925 }
 926
 927 static inline void
 928 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 929                         struct qede_dev *qdev, uint8_t count)
 930 {
 931         struct qede_rx_entry *curr_cons;
 932
 933         for (; count > 0; count--) {
 934                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 935                 qede_reuse_page(qdev, rxq, curr_cons);
 936                 qede_rx_bd_ring_consume(rxq);
 937         }
 938 }
 939
 940 static inline void
 941 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
 942                                      struct qede_rx_queue *rxq,
 943                                      uint8_t agg_index, uint16_t len)
 944 {
 945         struct qede_agg_info *tpa_info;
 946         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
 947         uint16_t cons_idx;
 948
 949         /* Under certain conditions it is possible that FW may not consume
 950          * additional or new BD. So decision to consume the BD must be made
 951          * based on len_list[0].
 952          */
 953         if (rte_le_to_cpu_16(len)) {
 954                 tpa_info = &rxq->tpa_info[agg_index];
 955                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 956                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
 957                 assert(curr_frag);
 958                 curr_frag->nb_segs = 1;
 959                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
 960                 curr_frag->data_len = curr_frag->pkt_len;
 961                 tpa_info->tpa_tail->next = curr_frag;
 962                 tpa_info->tpa_tail = curr_frag;
 963                 qede_rx_bd_ring_consume(rxq);
 964                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 965                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
 966                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 967                         rxq->rx_alloc_errors++;
 968                 }
 969         }
 970 }
 971
 972 static inline void
 973 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
 974                              struct qede_rx_queue *rxq,
 975                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
 976 {
 977         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
 978                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
 979         /* only len_list[0] will have value */
 980         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 981                                              cqe->len_list[0]);
 982 }
 983
 984 static inline void
 985 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
 986                             struct qede_rx_queue *rxq,
 987                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
 988 {
 989         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
 990
 991         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 992                                              cqe->len_list[0]);
 993         /* Update total length and frags based on end TPA */
 994         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
 995         /* TODO:  Add Sanity Checks */
 996         rx_mb->nb_segs = cqe->num_of_bds;
 997         rx_mb->pkt_len = cqe->total_packet_len;
 998
 999         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1000                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1001                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1002                    rx_mb->pkt_len);
1003 }
1004
1005 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1006 {
1007         uint32_t val;
1008
1009         /* Lookup table */
1010         static const uint32_t
1011         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1012                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1013                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1014                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1015                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1016                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1017                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1018                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1019                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1020                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1021                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1022                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1023                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1024                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1025                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1026                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1027                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1028                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1029                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1030                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1031                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1032                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1033                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1034                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1035                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1036                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1037                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1038                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1039                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1040                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1041                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1042                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1043                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1044                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1045                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1046                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1047                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1048                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1049                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1050                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1051                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1052         };
1053
1054         /* Cover bits[4-0] to include tunn_type and next protocol */
1055         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1056                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1057                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1058                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1059
1060         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1061                 return ptype_tunn_lkup_tbl[val];
1062         else
1063                 return RTE_PTYPE_UNKNOWN;
1064 }
1065
1066 static inline int
1067 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1068                      uint8_t num_segs, uint16_t pkt_len)
1069 {
1070         struct qede_rx_queue *rxq = p_rxq;
1071         struct qede_dev *qdev = rxq->qdev;
1072         register struct rte_mbuf *seg1 = NULL;
1073         register struct rte_mbuf *seg2 = NULL;
1074         uint16_t sw_rx_index;
1075         uint16_t cur_size;
1076
1077         seg1 = rx_mb;
1078         while (num_segs) {
1079                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1080                                                         pkt_len;
1081                 if (unlikely(!cur_size)) {
1082                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1083                                    " left for mapping jumbo\n", num_segs);
1084                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1085                         return -EINVAL;
1086                 }
1087                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1088                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1089                 qede_rx_bd_ring_consume(rxq);
1090                 pkt_len -= cur_size;
1091                 seg2->data_len = cur_size;
1092                 seg1->next = seg2;
1093                 seg1 = seg1->next;
1094                 num_segs--;
1095                 rxq->rx_segs++;
1096         }
1097
1098         return 0;
1099 }
1100
1101 uint16_t
1102 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1103 {
1104         struct qede_rx_queue *rxq = p_rxq;
1105         struct qede_dev *qdev = rxq->qdev;
1106         struct ecore_dev *edev = &qdev->edev;
1107         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1108         uint16_t rx_pkt = 0;
1109         union eth_rx_cqe *cqe;
1110         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1111         register struct rte_mbuf *rx_mb = NULL;
1112         register struct rte_mbuf *seg1 = NULL;
1113         enum eth_rx_cqe_type cqe_type;
1114         uint16_t pkt_len = 0; /* Sum of all BD segments */
1115         uint16_t len; /* Length of first BD */
1116         uint8_t num_segs = 1;
1117         uint16_t preload_idx;
1118         uint16_t parse_flag;
1119 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1120         uint8_t bitfield_val;
1121         enum rss_hash_type htype;
1122 #endif
1123         uint8_t tunn_parse_flag;
1124         uint8_t j;
1125         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1126         uint64_t ol_flags;
1127         uint32_t packet_type;
1128         uint16_t vlan_tci;
1129         bool tpa_start_flg;
1130         uint8_t offset, tpa_agg_idx, flags;
1131         struct qede_agg_info *tpa_info = NULL;
1132         uint32_t rss_hash;
1133
1134         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1135         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1136
1137         rte_rmb();
1138
1139         if (hw_comp_cons == sw_comp_cons)
1140                 return 0;
1141
1142         while (sw_comp_cons != hw_comp_cons) {
1143                 ol_flags = 0;
1144                 packet_type = RTE_PTYPE_UNKNOWN;
1145                 vlan_tci = 0;
1146                 tpa_start_flg = false;
1147                 rss_hash = 0;
1148
1149                 /* Get the CQE from the completion ring */
1150                 cqe =
1151                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1152                 cqe_type = cqe->fast_path_regular.type;
1153                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1154
1155                 switch (cqe_type) {
1156                 case ETH_RX_CQE_TYPE_REGULAR:
1157                         fp_cqe = &cqe->fast_path_regular;
1158                 break;
1159                 case ETH_RX_CQE_TYPE_TPA_START:
1160                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1161                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1162                         tpa_start_flg = true;
1163                         /* Mark it as LRO packet */
1164                         ol_flags |= PKT_RX_LRO;
1165                         /* In split mode,  seg_len is same as len_on_first_bd
1166                          * and ext_bd_len_list will be empty since there are
1167                          * no additional buffers
1168                          */
1169                         PMD_RX_LOG(INFO, rxq,
1170                             "TPA start[%d] - len_on_first_bd %d header %d"
1171                             " [bd_list[0] %d], [seg_len %d]\n",
1172                             cqe_start_tpa->tpa_agg_index,
1173                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1174                             cqe_start_tpa->header_len,
1175                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1176                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1177
1178                 break;
1179                 case ETH_RX_CQE_TYPE_TPA_CONT:
1180                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1181                                                      &cqe->fast_path_tpa_cont);
1182                         goto next_cqe;
1183                 case ETH_RX_CQE_TYPE_TPA_END:
1184                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1185                                                     &cqe->fast_path_tpa_end);
1186                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1187                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1188                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1189                         goto tpa_end;
1190                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1191                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1192                         ecore_eth_cqe_completion(
1193                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1194                                 (struct eth_slow_path_rx_cqe *)cqe);
1195                         /* fall-thru */
1196                 default:
1197                         goto next_cqe;
1198                 }
1199
1200                 /* Get the data from the SW ring */
1201                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1202                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1203                 assert(rx_mb != NULL);
1204
1205                 /* Handle regular CQE or TPA start CQE */
1206                 if (!tpa_start_flg) {
1207                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1208                         offset = fp_cqe->placement_offset;
1209                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1210                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1211                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1212                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1213 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1214                         bitfield_val = fp_cqe->bitfields;
1215                         htype = (uint8_t)GET_FIELD(bitfield_val,
1216                                         ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1217 #endif
1218                 } else {
1219                         parse_flag =
1220                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1221                         offset = cqe_start_tpa->placement_offset;
1222                         /* seg_len = len_on_first_bd */
1223                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1224                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1225 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1226                         bitfield_val = cqe_start_tpa->bitfields;
1227                         htype = (uint8_t)GET_FIELD(bitfield_val,
1228                                 ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE);
1229 #endif
1230                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1231                 }
1232                 if (qede_tunn_exist(parse_flag)) {
1233                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1234                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1235                                 PMD_RX_LOG(ERR, rxq,
1236                                             "L4 csum failed, flags = 0x%x\n",
1237                                             parse_flag);
1238                                 rxq->rx_hw_errors++;
1239                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1240                         } else {
1241                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1242                                 if (tpa_start_flg)
1243                                         flags =
1244                                          cqe_start_tpa->tunnel_pars_flags.flags;
1245                                 else
1246                                         flags = fp_cqe->tunnel_pars_flags.flags;
1247                                 tunn_parse_flag = flags;
1248                                 packet_type =
1249                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1250                         }
1251                 } else {
1252                         PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1253                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1254                                 PMD_RX_LOG(ERR, rxq,
1255                                             "L4 csum failed, flags = 0x%x\n",
1256                                             parse_flag);
1257                                 rxq->rx_hw_errors++;
1258                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1259                         } else {
1260                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1261                         }
1262                         if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1263                                                         parse_flag))) {
1264                                 PMD_RX_LOG(ERR, rxq,
1265                                            "IP csum failed, flags = 0x%x\n",
1266                                            parse_flag);
1267                                 rxq->rx_hw_errors++;
1268                                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1269                         } else {
1270                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1271                                 packet_type =
1272                                         qede_rx_cqe_to_pkt_type(parse_flag);
1273                         }
1274                 }
1275
1276                 if (CQE_HAS_VLAN(parse_flag)) {
1277                         ol_flags |= PKT_RX_VLAN_PKT;
1278                         if (qdev->vlan_strip_flg) {
1279                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1280                                 rx_mb->vlan_tci = vlan_tci;
1281                         }
1282                 }
1283                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1284                         ol_flags |= PKT_RX_QINQ_PKT;
1285                         if (qdev->vlan_strip_flg) {
1286                                 rx_mb->vlan_tci = vlan_tci;
1287                                 ol_flags |= PKT_RX_QINQ_STRIPPED;
1288                         }
1289                         rx_mb->vlan_tci_outer = 0;
1290                 }
1291                 /* RSS Hash */
1292                 if (qdev->rss_enable) {
1293                         ol_flags |= PKT_RX_RSS_HASH;
1294                         rx_mb->hash.rss = rss_hash;
1295                 }
1296
1297                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1298                         PMD_RX_LOG(ERR, rxq,
1299                                    "New buffer allocation failed,"
1300                                    "dropping incoming packet\n");
1301                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1302                         rte_eth_devices[rxq->port_id].
1303                             data->rx_mbuf_alloc_failed++;
1304                         rxq->rx_alloc_errors++;
1305                         break;
1306                 }
1307                 qede_rx_bd_ring_consume(rxq);
1308
1309                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1310                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1311                                    " len on first: %04x Total Len: %04x",
1312                                    fp_cqe->bd_num, len, pkt_len);
1313                         num_segs = fp_cqe->bd_num - 1;
1314                         seg1 = rx_mb;
1315                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1316                                                  pkt_len - len))
1317                                 goto next_cqe;
1318                         for (j = 0; j < num_segs; j++) {
1319                                 if (qede_alloc_rx_buffer(rxq)) {
1320                                         PMD_RX_LOG(ERR, rxq,
1321                                                 "Buffer allocation failed");
1322                                         rte_eth_devices[rxq->port_id].
1323                                                 data->rx_mbuf_alloc_failed++;
1324                                         rxq->rx_alloc_errors++;
1325                                         break;
1326                                 }
1327                                 rxq->rx_segs++;
1328                         }
1329                 }
1330                 rxq->rx_segs++; /* for the first segment */
1331
1332                 /* Prefetch next mbuf while processing current one. */
1333                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1334                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1335
1336                 /* Update rest of the MBUF fields */
1337                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1338                 rx_mb->port = rxq->port_id;
1339                 rx_mb->ol_flags = ol_flags;
1340                 rx_mb->data_len = len;
1341                 rx_mb->packet_type = packet_type;
1342                 PMD_RX_LOG(INFO, rxq,
1343                            "pkt_type 0x%04x len %u hash_type %d hash_val 0x%x"
1344                            " ol_flags 0x%04lx\n",
1345                            packet_type, len, htype, rx_mb->hash.rss,
1346                            (unsigned long)ol_flags);
1347                 if (!tpa_start_flg) {
1348                         rx_mb->nb_segs = fp_cqe->bd_num;
1349                         rx_mb->pkt_len = pkt_len;
1350                 } else {
1351                         /* store ref to the updated mbuf */
1352                         tpa_info->tpa_head = rx_mb;
1353                         tpa_info->tpa_tail = tpa_info->tpa_head;
1354                 }
1355                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1356 tpa_end:
1357                 if (!tpa_start_flg) {
1358                         rx_pkts[rx_pkt] = rx_mb;
1359                         rx_pkt++;
1360                 }
1361 next_cqe:
1362                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1363                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1364                 if (rx_pkt == nb_pkts) {
1365                         PMD_RX_LOG(DEBUG, rxq,
1366                                    "Budget reached nb_pkts=%u received=%u",
1367                                    rx_pkt, nb_pkts);
1368                         break;
1369                 }
1370         }
1371
1372         qede_update_rx_prod(qdev, rxq);
1373
1374         rxq->rcv_pkts += rx_pkt;
1375
1376         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1377
1378         return rx_pkt;
1379 }
1380
1381
1382 /* Populate scatter gather buffer descriptor fields */
1383 static inline uint8_t
1384 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1385                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1386 {
1387         struct qede_tx_queue *txq = p_txq;
1388         struct eth_tx_bd *tx_bd = NULL;
1389         dma_addr_t mapping;
1390         uint8_t nb_segs = 0;
1391
1392         /* Check for scattered buffers */
1393         while (m_seg) {
1394                 if (nb_segs == 0) {
1395                         if (!*bd2) {
1396                                 *bd2 = (struct eth_tx_2nd_bd *)
1397                                         ecore_chain_produce(&txq->tx_pbl);
1398                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1399                                 nb_segs++;
1400                         }
1401                         mapping = rte_mbuf_data_dma_addr(m_seg);
1402                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1403                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1404                 } else if (nb_segs == 1) {
1405                         if (!*bd3) {
1406                                 *bd3 = (struct eth_tx_3rd_bd *)
1407                                         ecore_chain_produce(&txq->tx_pbl);
1408                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1409                                 nb_segs++;
1410                         }
1411                         mapping = rte_mbuf_data_dma_addr(m_seg);
1412                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1413                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1414                 } else {
1415                         tx_bd = (struct eth_tx_bd *)
1416                                 ecore_chain_produce(&txq->tx_pbl);
1417                         memset(tx_bd, 0, sizeof(*tx_bd));
1418                         nb_segs++;
1419                         mapping = rte_mbuf_data_dma_addr(m_seg);
1420                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1421                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1422                 }
1423                 m_seg = m_seg->next;
1424         }
1425
1426         /* Return total scattered buffers */
1427         return nb_segs;
1428 }
1429
1430 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1431 static inline void
1432 print_tx_bd_info(struct qede_tx_queue *txq,
1433                  struct eth_tx_1st_bd *bd1,
1434                  struct eth_tx_2nd_bd *bd2,
1435                  struct eth_tx_3rd_bd *bd3,
1436                  uint64_t tx_ol_flags)
1437 {
1438         char ol_buf[256] = { 0 }; /* for verbose prints */
1439
1440         if (bd1)
1441                 PMD_TX_LOG(INFO, txq,
1442                            "BD1: nbytes=%u nbds=%u bd_flags=%04x bf=%04x",
1443                            rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1444                            bd1->data.bd_flags.bitfields,
1445                            rte_cpu_to_le_16(bd1->data.bitfields));
1446         if (bd2)
1447                 PMD_TX_LOG(INFO, txq,
1448                            "BD2: nbytes=%u bf=%04x\n",
1449                            rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1450         if (bd3)
1451                 PMD_TX_LOG(INFO, txq,
1452                            "BD3: nbytes=%u bf=%04x mss=%u\n",
1453                            rte_cpu_to_le_16(bd3->nbytes),
1454                            rte_cpu_to_le_16(bd3->data.bitfields),
1455                            rte_cpu_to_le_16(bd3->data.lso_mss));
1456
1457         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1458         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1459 }
1460 #endif
1461
1462 /* TX prepare to check packets meets TX conditions */
1463 uint16_t
1464 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1465 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1466                     uint16_t nb_pkts)
1467 {
1468         struct qede_tx_queue *txq = p_txq;
1469 #else
1470 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1471                     uint16_t nb_pkts)
1472 {
1473 #endif
1474         uint64_t ol_flags;
1475         struct rte_mbuf *m;
1476         uint16_t i;
1477 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1478         int ret;
1479 #endif
1480
1481         for (i = 0; i < nb_pkts; i++) {
1482                 m = tx_pkts[i];
1483                 ol_flags = m->ol_flags;
1484                 if (ol_flags & PKT_TX_TCP_SEG) {
1485                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1486                                 rte_errno = -EINVAL;
1487                                 break;
1488                         }
1489                         /* TBD: confirm its ~9700B for both ? */
1490                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1491                                 rte_errno = -EINVAL;
1492                                 break;
1493                         }
1494                 } else {
1495                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1496                                 rte_errno = -EINVAL;
1497                                 break;
1498                         }
1499                 }
1500                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1501                         rte_errno = -ENOTSUP;
1502                         break;
1503                 }
1504
1505 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1506                 ret = rte_validate_tx_offload(m);
1507                 if (ret != 0) {
1508                         rte_errno = ret;
1509                         break;
1510                 }
1511 #endif
1512         }
1513
1514 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1515         if (unlikely(i != nb_pkts))
1516                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1517                            nb_pkts - i);
1518 #endif
1519         return i;
1520 }
1521
1522 #define MPLSINUDP_HDR_SIZE                      (12)
1523
1524 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1525 static inline void
1526 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1527                                struct qede_tx_queue *txq)
1528 {
1529         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1530                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1531         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1532                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1533                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1534         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1535                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1536                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1537         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1538                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1539                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1540 }
1541 #endif
1542
1543 uint16_t
1544 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1545 {
1546         struct qede_tx_queue *txq = p_txq;
1547         struct qede_dev *qdev = txq->qdev;
1548         struct ecore_dev *edev = &qdev->edev;
1549         struct rte_mbuf *mbuf;
1550         struct rte_mbuf *m_seg = NULL;
1551         uint16_t nb_tx_pkts;
1552         uint16_t bd_prod;
1553         uint16_t idx;
1554         uint16_t nb_frags;
1555         uint16_t nb_pkt_sent = 0;
1556         uint8_t nbds;
1557         bool lso_flg;
1558         bool mplsoudp_flg;
1559         __rte_unused bool tunn_flg;
1560         bool tunn_ipv6_ext_flg;
1561         struct eth_tx_1st_bd *bd1;
1562         struct eth_tx_2nd_bd *bd2;
1563         struct eth_tx_3rd_bd *bd3;
1564         uint64_t tx_ol_flags;
1565         uint16_t hdr_size;
1566         /* BD1 */
1567         uint16_t bd1_bf;
1568         uint8_t bd1_bd_flags_bf;
1569         uint16_t vlan;
1570         /* BD2 */
1571         uint16_t bd2_bf1;
1572         uint16_t bd2_bf2;
1573         /* BD3 */
1574         uint16_t mss;
1575         uint16_t bd3_bf;
1576
1577         uint8_t tunn_l4_hdr_start_offset;
1578         uint8_t tunn_hdr_size;
1579         uint8_t inner_l2_hdr_size;
1580         uint16_t inner_l4_hdr_offset;
1581
1582         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1583                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1584                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1585                 qede_process_tx_compl(edev, txq);
1586         }
1587
1588         nb_tx_pkts  = nb_pkts;
1589         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1590         while (nb_tx_pkts--) {
1591                 /* Init flags/values */
1592                 tunn_flg = false;
1593                 lso_flg = false;
1594                 nbds = 0;
1595                 vlan = 0;
1596                 bd1 = NULL;
1597                 bd2 = NULL;
1598                 bd3 = NULL;
1599                 hdr_size = 0;
1600                 bd1_bf = 0;
1601                 bd1_bd_flags_bf = 0;
1602                 bd2_bf1 = 0;
1603                 bd2_bf2 = 0;
1604                 mss = 0;
1605                 bd3_bf = 0;
1606                 mplsoudp_flg = false;
1607                 tunn_ipv6_ext_flg = false;
1608                 tunn_hdr_size = 0;
1609                 tunn_l4_hdr_start_offset = 0;
1610
1611                 mbuf = *tx_pkts++;
1612                 assert(mbuf);
1613
1614                 /* Check minimum TX BDS availability against available BDs */
1615                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1616                         break;
1617
1618                 tx_ol_flags = mbuf->ol_flags;
1619                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1620
1621                 /* TX prepare would have already checked supported tunnel Tx
1622                  * offloads. Don't rely on pkt_type marked by Rx, instead use
1623                  * tx_ol_flags to decide.
1624                  */
1625                 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1626                                                 PKT_TX_TUNNEL_VXLAN) ||
1627                     ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1628                                                 PKT_TX_TUNNEL_MPLSINUDP)) {
1629                         /* Check against max which is Tunnel IPv6 + ext */
1630                         if (unlikely(txq->nb_tx_avail <
1631                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1632                                         break;
1633                         tunn_flg = true;
1634                         /* First indicate its a tunnel pkt */
1635                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1636                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1637                         /* Legacy FW had flipped behavior in regard to this bit
1638                          * i.e. it needed to set to prevent FW from touching
1639                          * encapsulated packets when it didn't need to.
1640                          */
1641                         if (unlikely(txq->is_legacy)) {
1642                                 bd1_bf ^= 1 <<
1643                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1644                         }
1645
1646                         /* Outer IP checksum offload */
1647                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1648                                            PKT_TX_OUTER_IPV4)) {
1649                                 bd1_bd_flags_bf |=
1650                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1651                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1652                         }
1653
1654                         /**
1655                          * Currently, only inner checksum offload in MPLS-in-UDP
1656                          * tunnel with one MPLS label is supported. Both outer
1657                          * and inner layers  lengths need to be provided in
1658                          * mbuf.
1659                          */
1660                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1661                                                 PKT_TX_TUNNEL_MPLSINUDP) {
1662                                 mplsoudp_flg = true;
1663 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1664                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1665 #endif
1666                                 /* Outer L4 offset in two byte words */
1667                                 tunn_l4_hdr_start_offset =
1668                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1669                                 /* Tunnel header size in two byte words */
1670                                 tunn_hdr_size = (mbuf->outer_l2_len +
1671                                                 mbuf->outer_l3_len +
1672                                                 MPLSINUDP_HDR_SIZE) / 2;
1673                                 /* Inner L2 header size in two byte words */
1674                                 inner_l2_hdr_size = (mbuf->l2_len -
1675                                                 MPLSINUDP_HDR_SIZE) / 2;
1676                                 /* Inner L4 header offset from the beggining
1677                                  * of inner packet in two byte words
1678                                  */
1679                                 inner_l4_hdr_offset = (mbuf->l2_len -
1680                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1681
1682                                 /* TODO: There's no DPDK flag to request outer
1683                                  * L4 checksum offload, so we don't do it.
1684                                  * bd1_bd_flags_bf |=
1685                                  *      ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1686                                  *      ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1687                                  */
1688                                 /* Inner L2 size and address type */
1689                                 bd2_bf1 |= (inner_l2_hdr_size &
1690                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1691                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1692                                 bd2_bf1 |= (UNICAST_ADDRESS &
1693                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1694                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1695                                 /* Treated as IPv6+Ext */
1696                                 bd2_bf1 |=
1697                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1698
1699                                 /* Mark inner IPv6 if present */
1700                                 if (tx_ol_flags & PKT_TX_IPV6)
1701                                         bd2_bf1 |=
1702                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1703
1704                                 /* Inner L4 offsets */
1705                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1706                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1707                                                         PKT_TX_TCP_CKSUM))) {
1708                                         /* Determines if BD3 is needed */
1709                                         tunn_ipv6_ext_flg = true;
1710                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1711                                                         PKT_TX_UDP_CKSUM) {
1712                                                 bd2_bf1 |=
1713                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1714                                         }
1715
1716                                         /* TODO other pseudo checksum modes are
1717                                          * not supported
1718                                          */
1719                                         bd2_bf1 |=
1720                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1721                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1722                                         bd2_bf2 |= (inner_l4_hdr_offset &
1723                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1724                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1725                                 }
1726                         } /* End MPLSoUDP */
1727                 } /* End Tunnel handling */
1728
1729                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1730                         lso_flg = true;
1731                         if (unlikely(txq->nb_tx_avail <
1732                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1733                                 break;
1734                         /* For LSO, packet header and payload must reside on
1735                          * buffers pointed by different BDs. Using BD1 for HDR
1736                          * and BD2 onwards for data.
1737                          */
1738                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1739                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1740                         bd1_bd_flags_bf |=
1741                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1742                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1743                         bd1_bd_flags_bf |=
1744                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1745                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1746                         /* Using one header BD */
1747                         bd3_bf |= rte_cpu_to_le_16(1 <<
1748                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1749                 } else {
1750                         if (unlikely(txq->nb_tx_avail <
1751                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1752                                 break;
1753                         bd1_bf |=
1754                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1755                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1756                 }
1757
1758                 /* Descriptor based VLAN insertion */
1759                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1760                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1761                         bd1_bd_flags_bf |=
1762                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1763                 }
1764
1765                 /* Offload the IP checksum in the hardware */
1766                 if (tx_ol_flags & PKT_TX_IP_CKSUM)
1767                         bd1_bd_flags_bf |=
1768                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1769
1770                 /* L4 checksum offload (tcp or udp) */
1771                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1772                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
1773                         bd1_bd_flags_bf |=
1774                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1775                 }
1776
1777                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1778                 idx = TX_PROD(txq);
1779                 txq->sw_tx_ring[idx].mbuf = mbuf;
1780
1781                 /* BD1 */
1782                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1783                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1784                 nbds++;
1785
1786                 /* Map MBUF linear data for DMA and set in the BD1 */
1787                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1788                                      mbuf->data_len);
1789                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
1790                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
1791                 bd1->data.vlan = vlan;
1792
1793                 if (lso_flg || mplsoudp_flg) {
1794                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1795                                                         (&txq->tx_pbl);
1796                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1797                         nbds++;
1798
1799                         /* BD1 */
1800                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1801                                              hdr_size);
1802                         /* BD2 */
1803                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
1804                                              rte_mbuf_data_dma_addr(mbuf)),
1805                                              mbuf->data_len - hdr_size);
1806                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
1807                         if (mplsoudp_flg) {
1808                                 bd2->data.bitfields2 =
1809                                         rte_cpu_to_le_16(bd2_bf2);
1810                                 /* Outer L3 size */
1811                                 bd2->data.tunn_ip_size =
1812                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
1813                         }
1814                         /* BD3 */
1815                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
1816                                 bd3 = (struct eth_tx_3rd_bd *)
1817                                         ecore_chain_produce(&txq->tx_pbl);
1818                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
1819                                 nbds++;
1820                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
1821                                 if (lso_flg)
1822                                         bd3->data.lso_mss = mss;
1823                                 if (mplsoudp_flg) {
1824                                         bd3->data.tunn_l4_hdr_start_offset_w =
1825                                                 tunn_l4_hdr_start_offset;
1826                                         bd3->data.tunn_hdr_size_w =
1827                                                 tunn_hdr_size;
1828                                 }
1829                         }
1830                 }
1831
1832                 /* Handle fragmented MBUF */
1833                 m_seg = mbuf->next;
1834                 /* Encode scatter gather buffer descriptors if required */
1835                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
1836                 bd1->data.nbds = nbds + nb_frags;
1837                 txq->nb_tx_avail -= bd1->data.nbds;
1838                 txq->sw_tx_prod++;
1839                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1840                 bd_prod =
1841                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1842 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1843                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
1844                 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d", lso_flg, tunn_flg);
1845 #endif
1846                 nb_pkt_sent++;
1847                 txq->xmit_pkts++;
1848         }
1849
1850         /* Write value of prod idx into bd_prod */
1851         txq->tx_db.data.bd_prod = bd_prod;
1852         rte_wmb();
1853         rte_compiler_barrier();
1854         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1855         rte_wmb();
1856
1857         /* Check again for Tx completions */
1858         qede_process_tx_compl(edev, txq);
1859
1860         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
1861                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
1862
1863         return nb_pkt_sent;
1864 }
1865
1866 uint16_t
1867 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
1868                      __rte_unused struct rte_mbuf **pkts,
1869                      __rte_unused uint16_t nb_pkts)
1870 {
1871         return 0;
1872 }