drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  41 {
  42         uint16_t i;
  43
  44         if (rxq->sw_rx_ring != NULL) {
  45                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  46                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  47                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  48                                 rxq->sw_rx_ring[i].mbuf = NULL;
  49                         }
  50                 }
  51         }
  52 }
  53
  54 void qede_rx_queue_release(void *rx_queue)
  55 {
  56         struct qede_rx_queue *rxq = rx_queue;
  57
  58         if (rxq != NULL) {
  59                 qede_rx_queue_release_mbufs(rxq);
  60                 rte_free(rxq->sw_rx_ring);
  61                 rxq->sw_rx_ring = NULL;
  62                 rte_free(rxq);
  63                 rxq = NULL;
  64         }
  65 }
  66
  67 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  68 {
  69         unsigned int i;
  70
  71         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs", txq->nb_tx_desc);
  72
  73         if (txq->sw_tx_ring) {
  74                 for (i = 0; i < txq->nb_tx_desc; i++) {
  75                         if (txq->sw_tx_ring[i].mbuf) {
  76                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  77                                 txq->sw_tx_ring[i].mbuf = NULL;
  78                         }
  79                 }
  80         }
  81 }
  82
  83 int
  84 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  85                     uint16_t nb_desc, unsigned int socket_id,
  86                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  87                     struct rte_mempool *mp)
  88 {
  89         struct qede_dev *qdev = dev->data->dev_private;
  90         struct ecore_dev *edev = &qdev->edev;
  91         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  92         struct qede_rx_queue *rxq;
  93         uint16_t max_rx_pkt_len;
  94         uint16_t bufsz;
  95         size_t size;
  96         int rc;
  97         int i;
  98
  99         PMD_INIT_FUNC_TRACE(edev);
 100
 101         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 102         if (!rte_is_power_of_2(nb_desc)) {
 103                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 104                           nb_desc);
 105                 return -EINVAL;
 106         }
 107
 108         /* Free memory prior to re-allocation if needed... */
 109         if (dev->data->rx_queues[queue_idx] != NULL) {
 110                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 111                 dev->data->rx_queues[queue_idx] = NULL;
 112         }
 113
 114         /* First allocate the rx queue data structure */
 115         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 116                                  RTE_CACHE_LINE_SIZE, socket_id);
 117
 118         if (!rxq) {
 119                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 120                           socket_id);
 121                 return -ENOMEM;
 122         }
 123
 124         rxq->qdev = qdev;
 125         rxq->mb_pool = mp;
 126         rxq->nb_rx_desc = nb_desc;
 127         rxq->queue_id = queue_idx;
 128         rxq->port_id = dev->data->port_id;
 129         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
 130         qdev->mtu = max_rx_pkt_len;
 131
 132         /* Fix up RX buffer size */
 133         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
 134         if ((rxmode->enable_scatter)                    ||
 135             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
 136                 if (!dev->data->scattered_rx) {
 137                         DP_INFO(edev, "Forcing scatter-gather mode\n");
 138                         dev->data->scattered_rx = 1;
 139                 }
 140         }
 141         if (dev->data->scattered_rx)
 142                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
 143         else
 144                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 145         /* Align to cache-line size if needed */
 146         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 147
 148         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 149                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 150
 151         /* Allocate the parallel driver ring for Rx buffers */
 152         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 153         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 154                                              RTE_CACHE_LINE_SIZE, socket_id);
 155         if (!rxq->sw_rx_ring) {
 156                 DP_NOTICE(edev, false,
 157                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 158                           socket_id);
 159                 rte_free(rxq);
 160                 rxq = NULL;
 161                 return -ENOMEM;
 162         }
 163
 164         /* Allocate FW Rx ring  */
 165         rc = qdev->ops->common->chain_alloc(edev,
 166                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 167                                             ECORE_CHAIN_MODE_NEXT_PTR,
 168                                             ECORE_CHAIN_CNT_TYPE_U16,
 169                                             rxq->nb_rx_desc,
 170                                             sizeof(struct eth_rx_bd),
 171                                             &rxq->rx_bd_ring,
 172                                             NULL);
 173
 174         if (rc != ECORE_SUCCESS) {
 175                 DP_NOTICE(edev, false,
 176                           "Unable to alloc memory for rxbd ring on socket %u\n",
 177                           socket_id);
 178                 rte_free(rxq->sw_rx_ring);
 179                 rxq->sw_rx_ring = NULL;
 180                 rte_free(rxq);
 181                 rxq = NULL;
 182                 return -ENOMEM;
 183         }
 184
 185         /* Allocate FW completion ring */
 186         rc = qdev->ops->common->chain_alloc(edev,
 187                                             ECORE_CHAIN_USE_TO_CONSUME,
 188                                             ECORE_CHAIN_MODE_PBL,
 189                                             ECORE_CHAIN_CNT_TYPE_U16,
 190                                             rxq->nb_rx_desc,
 191                                             sizeof(union eth_rx_cqe),
 192                                             &rxq->rx_comp_ring,
 193                                             NULL);
 194
 195         if (rc != ECORE_SUCCESS) {
 196                 DP_NOTICE(edev, false,
 197                           "Unable to alloc memory for cqe ring on socket %u\n",
 198                           socket_id);
 199                 /* TBD: Freeing RX BD ring */
 200                 rte_free(rxq->sw_rx_ring);
 201                 rxq->sw_rx_ring = NULL;
 202                 rte_free(rxq);
 203                 return -ENOMEM;
 204         }
 205
 206         /* Allocate buffers for the Rx ring */
 207         for (i = 0; i < rxq->nb_rx_desc; i++) {
 208                 rc = qede_alloc_rx_buffer(rxq);
 209                 if (rc) {
 210                         DP_NOTICE(edev, false,
 211                                   "RX buffer allocation failed at idx=%d\n", i);
 212                         goto err4;
 213                 }
 214         }
 215
 216         dev->data->rx_queues[queue_idx] = rxq;
 217
 218         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 219                   queue_idx, nb_desc, qdev->mtu, socket_id);
 220
 221         return 0;
 222 err4:
 223         qede_rx_queue_release(rxq);
 224         return -ENOMEM;
 225 }
 226
 227 void qede_tx_queue_release(void *tx_queue)
 228 {
 229         struct qede_tx_queue *txq = tx_queue;
 230
 231         if (txq != NULL) {
 232                 qede_tx_queue_release_mbufs(txq);
 233                 if (txq->sw_tx_ring) {
 234                         rte_free(txq->sw_tx_ring);
 235                         txq->sw_tx_ring = NULL;
 236                 }
 237                 rte_free(txq);
 238         }
 239         txq = NULL;
 240 }
 241
 242 int
 243 qede_tx_queue_setup(struct rte_eth_dev *dev,
 244                     uint16_t queue_idx,
 245                     uint16_t nb_desc,
 246                     unsigned int socket_id,
 247                     const struct rte_eth_txconf *tx_conf)
 248 {
 249         struct qede_dev *qdev = dev->data->dev_private;
 250         struct ecore_dev *edev = &qdev->edev;
 251         struct qede_tx_queue *txq;
 252         int rc;
 253
 254         PMD_INIT_FUNC_TRACE(edev);
 255
 256         if (!rte_is_power_of_2(nb_desc)) {
 257                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 258                        nb_desc);
 259                 return -EINVAL;
 260         }
 261
 262         /* Free memory prior to re-allocation if needed... */
 263         if (dev->data->tx_queues[queue_idx] != NULL) {
 264                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 265                 dev->data->tx_queues[queue_idx] = NULL;
 266         }
 267
 268         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 269                                  RTE_CACHE_LINE_SIZE, socket_id);
 270
 271         if (txq == NULL) {
 272                 DP_ERR(edev,
 273                        "Unable to allocate memory for txq on socket %u",
 274                        socket_id);
 275                 return -ENOMEM;
 276         }
 277
 278         txq->nb_tx_desc = nb_desc;
 279         txq->qdev = qdev;
 280         txq->port_id = dev->data->port_id;
 281
 282         rc = qdev->ops->common->chain_alloc(edev,
 283                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 284                                             ECORE_CHAIN_MODE_PBL,
 285                                             ECORE_CHAIN_CNT_TYPE_U16,
 286                                             txq->nb_tx_desc,
 287                                             sizeof(union eth_tx_bd_types),
 288                                             &txq->tx_pbl,
 289                                             NULL);
 290         if (rc != ECORE_SUCCESS) {
 291                 DP_ERR(edev,
 292                        "Unable to allocate memory for txbd ring on socket %u",
 293                        socket_id);
 294                 qede_tx_queue_release(txq);
 295                 return -ENOMEM;
 296         }
 297
 298         /* Allocate software ring */
 299         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 300                                              (sizeof(struct qede_tx_entry) *
 301                                               txq->nb_tx_desc),
 302                                              RTE_CACHE_LINE_SIZE, socket_id);
 303
 304         if (!txq->sw_tx_ring) {
 305                 DP_ERR(edev,
 306                        "Unable to allocate memory for txbd ring on socket %u",
 307                        socket_id);
 308                 qede_tx_queue_release(txq);
 309                 return -ENOMEM;
 310         }
 311
 312         txq->queue_id = queue_idx;
 313
 314         txq->nb_tx_avail = txq->nb_tx_desc;
 315
 316         txq->tx_free_thresh =
 317             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 318             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 319
 320         dev->data->tx_queues[queue_idx] = txq;
 321
 322         DP_INFO(edev,
 323                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 324                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 325
 326         return 0;
 327 }
 328
 329 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 330 static void qede_init_fp(struct qede_dev *qdev)
 331 {
 332         struct qede_fastpath *fp;
 333         uint8_t i;
 334         int fp_rx = qdev->fp_num_rx;
 335
 336         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 337                                            sizeof(*qdev->fp_array)));
 338         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 339                                            sizeof(*qdev->sb_array)));
 340         for_each_queue(i) {
 341                 fp = &qdev->fp_array[i];
 342                 if (fp_rx) {
 343                         fp->type = QEDE_FASTPATH_RX;
 344                         fp_rx--;
 345                 } else{
 346                         fp->type = QEDE_FASTPATH_TX;
 347                 }
 348                 fp->qdev = qdev;
 349                 fp->id = i;
 350                 fp->sb_info = &qdev->sb_array[i];
 351                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 352         }
 353
 354 }
 355
 356 void qede_free_fp_arrays(struct qede_dev *qdev)
 357 {
 358         /* It asseumes qede_free_mem_load() is called before */
 359         if (qdev->fp_array != NULL) {
 360                 rte_free(qdev->fp_array);
 361                 qdev->fp_array = NULL;
 362         }
 363
 364         if (qdev->sb_array != NULL) {
 365                 rte_free(qdev->sb_array);
 366                 qdev->sb_array = NULL;
 367         }
 368 }
 369
 370 static int qede_alloc_fp_array(struct qede_dev *qdev)
 371 {
 372         struct ecore_dev *edev = &qdev->edev;
 373
 374         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 375                                     sizeof(*qdev->fp_array),
 376                                     RTE_CACHE_LINE_SIZE);
 377
 378         if (!qdev->fp_array) {
 379                 DP_ERR(edev, "fp array allocation failed\n");
 380                 return -ENOMEM;
 381         }
 382
 383         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 384                                     sizeof(*qdev->sb_array),
 385                                     RTE_CACHE_LINE_SIZE);
 386
 387         if (!qdev->sb_array) {
 388                 DP_ERR(edev, "sb array allocation failed\n");
 389                 rte_free(qdev->fp_array);
 390                 return -ENOMEM;
 391         }
 392
 393         return 0;
 394 }
 395
 396 /* This function allocates fast-path status block memory */
 397 static int
 398 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 399                   uint16_t sb_id)
 400 {
 401         struct ecore_dev *edev = &qdev->edev;
 402         struct status_block *sb_virt;
 403         dma_addr_t sb_phys;
 404         int rc;
 405
 406         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 407
 408         if (!sb_virt) {
 409                 DP_ERR(edev, "Status block allocation failed\n");
 410                 return -ENOMEM;
 411         }
 412
 413         rc = qdev->ops->common->sb_init(edev, sb_info,
 414                                         sb_virt, sb_phys, sb_id,
 415                                         QED_SB_TYPE_L2_QUEUE);
 416         if (rc) {
 417                 DP_ERR(edev, "Status block initialization failed\n");
 418                 /* TBD: No dma_free_coherent possible */
 419                 return rc;
 420         }
 421
 422         return 0;
 423 }
 424
 425 int qede_alloc_fp_resc(struct qede_dev *qdev)
 426 {
 427         struct ecore_dev *edev = &qdev->edev;
 428         struct qede_fastpath *fp;
 429         uint32_t num_sbs;
 430         uint16_t i;
 431         uint16_t sb_idx;
 432         int rc;
 433
 434         if (IS_VF(edev))
 435                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 436         else
 437                 num_sbs = ecore_cxt_get_proto_cid_count
 438                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 439
 440         if (num_sbs == 0) {
 441                 DP_ERR(edev, "No status blocks available\n");
 442                 return -EINVAL;
 443         }
 444
 445         if (qdev->fp_array)
 446                 qede_free_fp_arrays(qdev);
 447
 448         rc = qede_alloc_fp_array(qdev);
 449         if (rc != 0)
 450                 return rc;
 451
 452         qede_init_fp(qdev);
 453
 454         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 455                 fp = &qdev->fp_array[i];
 456                 if (IS_VF(edev))
 457                         sb_idx = i % num_sbs;
 458                 else
 459                         sb_idx = i;
 460                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 461                         qede_free_fp_arrays(qdev);
 462                         return -ENOMEM;
 463                 }
 464         }
 465
 466         return 0;
 467 }
 468
 469 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 470 {
 471         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 472
 473         qede_free_mem_load(eth_dev);
 474         qede_free_fp_arrays(qdev);
 475 }
 476
 477 static inline void
 478 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 479                     struct qede_rx_queue *rxq)
 480 {
 481         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 482         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 483         struct eth_rx_prod_data rx_prods = { 0 };
 484
 485         /* Update producers */
 486         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 487         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 488
 489         /* Make sure that the BD and SGE data is updated before updating the
 490          * producers since FW might read the BD/SGE right after the producer
 491          * is updated.
 492          */
 493         rte_wmb();
 494
 495         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 496                         (uint32_t *)&rx_prods);
 497
 498         /* mmiowb is needed to synchronize doorbell writes from more than one
 499          * processor. It guarantees that the write arrives to the device before
 500          * the napi lock is released and another qede_poll is called (possibly
 501          * on another CPU). Without this barrier, the next doorbell can bypass
 502          * this doorbell. This is applicable to IA64/Altix systems.
 503          */
 504         rte_wmb();
 505
 506         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 507 }
 508
 509 static int qede_start_queues(struct rte_eth_dev *eth_dev)
 510 {
 511         struct qede_dev *qdev = eth_dev->data->dev_private;
 512         struct ecore_dev *edev = &qdev->edev;
 513         struct ecore_queue_start_common_params q_params;
 514         struct qede_tx_queue *txq;
 515         struct qede_fastpath *fp;
 516         dma_addr_t p_phys_table;
 517         int txq_index;
 518         uint16_t page_cnt;
 519         int rc, tc, i;
 520
 521         for_each_queue(i) {
 522                 fp = &qdev->fp_array[i];
 523                 if (fp->type & QEDE_FASTPATH_RX) {
 524                         struct ecore_rxq_start_ret_params ret_params;
 525
 526                         p_phys_table =
 527                             ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 528                         page_cnt =
 529                             ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 530
 531                         memset(&ret_params, 0, sizeof(ret_params));
 532                         memset(&q_params, 0, sizeof(q_params));
 533                         q_params.queue_id = i;
 534                         q_params.vport_id = 0;
 535                         q_params.sb = fp->sb_info->igu_sb_id;
 536                         q_params.sb_idx = RX_PI;
 537
 538                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 539
 540                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 541                                            fp->rxq->rx_buf_size,
 542                                            fp->rxq->rx_bd_ring.p_phys_addr,
 543                                            p_phys_table,
 544                                            page_cnt,
 545                                            &ret_params);
 546                         if (rc) {
 547                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 548                                        fp->rxq->queue_id, rc);
 549                                 return rc;
 550                         }
 551
 552                         /* Use the return parameters */
 553                         fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 554                         fp->rxq->handle = ret_params.p_handle;
 555
 556                         fp->rxq->hw_cons_ptr =
 557                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 558
 559                         qede_update_rx_prod(qdev, fp->rxq);
 560                 }
 561
 562                 if (!(fp->type & QEDE_FASTPATH_TX))
 563                         continue;
 564                 for (tc = 0; tc < qdev->num_tc; tc++) {
 565                         struct ecore_txq_start_ret_params ret_params;
 566
 567                         txq = fp->txqs[tc];
 568                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 569
 570                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 571                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 572
 573                         memset(&q_params, 0, sizeof(q_params));
 574                         memset(&ret_params, 0, sizeof(ret_params));
 575                         q_params.queue_id = txq->queue_id;
 576                         q_params.vport_id = 0;
 577                         q_params.sb = fp->sb_info->igu_sb_id;
 578                         q_params.sb_idx = TX_PI(tc);
 579
 580                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 581                                                    p_phys_table,
 582                                                    page_cnt, /* **pp_doorbell */
 583                                                    &ret_params);
 584                         if (rc) {
 585                                 DP_ERR(edev, "Start txq %u failed %d\n",
 586                                        txq_index, rc);
 587                                 return rc;
 588                         }
 589
 590                         txq->doorbell_addr = ret_params.p_doorbell;
 591                         txq->handle = ret_params.p_handle;
 592
 593                         txq->hw_cons_ptr =
 594                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 595                         SET_FIELD(txq->tx_db.data.params,
 596                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 597                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 598                                   DB_AGG_CMD_SET);
 599                         SET_FIELD(txq->tx_db.data.params,
 600                                   ETH_DB_DATA_AGG_VAL_SEL,
 601                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 602
 603                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 static bool qede_tunn_exist(uint16_t flag)
 611 {
 612         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 613                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 614 }
 615
 616 /*
 617  * qede_check_tunn_csum_l4:
 618  * Returns:
 619  * 1 : If L4 csum is enabled AND if the validation has failed.
 620  * 0 : Otherwise
 621  */
 622 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 623 {
 624         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 625              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 626                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 627                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 628
 629         return 0;
 630 }
 631
 632 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 633 {
 634         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 635              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 636                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 637                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 638
 639         return 0;
 640 }
 641
 642 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 643 {
 644         uint16_t val;
 645
 646         /* Lookup table */
 647         static const uint32_t
 648         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 649                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 650                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 651                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 652                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 653                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 654                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 655         };
 656
 657         /* Bits (0..3) provides L3/L4 protocol type */
 658         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 659                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 660                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 661                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 662
 663         if (val < QEDE_PKT_TYPE_MAX)
 664                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 665         else
 666                 return RTE_PTYPE_UNKNOWN;
 667 }
 668
 669 static inline uint8_t
 670 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 671 {
 672         struct ipv4_hdr *ip;
 673         uint16_t pkt_csum;
 674         uint16_t calc_csum;
 675         uint16_t val;
 676
 677         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 678                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 679
 680         if (unlikely(val)) {
 681                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 682                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 683                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 684                                            sizeof(struct ether_hdr));
 685                         pkt_csum = ip->hdr_checksum;
 686                         ip->hdr_checksum = 0;
 687                         calc_csum = rte_ipv4_cksum(ip);
 688                         ip->hdr_checksum = pkt_csum;
 689                         return (calc_csum != pkt_csum);
 690                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 691                         return 1;
 692                 }
 693         }
 694         return 0;
 695 }
 696
 697 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 698 {
 699         ecore_chain_consume(&rxq->rx_bd_ring);
 700         rxq->sw_rx_cons++;
 701 }
 702
 703 static inline void
 704 qede_reuse_page(__rte_unused struct qede_dev *qdev,
 705                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 706 {
 707         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 708         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 709         struct qede_rx_entry *curr_prod;
 710         dma_addr_t new_mapping;
 711
 712         curr_prod = &rxq->sw_rx_ring[idx];
 713         *curr_prod = *curr_cons;
 714
 715         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 716                       curr_prod->page_offset;
 717
 718         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 719         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 720
 721         rxq->sw_rx_prod++;
 722 }
 723
 724 static inline void
 725 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 726                         struct qede_dev *qdev, uint8_t count)
 727 {
 728         struct qede_rx_entry *curr_cons;
 729
 730         for (; count > 0; count--) {
 731                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 732                 qede_reuse_page(qdev, rxq, curr_cons);
 733                 qede_rx_bd_ring_consume(rxq);
 734         }
 735 }
 736
 737 static inline void
 738 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
 739                                      struct qede_rx_queue *rxq,
 740                                      uint8_t agg_index, uint16_t len)
 741 {
 742         struct qede_agg_info *tpa_info;
 743         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
 744         uint16_t cons_idx;
 745
 746         /* Under certain conditions it is possible that FW may not consume
 747          * additional or new BD. So decision to consume the BD must be made
 748          * based on len_list[0].
 749          */
 750         if (rte_le_to_cpu_16(len)) {
 751                 tpa_info = &rxq->tpa_info[agg_index];
 752                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 753                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
 754                 assert(curr_frag);
 755                 curr_frag->nb_segs = 1;
 756                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
 757                 curr_frag->data_len = curr_frag->pkt_len;
 758                 tpa_info->tpa_tail->next = curr_frag;
 759                 tpa_info->tpa_tail = curr_frag;
 760                 qede_rx_bd_ring_consume(rxq);
 761                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 762                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
 763                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 764                         rxq->rx_alloc_errors++;
 765                 }
 766         }
 767 }
 768
 769 static inline void
 770 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
 771                              struct qede_rx_queue *rxq,
 772                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
 773 {
 774         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
 775                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
 776         /* only len_list[0] will have value */
 777         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 778                                              cqe->len_list[0]);
 779 }
 780
 781 static inline void
 782 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
 783                             struct qede_rx_queue *rxq,
 784                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
 785 {
 786         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
 787
 788         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 789                                              cqe->len_list[0]);
 790         /* Update total length and frags based on end TPA */
 791         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
 792         /* TODO:  Add Sanity Checks */
 793         rx_mb->nb_segs = cqe->num_of_bds;
 794         rx_mb->pkt_len = cqe->total_packet_len;
 795
 796         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
 797                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
 798                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
 799                    rx_mb->pkt_len);
 800 }
 801
 802 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 803 {
 804         uint32_t val;
 805
 806         /* Lookup table */
 807         static const uint32_t
 808         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 809                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 810                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 811                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 812                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 813                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 814                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 815                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 816                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 817                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 818                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 819                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 820                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 821                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 822                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 823                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 824                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 825                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 826                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 827                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 828                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 829                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 830                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 831                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 832                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 833                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 834                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 835                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 836                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 837                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 838                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 839                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 840                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 841                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 842                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 843                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 844                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 845                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 846                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 847                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 848                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 849         };
 850
 851         /* Cover bits[4-0] to include tunn_type and next protocol */
 852         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 853                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 854                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 855                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 856
 857         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 858                 return ptype_tunn_lkup_tbl[val];
 859         else
 860                 return RTE_PTYPE_UNKNOWN;
 861 }
 862
 863 static inline int
 864 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 865                      uint8_t num_segs, uint16_t pkt_len)
 866 {
 867         struct qede_rx_queue *rxq = p_rxq;
 868         struct qede_dev *qdev = rxq->qdev;
 869         register struct rte_mbuf *seg1 = NULL;
 870         register struct rte_mbuf *seg2 = NULL;
 871         uint16_t sw_rx_index;
 872         uint16_t cur_size;
 873
 874         seg1 = rx_mb;
 875         while (num_segs) {
 876                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
 877                                                         pkt_len;
 878                 if (unlikely(!cur_size)) {
 879                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
 880                                    " left for mapping jumbo", num_segs);
 881                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 882                         return -EINVAL;
 883                 }
 884                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 885                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 886                 qede_rx_bd_ring_consume(rxq);
 887                 pkt_len -= cur_size;
 888                 seg2->data_len = cur_size;
 889                 seg1->next = seg2;
 890                 seg1 = seg1->next;
 891                 num_segs--;
 892                 rxq->rx_segs++;
 893         }
 894
 895         return 0;
 896 }
 897
 898 uint16_t
 899 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 900 {
 901         struct qede_rx_queue *rxq = p_rxq;
 902         struct qede_dev *qdev = rxq->qdev;
 903         struct ecore_dev *edev = &qdev->edev;
 904         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 905         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 906         uint16_t rx_pkt = 0;
 907         union eth_rx_cqe *cqe;
 908         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
 909         register struct rte_mbuf *rx_mb = NULL;
 910         register struct rte_mbuf *seg1 = NULL;
 911         enum eth_rx_cqe_type cqe_type;
 912         uint16_t pkt_len = 0; /* Sum of all BD segments */
 913         uint16_t len; /* Length of first BD */
 914         uint8_t num_segs = 1;
 915         uint16_t preload_idx;
 916         uint16_t parse_flag;
 917 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
 918         uint8_t bitfield_val;
 919         enum rss_hash_type htype;
 920 #endif
 921         uint8_t tunn_parse_flag;
 922         uint8_t j;
 923         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
 924         uint64_t ol_flags;
 925         uint32_t packet_type;
 926         uint16_t vlan_tci;
 927         bool tpa_start_flg;
 928         uint8_t offset, tpa_agg_idx, flags;
 929         struct qede_agg_info *tpa_info = NULL;
 930         uint32_t rss_hash;
 931
 932         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 933         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 934
 935         rte_rmb();
 936
 937         if (hw_comp_cons == sw_comp_cons)
 938                 return 0;
 939
 940         while (sw_comp_cons != hw_comp_cons) {
 941                 ol_flags = 0;
 942                 packet_type = RTE_PTYPE_UNKNOWN;
 943                 vlan_tci = 0;
 944                 tpa_start_flg = false;
 945                 rss_hash = 0;
 946
 947                 /* Get the CQE from the completion ring */
 948                 cqe =
 949                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 950                 cqe_type = cqe->fast_path_regular.type;
 951                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
 952
 953                 switch (cqe_type) {
 954                 case ETH_RX_CQE_TYPE_REGULAR:
 955                         fp_cqe = &cqe->fast_path_regular;
 956                 break;
 957                 case ETH_RX_CQE_TYPE_TPA_START:
 958                         cqe_start_tpa = &cqe->fast_path_tpa_start;
 959                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
 960                         tpa_start_flg = true;
 961                         /* Mark it as LRO packet */
 962                         ol_flags |= PKT_RX_LRO;
 963                         /* In split mode,  seg_len is same as len_on_first_bd
 964                          * and ext_bd_len_list will be empty since there are
 965                          * no additional buffers
 966                          */
 967                         PMD_RX_LOG(INFO, rxq,
 968                             "TPA start[%d] - len_on_first_bd %d header %d"
 969                             " [bd_list[0] %d], [seg_len %d]\n",
 970                             cqe_start_tpa->tpa_agg_index,
 971                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
 972                             cqe_start_tpa->header_len,
 973                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
 974                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
 975
 976                 break;
 977                 case ETH_RX_CQE_TYPE_TPA_CONT:
 978                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
 979                                                      &cqe->fast_path_tpa_cont);
 980                         goto next_cqe;
 981                 case ETH_RX_CQE_TYPE_TPA_END:
 982                         qede_rx_process_tpa_end_cqe(qdev, rxq,
 983                                                     &cqe->fast_path_tpa_end);
 984                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
 985                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
 986                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
 987                         goto tpa_end;
 988                 case ETH_RX_CQE_TYPE_SLOW_PATH:
 989                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
 990                         qdev->ops->eth_cqe_completion(edev, fp->id,
 991                                 (struct eth_slow_path_rx_cqe *)cqe);
 992                         /* fall-thru */
 993                 default:
 994                         goto next_cqe;
 995                 }
 996
 997                 /* Get the data from the SW ring */
 998                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 999                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1000                 assert(rx_mb != NULL);
1001
1002                 /* Handle regular CQE or TPA start CQE */
1003                 if (!tpa_start_flg) {
1004                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1005                         offset = fp_cqe->placement_offset;
1006                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1007                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1008                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1009                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1010 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1011                         bitfield_val = fp_cqe->bitfields;
1012                         htype = (uint8_t)GET_FIELD(bitfield_val,
1013                                         ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1014 #endif
1015                 } else {
1016                         parse_flag =
1017                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1018                         offset = cqe_start_tpa->placement_offset;
1019                         /* seg_len = len_on_first_bd */
1020                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1021                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1022 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1023                         bitfield_val = cqe_start_tpa->bitfields;
1024                         htype = (uint8_t)GET_FIELD(bitfield_val,
1025                                 ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE);
1026 #endif
1027                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1028                 }
1029                 if (qede_tunn_exist(parse_flag)) {
1030                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1031                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1032                                 PMD_RX_LOG(ERR, rxq,
1033                                             "L4 csum failed, flags = 0x%x\n",
1034                                             parse_flag);
1035                                 rxq->rx_hw_errors++;
1036                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1037                         } else {
1038                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1039                                 if (tpa_start_flg)
1040                                         flags =
1041                                          cqe_start_tpa->tunnel_pars_flags.flags;
1042                                 else
1043                                         flags = fp_cqe->tunnel_pars_flags.flags;
1044                                 tunn_parse_flag = flags;
1045                                 packet_type =
1046                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1047                         }
1048                 } else {
1049                         PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1050                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1051                                 PMD_RX_LOG(ERR, rxq,
1052                                             "L4 csum failed, flags = 0x%x\n",
1053                                             parse_flag);
1054                                 rxq->rx_hw_errors++;
1055                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1056                         } else {
1057                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1058                         }
1059                         if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1060                                                         parse_flag))) {
1061                                 PMD_RX_LOG(ERR, rxq,
1062                                            "IP csum failed, flags = 0x%x\n",
1063                                            parse_flag);
1064                                 rxq->rx_hw_errors++;
1065                                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1066                         } else {
1067                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1068                                 packet_type =
1069                                         qede_rx_cqe_to_pkt_type(parse_flag);
1070                         }
1071                 }
1072
1073                 if (CQE_HAS_VLAN(parse_flag)) {
1074                         ol_flags |= PKT_RX_VLAN_PKT;
1075                         if (qdev->vlan_strip_flg) {
1076                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1077                                 rx_mb->vlan_tci = vlan_tci;
1078                         }
1079                 }
1080                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1081                         ol_flags |= PKT_RX_QINQ_PKT;
1082                         if (qdev->vlan_strip_flg) {
1083                                 rx_mb->vlan_tci = vlan_tci;
1084                                 ol_flags |= PKT_RX_QINQ_STRIPPED;
1085                         }
1086                         rx_mb->vlan_tci_outer = 0;
1087                 }
1088                 /* RSS Hash */
1089                 if (qdev->rss_enable) {
1090                         ol_flags |= PKT_RX_RSS_HASH;
1091                         rx_mb->hash.rss = rss_hash;
1092                 }
1093
1094                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1095                         PMD_RX_LOG(ERR, rxq,
1096                                    "New buffer allocation failed,"
1097                                    "dropping incoming packet\n");
1098                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1099                         rte_eth_devices[rxq->port_id].
1100                             data->rx_mbuf_alloc_failed++;
1101                         rxq->rx_alloc_errors++;
1102                         break;
1103                 }
1104                 qede_rx_bd_ring_consume(rxq);
1105
1106                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1107                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1108                                    " len on first: %04x Total Len: %04x",
1109                                    fp_cqe->bd_num, len, pkt_len);
1110                         num_segs = fp_cqe->bd_num - 1;
1111                         seg1 = rx_mb;
1112                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1113                                                  pkt_len - len))
1114                                 goto next_cqe;
1115                         for (j = 0; j < num_segs; j++) {
1116                                 if (qede_alloc_rx_buffer(rxq)) {
1117                                         PMD_RX_LOG(ERR, rxq,
1118                                                 "Buffer allocation failed");
1119                                         rte_eth_devices[rxq->port_id].
1120                                                 data->rx_mbuf_alloc_failed++;
1121                                         rxq->rx_alloc_errors++;
1122                                         break;
1123                                 }
1124                                 rxq->rx_segs++;
1125                         }
1126                 }
1127                 rxq->rx_segs++; /* for the first segment */
1128
1129                 /* Prefetch next mbuf while processing current one. */
1130                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1131                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1132
1133                 /* Update rest of the MBUF fields */
1134                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1135                 rx_mb->port = rxq->port_id;
1136                 rx_mb->ol_flags = ol_flags;
1137                 rx_mb->data_len = len;
1138                 rx_mb->packet_type = packet_type;
1139                 PMD_RX_LOG(INFO, rxq,
1140                            "pkt_type 0x%04x len %u hash_type %d hash_val 0x%x"
1141                            " ol_flags 0x%04lx\n",
1142                            packet_type, len, htype, rx_mb->hash.rss,
1143                            (unsigned long)ol_flags);
1144                 if (!tpa_start_flg) {
1145                         rx_mb->nb_segs = fp_cqe->bd_num;
1146                         rx_mb->pkt_len = pkt_len;
1147                 } else {
1148                         /* store ref to the updated mbuf */
1149                         tpa_info->tpa_head = rx_mb;
1150                         tpa_info->tpa_tail = tpa_info->tpa_head;
1151                 }
1152                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1153 tpa_end:
1154                 if (!tpa_start_flg) {
1155                         rx_pkts[rx_pkt] = rx_mb;
1156                         rx_pkt++;
1157                 }
1158 next_cqe:
1159                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1160                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1161                 if (rx_pkt == nb_pkts) {
1162                         PMD_RX_LOG(DEBUG, rxq,
1163                                    "Budget reached nb_pkts=%u received=%u",
1164                                    rx_pkt, nb_pkts);
1165                         break;
1166                 }
1167         }
1168
1169         qede_update_rx_prod(qdev, rxq);
1170
1171         rxq->rcv_pkts += rx_pkt;
1172
1173         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1174
1175         return rx_pkt;
1176 }
1177
1178 static inline void
1179 qede_free_tx_pkt(struct qede_tx_queue *txq)
1180 {
1181         struct rte_mbuf *mbuf;
1182         uint16_t nb_segs;
1183         uint16_t idx;
1184
1185         idx = TX_CONS(txq);
1186         mbuf = txq->sw_tx_ring[idx].mbuf;
1187         if (mbuf) {
1188                 nb_segs = mbuf->nb_segs;
1189                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
1190                 while (nb_segs) {
1191                         /* It's like consuming rxbuf in recv() */
1192                         ecore_chain_consume(&txq->tx_pbl);
1193                         txq->nb_tx_avail++;
1194                         nb_segs--;
1195                 }
1196                 rte_pktmbuf_free(mbuf);
1197                 txq->sw_tx_ring[idx].mbuf = NULL;
1198                 txq->sw_tx_cons++;
1199                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
1200         } else {
1201                 ecore_chain_consume(&txq->tx_pbl);
1202                 txq->nb_tx_avail++;
1203         }
1204 }
1205
1206 static inline void
1207 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
1208                       struct qede_tx_queue *txq)
1209 {
1210         uint16_t hw_bd_cons;
1211 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1212         uint16_t sw_tx_cons;
1213 #endif
1214
1215         rte_compiler_barrier();
1216         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1217 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1218         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
1219         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
1220                    abs(hw_bd_cons - sw_tx_cons));
1221 #endif
1222         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
1223                 qede_free_tx_pkt(txq);
1224 }
1225
1226 /* Populate scatter gather buffer descriptor fields */
1227 static inline uint8_t
1228 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1229                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1230 {
1231         struct qede_tx_queue *txq = p_txq;
1232         struct eth_tx_bd *tx_bd = NULL;
1233         dma_addr_t mapping;
1234         uint8_t nb_segs = 0;
1235
1236         /* Check for scattered buffers */
1237         while (m_seg) {
1238                 if (nb_segs == 0) {
1239                         if (!*bd2) {
1240                                 *bd2 = (struct eth_tx_2nd_bd *)
1241                                         ecore_chain_produce(&txq->tx_pbl);
1242                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1243                                 nb_segs++;
1244                         }
1245                         mapping = rte_mbuf_data_dma_addr(m_seg);
1246                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1247                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1248                 } else if (nb_segs == 1) {
1249                         if (!*bd3) {
1250                                 *bd3 = (struct eth_tx_3rd_bd *)
1251                                         ecore_chain_produce(&txq->tx_pbl);
1252                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1253                                 nb_segs++;
1254                         }
1255                         mapping = rte_mbuf_data_dma_addr(m_seg);
1256                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1257                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1258                 } else {
1259                         tx_bd = (struct eth_tx_bd *)
1260                                 ecore_chain_produce(&txq->tx_pbl);
1261                         memset(tx_bd, 0, sizeof(*tx_bd));
1262                         nb_segs++;
1263                         mapping = rte_mbuf_data_dma_addr(m_seg);
1264                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1265                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1266                 }
1267                 m_seg = m_seg->next;
1268         }
1269
1270         /* Return total scattered buffers */
1271         return nb_segs;
1272 }
1273
1274 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1275 static inline void
1276 print_tx_bd_info(struct qede_tx_queue *txq,
1277                  struct eth_tx_1st_bd *bd1,
1278                  struct eth_tx_2nd_bd *bd2,
1279                  struct eth_tx_3rd_bd *bd3,
1280                  uint64_t tx_ol_flags)
1281 {
1282         char ol_buf[256] = { 0 }; /* for verbose prints */
1283
1284         if (bd1)
1285                 PMD_TX_LOG(INFO, txq,
1286                            "BD1: nbytes=%u nbds=%u bd_flags=04%x bf=%04x",
1287                            rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1288                            bd1->data.bd_flags.bitfields,
1289                            rte_cpu_to_le_16(bd1->data.bitfields));
1290         if (bd2)
1291                 PMD_TX_LOG(INFO, txq,
1292                            "BD2: nbytes=%u bf=%04x\n",
1293                            rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1294         if (bd3)
1295                 PMD_TX_LOG(INFO, txq,
1296                            "BD3: nbytes=%u bf=%04x mss=%u\n",
1297                            rte_cpu_to_le_16(bd3->nbytes),
1298                            rte_cpu_to_le_16(bd3->data.bitfields),
1299                            rte_cpu_to_le_16(bd3->data.lso_mss));
1300
1301         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1302         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1303 }
1304 #endif
1305
1306 /* TX prepare to check packets meets TX conditions */
1307 uint16_t
1308 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1309 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1310                     uint16_t nb_pkts)
1311 {
1312         struct qede_tx_queue *txq = p_txq;
1313 #else
1314 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1315                     uint16_t nb_pkts)
1316 {
1317 #endif
1318         uint64_t ol_flags;
1319         struct rte_mbuf *m;
1320         uint16_t i;
1321         int ret;
1322
1323         for (i = 0; i < nb_pkts; i++) {
1324                 m = tx_pkts[i];
1325                 ol_flags = m->ol_flags;
1326                 if (ol_flags & PKT_TX_TCP_SEG) {
1327                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1328                                 rte_errno = -EINVAL;
1329                                 break;
1330                         }
1331                         /* TBD: confirm its ~9700B for both ? */
1332                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1333                                 rte_errno = -EINVAL;
1334                                 break;
1335                         }
1336                 } else {
1337                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1338                                 rte_errno = -EINVAL;
1339                                 break;
1340                         }
1341                 }
1342                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1343                         rte_errno = -ENOTSUP;
1344                         break;
1345                 }
1346
1347 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1348                 ret = rte_validate_tx_offload(m);
1349                 if (ret != 0) {
1350                         rte_errno = ret;
1351                         break;
1352                 }
1353 #endif
1354                 /* TBD: pseudo csum calcuation required iff
1355                  * ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE not set?
1356                  */
1357                 ret = rte_net_intel_cksum_prepare(m);
1358                 if (ret != 0) {
1359                         rte_errno = ret;
1360                         break;
1361                 }
1362         }
1363
1364 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1365         if (unlikely(i != nb_pkts))
1366                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1367                            nb_pkts - i);
1368 #endif
1369         return i;
1370 }
1371
1372 uint16_t
1373 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1374 {
1375         struct qede_tx_queue *txq = p_txq;
1376         struct qede_dev *qdev = txq->qdev;
1377         struct ecore_dev *edev = &qdev->edev;
1378         struct rte_mbuf *mbuf;
1379         struct rte_mbuf *m_seg = NULL;
1380         uint16_t nb_tx_pkts;
1381         uint16_t bd_prod;
1382         uint16_t idx;
1383         uint16_t nb_frags;
1384         uint16_t nb_pkt_sent = 0;
1385         uint8_t nbds;
1386         bool ipv6_ext_flg;
1387         bool lso_flg;
1388         bool tunn_flg;
1389         struct eth_tx_1st_bd *bd1;
1390         struct eth_tx_2nd_bd *bd2;
1391         struct eth_tx_3rd_bd *bd3;
1392         uint64_t tx_ol_flags;
1393         uint16_t hdr_size;
1394
1395         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1396                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1397                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1398                 qede_process_tx_compl(edev, txq);
1399         }
1400
1401         nb_tx_pkts  = nb_pkts;
1402         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1403         while (nb_tx_pkts--) {
1404                 /* Init flags/values */
1405                 ipv6_ext_flg = false;
1406                 tunn_flg = false;
1407                 lso_flg = false;
1408                 nbds = 0;
1409                 bd1 = NULL;
1410                 bd2 = NULL;
1411                 bd3 = NULL;
1412                 hdr_size = 0;
1413
1414                 mbuf = *tx_pkts++;
1415                 assert(mbuf);
1416
1417                 /* Check minimum TX BDS availability against available BDs */
1418                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1419                         break;
1420
1421                 tx_ol_flags = mbuf->ol_flags;
1422
1423 #define RTE_ETH_IS_IPV6_HDR_EXT(ptype) ((ptype) & RTE_PTYPE_L3_IPV6_EXT)
1424                 if (RTE_ETH_IS_IPV6_HDR_EXT(mbuf->packet_type))
1425                         ipv6_ext_flg = true;
1426
1427                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type))
1428                         tunn_flg = true;
1429
1430                 if (tx_ol_flags & PKT_TX_TCP_SEG)
1431                         lso_flg = true;
1432
1433                 if (lso_flg) {
1434                         if (unlikely(txq->nb_tx_avail <
1435                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1436                                 break;
1437                 } else {
1438                         if (unlikely(txq->nb_tx_avail <
1439                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1440                                 break;
1441                 }
1442
1443                 if (tunn_flg && ipv6_ext_flg) {
1444                         if (unlikely(txq->nb_tx_avail <
1445                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1446                                 break;
1447                 }
1448                 if (ipv6_ext_flg) {
1449                         if (unlikely(txq->nb_tx_avail <
1450                                         ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT))
1451                                 break;
1452                 }
1453
1454                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1455                 idx = TX_PROD(txq);
1456                 txq->sw_tx_ring[idx].mbuf = mbuf;
1457
1458                 /* BD1 */
1459                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1460                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1461                 nbds++;
1462
1463                 bd1->data.bd_flags.bitfields |=
1464                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1465                 /* FW 8.10.x specific change */
1466                 if (!lso_flg) {
1467                         bd1->data.bitfields |=
1468                         (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1469                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1470                         /* Map MBUF linear data for DMA and set in the BD1 */
1471                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1472                                              mbuf->data_len);
1473                 } else {
1474                         /* For LSO, packet header and payload must reside on
1475                          * buffers pointed by different BDs. Using BD1 for HDR
1476                          * and BD2 onwards for data.
1477                          */
1478                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1479                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1480                                              hdr_size);
1481                 }
1482
1483                 if (tunn_flg) {
1484                         /* First indicate its a tunnel pkt */
1485                         bd1->data.bd_flags.bitfields |=
1486                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1487                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1488
1489                         /* Legacy FW had flipped behavior in regard to this bit
1490                          * i.e. it needed to set to prevent FW from touching
1491                          * encapsulated packets when it didn't need to.
1492                          */
1493                         if (unlikely(txq->is_legacy))
1494                                 bd1->data.bitfields ^=
1495                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1496
1497                         /* Outer IP checksum offload */
1498                         if (tx_ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1499                                 bd1->data.bd_flags.bitfields |=
1500                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1501                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1502                         }
1503
1504                         /* Outer UDP checksum offload */
1505                         bd1->data.bd_flags.bitfields |=
1506                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1507                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1508                 }
1509
1510                 /* Descriptor based VLAN insertion */
1511                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1512                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1513                         bd1->data.bd_flags.bitfields |=
1514                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1515                 }
1516
1517                 if (lso_flg)
1518                         bd1->data.bd_flags.bitfields |=
1519                                 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1520
1521                 /* Offload the IP checksum in the hardware */
1522                 if ((lso_flg) || (tx_ol_flags & PKT_TX_IP_CKSUM))
1523                         bd1->data.bd_flags.bitfields |=
1524                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1525
1526                 /* L4 checksum offload (tcp or udp) */
1527                 if ((lso_flg) || (tx_ol_flags & (PKT_TX_TCP_CKSUM |
1528                                                 PKT_TX_UDP_CKSUM)))
1529                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1530                         bd1->data.bd_flags.bitfields |=
1531                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1532
1533                 /* BD2 */
1534                 if (lso_flg || ipv6_ext_flg) {
1535                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1536                                                         (&txq->tx_pbl);
1537                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1538                         nbds++;
1539                         QEDE_BD_SET_ADDR_LEN(bd2,
1540                                             (hdr_size +
1541                                             rte_mbuf_data_dma_addr(mbuf)),
1542                                             mbuf->data_len - hdr_size);
1543                         /* TBD: check pseudo csum iff tx_prepare not called? */
1544                         if (ipv6_ext_flg) {
1545                                 bd2->data.bitfields1 |=
1546                                 ETH_L4_PSEUDO_CSUM_ZERO_LENGTH <<
1547                                 ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1548                         }
1549                 }
1550
1551                 /* BD3 */
1552                 if (lso_flg || ipv6_ext_flg) {
1553                         bd3 = (struct eth_tx_3rd_bd *)ecore_chain_produce
1554                                                         (&txq->tx_pbl);
1555                         memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
1556                         nbds++;
1557                         if (lso_flg) {
1558                                 bd3->data.lso_mss =
1559                                         rte_cpu_to_le_16(mbuf->tso_segsz);
1560                                 /* Using one header BD */
1561                                 bd3->data.bitfields |=
1562                                         rte_cpu_to_le_16(1 <<
1563                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1564                         }
1565                 }
1566
1567                 /* Handle fragmented MBUF */
1568                 m_seg = mbuf->next;
1569                 /* Encode scatter gather buffer descriptors if required */
1570                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
1571                 bd1->data.nbds = nbds + nb_frags;
1572                 txq->nb_tx_avail -= bd1->data.nbds;
1573                 txq->sw_tx_prod++;
1574                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1575                 bd_prod =
1576                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1577 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1578                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
1579                 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d ipv6_ext=%d\n",
1580                            lso_flg, tunn_flg, ipv6_ext_flg);
1581 #endif
1582                 nb_pkt_sent++;
1583                 txq->xmit_pkts++;
1584         }
1585
1586         /* Write value of prod idx into bd_prod */
1587         txq->tx_db.data.bd_prod = bd_prod;
1588         rte_wmb();
1589         rte_compiler_barrier();
1590         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1591         rte_wmb();
1592
1593         /* Check again for Tx completions */
1594         qede_process_tx_compl(edev, txq);
1595
1596         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
1597                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
1598
1599         return nb_pkt_sent;
1600 }
1601
1602 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1603 {
1604         struct qede_dev *qdev = eth_dev->data->dev_private;
1605         struct qede_fastpath *fp;
1606         uint8_t i, txq_index, tc;
1607         int rxq = 0, txq = 0;
1608
1609         for_each_queue(i) {
1610                 fp = &qdev->fp_array[i];
1611                 if (fp->type & QEDE_FASTPATH_RX) {
1612                         fp->rxq = eth_dev->data->rx_queues[i];
1613                         fp->rxq->queue_id = rxq++;
1614                 }
1615
1616                 if (fp->type & QEDE_FASTPATH_TX) {
1617                         for (tc = 0; tc < qdev->num_tc; tc++) {
1618                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1619                                 fp->txqs[tc] =
1620                                         eth_dev->data->tx_queues[txq_index];
1621                                 fp->txqs[tc]->queue_id = txq_index;
1622                                 if (qdev->dev_info.is_legacy)
1623                                         fp->txqs[tc]->is_legacy = true;
1624                         }
1625                         txq++;
1626                 }
1627         }
1628 }
1629
1630 int qede_dev_start(struct rte_eth_dev *eth_dev)
1631 {
1632         struct qede_dev *qdev = eth_dev->data->dev_private;
1633         struct ecore_dev *edev = &qdev->edev;
1634         int rc;
1635
1636         DP_INFO(edev, "Device state is %d\n", qdev->state);
1637
1638         if (qdev->state == QEDE_DEV_START) {
1639                 DP_INFO(edev, "Port is already started\n");
1640                 return 0;
1641         }
1642
1643         if (qdev->state == QEDE_DEV_CONFIG)
1644                 qede_init_fp_queue(eth_dev);
1645
1646         /* Update MTU only if it has changed */
1647         if (qdev->mtu != qdev->new_mtu) {
1648                 if (qede_update_mtu(eth_dev, qdev->new_mtu))
1649                         return -1;
1650                 qdev->mtu = qdev->new_mtu;
1651                 /* If MTU has changed then update TPA too */
1652                 if (qdev->enable_lro)
1653                         if (qede_enable_tpa(eth_dev, true))
1654                                 return -1;
1655         }
1656
1657         rc = qede_start_queues(eth_dev);
1658         if (rc) {
1659                 DP_ERR(edev, "Failed to start queues\n");
1660                 /* TBD: free */
1661                 return rc;
1662         }
1663
1664         /* Newer SR-IOV PF driver expects RX/TX queues to be started before
1665          * enabling RSS. Hence RSS configuration is deferred upto this point.
1666          * Also, we would like to retain similar behavior in PF case, so we
1667          * don't do PF/VF specific check here.
1668          */
1669         if (eth_dev->data->dev_conf.rxmode.mq_mode  == ETH_MQ_RX_RSS)
1670                 if (qede_config_rss(eth_dev))
1671                         return -1;
1672
1673         /* Enable vport*/
1674         if (qede_activate_vport(eth_dev, true))
1675                 return -1;
1676
1677         /* Bring-up the link */
1678         qede_dev_set_link_state(eth_dev, true);
1679
1680         /* Start/resume traffic */
1681         qdev->ops->fastpath_start(edev);
1682
1683         qdev->state = QEDE_DEV_START;
1684
1685         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1686
1687         return 0;
1688 }
1689
1690 static int qede_drain_txq(struct qede_dev *qdev,
1691                           struct qede_tx_queue *txq, bool allow_drain)
1692 {
1693         struct ecore_dev *edev = &qdev->edev;
1694         int rc, cnt = 1000;
1695
1696         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1697                 qede_process_tx_compl(edev, txq);
1698                 if (!cnt) {
1699                         if (allow_drain) {
1700                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
1701                                           "requesting MCP to drain\n",
1702                                           txq->queue_id);
1703                                 rc = qdev->ops->common->drain(edev);
1704                                 if (rc)
1705                                         return rc;
1706                                 return qede_drain_txq(qdev, txq, false);
1707                         }
1708                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
1709                                   "PROD=%d, CONS=%d\n",
1710                                   txq->queue_id, txq->sw_tx_prod,
1711                                   txq->sw_tx_cons);
1712                         return -1;
1713                 }
1714                 cnt--;
1715                 DELAY(1000);
1716                 rte_compiler_barrier();
1717         }
1718
1719         /* FW finished processing, wait for HW to transmit all tx packets */
1720         DELAY(2000);
1721
1722         return 0;
1723 }
1724
1725 static int qede_stop_queues(struct qede_dev *qdev)
1726 {
1727         struct ecore_dev *edev = &qdev->edev;
1728         struct qede_fastpath *fp;
1729         int rc, tc, i;
1730
1731         DP_INFO(edev, "Flushing tx queues\n");
1732
1733         /* Flush Tx queues. If needed, request drain from MCP */
1734         for_each_queue(i) {
1735                 fp = &qdev->fp_array[i];
1736
1737                 if (fp->type & QEDE_FASTPATH_TX) {
1738                         for (tc = 0; tc < qdev->num_tc; tc++) {
1739                                 struct qede_tx_queue *txq = fp->txqs[tc];
1740
1741                                 rc = qede_drain_txq(qdev, txq, true);
1742                                 if (rc)
1743                                         return rc;
1744                         }
1745                 }
1746         }
1747
1748         /* Stop all Queues in reverse order */
1749         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1750                 fp = &qdev->fp_array[i];
1751
1752                 /* Stop the Tx Queue(s) */
1753                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1754                         for (tc = 0; tc < qdev->num_tc; tc++) {
1755                                 struct qede_tx_queue *txq = fp->txqs[tc];
1756                                 DP_INFO(edev, "Stopping tx queues\n");
1757                                 rc = qdev->ops->q_tx_stop(edev, i, txq->handle);
1758                                 if (rc) {
1759                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1760                                                i);
1761                                         return rc;
1762                                 }
1763                         }
1764                 }
1765
1766                 /* Stop the Rx Queue */
1767                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1768                         DP_INFO(edev, "Stopping rx queues\n");
1769                         rc = qdev->ops->q_rx_stop(edev, i, fp->rxq->handle);
1770                         if (rc) {
1771                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1772                                 return rc;
1773                         }
1774                 }
1775         }
1776         qede_reset_fp_rings(qdev);
1777
1778         return 0;
1779 }
1780
1781 int qede_reset_fp_rings(struct qede_dev *qdev)
1782 {
1783         struct qede_fastpath *fp;
1784         struct qede_tx_queue *txq;
1785         uint8_t tc;
1786         uint16_t id, i;
1787
1788         for_each_queue(id) {
1789                 fp = &qdev->fp_array[id];
1790
1791                 if (fp->type & QEDE_FASTPATH_RX) {
1792                         DP_INFO(&qdev->edev,
1793                                 "Reset FP chain for RSS %u\n", id);
1794                         qede_rx_queue_release_mbufs(fp->rxq);
1795                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1796                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1797                         fp->rxq->sw_rx_prod = 0;
1798                         fp->rxq->sw_rx_cons = 0;
1799                         *fp->rxq->hw_cons_ptr = 0;
1800                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1801                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1802                                         DP_ERR(&qdev->edev,
1803                                                "RX buffer allocation failed\n");
1804                                         return -ENOMEM;
1805                                 }
1806                         }
1807                 }
1808                 if (fp->type & QEDE_FASTPATH_TX) {
1809                         for (tc = 0; tc < qdev->num_tc; tc++) {
1810                                 txq = fp->txqs[tc];
1811                                 qede_tx_queue_release_mbufs(txq);
1812                                 ecore_chain_reset(&txq->tx_pbl);
1813                                 txq->sw_tx_cons = 0;
1814                                 txq->sw_tx_prod = 0;
1815                                 *txq->hw_cons_ptr = 0;
1816                         }
1817                 }
1818         }
1819
1820         return 0;
1821 }
1822
1823 /* This function frees all memory of a single fp */
1824 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1825 {
1826         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1827         struct qede_fastpath *fp;
1828         uint16_t txq_idx;
1829         uint8_t id;
1830         uint8_t tc;
1831
1832         for_each_queue(id) {
1833                 fp = &qdev->fp_array[id];
1834                 if (fp->type & QEDE_FASTPATH_RX) {
1835                         if (!fp->rxq)
1836                                 continue;
1837                         qede_rx_queue_release(fp->rxq);
1838                         eth_dev->data->rx_queues[id] = NULL;
1839                 } else {
1840                         for (tc = 0; tc < qdev->num_tc; tc++) {
1841                                 if (!fp->txqs[tc])
1842                                         continue;
1843                                 txq_idx = fp->txqs[tc]->queue_id;
1844                                 qede_tx_queue_release(fp->txqs[tc]);
1845                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1846                         }
1847                 }
1848         }
1849 }
1850
1851 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1852 {
1853         struct qede_dev *qdev = eth_dev->data->dev_private;
1854         struct ecore_dev *edev = &qdev->edev;
1855
1856         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1857
1858         if (qdev->state != QEDE_DEV_START) {
1859                 DP_INFO(edev, "Device not yet started\n");
1860                 return;
1861         }
1862
1863         /* Disable vport */
1864         if (qede_activate_vport(eth_dev, false))
1865                 return;
1866
1867         if (qede_stop_queues(qdev))
1868                 DP_ERR(edev, "Didn't succeed to close queues\n");
1869
1870         DP_INFO(edev, "Stopped queues\n");
1871
1872         qdev->ops->fastpath_stop(edev);
1873
1874         /* Bring the link down */
1875         qede_dev_set_link_state(eth_dev, false);
1876
1877         qdev->state = QEDE_DEV_STOP;
1878
1879         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1880 }
1881
1882 uint16_t
1883 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
1884                      __rte_unused struct rte_mbuf **pkts,
1885                      __rte_unused uint16_t nb_pkts)
1886 {
1887         return 0;
1888 }