drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include <rte_net.h>
  10 #include "qede_rxtx.h"
  11
  12 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  13 {
  14         struct rte_mbuf *new_mb = NULL;
  15         struct eth_rx_bd *rx_bd;
  16         dma_addr_t mapping;
  17         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  18
  19         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  20         if (unlikely(!new_mb)) {
  21                 PMD_RX_LOG(ERR, rxq,
  22                            "Failed to allocate rx buffer "
  23                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  24                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  25                            rte_mempool_avail_count(rxq->mb_pool),
  26                            rte_mempool_in_use_count(rxq->mb_pool));
  27                 return -ENOMEM;
  28         }
  29         rxq->sw_rx_ring[idx].mbuf = new_mb;
  30         rxq->sw_rx_ring[idx].page_offset = 0;
  31         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  32         /* Advance PROD and get BD pointer */
  33         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  34         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  35         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  36         rxq->sw_rx_prod++;
  37         return 0;
  38 }
  39
  40 int
  41 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  42                     uint16_t nb_desc, unsigned int socket_id,
  43                     __rte_unused const struct rte_eth_rxconf *rx_conf,
  44                     struct rte_mempool *mp)
  45 {
  46         struct qede_dev *qdev = QEDE_INIT_QDEV(dev);
  47         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
  48         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
  49         struct qede_rx_queue *rxq;
  50         uint16_t max_rx_pkt_len;
  51         uint16_t bufsz;
  52         size_t size;
  53         int rc;
  54
  55         PMD_INIT_FUNC_TRACE(edev);
  56
  57         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
  58         if (!rte_is_power_of_2(nb_desc)) {
  59                 DP_ERR(edev, "Ring size %u is not power of 2\n",
  60                           nb_desc);
  61                 return -EINVAL;
  62         }
  63
  64         /* Free memory prior to re-allocation if needed... */
  65         if (dev->data->rx_queues[queue_idx] != NULL) {
  66                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
  67                 dev->data->rx_queues[queue_idx] = NULL;
  68         }
  69
  70         /* First allocate the rx queue data structure */
  71         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
  72                                  RTE_CACHE_LINE_SIZE, socket_id);
  73
  74         if (!rxq) {
  75                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
  76                           socket_id);
  77                 return -ENOMEM;
  78         }
  79
  80         rxq->qdev = qdev;
  81         rxq->mb_pool = mp;
  82         rxq->nb_rx_desc = nb_desc;
  83         rxq->queue_id = queue_idx;
  84         rxq->port_id = dev->data->port_id;
  85         max_rx_pkt_len = (uint16_t)rxmode->max_rx_pkt_len;
  86         qdev->mtu = max_rx_pkt_len;
  87
  88         /* Fix up RX buffer size */
  89         bufsz = (uint16_t)rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM;
  90         if ((rxmode->enable_scatter)                    ||
  91             (max_rx_pkt_len + QEDE_ETH_OVERHEAD) > bufsz) {
  92                 if (!dev->data->scattered_rx) {
  93                         DP_INFO(edev, "Forcing scatter-gather mode\n");
  94                         dev->data->scattered_rx = 1;
  95                 }
  96         }
  97         if (dev->data->scattered_rx)
  98                 rxq->rx_buf_size = bufsz + QEDE_ETH_OVERHEAD;
  99         else
 100                 rxq->rx_buf_size = qdev->mtu + QEDE_ETH_OVERHEAD;
 101         /* Align to cache-line size if needed */
 102         rxq->rx_buf_size = QEDE_CEIL_TO_CACHE_LINE_SIZE(rxq->rx_buf_size);
 103
 104         DP_INFO(edev, "mtu %u mbufsz %u bd_max_bytes %u scatter_mode %d\n",
 105                 qdev->mtu, bufsz, rxq->rx_buf_size, dev->data->scattered_rx);
 106
 107         /* Allocate the parallel driver ring for Rx buffers */
 108         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 109         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 110                                              RTE_CACHE_LINE_SIZE, socket_id);
 111         if (!rxq->sw_rx_ring) {
 112                 DP_NOTICE(edev, false,
 113                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 114                           socket_id);
 115                 rte_free(rxq);
 116                 return -ENOMEM;
 117         }
 118
 119         /* Allocate FW Rx ring  */
 120         rc = qdev->ops->common->chain_alloc(edev,
 121                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 122                                             ECORE_CHAIN_MODE_NEXT_PTR,
 123                                             ECORE_CHAIN_CNT_TYPE_U16,
 124                                             rxq->nb_rx_desc,
 125                                             sizeof(struct eth_rx_bd),
 126                                             &rxq->rx_bd_ring,
 127                                             NULL);
 128
 129         if (rc != ECORE_SUCCESS) {
 130                 DP_NOTICE(edev, false,
 131                           "Unable to alloc memory for rxbd ring on socket %u\n",
 132                           socket_id);
 133                 rte_free(rxq->sw_rx_ring);
 134                 rte_free(rxq);
 135                 return -ENOMEM;
 136         }
 137
 138         /* Allocate FW completion ring */
 139         rc = qdev->ops->common->chain_alloc(edev,
 140                                             ECORE_CHAIN_USE_TO_CONSUME,
 141                                             ECORE_CHAIN_MODE_PBL,
 142                                             ECORE_CHAIN_CNT_TYPE_U16,
 143                                             rxq->nb_rx_desc,
 144                                             sizeof(union eth_rx_cqe),
 145                                             &rxq->rx_comp_ring,
 146                                             NULL);
 147
 148         if (rc != ECORE_SUCCESS) {
 149                 DP_NOTICE(edev, false,
 150                           "Unable to alloc memory for cqe ring on socket %u\n",
 151                           socket_id);
 152                 qdev->ops->common->chain_free(edev, &rxq->rx_bd_ring);
 153                 rte_free(rxq->sw_rx_ring);
 154                 rte_free(rxq);
 155                 return -ENOMEM;
 156         }
 157
 158         dev->data->rx_queues[queue_idx] = rxq;
 159         qdev->fp_array[queue_idx].rxq = rxq;
 160
 161         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 162                   queue_idx, nb_desc, qdev->mtu, socket_id);
 163
 164         return 0;
 165 }
 166
 167 static void
 168 qede_rx_queue_reset(__rte_unused struct qede_dev *qdev,
 169                     struct qede_rx_queue *rxq)
 170 {
 171         DP_INFO(&qdev->edev, "Reset RX queue %u\n", rxq->queue_id);
 172         ecore_chain_reset(&rxq->rx_bd_ring);
 173         ecore_chain_reset(&rxq->rx_comp_ring);
 174         rxq->sw_rx_prod = 0;
 175         rxq->sw_rx_cons = 0;
 176         *rxq->hw_cons_ptr = 0;
 177 }
 178
 179 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
 180 {
 181         uint16_t i;
 182
 183         if (rxq->sw_rx_ring) {
 184                 for (i = 0; i < rxq->nb_rx_desc; i++) {
 185                         if (rxq->sw_rx_ring[i].mbuf) {
 186                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
 187                                 rxq->sw_rx_ring[i].mbuf = NULL;
 188                         }
 189                 }
 190         }
 191 }
 192
 193 void qede_rx_queue_release(void *rx_queue)
 194 {
 195         struct qede_rx_queue *rxq = rx_queue;
 196
 197         if (rxq) {
 198                 qede_rx_queue_release_mbufs(rxq);
 199                 rte_free(rxq->sw_rx_ring);
 200                 rte_free(rxq);
 201         }
 202 }
 203
 204 /* Stops a given RX queue in the HW */
 205 static int qede_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 206 {
 207         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 208         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 209         struct ecore_hwfn *p_hwfn;
 210         struct qede_rx_queue *rxq;
 211         int hwfn_index;
 212         int rc;
 213
 214         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 215                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 216                 hwfn_index = rx_queue_id % edev->num_hwfns;
 217                 p_hwfn = &edev->hwfns[hwfn_index];
 218                 rc = ecore_eth_rx_queue_stop(p_hwfn, rxq->handle,
 219                                 true, false);
 220                 if (rc != ECORE_SUCCESS) {
 221                         DP_ERR(edev, "RX queue %u stop fails\n", rx_queue_id);
 222                         return -1;
 223                 }
 224                 qede_rx_queue_release_mbufs(rxq);
 225                 qede_rx_queue_reset(qdev, rxq);
 226                 eth_dev->data->rx_queue_state[rx_queue_id] =
 227                         RTE_ETH_QUEUE_STATE_STOPPED;
 228                 DP_INFO(edev, "RX queue %u stopped\n", rx_queue_id);
 229         } else {
 230                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 231                 rc = -EINVAL;
 232         }
 233
 234         return rc;
 235 }
 236
 237 int
 238 qede_tx_queue_setup(struct rte_eth_dev *dev,
 239                     uint16_t queue_idx,
 240                     uint16_t nb_desc,
 241                     unsigned int socket_id,
 242                     const struct rte_eth_txconf *tx_conf)
 243 {
 244         struct qede_dev *qdev = dev->data->dev_private;
 245         struct ecore_dev *edev = &qdev->edev;
 246         struct qede_tx_queue *txq;
 247         int rc;
 248
 249         PMD_INIT_FUNC_TRACE(edev);
 250
 251         if (!rte_is_power_of_2(nb_desc)) {
 252                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 253                        nb_desc);
 254                 return -EINVAL;
 255         }
 256
 257         /* Free memory prior to re-allocation if needed... */
 258         if (dev->data->tx_queues[queue_idx] != NULL) {
 259                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 260                 dev->data->tx_queues[queue_idx] = NULL;
 261         }
 262
 263         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 264                                  RTE_CACHE_LINE_SIZE, socket_id);
 265
 266         if (txq == NULL) {
 267                 DP_ERR(edev,
 268                        "Unable to allocate memory for txq on socket %u",
 269                        socket_id);
 270                 return -ENOMEM;
 271         }
 272
 273         txq->nb_tx_desc = nb_desc;
 274         txq->qdev = qdev;
 275         txq->port_id = dev->data->port_id;
 276
 277         rc = qdev->ops->common->chain_alloc(edev,
 278                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 279                                             ECORE_CHAIN_MODE_PBL,
 280                                             ECORE_CHAIN_CNT_TYPE_U16,
 281                                             txq->nb_tx_desc,
 282                                             sizeof(union eth_tx_bd_types),
 283                                             &txq->tx_pbl,
 284                                             NULL);
 285         if (rc != ECORE_SUCCESS) {
 286                 DP_ERR(edev,
 287                        "Unable to allocate memory for txbd ring on socket %u",
 288                        socket_id);
 289                 qede_tx_queue_release(txq);
 290                 return -ENOMEM;
 291         }
 292
 293         /* Allocate software ring */
 294         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 295                                              (sizeof(struct qede_tx_entry) *
 296                                               txq->nb_tx_desc),
 297                                              RTE_CACHE_LINE_SIZE, socket_id);
 298
 299         if (!txq->sw_tx_ring) {
 300                 DP_ERR(edev,
 301                        "Unable to allocate memory for txbd ring on socket %u",
 302                        socket_id);
 303                 qdev->ops->common->chain_free(edev, &txq->tx_pbl);
 304                 qede_tx_queue_release(txq);
 305                 return -ENOMEM;
 306         }
 307
 308         txq->queue_id = queue_idx;
 309
 310         txq->nb_tx_avail = txq->nb_tx_desc;
 311
 312         txq->tx_free_thresh =
 313             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 314             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 315
 316         dev->data->tx_queues[queue_idx] = txq;
 317         qdev->fp_array[queue_idx].txq = txq;
 318
 319         DP_INFO(edev,
 320                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 321                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 322
 323         return 0;
 324 }
 325
 326 static void
 327 qede_tx_queue_reset(__rte_unused struct qede_dev *qdev,
 328                     struct qede_tx_queue *txq)
 329 {
 330         DP_INFO(&qdev->edev, "Reset TX queue %u\n", txq->queue_id);
 331         ecore_chain_reset(&txq->tx_pbl);
 332         txq->sw_tx_cons = 0;
 333         txq->sw_tx_prod = 0;
 334         *txq->hw_cons_ptr = 0;
 335 }
 336
 337 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
 338 {
 339         uint16_t i;
 340
 341         if (txq->sw_tx_ring) {
 342                 for (i = 0; i < txq->nb_tx_desc; i++) {
 343                         if (txq->sw_tx_ring[i].mbuf) {
 344                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
 345                                 txq->sw_tx_ring[i].mbuf = NULL;
 346                         }
 347                 }
 348         }
 349 }
 350
 351 void qede_tx_queue_release(void *tx_queue)
 352 {
 353         struct qede_tx_queue *txq = tx_queue;
 354
 355         if (txq) {
 356                 qede_tx_queue_release_mbufs(txq);
 357                 rte_free(txq->sw_tx_ring);
 358                 rte_free(txq);
 359         }
 360 }
 361
 362 /* This function allocates fast-path status block memory */
 363 static int
 364 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 365                   uint16_t sb_id)
 366 {
 367         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 368         struct status_block *sb_virt;
 369         dma_addr_t sb_phys;
 370         int rc;
 371
 372         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
 373                                           sizeof(struct status_block));
 374         if (!sb_virt) {
 375                 DP_ERR(edev, "Status block allocation failed\n");
 376                 return -ENOMEM;
 377         }
 378         rc = qdev->ops->common->sb_init(edev, sb_info, sb_virt,
 379                                         sb_phys, sb_id);
 380         if (rc) {
 381                 DP_ERR(edev, "Status block initialization failed\n");
 382                 OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
 383                                        sizeof(struct status_block));
 384                 return rc;
 385         }
 386
 387         return 0;
 388 }
 389
 390 int qede_alloc_fp_resc(struct qede_dev *qdev)
 391 {
 392         struct ecore_dev *edev = &qdev->edev;
 393         struct qede_fastpath *fp;
 394         uint32_t num_sbs;
 395         uint16_t sb_idx;
 396
 397         if (IS_VF(edev))
 398                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 399         else
 400                 num_sbs = ecore_cxt_get_proto_cid_count
 401                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL);
 402
 403         if (num_sbs == 0) {
 404                 DP_ERR(edev, "No status blocks available\n");
 405                 return -EINVAL;
 406         }
 407
 408         qdev->fp_array = rte_calloc("fp", QEDE_RXTX_MAX(qdev),
 409                                 sizeof(*qdev->fp_array), RTE_CACHE_LINE_SIZE);
 410
 411         if (!qdev->fp_array) {
 412                 DP_ERR(edev, "fp array allocation failed\n");
 413                 return -ENOMEM;
 414         }
 415
 416         memset((void *)qdev->fp_array, 0, QEDE_RXTX_MAX(qdev) *
 417                         sizeof(*qdev->fp_array));
 418
 419         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 420                 fp = &qdev->fp_array[sb_idx];
 421                 fp->sb_info = rte_calloc("sb", 1, sizeof(struct ecore_sb_info),
 422                                 RTE_CACHE_LINE_SIZE);
 423                 if (!fp->sb_info) {
 424                         DP_ERR(edev, "FP sb_info allocation fails\n");
 425                         return -1;
 426                 }
 427                 if (qede_alloc_mem_sb(qdev, fp->sb_info, sb_idx)) {
 428                         DP_ERR(edev, "FP status block allocation fails\n");
 429                         return -1;
 430                 }
 431                 DP_INFO(edev, "sb_info idx 0x%x initialized\n",
 432                                 fp->sb_info->igu_sb_id);
 433         }
 434
 435         return 0;
 436 }
 437
 438 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 439 {
 440         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 441         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 442         struct qede_fastpath *fp;
 443         struct qede_rx_queue *rxq;
 444         struct qede_tx_queue *txq;
 445         uint16_t sb_idx;
 446         uint8_t i;
 447
 448         PMD_INIT_FUNC_TRACE(edev);
 449
 450         for (sb_idx = 0; sb_idx < QEDE_RXTX_MAX(qdev); sb_idx++) {
 451                 fp = &qdev->fp_array[sb_idx];
 452                 DP_INFO(edev, "Free sb_info index 0x%x\n",
 453                                 fp->sb_info->igu_sb_id);
 454                 if (fp->sb_info) {
 455                         OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
 456                                 fp->sb_info->sb_phys,
 457                                 sizeof(struct status_block));
 458                         rte_free(fp->sb_info);
 459                         fp->sb_info = NULL;
 460                 }
 461         }
 462
 463         /* Free packet buffers and ring memories */
 464         for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
 465                 if (eth_dev->data->rx_queues[i]) {
 466                         qede_rx_queue_release(eth_dev->data->rx_queues[i]);
 467                         rxq = eth_dev->data->rx_queues[i];
 468                         qdev->ops->common->chain_free(edev,
 469                                                       &rxq->rx_bd_ring);
 470                         qdev->ops->common->chain_free(edev,
 471                                                       &rxq->rx_comp_ring);
 472                         eth_dev->data->rx_queues[i] = NULL;
 473                 }
 474         }
 475
 476         for (i = 0; i < eth_dev->data->nb_tx_queues; i++) {
 477                 if (eth_dev->data->tx_queues[i]) {
 478                         txq = eth_dev->data->tx_queues[i];
 479                         qede_tx_queue_release(eth_dev->data->tx_queues[i]);
 480                         qdev->ops->common->chain_free(edev,
 481                                                       &txq->tx_pbl);
 482                         eth_dev->data->tx_queues[i] = NULL;
 483                 }
 484         }
 485
 486         if (qdev->fp_array)
 487                 rte_free(qdev->fp_array);
 488         qdev->fp_array = NULL;
 489 }
 490
 491 static inline void
 492 qede_update_rx_prod(__rte_unused struct qede_dev *edev,
 493                     struct qede_rx_queue *rxq)
 494 {
 495         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 496         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 497         struct eth_rx_prod_data rx_prods = { 0 };
 498
 499         /* Update producers */
 500         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 501         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 502
 503         /* Make sure that the BD and SGE data is updated before updating the
 504          * producers since FW might read the BD/SGE right after the producer
 505          * is updated.
 506          */
 507         rte_wmb();
 508
 509         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 510                         (uint32_t *)&rx_prods);
 511
 512         /* mmiowb is needed to synchronize doorbell writes from more than one
 513          * processor. It guarantees that the write arrives to the device before
 514          * the napi lock is released and another qede_poll is called (possibly
 515          * on another CPU). Without this barrier, the next doorbell can bypass
 516          * this doorbell. This is applicable to IA64/Altix systems.
 517          */
 518         rte_wmb();
 519
 520         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u", bd_prod, cqe_prod);
 521 }
 522
 523 /* Starts a given RX queue in HW */
 524 static int
 525 qede_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
 526 {
 527         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 528         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 529         struct ecore_queue_start_common_params params;
 530         struct ecore_rxq_start_ret_params ret_params;
 531         struct qede_rx_queue *rxq;
 532         struct qede_fastpath *fp;
 533         struct ecore_hwfn *p_hwfn;
 534         dma_addr_t p_phys_table;
 535         uint16_t page_cnt;
 536         uint16_t j;
 537         int hwfn_index;
 538         int rc;
 539
 540         if (rx_queue_id < eth_dev->data->nb_rx_queues) {
 541                 fp = &qdev->fp_array[rx_queue_id];
 542                 rxq = eth_dev->data->rx_queues[rx_queue_id];
 543                 /* Allocate buffers for the Rx ring */
 544                 for (j = 0; j < rxq->nb_rx_desc; j++) {
 545                         rc = qede_alloc_rx_buffer(rxq);
 546                         if (rc) {
 547                                 DP_ERR(edev, "RX buffer allocation failed"
 548                                                 " for rxq = %u\n", rx_queue_id);
 549                                 return -ENOMEM;
 550                         }
 551                 }
 552                 /* disable interrupts */
 553                 ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 554                 /* Prepare ramrod */
 555                 memset(&params, 0, sizeof(params));
 556                 params.queue_id = rx_queue_id;
 557                 params.vport_id = 0;
 558                 params.sb = fp->sb_info->igu_sb_id;
 559                 DP_INFO(edev, "rxq %u igu_sb_id 0x%x\n",
 560                                 fp->rxq->queue_id, fp->sb_info->igu_sb_id);
 561                 params.sb_idx = RX_PI;
 562                 hwfn_index = rx_queue_id % edev->num_hwfns;
 563                 p_hwfn = &edev->hwfns[hwfn_index];
 564                 p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->rx_comp_ring);
 565                 page_cnt = ecore_chain_get_page_cnt(&fp->rxq->rx_comp_ring);
 566                 memset(&ret_params, 0, sizeof(ret_params));
 567                 rc = ecore_eth_rx_queue_start(p_hwfn,
 568                                 p_hwfn->hw_info.opaque_fid,
 569                                 &params, fp->rxq->rx_buf_size,
 570                                 fp->rxq->rx_bd_ring.p_phys_addr,
 571                                 p_phys_table, page_cnt,
 572                                 &ret_params);
 573                 if (rc) {
 574                         DP_ERR(edev, "RX queue %u could not be started, rc = %d\n",
 575                                         rx_queue_id, rc);
 576                         return -1;
 577                 }
 578                 /* Update with the returned parameters */
 579                 fp->rxq->hw_rxq_prod_addr = ret_params.p_prod;
 580                 fp->rxq->handle = ret_params.p_handle;
 581
 582                 fp->rxq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[RX_PI];
 583                 qede_update_rx_prod(qdev, fp->rxq);
 584                 eth_dev->data->rx_queue_state[rx_queue_id] =
 585                         RTE_ETH_QUEUE_STATE_STARTED;
 586                 DP_INFO(edev, "RX queue %u started\n", rx_queue_id);
 587         } else {
 588                 DP_ERR(edev, "RX queue %u is not in range\n", rx_queue_id);
 589                 rc = -EINVAL;
 590         }
 591
 592         return rc;
 593 }
 594
 595 static int
 596 qede_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 597 {
 598         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 599         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 600         struct ecore_queue_start_common_params params;
 601         struct ecore_txq_start_ret_params ret_params;
 602         struct ecore_hwfn *p_hwfn;
 603         dma_addr_t p_phys_table;
 604         struct qede_tx_queue *txq;
 605         struct qede_fastpath *fp;
 606         uint16_t page_cnt;
 607         int hwfn_index;
 608         int rc;
 609
 610         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 611                 txq = eth_dev->data->tx_queues[tx_queue_id];
 612                 fp = &qdev->fp_array[tx_queue_id];
 613                 memset(&params, 0, sizeof(params));
 614                 params.queue_id = tx_queue_id;
 615                 params.vport_id = 0;
 616                 params.sb = fp->sb_info->igu_sb_id;
 617                 DP_INFO(edev, "txq %u igu_sb_id 0x%x\n",
 618                                 fp->txq->queue_id, fp->sb_info->igu_sb_id);
 619                 params.sb_idx = TX_PI(0); /* tc = 0 */
 620                 p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 621                 page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 622                 hwfn_index = tx_queue_id % edev->num_hwfns;
 623                 p_hwfn = &edev->hwfns[hwfn_index];
 624                 if (qdev->dev_info.is_legacy)
 625                         fp->txq->is_legacy = true;
 626                 rc = ecore_eth_tx_queue_start(p_hwfn,
 627                                 p_hwfn->hw_info.opaque_fid,
 628                                 &params, 0 /* tc */,
 629                                 p_phys_table, page_cnt,
 630                                 &ret_params);
 631                 if (rc != ECORE_SUCCESS) {
 632                         DP_ERR(edev, "TX queue %u couldn't be started, rc=%d\n",
 633                                         tx_queue_id, rc);
 634                         return -1;
 635                 }
 636                 txq->doorbell_addr = ret_params.p_doorbell;
 637                 txq->handle = ret_params.p_handle;
 638
 639                 txq->hw_cons_ptr = &fp->sb_info->sb_virt->pi_array[TX_PI(0)];
 640                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_DEST,
 641                                 DB_DEST_XCM);
 642                 SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 643                                 DB_AGG_CMD_SET);
 644                 SET_FIELD(txq->tx_db.data.params,
 645                                 ETH_DB_DATA_AGG_VAL_SEL,
 646                                 DQ_XCM_ETH_TX_BD_PROD_CMD);
 647                 txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 648                 eth_dev->data->tx_queue_state[tx_queue_id] =
 649                         RTE_ETH_QUEUE_STATE_STARTED;
 650                 DP_INFO(edev, "TX queue %u started\n", tx_queue_id);
 651         } else {
 652                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 653                 rc = -EINVAL;
 654         }
 655
 656         return rc;
 657 }
 658
 659 static inline void
 660 qede_free_tx_pkt(struct qede_tx_queue *txq)
 661 {
 662         struct rte_mbuf *mbuf;
 663         uint16_t nb_segs;
 664         uint16_t idx;
 665
 666         idx = TX_CONS(txq);
 667         mbuf = txq->sw_tx_ring[idx].mbuf;
 668         if (mbuf) {
 669                 nb_segs = mbuf->nb_segs;
 670                 PMD_TX_LOG(DEBUG, txq, "nb_segs to free %u\n", nb_segs);
 671                 while (nb_segs) {
 672                         /* It's like consuming rxbuf in recv() */
 673                         ecore_chain_consume(&txq->tx_pbl);
 674                         txq->nb_tx_avail++;
 675                         nb_segs--;
 676                 }
 677                 rte_pktmbuf_free(mbuf);
 678                 txq->sw_tx_ring[idx].mbuf = NULL;
 679                 txq->sw_tx_cons++;
 680                 PMD_TX_LOG(DEBUG, txq, "Freed tx packet\n");
 681         } else {
 682                 ecore_chain_consume(&txq->tx_pbl);
 683                 txq->nb_tx_avail++;
 684         }
 685 }
 686
 687 static inline void
 688 qede_process_tx_compl(__rte_unused struct ecore_dev *edev,
 689                       struct qede_tx_queue *txq)
 690 {
 691         uint16_t hw_bd_cons;
 692 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 693         uint16_t sw_tx_cons;
 694 #endif
 695
 696         rte_compiler_barrier();
 697         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
 698 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
 699         sw_tx_cons = ecore_chain_get_cons_idx(&txq->tx_pbl);
 700         PMD_TX_LOG(DEBUG, txq, "Tx Completions = %u\n",
 701                    abs(hw_bd_cons - sw_tx_cons));
 702 #endif
 703         while (hw_bd_cons !=  ecore_chain_get_cons_idx(&txq->tx_pbl))
 704                 qede_free_tx_pkt(txq);
 705 }
 706
 707
 708 static int qede_drain_txq(struct qede_dev *qdev,
 709                           struct qede_tx_queue *txq, bool allow_drain)
 710 {
 711         struct ecore_dev *edev = &qdev->edev;
 712         int rc, cnt = 1000;
 713
 714         while (txq->sw_tx_cons != txq->sw_tx_prod) {
 715                 qede_process_tx_compl(edev, txq);
 716                 if (!cnt) {
 717                         if (allow_drain) {
 718                                 DP_ERR(edev, "Tx queue[%u] is stuck,"
 719                                           "requesting MCP to drain\n",
 720                                           txq->queue_id);
 721                                 rc = qdev->ops->common->drain(edev);
 722                                 if (rc)
 723                                         return rc;
 724                                 return qede_drain_txq(qdev, txq, false);
 725                         }
 726                         DP_ERR(edev, "Timeout waiting for tx queue[%d]:"
 727                                   "PROD=%d, CONS=%d\n",
 728                                   txq->queue_id, txq->sw_tx_prod,
 729                                   txq->sw_tx_cons);
 730                         return -1;
 731                 }
 732                 cnt--;
 733                 DELAY(1000);
 734                 rte_compiler_barrier();
 735         }
 736
 737         /* FW finished processing, wait for HW to transmit all tx packets */
 738         DELAY(2000);
 739
 740         return 0;
 741 }
 742
 743
 744 /* Stops a given TX queue in the HW */
 745 static int qede_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
 746 {
 747         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 748         struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
 749         struct ecore_hwfn *p_hwfn;
 750         struct qede_tx_queue *txq;
 751         int hwfn_index;
 752         int rc;
 753
 754         if (tx_queue_id < eth_dev->data->nb_tx_queues) {
 755                 txq = eth_dev->data->tx_queues[tx_queue_id];
 756                 /* Drain txq */
 757                 if (qede_drain_txq(qdev, txq, true))
 758                         return -1; /* For the lack of retcodes */
 759                 /* Stop txq */
 760                 hwfn_index = tx_queue_id % edev->num_hwfns;
 761                 p_hwfn = &edev->hwfns[hwfn_index];
 762                 rc = ecore_eth_tx_queue_stop(p_hwfn, txq->handle);
 763                 if (rc != ECORE_SUCCESS) {
 764                         DP_ERR(edev, "TX queue %u stop fails\n", tx_queue_id);
 765                         return -1;
 766                 }
 767                 qede_tx_queue_release_mbufs(txq);
 768                 qede_tx_queue_reset(qdev, txq);
 769                 eth_dev->data->tx_queue_state[tx_queue_id] =
 770                         RTE_ETH_QUEUE_STATE_STOPPED;
 771                 DP_INFO(edev, "TX queue %u stopped\n", tx_queue_id);
 772         } else {
 773                 DP_ERR(edev, "TX queue %u is not in range\n", tx_queue_id);
 774                 rc = -EINVAL;
 775         }
 776
 777         return rc;
 778 }
 779
 780 int qede_start_queues(struct rte_eth_dev *eth_dev)
 781 {
 782         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 783         uint8_t id;
 784         int rc;
 785
 786         for_each_rss(id) {
 787                 rc = qede_rx_queue_start(eth_dev, id);
 788                 if (rc != ECORE_SUCCESS)
 789                         return -1;
 790         }
 791
 792         for_each_tss(id) {
 793                 rc = qede_tx_queue_start(eth_dev, id);
 794                 if (rc != ECORE_SUCCESS)
 795                         return -1;
 796         }
 797
 798         return rc;
 799 }
 800
 801 void qede_stop_queues(struct rte_eth_dev *eth_dev)
 802 {
 803         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 804         uint8_t id;
 805
 806         /* Stopping RX/TX queues */
 807         for_each_tss(id) {
 808                 qede_tx_queue_stop(eth_dev, id);
 809         }
 810
 811         for_each_rss(id) {
 812                 qede_rx_queue_stop(eth_dev, id);
 813         }
 814 }
 815
 816 static bool qede_tunn_exist(uint16_t flag)
 817 {
 818         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 819                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 820 }
 821
 822 /*
 823  * qede_check_tunn_csum_l4:
 824  * Returns:
 825  * 1 : If L4 csum is enabled AND if the validation has failed.
 826  * 0 : Otherwise
 827  */
 828 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 829 {
 830         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 831              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 832                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 833                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 834
 835         return 0;
 836 }
 837
 838 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 839 {
 840         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 841              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 842                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 843                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 844
 845         return 0;
 846 }
 847
 848 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 849 {
 850         uint16_t val;
 851
 852         /* Lookup table */
 853         static const uint32_t
 854         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 855                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 856                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 857                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 858                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 859                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 860                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 861         };
 862
 863         /* Bits (0..3) provides L3/L4 protocol type */
 864         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 865                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 866                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 867                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 868
 869         if (val < QEDE_PKT_TYPE_MAX)
 870                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 871         else
 872                 return RTE_PTYPE_UNKNOWN;
 873 }
 874
 875 static inline uint8_t
 876 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 877 {
 878         struct ipv4_hdr *ip;
 879         uint16_t pkt_csum;
 880         uint16_t calc_csum;
 881         uint16_t val;
 882
 883         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 884                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 885
 886         if (unlikely(val)) {
 887                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 888                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 889                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 890                                            sizeof(struct ether_hdr));
 891                         pkt_csum = ip->hdr_checksum;
 892                         ip->hdr_checksum = 0;
 893                         calc_csum = rte_ipv4_cksum(ip);
 894                         ip->hdr_checksum = pkt_csum;
 895                         return (calc_csum != pkt_csum);
 896                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 897                         return 1;
 898                 }
 899         }
 900         return 0;
 901 }
 902
 903 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 904 {
 905         ecore_chain_consume(&rxq->rx_bd_ring);
 906         rxq->sw_rx_cons++;
 907 }
 908
 909 static inline void
 910 qede_reuse_page(__rte_unused struct qede_dev *qdev,
 911                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 912 {
 913         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 914         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 915         struct qede_rx_entry *curr_prod;
 916         dma_addr_t new_mapping;
 917
 918         curr_prod = &rxq->sw_rx_ring[idx];
 919         *curr_prod = *curr_cons;
 920
 921         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 922                       curr_prod->page_offset;
 923
 924         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 925         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 926
 927         rxq->sw_rx_prod++;
 928 }
 929
 930 static inline void
 931 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 932                         struct qede_dev *qdev, uint8_t count)
 933 {
 934         struct qede_rx_entry *curr_cons;
 935
 936         for (; count > 0; count--) {
 937                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 938                 qede_reuse_page(qdev, rxq, curr_cons);
 939                 qede_rx_bd_ring_consume(rxq);
 940         }
 941 }
 942
 943 static inline void
 944 qede_rx_process_tpa_cmn_cont_end_cqe(__rte_unused struct qede_dev *qdev,
 945                                      struct qede_rx_queue *rxq,
 946                                      uint8_t agg_index, uint16_t len)
 947 {
 948         struct qede_agg_info *tpa_info;
 949         struct rte_mbuf *curr_frag; /* Pointer to currently filled TPA seg */
 950         uint16_t cons_idx;
 951
 952         /* Under certain conditions it is possible that FW may not consume
 953          * additional or new BD. So decision to consume the BD must be made
 954          * based on len_list[0].
 955          */
 956         if (rte_le_to_cpu_16(len)) {
 957                 tpa_info = &rxq->tpa_info[agg_index];
 958                 cons_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 959                 curr_frag = rxq->sw_rx_ring[cons_idx].mbuf;
 960                 assert(curr_frag);
 961                 curr_frag->nb_segs = 1;
 962                 curr_frag->pkt_len = rte_le_to_cpu_16(len);
 963                 curr_frag->data_len = curr_frag->pkt_len;
 964                 tpa_info->tpa_tail->next = curr_frag;
 965                 tpa_info->tpa_tail = curr_frag;
 966                 qede_rx_bd_ring_consume(rxq);
 967                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 968                         PMD_RX_LOG(ERR, rxq, "mbuf allocation fails\n");
 969                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++;
 970                         rxq->rx_alloc_errors++;
 971                 }
 972         }
 973 }
 974
 975 static inline void
 976 qede_rx_process_tpa_cont_cqe(struct qede_dev *qdev,
 977                              struct qede_rx_queue *rxq,
 978                              struct eth_fast_path_rx_tpa_cont_cqe *cqe)
 979 {
 980         PMD_RX_LOG(INFO, rxq, "TPA cont[%d] - len [%d]\n",
 981                    cqe->tpa_agg_index, rte_le_to_cpu_16(cqe->len_list[0]));
 982         /* only len_list[0] will have value */
 983         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 984                                              cqe->len_list[0]);
 985 }
 986
 987 static inline void
 988 qede_rx_process_tpa_end_cqe(struct qede_dev *qdev,
 989                             struct qede_rx_queue *rxq,
 990                             struct eth_fast_path_rx_tpa_end_cqe *cqe)
 991 {
 992         struct rte_mbuf *rx_mb; /* Pointer to head of the chained agg */
 993
 994         qede_rx_process_tpa_cmn_cont_end_cqe(qdev, rxq, cqe->tpa_agg_index,
 995                                              cqe->len_list[0]);
 996         /* Update total length and frags based on end TPA */
 997         rx_mb = rxq->tpa_info[cqe->tpa_agg_index].tpa_head;
 998         /* TODO:  Add Sanity Checks */
 999         rx_mb->nb_segs = cqe->num_of_bds;
1000         rx_mb->pkt_len = cqe->total_packet_len;
1001
1002         PMD_RX_LOG(INFO, rxq, "TPA End[%d] reason %d cqe_len %d nb_segs %d"
1003                    " pkt_len %d\n", cqe->tpa_agg_index, cqe->end_reason,
1004                    rte_le_to_cpu_16(cqe->len_list[0]), rx_mb->nb_segs,
1005                    rx_mb->pkt_len);
1006 }
1007
1008 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
1009 {
1010         uint32_t val;
1011
1012         /* Lookup table */
1013         static const uint32_t
1014         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
1015                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
1016                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
1017                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
1018                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
1019                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
1020                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1021                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
1022                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1023                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
1024                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1025                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
1026                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
1027                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
1028                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
1029                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
1030                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
1031                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
1032                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1033                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
1034                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1035                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
1036                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1037                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
1038                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
1039                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
1040                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
1041                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
1042                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
1043                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
1044                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1045                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
1046                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1047                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
1048                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1049                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
1050                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
1051                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
1052                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
1053                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
1054                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
1055         };
1056
1057         /* Cover bits[4-0] to include tunn_type and next protocol */
1058         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
1059                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
1060                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
1061                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
1062
1063         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
1064                 return ptype_tunn_lkup_tbl[val];
1065         else
1066                 return RTE_PTYPE_UNKNOWN;
1067 }
1068
1069 static inline int
1070 qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
1071                      uint8_t num_segs, uint16_t pkt_len)
1072 {
1073         struct qede_rx_queue *rxq = p_rxq;
1074         struct qede_dev *qdev = rxq->qdev;
1075         register struct rte_mbuf *seg1 = NULL;
1076         register struct rte_mbuf *seg2 = NULL;
1077         uint16_t sw_rx_index;
1078         uint16_t cur_size;
1079
1080         seg1 = rx_mb;
1081         while (num_segs) {
1082                 cur_size = pkt_len > rxq->rx_buf_size ? rxq->rx_buf_size :
1083                                                         pkt_len;
1084                 if (unlikely(!cur_size)) {
1085                         PMD_RX_LOG(ERR, rxq, "Length is 0 while %u BDs"
1086                                    " left for mapping jumbo", num_segs);
1087                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
1088                         return -EINVAL;
1089                 }
1090                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1091                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
1092                 qede_rx_bd_ring_consume(rxq);
1093                 pkt_len -= cur_size;
1094                 seg2->data_len = cur_size;
1095                 seg1->next = seg2;
1096                 seg1 = seg1->next;
1097                 num_segs--;
1098                 rxq->rx_segs++;
1099         }
1100
1101         return 0;
1102 }
1103
1104 uint16_t
1105 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1106 {
1107         struct qede_rx_queue *rxq = p_rxq;
1108         struct qede_dev *qdev = rxq->qdev;
1109         struct ecore_dev *edev = &qdev->edev;
1110         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
1111         uint16_t rx_pkt = 0;
1112         union eth_rx_cqe *cqe;
1113         struct eth_fast_path_rx_reg_cqe *fp_cqe = NULL;
1114         register struct rte_mbuf *rx_mb = NULL;
1115         register struct rte_mbuf *seg1 = NULL;
1116         enum eth_rx_cqe_type cqe_type;
1117         uint16_t pkt_len = 0; /* Sum of all BD segments */
1118         uint16_t len; /* Length of first BD */
1119         uint8_t num_segs = 1;
1120         uint16_t preload_idx;
1121         uint16_t parse_flag;
1122 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1123         uint8_t bitfield_val;
1124         enum rss_hash_type htype;
1125 #endif
1126         uint8_t tunn_parse_flag;
1127         uint8_t j;
1128         struct eth_fast_path_rx_tpa_start_cqe *cqe_start_tpa;
1129         uint64_t ol_flags;
1130         uint32_t packet_type;
1131         uint16_t vlan_tci;
1132         bool tpa_start_flg;
1133         uint8_t offset, tpa_agg_idx, flags;
1134         struct qede_agg_info *tpa_info = NULL;
1135         uint32_t rss_hash;
1136
1137         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
1138         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1139
1140         rte_rmb();
1141
1142         if (hw_comp_cons == sw_comp_cons)
1143                 return 0;
1144
1145         while (sw_comp_cons != hw_comp_cons) {
1146                 ol_flags = 0;
1147                 packet_type = RTE_PTYPE_UNKNOWN;
1148                 vlan_tci = 0;
1149                 tpa_start_flg = false;
1150                 rss_hash = 0;
1151
1152                 /* Get the CQE from the completion ring */
1153                 cqe =
1154                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
1155                 cqe_type = cqe->fast_path_regular.type;
1156                 PMD_RX_LOG(INFO, rxq, "Rx CQE type %d\n", cqe_type);
1157
1158                 switch (cqe_type) {
1159                 case ETH_RX_CQE_TYPE_REGULAR:
1160                         fp_cqe = &cqe->fast_path_regular;
1161                 break;
1162                 case ETH_RX_CQE_TYPE_TPA_START:
1163                         cqe_start_tpa = &cqe->fast_path_tpa_start;
1164                         tpa_info = &rxq->tpa_info[cqe_start_tpa->tpa_agg_index];
1165                         tpa_start_flg = true;
1166                         /* Mark it as LRO packet */
1167                         ol_flags |= PKT_RX_LRO;
1168                         /* In split mode,  seg_len is same as len_on_first_bd
1169                          * and ext_bd_len_list will be empty since there are
1170                          * no additional buffers
1171                          */
1172                         PMD_RX_LOG(INFO, rxq,
1173                             "TPA start[%d] - len_on_first_bd %d header %d"
1174                             " [bd_list[0] %d], [seg_len %d]\n",
1175                             cqe_start_tpa->tpa_agg_index,
1176                             rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd),
1177                             cqe_start_tpa->header_len,
1178                             rte_le_to_cpu_16(cqe_start_tpa->ext_bd_len_list[0]),
1179                             rte_le_to_cpu_16(cqe_start_tpa->seg_len));
1180
1181                 break;
1182                 case ETH_RX_CQE_TYPE_TPA_CONT:
1183                         qede_rx_process_tpa_cont_cqe(qdev, rxq,
1184                                                      &cqe->fast_path_tpa_cont);
1185                         goto next_cqe;
1186                 case ETH_RX_CQE_TYPE_TPA_END:
1187                         qede_rx_process_tpa_end_cqe(qdev, rxq,
1188                                                     &cqe->fast_path_tpa_end);
1189                         tpa_agg_idx = cqe->fast_path_tpa_end.tpa_agg_index;
1190                         tpa_info = &rxq->tpa_info[tpa_agg_idx];
1191                         rx_mb = rxq->tpa_info[tpa_agg_idx].tpa_head;
1192                         goto tpa_end;
1193                 case ETH_RX_CQE_TYPE_SLOW_PATH:
1194                         PMD_RX_LOG(INFO, rxq, "Got unexpected slowpath CQE\n");
1195                         ecore_eth_cqe_completion(
1196                                 &edev->hwfns[rxq->queue_id % edev->num_hwfns],
1197                                 (struct eth_slow_path_rx_cqe *)cqe);
1198                         /* fall-thru */
1199                 default:
1200                         goto next_cqe;
1201                 }
1202
1203                 /* Get the data from the SW ring */
1204                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1205                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
1206                 assert(rx_mb != NULL);
1207
1208                 /* Handle regular CQE or TPA start CQE */
1209                 if (!tpa_start_flg) {
1210                         parse_flag = rte_le_to_cpu_16(fp_cqe->pars_flags.flags);
1211                         offset = fp_cqe->placement_offset;
1212                         len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
1213                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
1214                         vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1215                         rss_hash = rte_le_to_cpu_32(fp_cqe->rss_hash);
1216 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1217                         bitfield_val = fp_cqe->bitfields;
1218                         htype = (uint8_t)GET_FIELD(bitfield_val,
1219                                         ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1220 #endif
1221                 } else {
1222                         parse_flag =
1223                             rte_le_to_cpu_16(cqe_start_tpa->pars_flags.flags);
1224                         offset = cqe_start_tpa->placement_offset;
1225                         /* seg_len = len_on_first_bd */
1226                         len = rte_le_to_cpu_16(cqe_start_tpa->len_on_first_bd);
1227                         vlan_tci = rte_le_to_cpu_16(cqe_start_tpa->vlan_tag);
1228 #ifdef RTE_LIBRTE_QEDE_DEBUG_RX
1229                         bitfield_val = cqe_start_tpa->bitfields;
1230                         htype = (uint8_t)GET_FIELD(bitfield_val,
1231                                 ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE);
1232 #endif
1233                         rss_hash = rte_le_to_cpu_32(cqe_start_tpa->rss_hash);
1234                 }
1235                 if (qede_tunn_exist(parse_flag)) {
1236                         PMD_RX_LOG(INFO, rxq, "Rx tunneled packet\n");
1237                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
1238                                 PMD_RX_LOG(ERR, rxq,
1239                                             "L4 csum failed, flags = 0x%x\n",
1240                                             parse_flag);
1241                                 rxq->rx_hw_errors++;
1242                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1243                         } else {
1244                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1245                                 if (tpa_start_flg)
1246                                         flags =
1247                                          cqe_start_tpa->tunnel_pars_flags.flags;
1248                                 else
1249                                         flags = fp_cqe->tunnel_pars_flags.flags;
1250                                 tunn_parse_flag = flags;
1251                                 packet_type =
1252                                 qede_rx_cqe_to_tunn_pkt_type(tunn_parse_flag);
1253                         }
1254                 } else {
1255                         PMD_RX_LOG(INFO, rxq, "Rx non-tunneled packet\n");
1256                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
1257                                 PMD_RX_LOG(ERR, rxq,
1258                                             "L4 csum failed, flags = 0x%x\n",
1259                                             parse_flag);
1260                                 rxq->rx_hw_errors++;
1261                                 ol_flags |= PKT_RX_L4_CKSUM_BAD;
1262                         } else {
1263                                 ol_flags |= PKT_RX_L4_CKSUM_GOOD;
1264                         }
1265                         if (unlikely(qede_check_notunn_csum_l3(rx_mb,
1266                                                         parse_flag))) {
1267                                 PMD_RX_LOG(ERR, rxq,
1268                                            "IP csum failed, flags = 0x%x\n",
1269                                            parse_flag);
1270                                 rxq->rx_hw_errors++;
1271                                 ol_flags |= PKT_RX_IP_CKSUM_BAD;
1272                         } else {
1273                                 ol_flags |= PKT_RX_IP_CKSUM_GOOD;
1274                                 packet_type =
1275                                         qede_rx_cqe_to_pkt_type(parse_flag);
1276                         }
1277                 }
1278
1279                 if (CQE_HAS_VLAN(parse_flag)) {
1280                         ol_flags |= PKT_RX_VLAN_PKT;
1281                         if (qdev->vlan_strip_flg) {
1282                                 ol_flags |= PKT_RX_VLAN_STRIPPED;
1283                                 rx_mb->vlan_tci = vlan_tci;
1284                         }
1285                 }
1286                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1287                         ol_flags |= PKT_RX_QINQ_PKT;
1288                         if (qdev->vlan_strip_flg) {
1289                                 rx_mb->vlan_tci = vlan_tci;
1290                                 ol_flags |= PKT_RX_QINQ_STRIPPED;
1291                         }
1292                         rx_mb->vlan_tci_outer = 0;
1293                 }
1294                 /* RSS Hash */
1295                 if (qdev->rss_enable) {
1296                         ol_flags |= PKT_RX_RSS_HASH;
1297                         rx_mb->hash.rss = rss_hash;
1298                 }
1299
1300                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
1301                         PMD_RX_LOG(ERR, rxq,
1302                                    "New buffer allocation failed,"
1303                                    "dropping incoming packet\n");
1304                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
1305                         rte_eth_devices[rxq->port_id].
1306                             data->rx_mbuf_alloc_failed++;
1307                         rxq->rx_alloc_errors++;
1308                         break;
1309                 }
1310                 qede_rx_bd_ring_consume(rxq);
1311
1312                 if (!tpa_start_flg && fp_cqe->bd_num > 1) {
1313                         PMD_RX_LOG(DEBUG, rxq, "Jumbo-over-BD packet: %02x BDs"
1314                                    " len on first: %04x Total Len: %04x",
1315                                    fp_cqe->bd_num, len, pkt_len);
1316                         num_segs = fp_cqe->bd_num - 1;
1317                         seg1 = rx_mb;
1318                         if (qede_process_sg_pkts(p_rxq, seg1, num_segs,
1319                                                  pkt_len - len))
1320                                 goto next_cqe;
1321                         for (j = 0; j < num_segs; j++) {
1322                                 if (qede_alloc_rx_buffer(rxq)) {
1323                                         PMD_RX_LOG(ERR, rxq,
1324                                                 "Buffer allocation failed");
1325                                         rte_eth_devices[rxq->port_id].
1326                                                 data->rx_mbuf_alloc_failed++;
1327                                         rxq->rx_alloc_errors++;
1328                                         break;
1329                                 }
1330                                 rxq->rx_segs++;
1331                         }
1332                 }
1333                 rxq->rx_segs++; /* for the first segment */
1334
1335                 /* Prefetch next mbuf while processing current one. */
1336                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1337                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1338
1339                 /* Update rest of the MBUF fields */
1340                 rx_mb->data_off = offset + RTE_PKTMBUF_HEADROOM;
1341                 rx_mb->port = rxq->port_id;
1342                 rx_mb->ol_flags = ol_flags;
1343                 rx_mb->data_len = len;
1344                 rx_mb->packet_type = packet_type;
1345                 PMD_RX_LOG(INFO, rxq,
1346                            "pkt_type 0x%04x len %u hash_type %d hash_val 0x%x"
1347                            " ol_flags 0x%04lx\n",
1348                            packet_type, len, htype, rx_mb->hash.rss,
1349                            (unsigned long)ol_flags);
1350                 if (!tpa_start_flg) {
1351                         rx_mb->nb_segs = fp_cqe->bd_num;
1352                         rx_mb->pkt_len = pkt_len;
1353                 } else {
1354                         /* store ref to the updated mbuf */
1355                         tpa_info->tpa_head = rx_mb;
1356                         tpa_info->tpa_tail = tpa_info->tpa_head;
1357                 }
1358                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1359 tpa_end:
1360                 if (!tpa_start_flg) {
1361                         rx_pkts[rx_pkt] = rx_mb;
1362                         rx_pkt++;
1363                 }
1364 next_cqe:
1365                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1366                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1367                 if (rx_pkt == nb_pkts) {
1368                         PMD_RX_LOG(DEBUG, rxq,
1369                                    "Budget reached nb_pkts=%u received=%u",
1370                                    rx_pkt, nb_pkts);
1371                         break;
1372                 }
1373         }
1374
1375         qede_update_rx_prod(qdev, rxq);
1376
1377         rxq->rcv_pkts += rx_pkt;
1378
1379         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d", rx_pkt, rte_lcore_id());
1380
1381         return rx_pkt;
1382 }
1383
1384
1385 /* Populate scatter gather buffer descriptor fields */
1386 static inline uint8_t
1387 qede_encode_sg_bd(struct qede_tx_queue *p_txq, struct rte_mbuf *m_seg,
1388                   struct eth_tx_2nd_bd **bd2, struct eth_tx_3rd_bd **bd3)
1389 {
1390         struct qede_tx_queue *txq = p_txq;
1391         struct eth_tx_bd *tx_bd = NULL;
1392         dma_addr_t mapping;
1393         uint8_t nb_segs = 0;
1394
1395         /* Check for scattered buffers */
1396         while (m_seg) {
1397                 if (nb_segs == 0) {
1398                         if (!*bd2) {
1399                                 *bd2 = (struct eth_tx_2nd_bd *)
1400                                         ecore_chain_produce(&txq->tx_pbl);
1401                                 memset(*bd2, 0, sizeof(struct eth_tx_2nd_bd));
1402                                 nb_segs++;
1403                         }
1404                         mapping = rte_mbuf_data_dma_addr(m_seg);
1405                         QEDE_BD_SET_ADDR_LEN(*bd2, mapping, m_seg->data_len);
1406                         PMD_TX_LOG(DEBUG, txq, "BD2 len %04x", m_seg->data_len);
1407                 } else if (nb_segs == 1) {
1408                         if (!*bd3) {
1409                                 *bd3 = (struct eth_tx_3rd_bd *)
1410                                         ecore_chain_produce(&txq->tx_pbl);
1411                                 memset(*bd3, 0, sizeof(struct eth_tx_3rd_bd));
1412                                 nb_segs++;
1413                         }
1414                         mapping = rte_mbuf_data_dma_addr(m_seg);
1415                         QEDE_BD_SET_ADDR_LEN(*bd3, mapping, m_seg->data_len);
1416                         PMD_TX_LOG(DEBUG, txq, "BD3 len %04x", m_seg->data_len);
1417                 } else {
1418                         tx_bd = (struct eth_tx_bd *)
1419                                 ecore_chain_produce(&txq->tx_pbl);
1420                         memset(tx_bd, 0, sizeof(*tx_bd));
1421                         nb_segs++;
1422                         mapping = rte_mbuf_data_dma_addr(m_seg);
1423                         QEDE_BD_SET_ADDR_LEN(tx_bd, mapping, m_seg->data_len);
1424                         PMD_TX_LOG(DEBUG, txq, "BD len %04x", m_seg->data_len);
1425                 }
1426                 m_seg = m_seg->next;
1427         }
1428
1429         /* Return total scattered buffers */
1430         return nb_segs;
1431 }
1432
1433 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1434 static inline void
1435 print_tx_bd_info(struct qede_tx_queue *txq,
1436                  struct eth_tx_1st_bd *bd1,
1437                  struct eth_tx_2nd_bd *bd2,
1438                  struct eth_tx_3rd_bd *bd3,
1439                  uint64_t tx_ol_flags)
1440 {
1441         char ol_buf[256] = { 0 }; /* for verbose prints */
1442
1443         if (bd1)
1444                 PMD_TX_LOG(INFO, txq,
1445                            "BD1: nbytes=%u nbds=%u bd_flags=%04x bf=%04x",
1446                            rte_cpu_to_le_16(bd1->nbytes), bd1->data.nbds,
1447                            bd1->data.bd_flags.bitfields,
1448                            rte_cpu_to_le_16(bd1->data.bitfields));
1449         if (bd2)
1450                 PMD_TX_LOG(INFO, txq,
1451                            "BD2: nbytes=%u bf=%04x\n",
1452                            rte_cpu_to_le_16(bd2->nbytes), bd2->data.bitfields1);
1453         if (bd3)
1454                 PMD_TX_LOG(INFO, txq,
1455                            "BD3: nbytes=%u bf=%04x mss=%u\n",
1456                            rte_cpu_to_le_16(bd3->nbytes),
1457                            rte_cpu_to_le_16(bd3->data.bitfields),
1458                            rte_cpu_to_le_16(bd3->data.lso_mss));
1459
1460         rte_get_tx_ol_flag_list(tx_ol_flags, ol_buf, sizeof(ol_buf));
1461         PMD_TX_LOG(INFO, txq, "TX offloads = %s\n", ol_buf);
1462 }
1463 #endif
1464
1465 /* TX prepare to check packets meets TX conditions */
1466 uint16_t
1467 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1468 qede_xmit_prep_pkts(void *p_txq, struct rte_mbuf **tx_pkts,
1469                     uint16_t nb_pkts)
1470 {
1471         struct qede_tx_queue *txq = p_txq;
1472 #else
1473 qede_xmit_prep_pkts(__rte_unused void *p_txq, struct rte_mbuf **tx_pkts,
1474                     uint16_t nb_pkts)
1475 {
1476 #endif
1477         uint64_t ol_flags;
1478         struct rte_mbuf *m;
1479         uint16_t i;
1480 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1481         int ret;
1482 #endif
1483
1484         for (i = 0; i < nb_pkts; i++) {
1485                 m = tx_pkts[i];
1486                 ol_flags = m->ol_flags;
1487                 if (ol_flags & PKT_TX_TCP_SEG) {
1488                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_LSO_PACKET) {
1489                                 rte_errno = -EINVAL;
1490                                 break;
1491                         }
1492                         /* TBD: confirm its ~9700B for both ? */
1493                         if (m->tso_segsz > ETH_TX_MAX_NON_LSO_PKT_LEN) {
1494                                 rte_errno = -EINVAL;
1495                                 break;
1496                         }
1497                 } else {
1498                         if (m->nb_segs >= ETH_TX_MAX_BDS_PER_NON_LSO_PACKET) {
1499                                 rte_errno = -EINVAL;
1500                                 break;
1501                         }
1502                 }
1503                 if (ol_flags & QEDE_TX_OFFLOAD_NOTSUP_MASK) {
1504                         rte_errno = -ENOTSUP;
1505                         break;
1506                 }
1507
1508 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1509                 ret = rte_validate_tx_offload(m);
1510                 if (ret != 0) {
1511                         rte_errno = ret;
1512                         break;
1513                 }
1514 #endif
1515         }
1516
1517 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1518         if (unlikely(i != nb_pkts))
1519                 PMD_TX_LOG(ERR, txq, "TX prepare failed for %u\n",
1520                            nb_pkts - i);
1521 #endif
1522         return i;
1523 }
1524
1525 #define MPLSINUDP_HDR_SIZE                      (12)
1526
1527 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1528 static inline void
1529 qede_mpls_tunn_tx_sanity_check(struct rte_mbuf *mbuf,
1530                                struct qede_tx_queue *txq)
1531 {
1532         if (((mbuf->outer_l2_len + mbuf->outer_l3_len) / 2) > 0xff)
1533                 PMD_TX_LOG(ERR, txq, "tunn_l4_hdr_start_offset overflow\n");
1534         if (((mbuf->outer_l2_len + mbuf->outer_l3_len +
1535                 MPLSINUDP_HDR_SIZE) / 2) > 0xff)
1536                 PMD_TX_LOG(ERR, txq, "tunn_hdr_size overflow\n");
1537         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE) / 2) >
1538                 ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK)
1539                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1540         if (((mbuf->l2_len - MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2) >
1541                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK)
1542                 PMD_TX_LOG(ERR, txq, "inner_l2_hdr_size overflow\n");
1543 }
1544 #endif
1545
1546 uint16_t
1547 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1548 {
1549         struct qede_tx_queue *txq = p_txq;
1550         struct qede_dev *qdev = txq->qdev;
1551         struct ecore_dev *edev = &qdev->edev;
1552         struct rte_mbuf *mbuf;
1553         struct rte_mbuf *m_seg = NULL;
1554         uint16_t nb_tx_pkts;
1555         uint16_t bd_prod;
1556         uint16_t idx;
1557         uint16_t nb_frags;
1558         uint16_t nb_pkt_sent = 0;
1559         uint8_t nbds;
1560         bool lso_flg;
1561         bool mplsoudp_flg;
1562         __rte_unused bool tunn_flg;
1563         bool tunn_ipv6_ext_flg;
1564         struct eth_tx_1st_bd *bd1;
1565         struct eth_tx_2nd_bd *bd2;
1566         struct eth_tx_3rd_bd *bd3;
1567         uint64_t tx_ol_flags;
1568         uint16_t hdr_size;
1569         /* BD1 */
1570         uint16_t bd1_bf;
1571         uint8_t bd1_bd_flags_bf;
1572         uint16_t vlan;
1573         /* BD2 */
1574         uint16_t bd2_bf1;
1575         uint16_t bd2_bf2;
1576         /* BD3 */
1577         uint16_t mss;
1578         uint16_t bd3_bf;
1579
1580         uint8_t tunn_l4_hdr_start_offset;
1581         uint8_t tunn_hdr_size;
1582         uint8_t inner_l2_hdr_size;
1583         uint16_t inner_l4_hdr_offset;
1584
1585         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1586                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u",
1587                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1588                 qede_process_tx_compl(edev, txq);
1589         }
1590
1591         nb_tx_pkts  = nb_pkts;
1592         bd_prod = rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1593         while (nb_tx_pkts--) {
1594                 /* Init flags/values */
1595                 tunn_flg = false;
1596                 lso_flg = false;
1597                 nbds = 0;
1598                 vlan = 0;
1599                 bd1 = NULL;
1600                 bd2 = NULL;
1601                 bd3 = NULL;
1602                 hdr_size = 0;
1603                 bd1_bf = 0;
1604                 bd1_bd_flags_bf = 0;
1605                 bd2_bf1 = 0;
1606                 bd2_bf2 = 0;
1607                 mss = 0;
1608                 bd3_bf = 0;
1609                 mplsoudp_flg = false;
1610                 tunn_ipv6_ext_flg = false;
1611                 tunn_hdr_size = 0;
1612                 tunn_l4_hdr_start_offset = 0;
1613
1614                 mbuf = *tx_pkts++;
1615                 assert(mbuf);
1616
1617                 /* Check minimum TX BDS availability against available BDs */
1618                 if (unlikely(txq->nb_tx_avail < mbuf->nb_segs))
1619                         break;
1620
1621                 tx_ol_flags = mbuf->ol_flags;
1622                 bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1623
1624                 /* TX prepare would have already checked supported tunnel Tx
1625                  * offloads. Don't rely on pkt_type marked by Rx, instead use
1626                  * tx_ol_flags to decide.
1627                  */
1628                 if (((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1629                                                 PKT_TX_TUNNEL_VXLAN) ||
1630                     ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1631                                                 PKT_TX_TUNNEL_MPLSINUDP)) {
1632                         /* Check against max which is Tunnel IPv6 + ext */
1633                         if (unlikely(txq->nb_tx_avail <
1634                                 ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT))
1635                                         break;
1636                         tunn_flg = true;
1637                         /* First indicate its a tunnel pkt */
1638                         bd1_bf |= ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1639                                   ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1640                         /* Legacy FW had flipped behavior in regard to this bit
1641                          * i.e. it needed to set to prevent FW from touching
1642                          * encapsulated packets when it didn't need to.
1643                          */
1644                         if (unlikely(txq->is_legacy)) {
1645                                 bd1_bf ^= 1 <<
1646                                         ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1647                         }
1648
1649                         /* Outer IP checksum offload */
1650                         if (tx_ol_flags & (PKT_TX_OUTER_IP_CKSUM |
1651                                            PKT_TX_OUTER_IPV4)) {
1652                                 bd1_bd_flags_bf |=
1653                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1654                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1655                         }
1656
1657                         /**
1658                          * Currently, only inner checksum offload in MPLS-in-UDP
1659                          * tunnel with one MPLS label is supported. Both outer
1660                          * and inner layers  lengths need to be provided in
1661                          * mbuf.
1662                          */
1663                         if ((tx_ol_flags & PKT_TX_TUNNEL_MASK) ==
1664                                                 PKT_TX_TUNNEL_MPLSINUDP) {
1665                                 mplsoudp_flg = true;
1666 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1667                                 qede_mpls_tunn_tx_sanity_check(mbuf, txq);
1668 #endif
1669                                 /* Outer L4 offset in two byte words */
1670                                 tunn_l4_hdr_start_offset =
1671                                   (mbuf->outer_l2_len + mbuf->outer_l3_len) / 2;
1672                                 /* Tunnel header size in two byte words */
1673                                 tunn_hdr_size = (mbuf->outer_l2_len +
1674                                                 mbuf->outer_l3_len +
1675                                                 MPLSINUDP_HDR_SIZE) / 2;
1676                                 /* Inner L2 header size in two byte words */
1677                                 inner_l2_hdr_size = (mbuf->l2_len -
1678                                                 MPLSINUDP_HDR_SIZE) / 2;
1679                                 /* Inner L4 header offset from the beggining
1680                                  * of inner packet in two byte words
1681                                  */
1682                                 inner_l4_hdr_offset = (mbuf->l2_len -
1683                                         MPLSINUDP_HDR_SIZE + mbuf->l3_len) / 2;
1684
1685                                 /* TODO: There's no DPDK flag to request outer
1686                                  * L4 checksum offload, so we don't do it.
1687                                  * bd1_bd_flags_bf |=
1688                                  *      ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1689                                  *      ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1690                                  */
1691                                 /* Inner L2 size and address type */
1692                                 bd2_bf1 |= (inner_l2_hdr_size &
1693                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK) <<
1694                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT;
1695                                 bd2_bf1 |= (UNICAST_ADDRESS &
1696                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK) <<
1697                                         ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT;
1698                                 /* Treated as IPv6+Ext */
1699                                 bd2_bf1 |=
1700                                     1 << ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT;
1701
1702                                 /* Mark inner IPv6 if present */
1703                                 if (tx_ol_flags & PKT_TX_IPV6)
1704                                         bd2_bf1 |=
1705                                                 1 << ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT;
1706
1707                                 /* Inner L4 offsets */
1708                                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1709                                      (tx_ol_flags & (PKT_TX_UDP_CKSUM |
1710                                                         PKT_TX_TCP_CKSUM))) {
1711                                         /* Determines if BD3 is needed */
1712                                         tunn_ipv6_ext_flg = true;
1713                                         if ((tx_ol_flags & PKT_TX_L4_MASK) ==
1714                                                         PKT_TX_UDP_CKSUM) {
1715                                                 bd2_bf1 |=
1716                                                         1 << ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT;
1717                                         }
1718
1719                                         /* TODO other pseudo checksum modes are
1720                                          * not supported
1721                                          */
1722                                         bd2_bf1 |=
1723                                         ETH_L4_PSEUDO_CSUM_CORRECT_LENGTH <<
1724                                         ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT;
1725                                         bd2_bf2 |= (inner_l4_hdr_offset &
1726                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK) <<
1727                                                 ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT;
1728                                 }
1729                         } /* End MPLSoUDP */
1730                 } /* End Tunnel handling */
1731
1732                 if (tx_ol_flags & PKT_TX_TCP_SEG) {
1733                         lso_flg = true;
1734                         if (unlikely(txq->nb_tx_avail <
1735                                                 ETH_TX_MIN_BDS_PER_LSO_PKT))
1736                                 break;
1737                         /* For LSO, packet header and payload must reside on
1738                          * buffers pointed by different BDs. Using BD1 for HDR
1739                          * and BD2 onwards for data.
1740                          */
1741                         hdr_size = mbuf->l2_len + mbuf->l3_len + mbuf->l4_len;
1742                         bd1_bd_flags_bf |= 1 << ETH_TX_1ST_BD_FLAGS_LSO_SHIFT;
1743                         bd1_bd_flags_bf |=
1744                                         1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1745                         /* PKT_TX_TCP_SEG implies PKT_TX_TCP_CKSUM */
1746                         bd1_bd_flags_bf |=
1747                                         1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1748                         mss = rte_cpu_to_le_16(mbuf->tso_segsz);
1749                         /* Using one header BD */
1750                         bd3_bf |= rte_cpu_to_le_16(1 <<
1751                                         ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT);
1752                 } else {
1753                         if (unlikely(txq->nb_tx_avail <
1754                                         ETH_TX_MIN_BDS_PER_NON_LSO_PKT))
1755                                 break;
1756                         bd1_bf |=
1757                                (mbuf->pkt_len & ETH_TX_DATA_1ST_BD_PKT_LEN_MASK)
1758                                 << ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT;
1759                 }
1760
1761                 /* Descriptor based VLAN insertion */
1762                 if (tx_ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1763                         vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1764                         bd1_bd_flags_bf |=
1765                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1766                 }
1767
1768                 /* Offload the IP checksum in the hardware */
1769                 if (tx_ol_flags & PKT_TX_IP_CKSUM)
1770                         bd1_bd_flags_bf |=
1771                                 1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1772
1773                 /* L4 checksum offload (tcp or udp) */
1774                 if ((tx_ol_flags & (PKT_TX_IPV4 | PKT_TX_IPV6)) &&
1775                     (tx_ol_flags & (PKT_TX_UDP_CKSUM | PKT_TX_TCP_CKSUM))) {
1776                         bd1_bd_flags_bf |=
1777                                 1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1778                 }
1779
1780                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1781                 idx = TX_PROD(txq);
1782                 txq->sw_tx_ring[idx].mbuf = mbuf;
1783
1784                 /* BD1 */
1785                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1786                 memset(bd1, 0, sizeof(struct eth_tx_1st_bd));
1787                 nbds++;
1788
1789                 /* Map MBUF linear data for DMA and set in the BD1 */
1790                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1791                                      mbuf->data_len);
1792                 bd1->data.bitfields = rte_cpu_to_le_16(bd1_bf);
1793                 bd1->data.bd_flags.bitfields = bd1_bd_flags_bf;
1794                 bd1->data.vlan = vlan;
1795
1796                 if (lso_flg || mplsoudp_flg) {
1797                         bd2 = (struct eth_tx_2nd_bd *)ecore_chain_produce
1798                                                         (&txq->tx_pbl);
1799                         memset(bd2, 0, sizeof(struct eth_tx_2nd_bd));
1800                         nbds++;
1801
1802                         /* BD1 */
1803                         QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1804                                              hdr_size);
1805                         /* BD2 */
1806                         QEDE_BD_SET_ADDR_LEN(bd2, (hdr_size +
1807                                              rte_mbuf_data_dma_addr(mbuf)),
1808                                              mbuf->data_len - hdr_size);
1809                         bd2->data.bitfields1 = rte_cpu_to_le_16(bd2_bf1);
1810                         if (mplsoudp_flg) {
1811                                 bd2->data.bitfields2 =
1812                                         rte_cpu_to_le_16(bd2_bf2);
1813                                 /* Outer L3 size */
1814                                 bd2->data.tunn_ip_size =
1815                                         rte_cpu_to_le_16(mbuf->outer_l3_len);
1816                         }
1817                         /* BD3 */
1818                         if (lso_flg || (mplsoudp_flg && tunn_ipv6_ext_flg)) {
1819                                 bd3 = (struct eth_tx_3rd_bd *)
1820                                         ecore_chain_produce(&txq->tx_pbl);
1821                                 memset(bd3, 0, sizeof(struct eth_tx_3rd_bd));
1822                                 nbds++;
1823                                 bd3->data.bitfields = rte_cpu_to_le_16(bd3_bf);
1824                                 if (lso_flg)
1825                                         bd3->data.lso_mss = mss;
1826                                 if (mplsoudp_flg) {
1827                                         bd3->data.tunn_l4_hdr_start_offset_w =
1828                                                 tunn_l4_hdr_start_offset;
1829                                         bd3->data.tunn_hdr_size_w =
1830                                                 tunn_hdr_size;
1831                                 }
1832                         }
1833                 }
1834
1835                 /* Handle fragmented MBUF */
1836                 m_seg = mbuf->next;
1837                 /* Encode scatter gather buffer descriptors if required */
1838                 nb_frags = qede_encode_sg_bd(txq, m_seg, &bd2, &bd3);
1839                 bd1->data.nbds = nbds + nb_frags;
1840                 txq->nb_tx_avail -= bd1->data.nbds;
1841                 txq->sw_tx_prod++;
1842                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1843                 bd_prod =
1844                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1845 #ifdef RTE_LIBRTE_QEDE_DEBUG_TX
1846                 print_tx_bd_info(txq, bd1, bd2, bd3, tx_ol_flags);
1847                 PMD_TX_LOG(INFO, txq, "lso=%d tunn=%d", lso_flg, tunn_flg);
1848 #endif
1849                 nb_pkt_sent++;
1850                 txq->xmit_pkts++;
1851         }
1852
1853         /* Write value of prod idx into bd_prod */
1854         txq->tx_db.data.bd_prod = bd_prod;
1855         rte_wmb();
1856         rte_compiler_barrier();
1857         DIRECT_REG_WR_RELAXED(edev, txq->doorbell_addr, txq->tx_db.raw);
1858         rte_wmb();
1859
1860         /* Check again for Tx completions */
1861         qede_process_tx_compl(edev, txq);
1862
1863         PMD_TX_LOG(DEBUG, txq, "to_send=%u sent=%u bd_prod=%u core=%d",
1864                    nb_pkts, nb_pkt_sent, TX_PROD(txq), rte_lcore_id());
1865
1866         return nb_pkt_sent;
1867 }
1868
1869 uint16_t
1870 qede_rxtx_pkts_dummy(__rte_unused void *p_rxq,
1871                      __rte_unused struct rte_mbuf **pkts,
1872                      __rte_unused uint16_t nb_pkts)
1873 {
1874         return 0;
1875 }