drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 #define QEDE_FASTPATH_TX        (1 << 0)
  14 #define QEDE_FASTPATH_RX        (1 << 1)
  15
  16 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  17 {
  18         struct rte_mbuf *new_mb = NULL;
  19         struct eth_rx_bd *rx_bd;
  20         dma_addr_t mapping;
  21         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  22
  23         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  24         if (unlikely(!new_mb)) {
  25                 PMD_RX_LOG(ERR, rxq,
  26                            "Failed to allocate rx buffer "
  27                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  28                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  29                            rte_mempool_avail_count(rxq->mb_pool),
  30                            rte_mempool_in_use_count(rxq->mb_pool));
  31                 return -ENOMEM;
  32         }
  33         rxq->sw_rx_ring[idx].mbuf = new_mb;
  34         rxq->sw_rx_ring[idx].page_offset = 0;
  35         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  36         /* Advance PROD and get BD pointer */
  37         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  38         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  39         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  40         rxq->sw_rx_prod++;
  41         return 0;
  42 }
  43
  44 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  45 {
  46         uint16_t i;
  47
  48         if (rxq->sw_rx_ring != NULL) {
  49                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  50                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  51                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  52                                 rxq->sw_rx_ring[i].mbuf = NULL;
  53                         }
  54                 }
  55         }
  56 }
  57
  58 void qede_rx_queue_release(void *rx_queue)
  59 {
  60         struct qede_rx_queue *rxq = rx_queue;
  61
  62         if (rxq != NULL) {
  63                 qede_rx_queue_release_mbufs(rxq);
  64                 rte_free(rxq->sw_rx_ring);
  65                 rxq->sw_rx_ring = NULL;
  66                 rte_free(rxq);
  67                 rxq = NULL;
  68         }
  69 }
  70
  71 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  72 {
  73         unsigned int i;
  74
  75         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
  76
  77         if (txq->sw_tx_ring) {
  78                 for (i = 0; i < txq->nb_tx_desc; i++) {
  79                         if (txq->sw_tx_ring[i].mbuf) {
  80                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  81                                 txq->sw_tx_ring[i].mbuf = NULL;
  82                         }
  83                 }
  84         }
  85 }
  86
  87 int
  88 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  89                     uint16_t nb_desc, unsigned int socket_id,
  90                     const struct rte_eth_rxconf *rx_conf,
  91                     struct rte_mempool *mp)
  92 {
  93         struct qede_dev *qdev = dev->data->dev_private;
  94         struct ecore_dev *edev = &qdev->edev;
  95         struct rte_eth_dev_data *eth_data = dev->data;
  96         struct qede_rx_queue *rxq;
  97         uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
  98         size_t size;
  99         uint16_t data_size;
 100         int rc;
 101         int i;
 102
 103         PMD_INIT_FUNC_TRACE(edev);
 104
 105         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 106         if (!rte_is_power_of_2(nb_desc)) {
 107                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 108                           nb_desc);
 109                 return -EINVAL;
 110         }
 111
 112         /* Free memory prior to re-allocation if needed... */
 113         if (dev->data->rx_queues[queue_idx] != NULL) {
 114                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 115                 dev->data->rx_queues[queue_idx] = NULL;
 116         }
 117
 118         /* First allocate the rx queue data structure */
 119         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 120                                  RTE_CACHE_LINE_SIZE, socket_id);
 121
 122         if (!rxq) {
 123                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 124                           socket_id);
 125                 return -ENOMEM;
 126         }
 127
 128         rxq->qdev = qdev;
 129         rxq->mb_pool = mp;
 130         rxq->nb_rx_desc = nb_desc;
 131         rxq->queue_id = queue_idx;
 132         rxq->port_id = dev->data->port_id;
 133
 134         /* Sanity check */
 135         data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
 136                                 RTE_PKTMBUF_HEADROOM;
 137
 138         if (pkt_len > data_size && !dev->data->scattered_rx) {
 139                 DP_ERR(edev, "MTU %u should not exceed dataroom %u\n",
 140                        pkt_len, data_size);
 141                 rte_free(rxq);
 142                 return -EINVAL;
 143         }
 144
 145         if (dev->data->scattered_rx)
 146                 rxq->rx_buf_size = data_size;
 147         else
 148                 rxq->rx_buf_size = pkt_len + QEDE_ETH_OVERHEAD;
 149
 150         qdev->mtu = pkt_len;
 151
 152         DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
 153                 qdev->mtu, rxq->rx_buf_size);
 154
 155         if (pkt_len > ETHER_MAX_LEN) {
 156                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 157                 DP_NOTICE(edev, false, "jumbo frame enabled\n");
 158         } else {
 159                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 160         }
 161
 162         /* Allocate the parallel driver ring for Rx buffers */
 163         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 164         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 165                                              RTE_CACHE_LINE_SIZE, socket_id);
 166         if (!rxq->sw_rx_ring) {
 167                 DP_NOTICE(edev, false,
 168                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 169                           socket_id);
 170                 rte_free(rxq);
 171                 rxq = NULL;
 172                 return -ENOMEM;
 173         }
 174
 175         /* Allocate FW Rx ring  */
 176         rc = qdev->ops->common->chain_alloc(edev,
 177                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 178                                             ECORE_CHAIN_MODE_NEXT_PTR,
 179                                             ECORE_CHAIN_CNT_TYPE_U16,
 180                                             rxq->nb_rx_desc,
 181                                             sizeof(struct eth_rx_bd),
 182                                             &rxq->rx_bd_ring);
 183
 184         if (rc != ECORE_SUCCESS) {
 185                 DP_NOTICE(edev, false,
 186                           "Unable to alloc memory for rxbd ring on socket %u\n",
 187                           socket_id);
 188                 rte_free(rxq->sw_rx_ring);
 189                 rxq->sw_rx_ring = NULL;
 190                 rte_free(rxq);
 191                 rxq = NULL;
 192                 return -ENOMEM;
 193         }
 194
 195         /* Allocate FW completion ring */
 196         rc = qdev->ops->common->chain_alloc(edev,
 197                                             ECORE_CHAIN_USE_TO_CONSUME,
 198                                             ECORE_CHAIN_MODE_PBL,
 199                                             ECORE_CHAIN_CNT_TYPE_U16,
 200                                             rxq->nb_rx_desc,
 201                                             sizeof(union eth_rx_cqe),
 202                                             &rxq->rx_comp_ring);
 203
 204         if (rc != ECORE_SUCCESS) {
 205                 DP_NOTICE(edev, false,
 206                           "Unable to alloc memory for cqe ring on socket %u\n",
 207                           socket_id);
 208                 /* TBD: Freeing RX BD ring */
 209                 rte_free(rxq->sw_rx_ring);
 210                 rxq->sw_rx_ring = NULL;
 211                 rte_free(rxq);
 212                 return -ENOMEM;
 213         }
 214
 215         /* Allocate buffers for the Rx ring */
 216         for (i = 0; i < rxq->nb_rx_desc; i++) {
 217                 rc = qede_alloc_rx_buffer(rxq);
 218                 if (rc) {
 219                         DP_NOTICE(edev, false,
 220                                   "RX buffer allocation failed at idx=%d\n", i);
 221                         goto err4;
 222                 }
 223         }
 224
 225         dev->data->rx_queues[queue_idx] = rxq;
 226
 227         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 228                   queue_idx, nb_desc, qdev->mtu, socket_id);
 229
 230         return 0;
 231 err4:
 232         qede_rx_queue_release(rxq);
 233         return -ENOMEM;
 234 }
 235
 236 void qede_tx_queue_release(void *tx_queue)
 237 {
 238         struct qede_tx_queue *txq = tx_queue;
 239
 240         if (txq != NULL) {
 241                 qede_tx_queue_release_mbufs(txq);
 242                 if (txq->sw_tx_ring) {
 243                         rte_free(txq->sw_tx_ring);
 244                         txq->sw_tx_ring = NULL;
 245                 }
 246                 rte_free(txq);
 247         }
 248         txq = NULL;
 249 }
 250
 251 int
 252 qede_tx_queue_setup(struct rte_eth_dev *dev,
 253                     uint16_t queue_idx,
 254                     uint16_t nb_desc,
 255                     unsigned int socket_id,
 256                     const struct rte_eth_txconf *tx_conf)
 257 {
 258         struct qede_dev *qdev = dev->data->dev_private;
 259         struct ecore_dev *edev = &qdev->edev;
 260         struct qede_tx_queue *txq;
 261         int rc;
 262
 263         PMD_INIT_FUNC_TRACE(edev);
 264
 265         if (!rte_is_power_of_2(nb_desc)) {
 266                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 267                        nb_desc);
 268                 return -EINVAL;
 269         }
 270
 271         /* Free memory prior to re-allocation if needed... */
 272         if (dev->data->tx_queues[queue_idx] != NULL) {
 273                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 274                 dev->data->tx_queues[queue_idx] = NULL;
 275         }
 276
 277         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 278                                  RTE_CACHE_LINE_SIZE, socket_id);
 279
 280         if (txq == NULL) {
 281                 DP_ERR(edev,
 282                        "Unable to allocate memory for txq on socket %u",
 283                        socket_id);
 284                 return -ENOMEM;
 285         }
 286
 287         txq->nb_tx_desc = nb_desc;
 288         txq->qdev = qdev;
 289         txq->port_id = dev->data->port_id;
 290
 291         rc = qdev->ops->common->chain_alloc(edev,
 292                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 293                                             ECORE_CHAIN_MODE_PBL,
 294                                             ECORE_CHAIN_CNT_TYPE_U16,
 295                                             txq->nb_tx_desc,
 296                                             sizeof(union eth_tx_bd_types),
 297                                             &txq->tx_pbl);
 298         if (rc != ECORE_SUCCESS) {
 299                 DP_ERR(edev,
 300                        "Unable to allocate memory for txbd ring on socket %u",
 301                        socket_id);
 302                 qede_tx_queue_release(txq);
 303                 return -ENOMEM;
 304         }
 305
 306         /* Allocate software ring */
 307         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 308                                              (sizeof(struct qede_tx_entry) *
 309                                               txq->nb_tx_desc),
 310                                              RTE_CACHE_LINE_SIZE, socket_id);
 311
 312         if (!txq->sw_tx_ring) {
 313                 DP_ERR(edev,
 314                        "Unable to allocate memory for txbd ring on socket %u",
 315                        socket_id);
 316                 qede_tx_queue_release(txq);
 317                 return -ENOMEM;
 318         }
 319
 320         txq->queue_id = queue_idx;
 321
 322         txq->nb_tx_avail = txq->nb_tx_desc;
 323
 324         txq->tx_free_thresh =
 325             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 326             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 327
 328         dev->data->tx_queues[queue_idx] = txq;
 329
 330         DP_INFO(edev,
 331                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 332                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 333
 334         return 0;
 335 }
 336
 337 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 338 static void qede_init_fp(struct qede_dev *qdev)
 339 {
 340         struct qede_fastpath *fp;
 341         uint8_t i, rss_id, tc;
 342         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 343
 344         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 345                                            sizeof(*qdev->fp_array)));
 346         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 347                                            sizeof(*qdev->sb_array)));
 348         for_each_queue(i) {
 349                 fp = &qdev->fp_array[i];
 350                 if (fp_rx) {
 351                         fp->type = QEDE_FASTPATH_RX;
 352                         fp_rx--;
 353                 } else{
 354                         fp->type = QEDE_FASTPATH_TX;
 355                 }
 356                 fp->qdev = qdev;
 357                 fp->id = i;
 358                 fp->sb_info = &qdev->sb_array[i];
 359                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 360         }
 361
 362         qdev->gro_disable = gro_disable;
 363 }
 364
 365 void qede_free_fp_arrays(struct qede_dev *qdev)
 366 {
 367         /* It asseumes qede_free_mem_load() is called before */
 368         if (qdev->fp_array != NULL) {
 369                 rte_free(qdev->fp_array);
 370                 qdev->fp_array = NULL;
 371         }
 372
 373         if (qdev->sb_array != NULL) {
 374                 rte_free(qdev->sb_array);
 375                 qdev->sb_array = NULL;
 376         }
 377 }
 378
 379 int qede_alloc_fp_array(struct qede_dev *qdev)
 380 {
 381         struct qede_fastpath *fp;
 382         struct ecore_dev *edev = &qdev->edev;
 383         int i;
 384
 385         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 386                                     sizeof(*qdev->fp_array),
 387                                     RTE_CACHE_LINE_SIZE);
 388
 389         if (!qdev->fp_array) {
 390                 DP_ERR(edev, "fp array allocation failed\n");
 391                 return -ENOMEM;
 392         }
 393
 394         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 395                                     sizeof(*qdev->sb_array),
 396                                     RTE_CACHE_LINE_SIZE);
 397
 398         if (!qdev->sb_array) {
 399                 DP_ERR(edev, "sb array allocation failed\n");
 400                 rte_free(qdev->fp_array);
 401                 return -ENOMEM;
 402         }
 403
 404         return 0;
 405 }
 406
 407 /* This function allocates fast-path status block memory */
 408 static int
 409 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 410                   uint16_t sb_id)
 411 {
 412         struct ecore_dev *edev = &qdev->edev;
 413         struct status_block *sb_virt;
 414         dma_addr_t sb_phys;
 415         int rc;
 416
 417         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 418
 419         if (!sb_virt) {
 420                 DP_ERR(edev, "Status block allocation failed\n");
 421                 return -ENOMEM;
 422         }
 423
 424         rc = qdev->ops->common->sb_init(edev, sb_info,
 425                                         sb_virt, sb_phys, sb_id,
 426                                         QED_SB_TYPE_L2_QUEUE);
 427         if (rc) {
 428                 DP_ERR(edev, "Status block initialization failed\n");
 429                 /* TBD: No dma_free_coherent possible */
 430                 return rc;
 431         }
 432
 433         return 0;
 434 }
 435
 436 int qede_alloc_fp_resc(struct qede_dev *qdev)
 437 {
 438         struct ecore_dev *edev = &qdev->edev;
 439         struct qede_fastpath *fp;
 440         uint32_t num_sbs;
 441         int rc, i;
 442
 443         if (IS_VF(edev))
 444                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 445         else
 446                 num_sbs = (ecore_cxt_get_proto_cid_count
 447                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL)) / 2;
 448
 449         if (num_sbs == 0) {
 450                 DP_ERR(edev, "No status blocks available\n");
 451                 return -EINVAL;
 452         }
 453
 454         if (qdev->fp_array)
 455                 qede_free_fp_arrays(qdev);
 456
 457         rc = qede_alloc_fp_array(qdev);
 458         if (rc != 0)
 459                 return rc;
 460
 461         qede_init_fp(qdev);
 462
 463         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 464                 fp = &qdev->fp_array[i];
 465                 if (qede_alloc_mem_sb(qdev, fp->sb_info, i % num_sbs)) {
 466                         qede_free_fp_arrays(qdev);
 467                         return -ENOMEM;
 468                 }
 469         }
 470
 471         return 0;
 472 }
 473
 474 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 475 {
 476         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 477
 478         qede_free_mem_load(eth_dev);
 479         qede_free_fp_arrays(qdev);
 480 }
 481
 482 static inline void
 483 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 484 {
 485         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 486         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 487         struct eth_rx_prod_data rx_prods = { 0 };
 488
 489         /* Update producers */
 490         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 491         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 492
 493         /* Make sure that the BD and SGE data is updated before updating the
 494          * producers since FW might read the BD/SGE right after the producer
 495          * is updated.
 496          */
 497         rte_wmb();
 498
 499         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 500                         (uint32_t *)&rx_prods);
 501
 502         /* mmiowb is needed to synchronize doorbell writes from more than one
 503          * processor. It guarantees that the write arrives to the device before
 504          * the napi lock is released and another qede_poll is called (possibly
 505          * on another CPU). Without this barrier, the next doorbell can bypass
 506          * this doorbell. This is applicable to IA64/Altix systems.
 507          */
 508         rte_wmb();
 509
 510         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u\n", bd_prod, cqe_prod);
 511 }
 512
 513 static inline uint32_t
 514 qede_rxfh_indir_default(uint32_t index, uint32_t n_rx_rings)
 515 {
 516         return index % n_rx_rings;
 517 }
 518
 519 static void qede_prandom_bytes(uint32_t *buff, size_t bytes)
 520 {
 521         unsigned int i;
 522
 523         srand((unsigned int)time(NULL));
 524
 525         for (i = 0; i < ECORE_RSS_KEY_SIZE; i++)
 526                 buff[i] = rand();
 527 }
 528
 529 static bool
 530 qede_check_vport_rss_enable(struct rte_eth_dev *eth_dev,
 531                             struct qed_update_vport_rss_params *rss_params)
 532 {
 533         struct rte_eth_rss_conf rss_conf;
 534         enum rte_eth_rx_mq_mode mode = eth_dev->data->dev_conf.rxmode.mq_mode;
 535         struct qede_dev *qdev = eth_dev->data->dev_private;
 536         struct ecore_dev *edev = &qdev->edev;
 537         uint8_t rss_caps;
 538         unsigned int i;
 539         uint64_t hf;
 540         uint32_t *key;
 541
 542         PMD_INIT_FUNC_TRACE(edev);
 543
 544         rss_conf = eth_dev->data->dev_conf.rx_adv_conf.rss_conf;
 545         key = (uint32_t *)rss_conf.rss_key;
 546         hf = rss_conf.rss_hf;
 547
 548         /* Check if RSS conditions are met.
 549          * Note: Even though its meaningless to enable RSS with one queue, it
 550          * could be used to produce RSS Hash, so skipping that check.
 551          */
 552         if (!(mode & ETH_MQ_RX_RSS)) {
 553                 DP_INFO(edev, "RSS flag is not set\n");
 554                 return false;
 555         }
 556
 557         if (hf == 0) {
 558                 DP_INFO(edev, "Request to disable RSS\n");
 559                 return false;
 560         }
 561
 562         memset(rss_params, 0, sizeof(*rss_params));
 563
 564         for (i = 0; i < ECORE_RSS_IND_TABLE_SIZE; i++)
 565                 rss_params->rss_ind_table[i] = qede_rxfh_indir_default(i,
 566                                                         QEDE_RSS_COUNT(qdev));
 567
 568         if (!key)
 569                 qede_prandom_bytes(rss_params->rss_key,
 570                                    sizeof(rss_params->rss_key));
 571         else
 572                 memcpy(rss_params->rss_key, rss_conf.rss_key,
 573                        rss_conf.rss_key_len);
 574
 575         qede_init_rss_caps(&rss_caps, hf);
 576
 577         rss_params->rss_caps = rss_caps;
 578
 579         DP_INFO(edev, "RSS conditions are met\n");
 580
 581         return true;
 582 }
 583
 584 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 585 {
 586         struct qede_dev *qdev = eth_dev->data->dev_private;
 587         struct ecore_dev *edev = &qdev->edev;
 588         struct ecore_queue_start_common_params q_params;
 589         struct qed_update_vport_rss_params *rss_params = &qdev->rss_params;
 590         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 591         struct qed_update_vport_params vport_update_params;
 592         struct qede_tx_queue *txq;
 593         struct qede_fastpath *fp;
 594         dma_addr_t p_phys_table;
 595         int txq_index;
 596         uint16_t page_cnt;
 597         int vlan_removal_en = 1;
 598         int rc, tc, i;
 599
 600         for_each_queue(i) {
 601                 fp = &qdev->fp_array[i];
 602                 if (fp->type & QEDE_FASTPATH_RX) {
 603                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 604                                                                 rx_comp_ring);
 605                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 606                                                                 rx_comp_ring);
 607
 608                         memset(&q_params, 0, sizeof(q_params));
 609                         q_params.queue_id = i;
 610                         q_params.vport_id = 0;
 611                         q_params.sb = fp->sb_info->igu_sb_id;
 612                         q_params.sb_idx = RX_PI;
 613
 614                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 615
 616                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 617                                            fp->rxq->rx_buf_size,
 618                                            fp->rxq->rx_bd_ring.p_phys_addr,
 619                                            p_phys_table,
 620                                            page_cnt,
 621                                            &fp->rxq->hw_rxq_prod_addr);
 622                         if (rc) {
 623                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 624                                        fp->rxq->queue_id, rc);
 625                                 return rc;
 626                         }
 627
 628                         fp->rxq->hw_cons_ptr =
 629                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 630
 631                         qede_update_rx_prod(qdev, fp->rxq);
 632                 }
 633
 634                 if (!(fp->type & QEDE_FASTPATH_TX))
 635                         continue;
 636                 for (tc = 0; tc < qdev->num_tc; tc++) {
 637                         txq = fp->txqs[tc];
 638                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 639
 640                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 641                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 642
 643                         memset(&q_params, 0, sizeof(q_params));
 644                         q_params.queue_id = txq->queue_id;
 645                         q_params.vport_id = 0;
 646                         q_params.sb = fp->sb_info->igu_sb_id;
 647                         q_params.sb_idx = TX_PI(tc);
 648
 649                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 650                                                    p_phys_table,
 651                                                    page_cnt, /* **pp_doorbell */
 652                                                    &txq->doorbell_addr);
 653                         if (rc) {
 654                                 DP_ERR(edev, "Start txq %u failed %d\n",
 655                                        txq_index, rc);
 656                                 return rc;
 657                         }
 658
 659                         txq->hw_cons_ptr =
 660                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 661                         SET_FIELD(txq->tx_db.data.params,
 662                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 663                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 664                                   DB_AGG_CMD_SET);
 665                         SET_FIELD(txq->tx_db.data.params,
 666                                   ETH_DB_DATA_AGG_VAL_SEL,
 667                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 668
 669                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 670                 }
 671         }
 672
 673         /* Prepare and send the vport enable */
 674         memset(&vport_update_params, 0, sizeof(vport_update_params));
 675         /* Update MTU via vport update */
 676         vport_update_params.mtu = qdev->mtu;
 677         vport_update_params.vport_id = 0;
 678         vport_update_params.update_vport_active_flg = 1;
 679         vport_update_params.vport_active_flg = 1;
 680
 681         /* @DPDK */
 682         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 683                 /* TBD: Check SRIOV enabled for VF */
 684                 vport_update_params.update_tx_switching_flg = 1;
 685                 vport_update_params.tx_switching_flg = 1;
 686         }
 687
 688         if (qede_check_vport_rss_enable(eth_dev, rss_params)) {
 689                 vport_update_params.update_rss_flg = 1;
 690                 qdev->rss_enabled = 1;
 691         } else {
 692                 qdev->rss_enabled = 0;
 693         }
 694
 695         rte_memcpy(&vport_update_params.rss_params, rss_params,
 696                sizeof(*rss_params));
 697
 698         rc = qdev->ops->vport_update(edev, &vport_update_params);
 699         if (rc) {
 700                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 701                 return rc;
 702         }
 703
 704         return 0;
 705 }
 706
 707 #ifdef ENC_SUPPORTED
 708 static bool qede_tunn_exist(uint16_t flag)
 709 {
 710         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 711                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 712 }
 713
 714 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
 715 {
 716         uint8_t tcsum = 0;
 717         uint16_t csum_flag = 0;
 718
 719         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 720              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 721                 csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 722                     PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT;
 723
 724         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 725              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
 726                 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 727                     PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
 728                 tcsum = QEDE_TUNN_CSUM_UNNECESSARY;
 729         }
 730
 731         csum_flag |= PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK <<
 732             PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT |
 733             PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 734             PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
 735
 736         if (csum_flag & flag)
 737                 return QEDE_CSUM_ERROR;
 738
 739         return QEDE_CSUM_UNNECESSARY | tcsum;
 740 }
 741 #else
 742 static inline uint8_t qede_tunn_exist(uint16_t flag)
 743 {
 744         return 0;
 745 }
 746
 747 static inline uint8_t qede_check_tunn_csum(uint16_t flag)
 748 {
 749         return 0;
 750 }
 751 #endif
 752
 753 static inline uint8_t qede_check_notunn_csum(uint16_t flag)
 754 {
 755         uint8_t csum = 0;
 756         uint16_t csum_flag = 0;
 757
 758         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 759              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag) {
 760                 csum_flag |= PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 761                     PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT;
 762                 csum = QEDE_CSUM_UNNECESSARY;
 763         }
 764
 765         csum_flag |= PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 766             PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT;
 767
 768         if (csum_flag & flag)
 769                 return QEDE_CSUM_ERROR;
 770
 771         return csum;
 772 }
 773
 774 static inline uint8_t qede_check_csum(uint16_t flag)
 775 {
 776         if (likely(!qede_tunn_exist(flag)))
 777                 return qede_check_notunn_csum(flag);
 778         else
 779                 return qede_check_tunn_csum(flag);
 780 }
 781
 782 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 783 {
 784         ecore_chain_consume(&rxq->rx_bd_ring);
 785         rxq->sw_rx_cons++;
 786 }
 787
 788 static inline void
 789 qede_reuse_page(struct qede_dev *qdev,
 790                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 791 {
 792         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 793         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 794         struct qede_rx_entry *curr_prod;
 795         dma_addr_t new_mapping;
 796
 797         curr_prod = &rxq->sw_rx_ring[idx];
 798         *curr_prod = *curr_cons;
 799
 800         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 801                       curr_prod->page_offset;
 802
 803         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 804         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 805
 806         rxq->sw_rx_prod++;
 807 }
 808
 809 static inline void
 810 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 811                         struct qede_dev *qdev, uint8_t count)
 812 {
 813         struct qede_rx_entry *curr_cons;
 814
 815         for (; count > 0; count--) {
 816                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 817                 qede_reuse_page(qdev, rxq, curr_cons);
 818                 qede_rx_bd_ring_consume(rxq);
 819         }
 820 }
 821
 822 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 823 {
 824         uint32_t p_type;
 825         /* TBD - L4 indications needed ? */
 826         uint16_t protocol = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 827                               PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) & flags);
 828
 829         /* protocol = 3 means LLC/SNAP over Ethernet */
 830         if (unlikely(protocol == 0 || protocol == 3))
 831                 p_type = RTE_PTYPE_UNKNOWN;
 832         else if (protocol == 1)
 833                 p_type = RTE_PTYPE_L3_IPV4;
 834         else if (protocol == 2)
 835                 p_type = RTE_PTYPE_L3_IPV6;
 836
 837         return RTE_PTYPE_L2_ETHER | p_type;
 838 }
 839
 840 int qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 841                          int num_frags, uint16_t pkt_len)
 842 {
 843         struct qede_rx_queue *rxq = p_rxq;
 844         struct qede_dev *qdev = rxq->qdev;
 845         struct ecore_dev *edev = &qdev->edev;
 846         uint16_t sw_rx_index, cur_size;
 847
 848         register struct rte_mbuf *seg1 = NULL;
 849         register struct rte_mbuf *seg2 = NULL;
 850
 851         seg1 = rx_mb;
 852         while (num_frags) {
 853                 cur_size = pkt_len > rxq->rx_buf_size ?
 854                                 rxq->rx_buf_size : pkt_len;
 855                 if (!cur_size) {
 856                         PMD_RX_LOG(DEBUG, rxq,
 857                                    "SG packet, len and num BD mismatch\n");
 858                         qede_recycle_rx_bd_ring(rxq, qdev, num_frags);
 859                         return -EINVAL;
 860                 }
 861
 862                 if (qede_alloc_rx_buffer(rxq)) {
 863                         uint8_t index;
 864
 865                         PMD_RX_LOG(DEBUG, rxq, "Buffer allocation failed\n");
 866                         index = rxq->port_id;
 867                         rte_eth_devices[index].data->rx_mbuf_alloc_failed++;
 868                         rxq->rx_alloc_errors++;
 869                         return -ENOMEM;
 870                 }
 871
 872                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 873                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 874                 qede_rx_bd_ring_consume(rxq);
 875                 pkt_len -= cur_size;
 876                 seg2->data_len = cur_size;
 877                 seg1->next = seg2;
 878                 seg1 = seg1->next;
 879                 num_frags--;
 880                 continue;
 881         }
 882         seg1 = NULL;
 883
 884         if (pkt_len)
 885                 PMD_RX_LOG(DEBUG, rxq,
 886                            "Mapped all BDs of jumbo, but still have %d bytes\n",
 887                            pkt_len);
 888
 889         return ECORE_SUCCESS;
 890 }
 891
 892 uint16_t
 893 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 894 {
 895         struct qede_rx_queue *rxq = p_rxq;
 896         struct qede_dev *qdev = rxq->qdev;
 897         struct ecore_dev *edev = &qdev->edev;
 898         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 899         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 900         uint16_t rx_pkt = 0;
 901         union eth_rx_cqe *cqe;
 902         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 903         register struct rte_mbuf *rx_mb = NULL;
 904         register struct rte_mbuf *seg1 = NULL;
 905         enum eth_rx_cqe_type cqe_type;
 906         uint16_t len, pad, preload_idx, pkt_len, parse_flag;
 907         uint8_t csum_flag, num_frags;
 908         enum rss_hash_type htype;
 909         int ret;
 910
 911         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 912         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 913
 914         rte_rmb();
 915
 916         if (hw_comp_cons == sw_comp_cons)
 917                 return 0;
 918
 919         while (sw_comp_cons != hw_comp_cons) {
 920                 /* Get the CQE from the completion ring */
 921                 cqe =
 922                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 923                 cqe_type = cqe->fast_path_regular.type;
 924
 925                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 926                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
 927
 928                         qdev->ops->eth_cqe_completion(edev, fp->id,
 929                                 (struct eth_slow_path_rx_cqe *)cqe);
 930                         goto next_cqe;
 931                 }
 932
 933                 /* Get the data from the SW ring */
 934                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 935                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 936                 assert(rx_mb != NULL);
 937
 938                 /* non GRO */
 939                 fp_cqe = &cqe->fast_path_regular;
 940
 941                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 942                 pad = fp_cqe->placement_offset;
 943                 assert((len + pad) <= rx_mb->buf_len);
 944
 945                 PMD_RX_LOG(DEBUG, rxq,
 946                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 947                            " len = %u, parsing_flags = %d\n",
 948                            cqe_type, fp_cqe->bitfields,
 949                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 950                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 951
 952                 /* If this is an error packet then drop it */
 953                 parse_flag =
 954                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 955                 csum_flag = qede_check_csum(parse_flag);
 956                 if (unlikely(csum_flag == QEDE_CSUM_ERROR)) {
 957                         PMD_RX_LOG(ERR, rxq,
 958                                    "CQE in CONS = %u has error, flags = 0x%x "
 959                                    "dropping incoming packet\n",
 960                                    sw_comp_cons, parse_flag);
 961                         rxq->rx_hw_errors++;
 962                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 963                         goto next_cqe;
 964                 }
 965
 966                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 967                         PMD_RX_LOG(ERR, rxq,
 968                                    "New buffer allocation failed,"
 969                                    "dropping incoming packet\n");
 970                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 971                         rte_eth_devices[rxq->port_id].
 972                             data->rx_mbuf_alloc_failed++;
 973                         rxq->rx_alloc_errors++;
 974                         break;
 975                 }
 976
 977                 qede_rx_bd_ring_consume(rxq);
 978
 979                 if (fp_cqe->bd_num > 1) {
 980                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 981                         num_frags = fp_cqe->bd_num - 1;
 982
 983                         pkt_len -= len;
 984                         seg1 = rx_mb;
 985                         ret = qede_process_sg_pkts(p_rxq, seg1, num_frags,
 986                                                    pkt_len);
 987                         if (ret != ECORE_SUCCESS) {
 988                                 qede_recycle_rx_bd_ring(rxq, qdev,
 989                                                         fp_cqe->bd_num);
 990                                 goto next_cqe;
 991                         }
 992                 }
 993
 994                 /* Prefetch next mbuf while processing current one. */
 995                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 996                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
 997
 998                 /* Update MBUF fields */
 999                 rx_mb->ol_flags = 0;
1000                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1001                 rx_mb->nb_segs = fp_cqe->bd_num;
1002                 rx_mb->data_len = len;
1003                 rx_mb->pkt_len = fp_cqe->pkt_len;
1004                 rx_mb->port = rxq->port_id;
1005                 rx_mb->packet_type = qede_rx_cqe_to_pkt_type(parse_flag);
1006
1007                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1008                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1009                 if (qdev->rss_enabled && htype) {
1010                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1011                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1012                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1013                                    rx_mb->hash.rss);
1014                 }
1015
1016                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1017
1018                 if (CQE_HAS_VLAN(parse_flag)) {
1019                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1020                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1021                 }
1022
1023                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1024                         /* FW does not provide indication of Outer VLAN tag,
1025                          * which is always stripped, so vlan_tci_outer is set
1026                          * to 0. Here vlan_tag represents inner VLAN tag.
1027                          */
1028                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1029                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1030                         rx_mb->vlan_tci_outer = 0;
1031                 }
1032
1033                 rx_pkts[rx_pkt] = rx_mb;
1034                 rx_pkt++;
1035 next_cqe:
1036                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1037                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1038                 if (rx_pkt == nb_pkts) {
1039                         PMD_RX_LOG(DEBUG, rxq,
1040                                    "Budget reached nb_pkts=%u received=%u\n",
1041                                    rx_pkt, nb_pkts);
1042                         break;
1043                 }
1044         }
1045
1046         qede_update_rx_prod(qdev, rxq);
1047
1048         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1049
1050         return rx_pkt;
1051 }
1052
1053 static inline int
1054 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1055 {
1056         uint16_t nb_segs, idx = TX_CONS(txq);
1057         struct eth_tx_bd *tx_data_bd;
1058         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1059
1060         if (unlikely(!mbuf)) {
1061                 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1062                 PMD_TX_LOG(ERR, txq,
1063                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1064                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1065                            TX_PROD(txq));
1066                 return -1;
1067         }
1068
1069         nb_segs = mbuf->nb_segs;
1070         while (nb_segs) {
1071                 /* It's like consuming rxbuf in recv() */
1072                 ecore_chain_consume(&txq->tx_pbl);
1073                 txq->nb_tx_avail++;
1074                 nb_segs--;
1075         }
1076         rte_pktmbuf_free(mbuf);
1077         txq->sw_tx_ring[idx].mbuf = NULL;
1078
1079         return 0;
1080 }
1081
1082 static inline uint16_t
1083 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1084 {
1085         uint16_t tx_compl = 0;
1086         uint16_t hw_bd_cons;
1087
1088         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1089         rte_compiler_barrier();
1090
1091         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1092                 if (qede_free_tx_pkt(edev, txq)) {
1093                         PMD_TX_LOG(ERR, txq,
1094                                    "hw_bd_cons = %u, chain_cons = %u\n",
1095                                    hw_bd_cons,
1096                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1097                         break;
1098                 }
1099                 txq->sw_tx_cons++;      /* Making TXD available */
1100                 tx_compl++;
1101         }
1102
1103         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1104                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1105         return tx_compl;
1106 }
1107
1108 /* Populate scatter gather buffer descriptor fields */
1109 static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq,
1110                                          struct rte_mbuf *m_seg,
1111                                          uint16_t count,
1112                                          struct eth_tx_1st_bd *bd1)
1113 {
1114         struct qede_tx_queue *txq = p_txq;
1115         struct eth_tx_2nd_bd *bd2 = NULL;
1116         struct eth_tx_3rd_bd *bd3 = NULL;
1117         struct eth_tx_bd *tx_bd = NULL;
1118         uint16_t nb_segs = count;
1119         dma_addr_t mapping;
1120
1121         /* Check for scattered buffers */
1122         while (m_seg) {
1123                 if (nb_segs == 1) {
1124                         bd2 = (struct eth_tx_2nd_bd *)
1125                                 ecore_chain_produce(&txq->tx_pbl);
1126                         memset(bd2, 0, sizeof(*bd2));
1127                         mapping = rte_mbuf_data_dma_addr(m_seg);
1128                         bd2->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1129                         bd2->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1130                         bd2->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1131                 } else if (nb_segs == 2) {
1132                         bd3 = (struct eth_tx_3rd_bd *)
1133                                 ecore_chain_produce(&txq->tx_pbl);
1134                         memset(bd3, 0, sizeof(*bd3));
1135                         mapping = rte_mbuf_data_dma_addr(m_seg);
1136                         bd3->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1137                         bd3->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1138                         bd3->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1139                 } else {
1140                         tx_bd = (struct eth_tx_bd *)
1141                                 ecore_chain_produce(&txq->tx_pbl);
1142                         memset(tx_bd, 0, sizeof(*tx_bd));
1143                         mapping = rte_mbuf_data_dma_addr(m_seg);
1144                         tx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1145                         tx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1146                         tx_bd->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1147                 }
1148                 nb_segs++;
1149                 bd1->data.nbds = nb_segs;
1150                 m_seg = m_seg->next;
1151         }
1152
1153         /* Return total scattered buffers */
1154         return nb_segs;
1155 }
1156
1157 uint16_t
1158 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1159 {
1160         struct qede_tx_queue *txq = p_txq;
1161         struct qede_dev *qdev = txq->qdev;
1162         struct ecore_dev *edev = &qdev->edev;
1163         struct qede_fastpath *fp;
1164         struct eth_tx_1st_bd *bd1;
1165         struct rte_mbuf *m_seg = NULL;
1166         uint16_t nb_tx_pkts;
1167         uint16_t nb_pkt_sent = 0;
1168         uint16_t bd_prod;
1169         uint16_t idx;
1170         uint16_t tx_count;
1171         uint16_t nb_segs = 0;
1172
1173         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1174
1175         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1176                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1177                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1178                 (void)qede_process_tx_compl(edev, txq);
1179         }
1180
1181         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1182                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1183         if (unlikely(nb_tx_pkts == 0)) {
1184                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1185                            nb_pkts, txq->nb_tx_avail);
1186                 return 0;
1187         }
1188
1189         tx_count = nb_tx_pkts;
1190         while (nb_tx_pkts--) {
1191                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1192                 idx = TX_PROD(txq);
1193                 struct rte_mbuf *mbuf = *tx_pkts++;
1194
1195                 txq->sw_tx_ring[idx].mbuf = mbuf;
1196                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1197                 /* Zero init struct fields */
1198                 bd1->data.bd_flags.bitfields = 0;
1199                 bd1->data.bitfields = 0;
1200
1201                 bd1->data.bd_flags.bitfields =
1202                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1203                 /* Map MBUF linear data for DMA and set in the first BD */
1204                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1205                                      mbuf->pkt_len);
1206
1207                 /* Descriptor based VLAN insertion */
1208                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1209                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1210                         bd1->data.bd_flags.bitfields |=
1211                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1212                 }
1213
1214                 /* Offload the IP checksum in the hardware */
1215                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1216                         bd1->data.bd_flags.bitfields |=
1217                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1218                 }
1219
1220                 /* L4 checksum offload (tcp or udp) */
1221                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1222                         bd1->data.bd_flags.bitfields |=
1223                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1224                         /* IPv6 + extn. -> later */
1225                 }
1226
1227                 /* Handle fragmented MBUF */
1228                 m_seg = mbuf->next;
1229                 nb_segs++;
1230                 bd1->data.nbds = nb_segs;
1231                 /* Encode scatter gather buffer descriptors if required */
1232                 nb_segs = qede_encode_sg_bd(txq, m_seg, nb_segs, bd1);
1233                 txq->nb_tx_avail = txq->nb_tx_avail - nb_segs;
1234                 nb_segs = 0;
1235                 txq->sw_tx_prod++;
1236                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1237                 bd_prod =
1238                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1239                 nb_pkt_sent++;
1240         }
1241
1242         /* Write value of prod idx into bd_prod */
1243         txq->tx_db.data.bd_prod = bd_prod;
1244         rte_wmb();
1245         rte_compiler_barrier();
1246         DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1247         rte_wmb();
1248
1249         /* Check again for Tx completions */
1250         (void)qede_process_tx_compl(edev, txq);
1251
1252         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1253                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1254
1255         return nb_pkt_sent;
1256 }
1257
1258 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1259 {
1260         struct qede_dev *qdev = eth_dev->data->dev_private;
1261         struct qede_fastpath *fp;
1262         uint8_t i, rss_id, txq_index, tc;
1263         int rxq = 0, txq = 0;
1264
1265         for_each_queue(i) {
1266                 fp = &qdev->fp_array[i];
1267                 if (fp->type & QEDE_FASTPATH_RX) {
1268                         fp->rxq = eth_dev->data->rx_queues[i];
1269                         fp->rxq->queue_id = rxq++;
1270                 }
1271
1272                 if (fp->type & QEDE_FASTPATH_TX) {
1273                         for (tc = 0; tc < qdev->num_tc; tc++) {
1274                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1275                                 fp->txqs[tc] =
1276                                         eth_dev->data->tx_queues[txq_index];
1277                                 fp->txqs[tc]->queue_id = txq_index;
1278                         }
1279                         txq++;
1280                 }
1281         }
1282 }
1283
1284 int qede_dev_start(struct rte_eth_dev *eth_dev)
1285 {
1286         struct qede_dev *qdev = eth_dev->data->dev_private;
1287         struct ecore_dev *edev = &qdev->edev;
1288         struct qed_link_output link_output;
1289         struct qede_fastpath *fp;
1290         int rc, i;
1291
1292         DP_INFO(edev, "Device state is %d\n", qdev->state);
1293
1294         if (qdev->state == QEDE_DEV_START) {
1295                 DP_INFO(edev, "Port is already started\n");
1296                 return 0;
1297         }
1298
1299         if (qdev->state == QEDE_DEV_CONFIG)
1300                 qede_init_fp_queue(eth_dev);
1301
1302         rc = qede_start_queues(eth_dev, true);
1303         if (rc) {
1304                 DP_ERR(edev, "Failed to start queues\n");
1305                 /* TBD: free */
1306                 return rc;
1307         }
1308
1309         /* Bring-up the link */
1310         qede_dev_set_link_state(eth_dev, true);
1311
1312         /* Reset ring */
1313         if (qede_reset_fp_rings(qdev))
1314                 return -ENOMEM;
1315
1316         /* Start/resume traffic */
1317         qdev->ops->fastpath_start(edev);
1318
1319         qdev->state = QEDE_DEV_START;
1320
1321         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1322
1323         return 0;
1324 }
1325
1326 static int qede_drain_txq(struct qede_dev *qdev,
1327                           struct qede_tx_queue *txq, bool allow_drain)
1328 {
1329         struct ecore_dev *edev = &qdev->edev;
1330         int rc, cnt = 1000;
1331
1332         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1333                 qede_process_tx_compl(edev, txq);
1334                 if (!cnt) {
1335                         if (allow_drain) {
1336                                 DP_NOTICE(edev, false,
1337                                           "Tx queue[%u] is stuck,"
1338                                           "requesting MCP to drain\n",
1339                                           txq->queue_id);
1340                                 rc = qdev->ops->common->drain(edev);
1341                                 if (rc)
1342                                         return rc;
1343                                 return qede_drain_txq(qdev, txq, false);
1344                         }
1345
1346                         DP_NOTICE(edev, false,
1347                                   "Timeout waiting for tx queue[%d]:"
1348                                   "PROD=%d, CONS=%d\n",
1349                                   txq->queue_id, txq->sw_tx_prod,
1350                                   txq->sw_tx_cons);
1351                         return -ENODEV;
1352                 }
1353                 cnt--;
1354                 DELAY(1000);
1355                 rte_compiler_barrier();
1356         }
1357
1358         /* FW finished processing, wait for HW to transmit all tx packets */
1359         DELAY(2000);
1360
1361         return 0;
1362 }
1363
1364 static int qede_stop_queues(struct qede_dev *qdev)
1365 {
1366         struct qed_update_vport_params vport_update_params;
1367         struct ecore_dev *edev = &qdev->edev;
1368         int rc, tc, i;
1369
1370         /* Disable the vport */
1371         memset(&vport_update_params, 0, sizeof(vport_update_params));
1372         vport_update_params.vport_id = 0;
1373         vport_update_params.update_vport_active_flg = 1;
1374         vport_update_params.vport_active_flg = 0;
1375         vport_update_params.update_rss_flg = 0;
1376
1377         DP_INFO(edev, "Deactivate vport\n");
1378
1379         rc = qdev->ops->vport_update(edev, &vport_update_params);
1380         if (rc) {
1381                 DP_ERR(edev, "Failed to update vport\n");
1382                 return rc;
1383         }
1384
1385         DP_INFO(edev, "Flushing tx queues\n");
1386
1387         /* Flush Tx queues. If needed, request drain from MCP */
1388         for_each_queue(i) {
1389                 struct qede_fastpath *fp = &qdev->fp_array[i];
1390
1391                 if (fp->type & QEDE_FASTPATH_TX) {
1392                         for (tc = 0; tc < qdev->num_tc; tc++) {
1393                                 struct qede_tx_queue *txq = fp->txqs[tc];
1394
1395                                 rc = qede_drain_txq(qdev, txq, true);
1396                                 if (rc)
1397                                         return rc;
1398                         }
1399                 }
1400         }
1401
1402         /* Stop all Queues in reverse order */
1403         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1404                 struct qed_stop_rxq_params rx_params;
1405
1406                 /* Stop the Tx Queue(s) */
1407                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1408                         for (tc = 0; tc < qdev->num_tc; tc++) {
1409                                 struct qed_stop_txq_params tx_params;
1410                                 u8 val;
1411
1412                                 tx_params.rss_id = i;
1413                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1414                                 tx_params.tx_queue_id = val;
1415
1416                                 DP_INFO(edev, "Stopping tx queues\n");
1417                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1418                                 if (rc) {
1419                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1420                                                tx_params.tx_queue_id);
1421                                         return rc;
1422                                 }
1423                         }
1424                 }
1425
1426                 /* Stop the Rx Queue */
1427                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1428                         memset(&rx_params, 0, sizeof(rx_params));
1429                         rx_params.rss_id = i;
1430                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1431                         rx_params.eq_completion_only = 1;
1432
1433                         DP_INFO(edev, "Stopping rx queues\n");
1434
1435                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1436                         if (rc) {
1437                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1438                                 return rc;
1439                         }
1440                 }
1441         }
1442
1443         return 0;
1444 }
1445
1446 int qede_reset_fp_rings(struct qede_dev *qdev)
1447 {
1448         struct qede_fastpath *fp;
1449         struct qede_tx_queue *txq;
1450         uint8_t tc;
1451         uint16_t id, i;
1452
1453         for_each_queue(id) {
1454                 fp = &qdev->fp_array[id];
1455
1456                 if (fp->type & QEDE_FASTPATH_RX) {
1457                         DP_INFO(&qdev->edev,
1458                                 "Reset FP chain for RSS %u\n", id);
1459                         qede_rx_queue_release_mbufs(fp->rxq);
1460                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1461                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1462                         fp->rxq->sw_rx_prod = 0;
1463                         fp->rxq->sw_rx_cons = 0;
1464                         *fp->rxq->hw_cons_ptr = 0;
1465                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1466                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1467                                         DP_ERR(&qdev->edev,
1468                                                "RX buffer allocation failed\n");
1469                                         return -ENOMEM;
1470                                 }
1471                         }
1472                 }
1473                 if (fp->type & QEDE_FASTPATH_TX) {
1474                         for (tc = 0; tc < qdev->num_tc; tc++) {
1475                                 txq = fp->txqs[tc];
1476                                 qede_tx_queue_release_mbufs(txq);
1477                                 ecore_chain_reset(&txq->tx_pbl);
1478                                 txq->sw_tx_cons = 0;
1479                                 txq->sw_tx_prod = 0;
1480                                 *txq->hw_cons_ptr = 0;
1481                         }
1482                 }
1483         }
1484
1485         return 0;
1486 }
1487
1488 /* This function frees all memory of a single fp */
1489 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1490 {
1491         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1492         struct qede_fastpath *fp;
1493         uint16_t txq_idx;
1494         uint8_t id;
1495         uint8_t tc;
1496
1497         for_each_queue(id) {
1498                 fp = &qdev->fp_array[id];
1499                 if (fp->type & QEDE_FASTPATH_RX) {
1500                         qede_rx_queue_release(fp->rxq);
1501                         eth_dev->data->rx_queues[id] = NULL;
1502                 } else {
1503                         for (tc = 0; tc < qdev->num_tc; tc++) {
1504                                 txq_idx = fp->txqs[tc]->queue_id;
1505                                 qede_tx_queue_release(fp->txqs[tc]);
1506                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1507                         }
1508                 }
1509         }
1510 }
1511
1512 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1513 {
1514         struct qede_dev *qdev = eth_dev->data->dev_private;
1515         struct ecore_dev *edev = &qdev->edev;
1516
1517         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1518
1519         if (qdev->state != QEDE_DEV_START) {
1520                 DP_INFO(edev, "Device not yet started\n");
1521                 return;
1522         }
1523
1524         if (qede_stop_queues(qdev))
1525                 DP_ERR(edev, "Didn't succeed to close queues\n");
1526
1527         DP_INFO(edev, "Stopped queues\n");
1528
1529         qdev->ops->fastpath_stop(edev);
1530
1531         /* Bring the link down */
1532         qede_dev_set_link_state(eth_dev, false);
1533
1534         qdev->state = QEDE_DEV_STOP;
1535
1536         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1537 }