drivers/net/qede/qede_rxtx.c

   1 /*
   2  * Copyright (c) 2016 QLogic Corporation.
   3  * All rights reserved.
   4  * www.qlogic.com
   5  *
   6  * See LICENSE.qede_pmd for copyright and licensing details.
   7  */
   8
   9 #include "qede_rxtx.h"
  10
  11 static bool gro_disable = 1;    /* mod_param */
  12
  13 static inline int qede_alloc_rx_buffer(struct qede_rx_queue *rxq)
  14 {
  15         struct rte_mbuf *new_mb = NULL;
  16         struct eth_rx_bd *rx_bd;
  17         dma_addr_t mapping;
  18         uint16_t idx = rxq->sw_rx_prod & NUM_RX_BDS(rxq);
  19
  20         new_mb = rte_mbuf_raw_alloc(rxq->mb_pool);
  21         if (unlikely(!new_mb)) {
  22                 PMD_RX_LOG(ERR, rxq,
  23                            "Failed to allocate rx buffer "
  24                            "sw_rx_prod %u sw_rx_cons %u mp entries %u free %u",
  25                            idx, rxq->sw_rx_cons & NUM_RX_BDS(rxq),
  26                            rte_mempool_avail_count(rxq->mb_pool),
  27                            rte_mempool_in_use_count(rxq->mb_pool));
  28                 return -ENOMEM;
  29         }
  30         rxq->sw_rx_ring[idx].mbuf = new_mb;
  31         rxq->sw_rx_ring[idx].page_offset = 0;
  32         mapping = rte_mbuf_data_dma_addr_default(new_mb);
  33         /* Advance PROD and get BD pointer */
  34         rx_bd = (struct eth_rx_bd *)ecore_chain_produce(&rxq->rx_bd_ring);
  35         rx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
  36         rx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
  37         rxq->sw_rx_prod++;
  38         return 0;
  39 }
  40
  41 static void qede_rx_queue_release_mbufs(struct qede_rx_queue *rxq)
  42 {
  43         uint16_t i;
  44
  45         if (rxq->sw_rx_ring != NULL) {
  46                 for (i = 0; i < rxq->nb_rx_desc; i++) {
  47                         if (rxq->sw_rx_ring[i].mbuf != NULL) {
  48                                 rte_pktmbuf_free(rxq->sw_rx_ring[i].mbuf);
  49                                 rxq->sw_rx_ring[i].mbuf = NULL;
  50                         }
  51                 }
  52         }
  53 }
  54
  55 void qede_rx_queue_release(void *rx_queue)
  56 {
  57         struct qede_rx_queue *rxq = rx_queue;
  58
  59         if (rxq != NULL) {
  60                 qede_rx_queue_release_mbufs(rxq);
  61                 rte_free(rxq->sw_rx_ring);
  62                 rxq->sw_rx_ring = NULL;
  63                 rte_free(rxq);
  64                 rxq = NULL;
  65         }
  66 }
  67
  68 static void qede_tx_queue_release_mbufs(struct qede_tx_queue *txq)
  69 {
  70         unsigned int i;
  71
  72         PMD_TX_LOG(DEBUG, txq, "releasing %u mbufs\n", txq->nb_tx_desc);
  73
  74         if (txq->sw_tx_ring) {
  75                 for (i = 0; i < txq->nb_tx_desc; i++) {
  76                         if (txq->sw_tx_ring[i].mbuf) {
  77                                 rte_pktmbuf_free(txq->sw_tx_ring[i].mbuf);
  78                                 txq->sw_tx_ring[i].mbuf = NULL;
  79                         }
  80                 }
  81         }
  82 }
  83
  84 int
  85 qede_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
  86                     uint16_t nb_desc, unsigned int socket_id,
  87                     const struct rte_eth_rxconf *rx_conf,
  88                     struct rte_mempool *mp)
  89 {
  90         struct qede_dev *qdev = dev->data->dev_private;
  91         struct ecore_dev *edev = &qdev->edev;
  92         struct rte_eth_dev_data *eth_data = dev->data;
  93         struct qede_rx_queue *rxq;
  94         uint16_t pkt_len = (uint16_t)dev->data->dev_conf.rxmode.max_rx_pkt_len;
  95         size_t size;
  96         uint16_t data_size;
  97         int rc;
  98         int i;
  99
 100         PMD_INIT_FUNC_TRACE(edev);
 101
 102         /* Note: Ring size/align is controlled by struct rte_eth_desc_lim */
 103         if (!rte_is_power_of_2(nb_desc)) {
 104                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 105                           nb_desc);
 106                 return -EINVAL;
 107         }
 108
 109         /* Free memory prior to re-allocation if needed... */
 110         if (dev->data->rx_queues[queue_idx] != NULL) {
 111                 qede_rx_queue_release(dev->data->rx_queues[queue_idx]);
 112                 dev->data->rx_queues[queue_idx] = NULL;
 113         }
 114
 115         /* First allocate the rx queue data structure */
 116         rxq = rte_zmalloc_socket("qede_rx_queue", sizeof(struct qede_rx_queue),
 117                                  RTE_CACHE_LINE_SIZE, socket_id);
 118
 119         if (!rxq) {
 120                 DP_ERR(edev, "Unable to allocate memory for rxq on socket %u",
 121                           socket_id);
 122                 return -ENOMEM;
 123         }
 124
 125         rxq->qdev = qdev;
 126         rxq->mb_pool = mp;
 127         rxq->nb_rx_desc = nb_desc;
 128         rxq->queue_id = queue_idx;
 129         rxq->port_id = dev->data->port_id;
 130
 131         /* Sanity check */
 132         data_size = (uint16_t)rte_pktmbuf_data_room_size(mp) -
 133                                 RTE_PKTMBUF_HEADROOM;
 134
 135         if (pkt_len > data_size && !dev->data->scattered_rx) {
 136                 DP_ERR(edev, "MTU %u should not exceed dataroom %u\n",
 137                        pkt_len, data_size);
 138                 rte_free(rxq);
 139                 return -EINVAL;
 140         }
 141
 142         if (dev->data->scattered_rx)
 143                 rxq->rx_buf_size = data_size;
 144         else
 145                 rxq->rx_buf_size = pkt_len + QEDE_ETH_OVERHEAD;
 146
 147         qdev->mtu = pkt_len;
 148
 149         DP_INFO(edev, "MTU = %u ; RX buffer = %u\n",
 150                 qdev->mtu, rxq->rx_buf_size);
 151
 152         if (pkt_len > ETHER_MAX_LEN) {
 153                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 154                 DP_NOTICE(edev, false, "jumbo frame enabled\n");
 155         } else {
 156                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 157         }
 158
 159         /* Allocate the parallel driver ring for Rx buffers */
 160         size = sizeof(*rxq->sw_rx_ring) * rxq->nb_rx_desc;
 161         rxq->sw_rx_ring = rte_zmalloc_socket("sw_rx_ring", size,
 162                                              RTE_CACHE_LINE_SIZE, socket_id);
 163         if (!rxq->sw_rx_ring) {
 164                 DP_NOTICE(edev, false,
 165                           "Unable to alloc memory for sw_rx_ring on socket %u\n",
 166                           socket_id);
 167                 rte_free(rxq);
 168                 rxq = NULL;
 169                 return -ENOMEM;
 170         }
 171
 172         /* Allocate FW Rx ring  */
 173         rc = qdev->ops->common->chain_alloc(edev,
 174                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 175                                             ECORE_CHAIN_MODE_NEXT_PTR,
 176                                             ECORE_CHAIN_CNT_TYPE_U16,
 177                                             rxq->nb_rx_desc,
 178                                             sizeof(struct eth_rx_bd),
 179                                             &rxq->rx_bd_ring,
 180                                             NULL);
 181
 182         if (rc != ECORE_SUCCESS) {
 183                 DP_NOTICE(edev, false,
 184                           "Unable to alloc memory for rxbd ring on socket %u\n",
 185                           socket_id);
 186                 rte_free(rxq->sw_rx_ring);
 187                 rxq->sw_rx_ring = NULL;
 188                 rte_free(rxq);
 189                 rxq = NULL;
 190                 return -ENOMEM;
 191         }
 192
 193         /* Allocate FW completion ring */
 194         rc = qdev->ops->common->chain_alloc(edev,
 195                                             ECORE_CHAIN_USE_TO_CONSUME,
 196                                             ECORE_CHAIN_MODE_PBL,
 197                                             ECORE_CHAIN_CNT_TYPE_U16,
 198                                             rxq->nb_rx_desc,
 199                                             sizeof(union eth_rx_cqe),
 200                                             &rxq->rx_comp_ring,
 201                                             NULL);
 202
 203         if (rc != ECORE_SUCCESS) {
 204                 DP_NOTICE(edev, false,
 205                           "Unable to alloc memory for cqe ring on socket %u\n",
 206                           socket_id);
 207                 /* TBD: Freeing RX BD ring */
 208                 rte_free(rxq->sw_rx_ring);
 209                 rxq->sw_rx_ring = NULL;
 210                 rte_free(rxq);
 211                 return -ENOMEM;
 212         }
 213
 214         /* Allocate buffers for the Rx ring */
 215         for (i = 0; i < rxq->nb_rx_desc; i++) {
 216                 rc = qede_alloc_rx_buffer(rxq);
 217                 if (rc) {
 218                         DP_NOTICE(edev, false,
 219                                   "RX buffer allocation failed at idx=%d\n", i);
 220                         goto err4;
 221                 }
 222         }
 223
 224         dev->data->rx_queues[queue_idx] = rxq;
 225
 226         DP_INFO(edev, "rxq %d num_desc %u rx_buf_size=%u socket %u\n",
 227                   queue_idx, nb_desc, qdev->mtu, socket_id);
 228
 229         return 0;
 230 err4:
 231         qede_rx_queue_release(rxq);
 232         return -ENOMEM;
 233 }
 234
 235 void qede_tx_queue_release(void *tx_queue)
 236 {
 237         struct qede_tx_queue *txq = tx_queue;
 238
 239         if (txq != NULL) {
 240                 qede_tx_queue_release_mbufs(txq);
 241                 if (txq->sw_tx_ring) {
 242                         rte_free(txq->sw_tx_ring);
 243                         txq->sw_tx_ring = NULL;
 244                 }
 245                 rte_free(txq);
 246         }
 247         txq = NULL;
 248 }
 249
 250 int
 251 qede_tx_queue_setup(struct rte_eth_dev *dev,
 252                     uint16_t queue_idx,
 253                     uint16_t nb_desc,
 254                     unsigned int socket_id,
 255                     const struct rte_eth_txconf *tx_conf)
 256 {
 257         struct qede_dev *qdev = dev->data->dev_private;
 258         struct ecore_dev *edev = &qdev->edev;
 259         struct qede_tx_queue *txq;
 260         int rc;
 261
 262         PMD_INIT_FUNC_TRACE(edev);
 263
 264         if (!rte_is_power_of_2(nb_desc)) {
 265                 DP_ERR(edev, "Ring size %u is not power of 2\n",
 266                        nb_desc);
 267                 return -EINVAL;
 268         }
 269
 270         /* Free memory prior to re-allocation if needed... */
 271         if (dev->data->tx_queues[queue_idx] != NULL) {
 272                 qede_tx_queue_release(dev->data->tx_queues[queue_idx]);
 273                 dev->data->tx_queues[queue_idx] = NULL;
 274         }
 275
 276         txq = rte_zmalloc_socket("qede_tx_queue", sizeof(struct qede_tx_queue),
 277                                  RTE_CACHE_LINE_SIZE, socket_id);
 278
 279         if (txq == NULL) {
 280                 DP_ERR(edev,
 281                        "Unable to allocate memory for txq on socket %u",
 282                        socket_id);
 283                 return -ENOMEM;
 284         }
 285
 286         txq->nb_tx_desc = nb_desc;
 287         txq->qdev = qdev;
 288         txq->port_id = dev->data->port_id;
 289
 290         rc = qdev->ops->common->chain_alloc(edev,
 291                                             ECORE_CHAIN_USE_TO_CONSUME_PRODUCE,
 292                                             ECORE_CHAIN_MODE_PBL,
 293                                             ECORE_CHAIN_CNT_TYPE_U16,
 294                                             txq->nb_tx_desc,
 295                                             sizeof(union eth_tx_bd_types),
 296                                             &txq->tx_pbl,
 297                                             NULL);
 298         if (rc != ECORE_SUCCESS) {
 299                 DP_ERR(edev,
 300                        "Unable to allocate memory for txbd ring on socket %u",
 301                        socket_id);
 302                 qede_tx_queue_release(txq);
 303                 return -ENOMEM;
 304         }
 305
 306         /* Allocate software ring */
 307         txq->sw_tx_ring = rte_zmalloc_socket("txq->sw_tx_ring",
 308                                              (sizeof(struct qede_tx_entry) *
 309                                               txq->nb_tx_desc),
 310                                              RTE_CACHE_LINE_SIZE, socket_id);
 311
 312         if (!txq->sw_tx_ring) {
 313                 DP_ERR(edev,
 314                        "Unable to allocate memory for txbd ring on socket %u",
 315                        socket_id);
 316                 qede_tx_queue_release(txq);
 317                 return -ENOMEM;
 318         }
 319
 320         txq->queue_id = queue_idx;
 321
 322         txq->nb_tx_avail = txq->nb_tx_desc;
 323
 324         txq->tx_free_thresh =
 325             tx_conf->tx_free_thresh ? tx_conf->tx_free_thresh :
 326             (txq->nb_tx_desc - QEDE_DEFAULT_TX_FREE_THRESH);
 327
 328         dev->data->tx_queues[queue_idx] = txq;
 329
 330         DP_INFO(edev,
 331                   "txq %u num_desc %u tx_free_thresh %u socket %u\n",
 332                   queue_idx, nb_desc, txq->tx_free_thresh, socket_id);
 333
 334         return 0;
 335 }
 336
 337 /* This function inits fp content and resets the SB, RXQ and TXQ arrays */
 338 static void qede_init_fp(struct qede_dev *qdev)
 339 {
 340         struct qede_fastpath *fp;
 341         uint8_t i, rss_id, tc;
 342         int fp_rx = qdev->fp_num_rx, rxq = 0, txq = 0;
 343
 344         memset((void *)qdev->fp_array, 0, (QEDE_QUEUE_CNT(qdev) *
 345                                            sizeof(*qdev->fp_array)));
 346         memset((void *)qdev->sb_array, 0, (QEDE_QUEUE_CNT(qdev) *
 347                                            sizeof(*qdev->sb_array)));
 348         for_each_queue(i) {
 349                 fp = &qdev->fp_array[i];
 350                 if (fp_rx) {
 351                         fp->type = QEDE_FASTPATH_RX;
 352                         fp_rx--;
 353                 } else{
 354                         fp->type = QEDE_FASTPATH_TX;
 355                 }
 356                 fp->qdev = qdev;
 357                 fp->id = i;
 358                 fp->sb_info = &qdev->sb_array[i];
 359                 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d", "qdev", i);
 360         }
 361
 362         qdev->gro_disable = gro_disable;
 363 }
 364
 365 void qede_free_fp_arrays(struct qede_dev *qdev)
 366 {
 367         /* It asseumes qede_free_mem_load() is called before */
 368         if (qdev->fp_array != NULL) {
 369                 rte_free(qdev->fp_array);
 370                 qdev->fp_array = NULL;
 371         }
 372
 373         if (qdev->sb_array != NULL) {
 374                 rte_free(qdev->sb_array);
 375                 qdev->sb_array = NULL;
 376         }
 377 }
 378
 379 int qede_alloc_fp_array(struct qede_dev *qdev)
 380 {
 381         struct qede_fastpath *fp;
 382         struct ecore_dev *edev = &qdev->edev;
 383         int i;
 384
 385         qdev->fp_array = rte_calloc("fp", QEDE_QUEUE_CNT(qdev),
 386                                     sizeof(*qdev->fp_array),
 387                                     RTE_CACHE_LINE_SIZE);
 388
 389         if (!qdev->fp_array) {
 390                 DP_ERR(edev, "fp array allocation failed\n");
 391                 return -ENOMEM;
 392         }
 393
 394         qdev->sb_array = rte_calloc("sb", QEDE_QUEUE_CNT(qdev),
 395                                     sizeof(*qdev->sb_array),
 396                                     RTE_CACHE_LINE_SIZE);
 397
 398         if (!qdev->sb_array) {
 399                 DP_ERR(edev, "sb array allocation failed\n");
 400                 rte_free(qdev->fp_array);
 401                 return -ENOMEM;
 402         }
 403
 404         return 0;
 405 }
 406
 407 /* This function allocates fast-path status block memory */
 408 static int
 409 qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
 410                   uint16_t sb_id)
 411 {
 412         struct ecore_dev *edev = &qdev->edev;
 413         struct status_block *sb_virt;
 414         dma_addr_t sb_phys;
 415         int rc;
 416
 417         sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys, sizeof(*sb_virt));
 418
 419         if (!sb_virt) {
 420                 DP_ERR(edev, "Status block allocation failed\n");
 421                 return -ENOMEM;
 422         }
 423
 424         rc = qdev->ops->common->sb_init(edev, sb_info,
 425                                         sb_virt, sb_phys, sb_id,
 426                                         QED_SB_TYPE_L2_QUEUE);
 427         if (rc) {
 428                 DP_ERR(edev, "Status block initialization failed\n");
 429                 /* TBD: No dma_free_coherent possible */
 430                 return rc;
 431         }
 432
 433         return 0;
 434 }
 435
 436 int qede_alloc_fp_resc(struct qede_dev *qdev)
 437 {
 438         struct ecore_dev *edev = &qdev->edev;
 439         struct qede_fastpath *fp;
 440         uint32_t num_sbs;
 441         int rc, i;
 442
 443         if (IS_VF(edev))
 444                 ecore_vf_get_num_sbs(ECORE_LEADING_HWFN(edev), &num_sbs);
 445         else
 446                 num_sbs = (ecore_cxt_get_proto_cid_count
 447                           (ECORE_LEADING_HWFN(edev), PROTOCOLID_ETH, NULL)) / 2;
 448
 449         if (num_sbs == 0) {
 450                 DP_ERR(edev, "No status blocks available\n");
 451                 return -EINVAL;
 452         }
 453
 454         if (qdev->fp_array)
 455                 qede_free_fp_arrays(qdev);
 456
 457         rc = qede_alloc_fp_array(qdev);
 458         if (rc != 0)
 459                 return rc;
 460
 461         qede_init_fp(qdev);
 462
 463         for (i = 0; i < QEDE_QUEUE_CNT(qdev); i++) {
 464                 fp = &qdev->fp_array[i];
 465                 if (qede_alloc_mem_sb(qdev, fp->sb_info, i % num_sbs)) {
 466                         qede_free_fp_arrays(qdev);
 467                         return -ENOMEM;
 468                 }
 469         }
 470
 471         return 0;
 472 }
 473
 474 void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
 475 {
 476         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
 477
 478         qede_free_mem_load(eth_dev);
 479         qede_free_fp_arrays(qdev);
 480 }
 481
 482 static inline void
 483 qede_update_rx_prod(struct qede_dev *edev, struct qede_rx_queue *rxq)
 484 {
 485         uint16_t bd_prod = ecore_chain_get_prod_idx(&rxq->rx_bd_ring);
 486         uint16_t cqe_prod = ecore_chain_get_prod_idx(&rxq->rx_comp_ring);
 487         struct eth_rx_prod_data rx_prods = { 0 };
 488
 489         /* Update producers */
 490         rx_prods.bd_prod = rte_cpu_to_le_16(bd_prod);
 491         rx_prods.cqe_prod = rte_cpu_to_le_16(cqe_prod);
 492
 493         /* Make sure that the BD and SGE data is updated before updating the
 494          * producers since FW might read the BD/SGE right after the producer
 495          * is updated.
 496          */
 497         rte_wmb();
 498
 499         internal_ram_wr(rxq->hw_rxq_prod_addr, sizeof(rx_prods),
 500                         (uint32_t *)&rx_prods);
 501
 502         /* mmiowb is needed to synchronize doorbell writes from more than one
 503          * processor. It guarantees that the write arrives to the device before
 504          * the napi lock is released and another qede_poll is called (possibly
 505          * on another CPU). Without this barrier, the next doorbell can bypass
 506          * this doorbell. This is applicable to IA64/Altix systems.
 507          */
 508         rte_wmb();
 509
 510         PMD_RX_LOG(DEBUG, rxq, "bd_prod %u  cqe_prod %u\n", bd_prod, cqe_prod);
 511 }
 512
 513 static int qede_start_queues(struct rte_eth_dev *eth_dev, bool clear_stats)
 514 {
 515         struct qede_dev *qdev = eth_dev->data->dev_private;
 516         struct ecore_dev *edev = &qdev->edev;
 517         struct ecore_queue_start_common_params q_params;
 518         struct qed_dev_info *qed_info = &qdev->dev_info.common;
 519         struct qed_update_vport_params vport_update_params;
 520         struct qede_tx_queue *txq;
 521         struct qede_fastpath *fp;
 522         dma_addr_t p_phys_table;
 523         int txq_index;
 524         uint16_t page_cnt;
 525         int vlan_removal_en = 1;
 526         int rc, tc, i;
 527
 528         for_each_queue(i) {
 529                 fp = &qdev->fp_array[i];
 530                 if (fp->type & QEDE_FASTPATH_RX) {
 531                         p_phys_table = ecore_chain_get_pbl_phys(&fp->rxq->
 532                                                                 rx_comp_ring);
 533                         page_cnt = ecore_chain_get_page_cnt(&fp->rxq->
 534                                                                 rx_comp_ring);
 535
 536                         memset(&q_params, 0, sizeof(q_params));
 537                         q_params.queue_id = i;
 538                         q_params.vport_id = 0;
 539                         q_params.sb = fp->sb_info->igu_sb_id;
 540                         q_params.sb_idx = RX_PI;
 541
 542                         ecore_sb_ack(fp->sb_info, IGU_INT_DISABLE, 0);
 543
 544                         rc = qdev->ops->q_rx_start(edev, i, &q_params,
 545                                            fp->rxq->rx_buf_size,
 546                                            fp->rxq->rx_bd_ring.p_phys_addr,
 547                                            p_phys_table,
 548                                            page_cnt,
 549                                            &fp->rxq->hw_rxq_prod_addr);
 550                         if (rc) {
 551                                 DP_ERR(edev, "Start rxq #%d failed %d\n",
 552                                        fp->rxq->queue_id, rc);
 553                                 return rc;
 554                         }
 555
 556                         fp->rxq->hw_cons_ptr =
 557                                         &fp->sb_info->sb_virt->pi_array[RX_PI];
 558
 559                         qede_update_rx_prod(qdev, fp->rxq);
 560                 }
 561
 562                 if (!(fp->type & QEDE_FASTPATH_TX))
 563                         continue;
 564                 for (tc = 0; tc < qdev->num_tc; tc++) {
 565                         txq = fp->txqs[tc];
 566                         txq_index = tc * QEDE_RSS_COUNT(qdev) + i;
 567
 568                         p_phys_table = ecore_chain_get_pbl_phys(&txq->tx_pbl);
 569                         page_cnt = ecore_chain_get_page_cnt(&txq->tx_pbl);
 570
 571                         memset(&q_params, 0, sizeof(q_params));
 572                         q_params.queue_id = txq->queue_id;
 573                         q_params.vport_id = 0;
 574                         q_params.sb = fp->sb_info->igu_sb_id;
 575                         q_params.sb_idx = TX_PI(tc);
 576
 577                         rc = qdev->ops->q_tx_start(edev, i, &q_params,
 578                                                    p_phys_table,
 579                                                    page_cnt, /* **pp_doorbell */
 580                                                    &txq->doorbell_addr);
 581                         if (rc) {
 582                                 DP_ERR(edev, "Start txq %u failed %d\n",
 583                                        txq_index, rc);
 584                                 return rc;
 585                         }
 586
 587                         txq->hw_cons_ptr =
 588                             &fp->sb_info->sb_virt->pi_array[TX_PI(tc)];
 589                         SET_FIELD(txq->tx_db.data.params,
 590                                   ETH_DB_DATA_DEST, DB_DEST_XCM);
 591                         SET_FIELD(txq->tx_db.data.params, ETH_DB_DATA_AGG_CMD,
 592                                   DB_AGG_CMD_SET);
 593                         SET_FIELD(txq->tx_db.data.params,
 594                                   ETH_DB_DATA_AGG_VAL_SEL,
 595                                   DQ_XCM_ETH_TX_BD_PROD_CMD);
 596
 597                         txq->tx_db.data.agg_flags = DQ_XCM_ETH_DQ_CF_CMD;
 598                 }
 599         }
 600
 601         /* Prepare and send the vport enable */
 602         memset(&vport_update_params, 0, sizeof(vport_update_params));
 603         /* Update MTU via vport update */
 604         vport_update_params.mtu = qdev->mtu;
 605         vport_update_params.vport_id = 0;
 606         vport_update_params.update_vport_active_flg = 1;
 607         vport_update_params.vport_active_flg = 1;
 608
 609         /* @DPDK */
 610         if (qed_info->mf_mode == MF_NPAR && qed_info->tx_switching) {
 611                 /* TBD: Check SRIOV enabled for VF */
 612                 vport_update_params.update_tx_switching_flg = 1;
 613                 vport_update_params.tx_switching_flg = 1;
 614         }
 615
 616         rc = qdev->ops->vport_update(edev, &vport_update_params);
 617         if (rc) {
 618                 DP_ERR(edev, "Update V-PORT failed %d\n", rc);
 619                 return rc;
 620         }
 621
 622         return 0;
 623 }
 624
 625 static bool qede_tunn_exist(uint16_t flag)
 626 {
 627         return !!((PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK <<
 628                     PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT) & flag);
 629 }
 630
 631 /*
 632  * qede_check_tunn_csum_l4:
 633  * Returns:
 634  * 1 : If L4 csum is enabled AND if the validation has failed.
 635  * 0 : Otherwise
 636  */
 637 static inline uint8_t qede_check_tunn_csum_l4(uint16_t flag)
 638 {
 639         if ((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK <<
 640              PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT) & flag)
 641                 return !!((PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK <<
 642                         PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT) & flag);
 643
 644         return 0;
 645 }
 646
 647 static inline uint8_t qede_check_notunn_csum_l4(uint16_t flag)
 648 {
 649         if ((PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK <<
 650              PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT) & flag)
 651                 return !!((PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK <<
 652                            PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT) & flag);
 653
 654         return 0;
 655 }
 656
 657 static inline uint8_t
 658 qede_check_notunn_csum_l3(struct rte_mbuf *m, uint16_t flag)
 659 {
 660         struct ipv4_hdr *ip;
 661         uint16_t pkt_csum;
 662         uint16_t calc_csum;
 663         uint16_t val;
 664
 665         val = ((PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<
 666                 PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT) & flag);
 667
 668         if (unlikely(val)) {
 669                 m->packet_type = qede_rx_cqe_to_pkt_type(flag);
 670                 if (RTE_ETH_IS_IPV4_HDR(m->packet_type)) {
 671                         ip = rte_pktmbuf_mtod_offset(m, struct ipv4_hdr *,
 672                                            sizeof(struct ether_hdr));
 673                         pkt_csum = ip->hdr_checksum;
 674                         ip->hdr_checksum = 0;
 675                         calc_csum = rte_ipv4_cksum(ip);
 676                         ip->hdr_checksum = pkt_csum;
 677                         return (calc_csum != pkt_csum);
 678                 } else if (RTE_ETH_IS_IPV6_HDR(m->packet_type)) {
 679                         return 1;
 680                 }
 681         }
 682         return 0;
 683 }
 684
 685 static inline void qede_rx_bd_ring_consume(struct qede_rx_queue *rxq)
 686 {
 687         ecore_chain_consume(&rxq->rx_bd_ring);
 688         rxq->sw_rx_cons++;
 689 }
 690
 691 static inline void
 692 qede_reuse_page(struct qede_dev *qdev,
 693                 struct qede_rx_queue *rxq, struct qede_rx_entry *curr_cons)
 694 {
 695         struct eth_rx_bd *rx_bd_prod = ecore_chain_produce(&rxq->rx_bd_ring);
 696         uint16_t idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 697         struct qede_rx_entry *curr_prod;
 698         dma_addr_t new_mapping;
 699
 700         curr_prod = &rxq->sw_rx_ring[idx];
 701         *curr_prod = *curr_cons;
 702
 703         new_mapping = rte_mbuf_data_dma_addr_default(curr_prod->mbuf) +
 704                       curr_prod->page_offset;
 705
 706         rx_bd_prod->addr.hi = rte_cpu_to_le_32(U64_HI(new_mapping));
 707         rx_bd_prod->addr.lo = rte_cpu_to_le_32(U64_LO(new_mapping));
 708
 709         rxq->sw_rx_prod++;
 710 }
 711
 712 static inline void
 713 qede_recycle_rx_bd_ring(struct qede_rx_queue *rxq,
 714                         struct qede_dev *qdev, uint8_t count)
 715 {
 716         struct qede_rx_entry *curr_cons;
 717
 718         for (; count > 0; count--) {
 719                 curr_cons = &rxq->sw_rx_ring[rxq->sw_rx_cons & NUM_RX_BDS(rxq)];
 720                 qede_reuse_page(qdev, rxq, curr_cons);
 721                 qede_rx_bd_ring_consume(rxq);
 722         }
 723 }
 724
 725 static inline uint32_t qede_rx_cqe_to_pkt_type(uint16_t flags)
 726 {
 727         uint16_t val;
 728
 729         /* Lookup table */
 730         static const uint32_t
 731         ptype_lkup_tbl[QEDE_PKT_TYPE_MAX] __rte_cache_aligned = {
 732                 [QEDE_PKT_TYPE_IPV4] = RTE_PTYPE_L3_IPV4,
 733                 [QEDE_PKT_TYPE_IPV6] = RTE_PTYPE_L3_IPV6,
 734                 [QEDE_PKT_TYPE_IPV4_TCP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_TCP,
 735                 [QEDE_PKT_TYPE_IPV6_TCP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_TCP,
 736                 [QEDE_PKT_TYPE_IPV4_UDP] = RTE_PTYPE_L3_IPV4 | RTE_PTYPE_L4_UDP,
 737                 [QEDE_PKT_TYPE_IPV6_UDP] = RTE_PTYPE_L3_IPV6 | RTE_PTYPE_L4_UDP,
 738         };
 739
 740         /* Bits (0..3) provides L3/L4 protocol type */
 741         val = ((PARSING_AND_ERR_FLAGS_L3TYPE_MASK <<
 742                PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT) |
 743                (PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK <<
 744                 PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT)) & flags;
 745
 746         if (val < QEDE_PKT_TYPE_MAX)
 747                 return ptype_lkup_tbl[val] | RTE_PTYPE_L2_ETHER;
 748         else
 749                 return RTE_PTYPE_UNKNOWN;
 750 }
 751
 752 static inline uint32_t qede_rx_cqe_to_tunn_pkt_type(uint16_t flags)
 753 {
 754         uint32_t val;
 755
 756         /* Lookup table */
 757         static const uint32_t
 758         ptype_tunn_lkup_tbl[QEDE_PKT_TYPE_TUNN_MAX_TYPE] __rte_cache_aligned = {
 759                 [QEDE_PKT_TYPE_UNKNOWN] = RTE_PTYPE_UNKNOWN,
 760                 [QEDE_PKT_TYPE_TUNN_GENEVE] = RTE_PTYPE_TUNNEL_GENEVE,
 761                 [QEDE_PKT_TYPE_TUNN_GRE] = RTE_PTYPE_TUNNEL_GRE,
 762                 [QEDE_PKT_TYPE_TUNN_VXLAN] = RTE_PTYPE_TUNNEL_VXLAN,
 763                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GENEVE] =
 764                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 765                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_GRE] =
 766                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 767                 [QEDE_PKT_TYPE_TUNN_L2_TENID_NOEXIST_VXLAN] =
 768                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 769                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GENEVE] =
 770                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L2_ETHER,
 771                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_GRE] =
 772                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L2_ETHER,
 773                 [QEDE_PKT_TYPE_TUNN_L2_TENID_EXIST_VXLAN] =
 774                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L2_ETHER,
 775                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GENEVE] =
 776                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 777                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_GRE] =
 778                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 779                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_NOEXIST_VXLAN] =
 780                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 781                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GENEVE] =
 782                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV4,
 783                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_GRE] =
 784                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV4,
 785                 [QEDE_PKT_TYPE_TUNN_IPV4_TENID_EXIST_VXLAN] =
 786                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV4,
 787                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GENEVE] =
 788                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 789                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_GRE] =
 790                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 791                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_NOEXIST_VXLAN] =
 792                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 793                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GENEVE] =
 794                                 RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L3_IPV6,
 795                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_GRE] =
 796                                 RTE_PTYPE_TUNNEL_GRE | RTE_PTYPE_L3_IPV6,
 797                 [QEDE_PKT_TYPE_TUNN_IPV6_TENID_EXIST_VXLAN] =
 798                                 RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L3_IPV6,
 799         };
 800
 801         /* Cover bits[4-0] to include tunn_type and next protocol */
 802         val = ((ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK <<
 803                 ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT) |
 804                 (ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK <<
 805                 ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT)) & flags;
 806
 807         if (val < QEDE_PKT_TYPE_TUNN_MAX_TYPE)
 808                 return ptype_tunn_lkup_tbl[val];
 809         else
 810                 return RTE_PTYPE_UNKNOWN;
 811 }
 812
 813
 814 int qede_process_sg_pkts(void *p_rxq,  struct rte_mbuf *rx_mb,
 815                          int num_segs, uint16_t pkt_len)
 816 {
 817         struct qede_rx_queue *rxq = p_rxq;
 818         struct qede_dev *qdev = rxq->qdev;
 819         struct ecore_dev *edev = &qdev->edev;
 820         uint16_t sw_rx_index, cur_size;
 821
 822         register struct rte_mbuf *seg1 = NULL;
 823         register struct rte_mbuf *seg2 = NULL;
 824
 825         seg1 = rx_mb;
 826         while (num_segs) {
 827                 cur_size = pkt_len > rxq->rx_buf_size ?
 828                                 rxq->rx_buf_size : pkt_len;
 829                 if (!cur_size) {
 830                         PMD_RX_LOG(DEBUG, rxq,
 831                                    "SG packet, len and num BD mismatch\n");
 832                         qede_recycle_rx_bd_ring(rxq, qdev, num_segs);
 833                         return -EINVAL;
 834                 }
 835
 836                 if (qede_alloc_rx_buffer(rxq)) {
 837                         uint8_t index;
 838
 839                         PMD_RX_LOG(DEBUG, rxq, "Buffer allocation failed\n");
 840                         index = rxq->port_id;
 841                         rte_eth_devices[index].data->rx_mbuf_alloc_failed++;
 842                         rxq->rx_alloc_errors++;
 843                         return -ENOMEM;
 844                 }
 845
 846                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 847                 seg2 = rxq->sw_rx_ring[sw_rx_index].mbuf;
 848                 qede_rx_bd_ring_consume(rxq);
 849                 pkt_len -= cur_size;
 850                 seg2->data_len = cur_size;
 851                 seg1->next = seg2;
 852                 seg1 = seg1->next;
 853                 num_segs--;
 854                 rxq->rx_segs++;
 855                 continue;
 856         }
 857         seg1 = NULL;
 858
 859         if (pkt_len)
 860                 PMD_RX_LOG(DEBUG, rxq,
 861                            "Mapped all BDs of jumbo, but still have %d bytes\n",
 862                            pkt_len);
 863
 864         return ECORE_SUCCESS;
 865 }
 866
 867 uint16_t
 868 qede_recv_pkts(void *p_rxq, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 869 {
 870         struct qede_rx_queue *rxq = p_rxq;
 871         struct qede_dev *qdev = rxq->qdev;
 872         struct ecore_dev *edev = &qdev->edev;
 873         struct qede_fastpath *fp = &qdev->fp_array[rxq->queue_id];
 874         uint16_t hw_comp_cons, sw_comp_cons, sw_rx_index;
 875         uint16_t rx_pkt = 0;
 876         union eth_rx_cqe *cqe;
 877         struct eth_fast_path_rx_reg_cqe *fp_cqe;
 878         register struct rte_mbuf *rx_mb = NULL;
 879         register struct rte_mbuf *seg1 = NULL;
 880         enum eth_rx_cqe_type cqe_type;
 881         uint16_t len, pad, preload_idx, pkt_len, parse_flag;
 882         uint8_t csum_flag, num_segs;
 883         enum rss_hash_type htype;
 884         uint8_t tunn_parse_flag;
 885         int ret;
 886
 887         hw_comp_cons = rte_le_to_cpu_16(*rxq->hw_cons_ptr);
 888         sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
 889
 890         rte_rmb();
 891
 892         if (hw_comp_cons == sw_comp_cons)
 893                 return 0;
 894
 895         while (sw_comp_cons != hw_comp_cons) {
 896                 /* Get the CQE from the completion ring */
 897                 cqe =
 898                     (union eth_rx_cqe *)ecore_chain_consume(&rxq->rx_comp_ring);
 899                 cqe_type = cqe->fast_path_regular.type;
 900
 901                 if (unlikely(cqe_type == ETH_RX_CQE_TYPE_SLOW_PATH)) {
 902                         PMD_RX_LOG(DEBUG, rxq, "Got a slowath CQE\n");
 903
 904                         qdev->ops->eth_cqe_completion(edev, fp->id,
 905                                 (struct eth_slow_path_rx_cqe *)cqe);
 906                         goto next_cqe;
 907                 }
 908
 909                 /* Get the data from the SW ring */
 910                 sw_rx_index = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
 911                 rx_mb = rxq->sw_rx_ring[sw_rx_index].mbuf;
 912                 assert(rx_mb != NULL);
 913
 914                 /* non GRO */
 915                 fp_cqe = &cqe->fast_path_regular;
 916
 917                 len = rte_le_to_cpu_16(fp_cqe->len_on_first_bd);
 918                 pad = fp_cqe->placement_offset;
 919                 assert((len + pad) <= rx_mb->buf_len);
 920
 921                 PMD_RX_LOG(DEBUG, rxq,
 922                            "CQE type = 0x%x, flags = 0x%x, vlan = 0x%x"
 923                            " len = %u, parsing_flags = %d\n",
 924                            cqe_type, fp_cqe->bitfields,
 925                            rte_le_to_cpu_16(fp_cqe->vlan_tag),
 926                            len, rte_le_to_cpu_16(fp_cqe->pars_flags.flags));
 927
 928                 /* If this is an error packet then drop it */
 929                 parse_flag =
 930                     rte_le_to_cpu_16(cqe->fast_path_regular.pars_flags.flags);
 931
 932                 rx_mb->ol_flags = 0;
 933
 934                 if (qede_tunn_exist(parse_flag)) {
 935                         PMD_RX_LOG(DEBUG, rxq, "Rx tunneled packet\n");
 936                         if (unlikely(qede_check_tunn_csum_l4(parse_flag))) {
 937                                 PMD_RX_LOG(ERR, rxq,
 938                                             "L4 csum failed, flags = 0x%x\n",
 939                                             parse_flag);
 940                                 rxq->rx_hw_errors++;
 941                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 942                         } else {
 943                                 tunn_parse_flag =
 944                                                 fp_cqe->tunnel_pars_flags.flags;
 945                                 rx_mb->packet_type =
 946                                         qede_rx_cqe_to_tunn_pkt_type(
 947                                                         tunn_parse_flag);
 948                         }
 949                 } else {
 950                         PMD_RX_LOG(DEBUG, rxq, "Rx non-tunneled packet\n");
 951                         if (unlikely(qede_check_notunn_csum_l4(parse_flag))) {
 952                                 PMD_RX_LOG(ERR, rxq,
 953                                             "L4 csum failed, flags = 0x%x\n",
 954                                             parse_flag);
 955                                 rxq->rx_hw_errors++;
 956                                 rx_mb->ol_flags |= PKT_RX_L4_CKSUM_BAD;
 957                         } else if (unlikely(qede_check_notunn_csum_l3(rx_mb,
 958                                                         parse_flag))) {
 959                                 PMD_RX_LOG(ERR, rxq,
 960                                            "IP csum failed, flags = 0x%x\n",
 961                                            parse_flag);
 962                                 rxq->rx_hw_errors++;
 963                                 rx_mb->ol_flags |= PKT_RX_IP_CKSUM_BAD;
 964                         } else {
 965                                 rx_mb->packet_type =
 966                                         qede_rx_cqe_to_pkt_type(parse_flag);
 967                         }
 968                 }
 969
 970                 PMD_RX_LOG(INFO, rxq, "packet_type 0x%x\n", rx_mb->packet_type);
 971
 972                 if (unlikely(qede_alloc_rx_buffer(rxq) != 0)) {
 973                         PMD_RX_LOG(ERR, rxq,
 974                                    "New buffer allocation failed,"
 975                                    "dropping incoming packet\n");
 976                         qede_recycle_rx_bd_ring(rxq, qdev, fp_cqe->bd_num);
 977                         rte_eth_devices[rxq->port_id].
 978                             data->rx_mbuf_alloc_failed++;
 979                         rxq->rx_alloc_errors++;
 980                         break;
 981                 }
 982
 983                 qede_rx_bd_ring_consume(rxq);
 984
 985                 if (fp_cqe->bd_num > 1) {
 986                         pkt_len = rte_le_to_cpu_16(fp_cqe->pkt_len);
 987                         num_segs = fp_cqe->bd_num - 1;
 988
 989                         rxq->rx_segs++;
 990
 991                         pkt_len -= len;
 992                         seg1 = rx_mb;
 993                         ret = qede_process_sg_pkts(p_rxq, seg1, num_segs,
 994                                                    pkt_len);
 995                         if (ret != ECORE_SUCCESS) {
 996                                 qede_recycle_rx_bd_ring(rxq, qdev,
 997                                                         fp_cqe->bd_num);
 998                                 goto next_cqe;
 999                         }
1000                 }
1001
1002                 /* Prefetch next mbuf while processing current one. */
1003                 preload_idx = rxq->sw_rx_cons & NUM_RX_BDS(rxq);
1004                 rte_prefetch0(rxq->sw_rx_ring[preload_idx].mbuf);
1005
1006                 /* Update rest of the MBUF fields */
1007                 rx_mb->data_off = pad + RTE_PKTMBUF_HEADROOM;
1008                 rx_mb->nb_segs = fp_cqe->bd_num;
1009                 rx_mb->data_len = len;
1010                 rx_mb->pkt_len = fp_cqe->pkt_len;
1011                 rx_mb->port = rxq->port_id;
1012
1013                 htype = (uint8_t)GET_FIELD(fp_cqe->bitfields,
1014                                 ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE);
1015                 if (qdev->rss_enable && htype) {
1016                         rx_mb->ol_flags |= PKT_RX_RSS_HASH;
1017                         rx_mb->hash.rss = rte_le_to_cpu_32(fp_cqe->rss_hash);
1018                         PMD_RX_LOG(DEBUG, rxq, "Hash result 0x%x\n",
1019                                    rx_mb->hash.rss);
1020                 }
1021
1022                 rte_prefetch1(rte_pktmbuf_mtod(rx_mb, void *));
1023
1024                 if (CQE_HAS_VLAN(parse_flag)) {
1025                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1026                         rx_mb->ol_flags |= PKT_RX_VLAN_PKT;
1027                 }
1028
1029                 if (CQE_HAS_OUTER_VLAN(parse_flag)) {
1030                         /* FW does not provide indication of Outer VLAN tag,
1031                          * which is always stripped, so vlan_tci_outer is set
1032                          * to 0. Here vlan_tag represents inner VLAN tag.
1033                          */
1034                         rx_mb->vlan_tci = rte_le_to_cpu_16(fp_cqe->vlan_tag);
1035                         rx_mb->ol_flags |= PKT_RX_QINQ_PKT;
1036                         rx_mb->vlan_tci_outer = 0;
1037                 }
1038
1039                 rx_pkts[rx_pkt] = rx_mb;
1040                 rx_pkt++;
1041 next_cqe:
1042                 ecore_chain_recycle_consumed(&rxq->rx_comp_ring);
1043                 sw_comp_cons = ecore_chain_get_cons_idx(&rxq->rx_comp_ring);
1044                 if (rx_pkt == nb_pkts) {
1045                         PMD_RX_LOG(DEBUG, rxq,
1046                                    "Budget reached nb_pkts=%u received=%u\n",
1047                                    rx_pkt, nb_pkts);
1048                         break;
1049                 }
1050         }
1051
1052         qede_update_rx_prod(qdev, rxq);
1053
1054         rxq->rcv_pkts += rx_pkt;
1055
1056         PMD_RX_LOG(DEBUG, rxq, "rx_pkts=%u core=%d\n", rx_pkt, rte_lcore_id());
1057
1058         return rx_pkt;
1059 }
1060
1061 static inline int
1062 qede_free_tx_pkt(struct ecore_dev *edev, struct qede_tx_queue *txq)
1063 {
1064         uint16_t nb_segs, idx = TX_CONS(txq);
1065         struct eth_tx_bd *tx_data_bd;
1066         struct rte_mbuf *mbuf = txq->sw_tx_ring[idx].mbuf;
1067
1068         if (unlikely(!mbuf)) {
1069                 PMD_TX_LOG(ERR, txq, "null mbuf\n");
1070                 PMD_TX_LOG(ERR, txq,
1071                            "tx_desc %u tx_avail %u tx_cons %u tx_prod %u\n",
1072                            txq->nb_tx_desc, txq->nb_tx_avail, idx,
1073                            TX_PROD(txq));
1074                 return -1;
1075         }
1076
1077         nb_segs = mbuf->nb_segs;
1078         while (nb_segs) {
1079                 /* It's like consuming rxbuf in recv() */
1080                 ecore_chain_consume(&txq->tx_pbl);
1081                 txq->nb_tx_avail++;
1082                 nb_segs--;
1083         }
1084         rte_pktmbuf_free(mbuf);
1085         txq->sw_tx_ring[idx].mbuf = NULL;
1086
1087         return 0;
1088 }
1089
1090 static inline uint16_t
1091 qede_process_tx_compl(struct ecore_dev *edev, struct qede_tx_queue *txq)
1092 {
1093         uint16_t tx_compl = 0;
1094         uint16_t hw_bd_cons;
1095
1096         hw_bd_cons = rte_le_to_cpu_16(*txq->hw_cons_ptr);
1097         rte_compiler_barrier();
1098
1099         while (hw_bd_cons != ecore_chain_get_cons_idx(&txq->tx_pbl)) {
1100                 if (qede_free_tx_pkt(edev, txq)) {
1101                         PMD_TX_LOG(ERR, txq,
1102                                    "hw_bd_cons = %u, chain_cons = %u\n",
1103                                    hw_bd_cons,
1104                                    ecore_chain_get_cons_idx(&txq->tx_pbl));
1105                         break;
1106                 }
1107                 txq->sw_tx_cons++;      /* Making TXD available */
1108                 tx_compl++;
1109         }
1110
1111         PMD_TX_LOG(DEBUG, txq, "Tx compl %u sw_tx_cons %u avail %u\n",
1112                    tx_compl, txq->sw_tx_cons, txq->nb_tx_avail);
1113         return tx_compl;
1114 }
1115
1116 /* Populate scatter gather buffer descriptor fields */
1117 static inline uint16_t qede_encode_sg_bd(struct qede_tx_queue *p_txq,
1118                                          struct rte_mbuf *m_seg,
1119                                          uint16_t count,
1120                                          struct eth_tx_1st_bd *bd1)
1121 {
1122         struct qede_tx_queue *txq = p_txq;
1123         struct eth_tx_2nd_bd *bd2 = NULL;
1124         struct eth_tx_3rd_bd *bd3 = NULL;
1125         struct eth_tx_bd *tx_bd = NULL;
1126         uint16_t nb_segs = count;
1127         dma_addr_t mapping;
1128
1129         /* Check for scattered buffers */
1130         while (m_seg) {
1131                 if (nb_segs == 1) {
1132                         bd2 = (struct eth_tx_2nd_bd *)
1133                                 ecore_chain_produce(&txq->tx_pbl);
1134                         memset(bd2, 0, sizeof(*bd2));
1135                         mapping = rte_mbuf_data_dma_addr(m_seg);
1136                         bd2->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1137                         bd2->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1138                         bd2->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1139                 } else if (nb_segs == 2) {
1140                         bd3 = (struct eth_tx_3rd_bd *)
1141                                 ecore_chain_produce(&txq->tx_pbl);
1142                         memset(bd3, 0, sizeof(*bd3));
1143                         mapping = rte_mbuf_data_dma_addr(m_seg);
1144                         bd3->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1145                         bd3->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1146                         bd3->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1147                 } else {
1148                         tx_bd = (struct eth_tx_bd *)
1149                                 ecore_chain_produce(&txq->tx_pbl);
1150                         memset(tx_bd, 0, sizeof(*tx_bd));
1151                         mapping = rte_mbuf_data_dma_addr(m_seg);
1152                         tx_bd->addr.hi = rte_cpu_to_le_32(U64_HI(mapping));
1153                         tx_bd->addr.lo = rte_cpu_to_le_32(U64_LO(mapping));
1154                         tx_bd->nbytes = rte_cpu_to_le_16(m_seg->data_len);
1155                 }
1156                 nb_segs++;
1157                 bd1->data.nbds = nb_segs;
1158                 m_seg = m_seg->next;
1159         }
1160
1161         /* Return total scattered buffers */
1162         return nb_segs;
1163 }
1164
1165 uint16_t
1166 qede_xmit_pkts(void *p_txq, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1167 {
1168         struct qede_tx_queue *txq = p_txq;
1169         struct qede_dev *qdev = txq->qdev;
1170         struct ecore_dev *edev = &qdev->edev;
1171         struct qede_fastpath *fp;
1172         struct eth_tx_1st_bd *bd1;
1173         struct rte_mbuf *m_seg = NULL;
1174         uint16_t nb_tx_pkts;
1175         uint16_t nb_pkt_sent = 0;
1176         uint16_t bd_prod;
1177         uint16_t idx;
1178         uint16_t tx_count;
1179         uint16_t nb_segs = 0;
1180
1181         fp = &qdev->fp_array[QEDE_RSS_COUNT(qdev) + txq->queue_id];
1182
1183         if (unlikely(txq->nb_tx_avail < txq->tx_free_thresh)) {
1184                 PMD_TX_LOG(DEBUG, txq, "send=%u avail=%u free_thresh=%u\n",
1185                            nb_pkts, txq->nb_tx_avail, txq->tx_free_thresh);
1186                 (void)qede_process_tx_compl(edev, txq);
1187         }
1188
1189         nb_tx_pkts = RTE_MIN(nb_pkts, (txq->nb_tx_avail /
1190                         ETH_TX_MAX_BDS_PER_NON_LSO_PACKET));
1191         if (unlikely(nb_tx_pkts == 0)) {
1192                 PMD_TX_LOG(DEBUG, txq, "Out of BDs nb_pkts=%u avail=%u\n",
1193                            nb_pkts, txq->nb_tx_avail);
1194                 return 0;
1195         }
1196
1197         tx_count = nb_tx_pkts;
1198         while (nb_tx_pkts--) {
1199                 /* Fill the entry in the SW ring and the BDs in the FW ring */
1200                 idx = TX_PROD(txq);
1201                 struct rte_mbuf *mbuf = *tx_pkts++;
1202
1203                 txq->sw_tx_ring[idx].mbuf = mbuf;
1204                 bd1 = (struct eth_tx_1st_bd *)ecore_chain_produce(&txq->tx_pbl);
1205                 /* Zero init struct fields */
1206                 bd1->data.bd_flags.bitfields = 0;
1207                 bd1->data.bitfields = 0;
1208
1209                 bd1->data.bd_flags.bitfields =
1210                         1 << ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT;
1211                 /* Map MBUF linear data for DMA and set in the first BD */
1212                 QEDE_BD_SET_ADDR_LEN(bd1, rte_mbuf_data_dma_addr(mbuf),
1213                                      mbuf->pkt_len);
1214
1215                 if (RTE_ETH_IS_TUNNEL_PKT(mbuf->packet_type)) {
1216                         PMD_TX_LOG(INFO, txq, "Tx tunnel packet\n");
1217                         /* First indicate its a tunnel pkt */
1218                         bd1->data.bd_flags.bitfields |=
1219                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK <<
1220                                 ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1221
1222                         /* Legacy FW had flipped behavior in regard to this bit
1223                          * i.e. it needed to set to prevent FW from touching
1224                          * encapsulated packets when it didn't need to.
1225                          */
1226                         if (unlikely(txq->is_legacy))
1227                                 bd1->data.bitfields ^=
1228                                         1 << ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT;
1229
1230                         /* Outer IP checksum offload */
1231                         if (mbuf->ol_flags & PKT_TX_OUTER_IP_CKSUM) {
1232                                 PMD_TX_LOG(INFO, txq, "OuterIP csum offload\n");
1233                                 bd1->data.bd_flags.bitfields |=
1234                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK <<
1235                                         ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT;
1236                         }
1237
1238                         /* Outer UDP checksum offload */
1239                         bd1->data.bd_flags.bitfields |=
1240                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK <<
1241                                 ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT;
1242                 }
1243
1244                 /* Descriptor based VLAN insertion */
1245                 if (mbuf->ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1246                         PMD_TX_LOG(INFO, txq, "Insert VLAN 0x%x\n",
1247                                    mbuf->vlan_tci);
1248                         bd1->data.vlan = rte_cpu_to_le_16(mbuf->vlan_tci);
1249                         bd1->data.bd_flags.bitfields |=
1250                             1 << ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT;
1251                 }
1252
1253                 /* Offload the IP checksum in the hardware */
1254                 if (mbuf->ol_flags & PKT_TX_IP_CKSUM) {
1255                         PMD_TX_LOG(INFO, txq, "IP csum offload\n");
1256                         bd1->data.bd_flags.bitfields |=
1257                             1 << ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT;
1258                 }
1259
1260                 /* L4 checksum offload (tcp or udp) */
1261                 if (mbuf->ol_flags & (PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
1262                         PMD_TX_LOG(INFO, txq, "L4 csum offload\n");
1263                         bd1->data.bd_flags.bitfields |=
1264                             1 << ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT;
1265                         /* IPv6 + extn. -> later */
1266                 }
1267
1268                 /* Handle fragmented MBUF */
1269                 m_seg = mbuf->next;
1270                 nb_segs++;
1271                 bd1->data.nbds = nb_segs;
1272                 /* Encode scatter gather buffer descriptors if required */
1273                 nb_segs = qede_encode_sg_bd(txq, m_seg, nb_segs, bd1);
1274                 txq->nb_tx_avail = txq->nb_tx_avail - nb_segs;
1275                 nb_segs = 0;
1276                 txq->sw_tx_prod++;
1277                 rte_prefetch0(txq->sw_tx_ring[TX_PROD(txq)].mbuf);
1278                 bd_prod =
1279                     rte_cpu_to_le_16(ecore_chain_get_prod_idx(&txq->tx_pbl));
1280                 nb_pkt_sent++;
1281                 txq->xmit_pkts++;
1282         }
1283
1284         /* Write value of prod idx into bd_prod */
1285         txq->tx_db.data.bd_prod = bd_prod;
1286         rte_wmb();
1287         rte_compiler_barrier();
1288         DIRECT_REG_WR(edev, txq->doorbell_addr, txq->tx_db.raw);
1289         rte_wmb();
1290
1291         /* Check again for Tx completions */
1292         (void)qede_process_tx_compl(edev, txq);
1293
1294         PMD_TX_LOG(DEBUG, txq, "to_send=%u can_send=%u sent=%u core=%d\n",
1295                    nb_pkts, tx_count, nb_pkt_sent, rte_lcore_id());
1296
1297         return nb_pkt_sent;
1298 }
1299
1300 static void qede_init_fp_queue(struct rte_eth_dev *eth_dev)
1301 {
1302         struct qede_dev *qdev = eth_dev->data->dev_private;
1303         struct qede_fastpath *fp;
1304         uint8_t i, rss_id, txq_index, tc;
1305         int rxq = 0, txq = 0;
1306
1307         for_each_queue(i) {
1308                 fp = &qdev->fp_array[i];
1309                 if (fp->type & QEDE_FASTPATH_RX) {
1310                         fp->rxq = eth_dev->data->rx_queues[i];
1311                         fp->rxq->queue_id = rxq++;
1312                 }
1313
1314                 if (fp->type & QEDE_FASTPATH_TX) {
1315                         for (tc = 0; tc < qdev->num_tc; tc++) {
1316                                 txq_index = tc * QEDE_TSS_COUNT(qdev) + txq;
1317                                 fp->txqs[tc] =
1318                                         eth_dev->data->tx_queues[txq_index];
1319                                 fp->txqs[tc]->queue_id = txq_index;
1320                                 if (qdev->dev_info.is_legacy)
1321                                         fp->txqs[tc]->is_legacy = true;
1322                         }
1323                         txq++;
1324                 }
1325         }
1326 }
1327
1328 int qede_dev_start(struct rte_eth_dev *eth_dev)
1329 {
1330         struct qede_dev *qdev = eth_dev->data->dev_private;
1331         struct ecore_dev *edev = &qdev->edev;
1332         struct qed_link_output link_output;
1333         struct qede_fastpath *fp;
1334         int rc;
1335
1336         DP_INFO(edev, "Device state is %d\n", qdev->state);
1337
1338         if (qdev->state == QEDE_DEV_START) {
1339                 DP_INFO(edev, "Port is already started\n");
1340                 return 0;
1341         }
1342
1343         if (qdev->state == QEDE_DEV_CONFIG)
1344                 qede_init_fp_queue(eth_dev);
1345
1346         rc = qede_start_queues(eth_dev, true);
1347         if (rc) {
1348                 DP_ERR(edev, "Failed to start queues\n");
1349                 /* TBD: free */
1350                 return rc;
1351         }
1352
1353         /* Bring-up the link */
1354         qede_dev_set_link_state(eth_dev, true);
1355
1356         /* Reset ring */
1357         if (qede_reset_fp_rings(qdev))
1358                 return -ENOMEM;
1359
1360         /* Start/resume traffic */
1361         qdev->ops->fastpath_start(edev);
1362
1363         qdev->state = QEDE_DEV_START;
1364
1365         DP_INFO(edev, "dev_state is QEDE_DEV_START\n");
1366
1367         return 0;
1368 }
1369
1370 static int qede_drain_txq(struct qede_dev *qdev,
1371                           struct qede_tx_queue *txq, bool allow_drain)
1372 {
1373         struct ecore_dev *edev = &qdev->edev;
1374         int rc, cnt = 1000;
1375
1376         while (txq->sw_tx_cons != txq->sw_tx_prod) {
1377                 qede_process_tx_compl(edev, txq);
1378                 if (!cnt) {
1379                         if (allow_drain) {
1380                                 DP_NOTICE(edev, false,
1381                                           "Tx queue[%u] is stuck,"
1382                                           "requesting MCP to drain\n",
1383                                           txq->queue_id);
1384                                 rc = qdev->ops->common->drain(edev);
1385                                 if (rc)
1386                                         return rc;
1387                                 return qede_drain_txq(qdev, txq, false);
1388                         }
1389
1390                         DP_NOTICE(edev, false,
1391                                   "Timeout waiting for tx queue[%d]:"
1392                                   "PROD=%d, CONS=%d\n",
1393                                   txq->queue_id, txq->sw_tx_prod,
1394                                   txq->sw_tx_cons);
1395                         return -ENODEV;
1396                 }
1397                 cnt--;
1398                 DELAY(1000);
1399                 rte_compiler_barrier();
1400         }
1401
1402         /* FW finished processing, wait for HW to transmit all tx packets */
1403         DELAY(2000);
1404
1405         return 0;
1406 }
1407
1408 static int qede_stop_queues(struct qede_dev *qdev)
1409 {
1410         struct qed_update_vport_params vport_update_params;
1411         struct ecore_dev *edev = &qdev->edev;
1412         int rc, tc, i;
1413
1414         /* Disable the vport */
1415         memset(&vport_update_params, 0, sizeof(vport_update_params));
1416         vport_update_params.vport_id = 0;
1417         vport_update_params.update_vport_active_flg = 1;
1418         vport_update_params.vport_active_flg = 0;
1419         vport_update_params.update_rss_flg = 0;
1420
1421         DP_INFO(edev, "Deactivate vport\n");
1422
1423         rc = qdev->ops->vport_update(edev, &vport_update_params);
1424         if (rc) {
1425                 DP_ERR(edev, "Failed to update vport\n");
1426                 return rc;
1427         }
1428
1429         DP_INFO(edev, "Flushing tx queues\n");
1430
1431         /* Flush Tx queues. If needed, request drain from MCP */
1432         for_each_queue(i) {
1433                 struct qede_fastpath *fp = &qdev->fp_array[i];
1434
1435                 if (fp->type & QEDE_FASTPATH_TX) {
1436                         for (tc = 0; tc < qdev->num_tc; tc++) {
1437                                 struct qede_tx_queue *txq = fp->txqs[tc];
1438
1439                                 rc = qede_drain_txq(qdev, txq, true);
1440                                 if (rc)
1441                                         return rc;
1442                         }
1443                 }
1444         }
1445
1446         /* Stop all Queues in reverse order */
1447         for (i = QEDE_QUEUE_CNT(qdev) - 1; i >= 0; i--) {
1448                 struct qed_stop_rxq_params rx_params;
1449
1450                 /* Stop the Tx Queue(s) */
1451                 if (qdev->fp_array[i].type & QEDE_FASTPATH_TX) {
1452                         for (tc = 0; tc < qdev->num_tc; tc++) {
1453                                 struct qed_stop_txq_params tx_params;
1454                                 u8 val;
1455
1456                                 tx_params.rss_id = i;
1457                                 val = qdev->fp_array[i].txqs[tc]->queue_id;
1458                                 tx_params.tx_queue_id = val;
1459
1460                                 DP_INFO(edev, "Stopping tx queues\n");
1461                                 rc = qdev->ops->q_tx_stop(edev, &tx_params);
1462                                 if (rc) {
1463                                         DP_ERR(edev, "Failed to stop TXQ #%d\n",
1464                                                tx_params.tx_queue_id);
1465                                         return rc;
1466                                 }
1467                         }
1468                 }
1469
1470                 /* Stop the Rx Queue */
1471                 if (qdev->fp_array[i].type & QEDE_FASTPATH_RX) {
1472                         memset(&rx_params, 0, sizeof(rx_params));
1473                         rx_params.rss_id = i;
1474                         rx_params.rx_queue_id = qdev->fp_array[i].rxq->queue_id;
1475                         rx_params.eq_completion_only = 1;
1476
1477                         DP_INFO(edev, "Stopping rx queues\n");
1478
1479                         rc = qdev->ops->q_rx_stop(edev, &rx_params);
1480                         if (rc) {
1481                                 DP_ERR(edev, "Failed to stop RXQ #%d\n", i);
1482                                 return rc;
1483                         }
1484                 }
1485         }
1486
1487         return 0;
1488 }
1489
1490 int qede_reset_fp_rings(struct qede_dev *qdev)
1491 {
1492         struct qede_fastpath *fp;
1493         struct qede_tx_queue *txq;
1494         uint8_t tc;
1495         uint16_t id, i;
1496
1497         for_each_queue(id) {
1498                 fp = &qdev->fp_array[id];
1499
1500                 if (fp->type & QEDE_FASTPATH_RX) {
1501                         DP_INFO(&qdev->edev,
1502                                 "Reset FP chain for RSS %u\n", id);
1503                         qede_rx_queue_release_mbufs(fp->rxq);
1504                         ecore_chain_reset(&fp->rxq->rx_bd_ring);
1505                         ecore_chain_reset(&fp->rxq->rx_comp_ring);
1506                         fp->rxq->sw_rx_prod = 0;
1507                         fp->rxq->sw_rx_cons = 0;
1508                         *fp->rxq->hw_cons_ptr = 0;
1509                         for (i = 0; i < fp->rxq->nb_rx_desc; i++) {
1510                                 if (qede_alloc_rx_buffer(fp->rxq)) {
1511                                         DP_ERR(&qdev->edev,
1512                                                "RX buffer allocation failed\n");
1513                                         return -ENOMEM;
1514                                 }
1515                         }
1516                 }
1517                 if (fp->type & QEDE_FASTPATH_TX) {
1518                         for (tc = 0; tc < qdev->num_tc; tc++) {
1519                                 txq = fp->txqs[tc];
1520                                 qede_tx_queue_release_mbufs(txq);
1521                                 ecore_chain_reset(&txq->tx_pbl);
1522                                 txq->sw_tx_cons = 0;
1523                                 txq->sw_tx_prod = 0;
1524                                 *txq->hw_cons_ptr = 0;
1525                         }
1526                 }
1527         }
1528
1529         return 0;
1530 }
1531
1532 /* This function frees all memory of a single fp */
1533 void qede_free_mem_load(struct rte_eth_dev *eth_dev)
1534 {
1535         struct qede_dev *qdev = QEDE_INIT_QDEV(eth_dev);
1536         struct qede_fastpath *fp;
1537         uint16_t txq_idx;
1538         uint8_t id;
1539         uint8_t tc;
1540
1541         for_each_queue(id) {
1542                 fp = &qdev->fp_array[id];
1543                 if (fp->type & QEDE_FASTPATH_RX) {
1544                         if (!fp->rxq)
1545                                 continue;
1546                         qede_rx_queue_release(fp->rxq);
1547                         eth_dev->data->rx_queues[id] = NULL;
1548                 } else {
1549                         for (tc = 0; tc < qdev->num_tc; tc++) {
1550                                 if (!fp->txqs[tc])
1551                                         continue;
1552                                 txq_idx = fp->txqs[tc]->queue_id;
1553                                 qede_tx_queue_release(fp->txqs[tc]);
1554                                 eth_dev->data->tx_queues[txq_idx] = NULL;
1555                         }
1556                 }
1557         }
1558 }
1559
1560 void qede_dev_stop(struct rte_eth_dev *eth_dev)
1561 {
1562         struct qede_dev *qdev = eth_dev->data->dev_private;
1563         struct ecore_dev *edev = &qdev->edev;
1564
1565         DP_INFO(edev, "port %u\n", eth_dev->data->port_id);
1566
1567         if (qdev->state != QEDE_DEV_START) {
1568                 DP_INFO(edev, "Device not yet started\n");
1569                 return;
1570         }
1571
1572         if (qede_stop_queues(qdev))
1573                 DP_ERR(edev, "Didn't succeed to close queues\n");
1574
1575         DP_INFO(edev, "Stopped queues\n");
1576
1577         qdev->ops->fastpath_stop(edev);
1578
1579         /* Bring the link down */
1580         qede_dev_set_link_state(eth_dev, false);
1581
1582         qdev->state = QEDE_DEV_STOP;
1583
1584         DP_INFO(edev, "dev_state is QEDE_DEV_STOP\n");
1585 }