2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
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14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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34 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
36 #define EFX_EV_QSTAT_INCR(_eep, _stat)
39 * Non-interrupting event queue requires interrrupting event queue to
40 * refer to for wake-up events even if wake ups are never used.
41 * It could be even non-allocated event queue.
43 #define EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX (0)
45 static __checkReturn boolean_t
48 __in efx_qword_t *eqp,
49 __in const efx_ev_callbacks_t *eecp,
52 static __checkReturn boolean_t
55 __in efx_qword_t *eqp,
56 __in const efx_ev_callbacks_t *eecp,
59 static __checkReturn boolean_t
62 __in efx_qword_t *eqp,
63 __in const efx_ev_callbacks_t *eecp,
66 static __checkReturn boolean_t
69 __in efx_qword_t *eqp,
70 __in const efx_ev_callbacks_t *eecp,
73 static __checkReturn boolean_t
76 __in efx_qword_t *eqp,
77 __in const efx_ev_callbacks_t *eecp,
81 static __checkReturn efx_rc_t
84 __in uint32_t instance,
86 __in uint32_t timer_ns)
89 uint8_t payload[MAX(MC_CMD_SET_EVQ_TMR_IN_LEN,
90 MC_CMD_SET_EVQ_TMR_OUT_LEN)];
93 (void) memset(payload, 0, sizeof (payload));
94 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
95 req.emr_in_buf = payload;
96 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
97 req.emr_out_buf = payload;
98 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
100 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
101 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
102 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
103 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
105 efx_mcdi_execute(enp, &req);
107 if (req.emr_rc != 0) {
112 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
122 EFSYS_PROBE1(fail1, efx_rc_t, rc);
127 static __checkReturn efx_rc_t
130 __in unsigned int instance,
131 __in efsys_mem_t *esmp,
136 __in boolean_t low_latency)
140 MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
141 MC_CMD_INIT_EVQ_OUT_LEN)];
142 efx_qword_t *dma_addr;
146 boolean_t interrupting;
150 npages = EFX_EVQ_NBUFS(nevs);
151 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
156 (void) memset(payload, 0, sizeof (payload));
157 req.emr_cmd = MC_CMD_INIT_EVQ;
158 req.emr_in_buf = payload;
159 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
160 req.emr_out_buf = payload;
161 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
163 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
164 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
165 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
167 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
168 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
171 * On Huntington RX and TX event batching can only be requested together
172 * (even if the datapath firmware doesn't actually support RX
173 * batching). If event cut through is enabled no RX batching will occur.
175 * So always enable RX and TX event batching, and enable event cut
176 * through if we want low latency operation.
178 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
179 case EFX_EVQ_FLAGS_TYPE_AUTO:
180 ev_cut_through = low_latency ? 1 : 0;
182 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
185 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
192 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
193 INIT_EVQ_IN_FLAG_INTERRUPTING, interrupting,
194 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
195 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
196 INIT_EVQ_IN_FLAG_CUT_THRU, ev_cut_through,
197 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
198 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
200 /* If the value is zero then disable the timer */
202 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
203 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
204 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
205 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
209 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
212 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
213 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
214 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, ticks);
215 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, ticks);
218 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
219 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
220 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
222 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
223 addr = EFSYS_MEM_ADDR(esmp);
225 for (i = 0; i < npages; i++) {
226 EFX_POPULATE_QWORD_2(*dma_addr,
227 EFX_DWORD_1, (uint32_t)(addr >> 32),
228 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
231 addr += EFX_BUF_SIZE;
234 efx_mcdi_execute(enp, &req);
236 if (req.emr_rc != 0) {
241 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
246 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
259 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 static __checkReturn efx_rc_t
266 efx_mcdi_init_evq_v2(
268 __in unsigned int instance,
269 __in efsys_mem_t *esmp,
277 MAX(MC_CMD_INIT_EVQ_V2_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
278 MC_CMD_INIT_EVQ_V2_OUT_LEN)];
279 boolean_t interrupting;
280 unsigned int evq_type;
281 efx_qword_t *dma_addr;
287 npages = EFX_EVQ_NBUFS(nevs);
288 if (MC_CMD_INIT_EVQ_V2_IN_LEN(npages) > MC_CMD_INIT_EVQ_V2_IN_LENMAX) {
293 (void) memset(payload, 0, sizeof (payload));
294 req.emr_cmd = MC_CMD_INIT_EVQ;
295 req.emr_in_buf = payload;
296 req.emr_in_length = MC_CMD_INIT_EVQ_V2_IN_LEN(npages);
297 req.emr_out_buf = payload;
298 req.emr_out_length = MC_CMD_INIT_EVQ_V2_OUT_LEN;
300 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_SIZE, nevs);
301 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_INSTANCE, instance);
302 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_IRQ_NUM, irq);
304 interrupting = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
305 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
307 switch (flags & EFX_EVQ_FLAGS_TYPE_MASK) {
308 case EFX_EVQ_FLAGS_TYPE_AUTO:
309 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO;
311 case EFX_EVQ_FLAGS_TYPE_THROUGHPUT:
312 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT;
314 case EFX_EVQ_FLAGS_TYPE_LOW_LATENCY:
315 evq_type = MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY;
321 MCDI_IN_POPULATE_DWORD_4(req, INIT_EVQ_V2_IN_FLAGS,
322 INIT_EVQ_V2_IN_FLAG_INTERRUPTING, interrupting,
323 INIT_EVQ_V2_IN_FLAG_RPTR_DOS, 0,
324 INIT_EVQ_V2_IN_FLAG_INT_ARMD, 0,
325 INIT_EVQ_V2_IN_FLAG_TYPE, evq_type);
327 /* If the value is zero then disable the timer */
329 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
330 MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS);
331 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, 0);
332 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, 0);
336 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
339 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_MODE,
340 MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF);
341 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_LOAD, ticks);
342 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_TMR_RELOAD, ticks);
345 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_MODE,
346 MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS);
347 MCDI_IN_SET_DWORD(req, INIT_EVQ_V2_IN_COUNT_THRSHLD, 0);
349 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_V2_IN_DMA_ADDR);
350 addr = EFSYS_MEM_ADDR(esmp);
352 for (i = 0; i < npages; i++) {
353 EFX_POPULATE_QWORD_2(*dma_addr,
354 EFX_DWORD_1, (uint32_t)(addr >> 32),
355 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
358 addr += EFX_BUF_SIZE;
361 efx_mcdi_execute(enp, &req);
363 if (req.emr_rc != 0) {
368 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_V2_OUT_LEN) {
373 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
375 EFSYS_PROBE1(mcdi_evq_flags, uint32_t,
376 MCDI_OUT_DWORD(req, INIT_EVQ_V2_OUT_FLAGS));
389 EFSYS_PROBE1(fail1, efx_rc_t, rc);
394 static __checkReturn efx_rc_t
397 __in uint32_t instance)
400 uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
401 MC_CMD_FINI_EVQ_OUT_LEN)];
404 (void) memset(payload, 0, sizeof (payload));
405 req.emr_cmd = MC_CMD_FINI_EVQ;
406 req.emr_in_buf = payload;
407 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
408 req.emr_out_buf = payload;
409 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
411 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
413 efx_mcdi_execute_quiet(enp, &req);
415 if (req.emr_rc != 0) {
423 EFSYS_PROBE1(fail1, efx_rc_t, rc);
430 __checkReturn efx_rc_t
434 _NOTE(ARGUNUSED(enp))
442 _NOTE(ARGUNUSED(enp))
445 __checkReturn efx_rc_t
448 __in unsigned int index,
449 __in efsys_mem_t *esmp,
456 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
460 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
461 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
462 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
464 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
469 if (index >= encp->enc_evq_limit) {
474 if (us > encp->enc_evq_timer_max_us) {
479 /* Set up the handler table */
480 eep->ee_rx = ef10_ev_rx;
481 eep->ee_tx = ef10_ev_tx;
482 eep->ee_driver = ef10_ev_driver;
483 eep->ee_drv_gen = ef10_ev_drv_gen;
484 eep->ee_mcdi = ef10_ev_mcdi;
486 /* Set up the event queue */
487 /* INIT_EVQ expects function-relative vector number */
488 if ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
489 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT) {
491 } else if (index == EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX) {
493 flags = (flags & ~EFX_EVQ_FLAGS_NOTIFY_MASK) |
494 EFX_EVQ_FLAGS_NOTIFY_INTERRUPT;
496 irq = EFX_EF10_ALWAYS_INTERRUPTING_EVQ_INDEX;
500 * Interrupts may be raised for events immediately after the queue is
501 * created. See bug58606.
504 if (encp->enc_init_evq_v2_supported) {
506 * On Medford the low latency license is required to enable RX
507 * and event cut through and to disable RX batching. If event
508 * queue type in flags is auto, we let the firmware decide the
509 * settings to use. If the adapter has a low latency license,
510 * it will choose the best settings for low latency, otherwise
511 * it will choose the best settings for throughput.
513 rc = efx_mcdi_init_evq_v2(enp, index, esmp, n, irq, us, flags);
518 * On Huntington we need to specify the settings to use.
519 * If event queue type in flags is auto, we favour throughput
520 * if the adapter is running virtualization supporting firmware
521 * (i.e. the full featured firmware variant)
522 * and latency otherwise. The Ethernet Virtual Bridging
523 * capability is used to make this decision. (Note though that
524 * the low latency firmware variant is also best for
525 * throughput and corresponding type should be specified
528 boolean_t low_latency = encp->enc_datapath_cap_evb ? 0 : 1;
529 rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us, flags,
546 EFSYS_PROBE1(fail1, efx_rc_t, rc);
555 efx_nic_t *enp = eep->ee_enp;
557 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
558 enp->en_family == EFX_FAMILY_MEDFORD);
560 (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
563 __checkReturn efx_rc_t
566 __in unsigned int count)
568 efx_nic_t *enp = eep->ee_enp;
572 rptr = count & eep->ee_mask;
574 if (enp->en_nic_cfg.enc_bug35388_workaround) {
575 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
576 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
577 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
578 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
580 EFX_POPULATE_DWORD_2(dword,
581 ERF_DD_EVQ_IND_RPTR_FLAGS,
582 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
584 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
585 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
588 EFX_POPULATE_DWORD_2(dword,
589 ERF_DD_EVQ_IND_RPTR_FLAGS,
590 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
592 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
593 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
596 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
597 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
604 static __checkReturn efx_rc_t
605 efx_mcdi_driver_event(
608 __in efx_qword_t data)
611 uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
612 MC_CMD_DRIVER_EVENT_OUT_LEN)];
615 req.emr_cmd = MC_CMD_DRIVER_EVENT;
616 req.emr_in_buf = payload;
617 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
618 req.emr_out_buf = payload;
619 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
621 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
623 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
624 EFX_QWORD_FIELD(data, EFX_DWORD_0));
625 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
626 EFX_QWORD_FIELD(data, EFX_DWORD_1));
628 efx_mcdi_execute(enp, &req);
630 if (req.emr_rc != 0) {
638 EFSYS_PROBE1(fail1, efx_rc_t, rc);
648 efx_nic_t *enp = eep->ee_enp;
651 EFX_POPULATE_QWORD_3(event,
652 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
653 ESF_DZ_DRV_SUB_CODE, 0,
654 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
656 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
659 __checkReturn efx_rc_t
662 __in unsigned int us)
664 efx_nic_t *enp = eep->ee_enp;
665 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
670 /* Check that hardware and MCDI use the same timer MODE values */
671 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
672 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
673 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
674 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
675 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
676 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
677 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
678 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
680 if (us > encp->enc_evq_timer_max_us) {
685 /* If the value is zero then disable the timer */
687 mode = FFE_CZ_TIMER_MODE_DIS;
689 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
692 if (encp->enc_bug61265_workaround) {
693 uint32_t ns = us * 1000;
695 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, ns);
701 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
704 if (encp->enc_bug35388_workaround) {
705 EFX_POPULATE_DWORD_3(dword,
706 ERF_DD_EVQ_IND_TIMER_FLAGS,
707 EFE_DD_EVQ_IND_TIMER_FLAGS,
708 ERF_DD_EVQ_IND_TIMER_MODE, mode,
709 ERF_DD_EVQ_IND_TIMER_VAL, ticks);
710 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
711 eep->ee_index, &dword, 0);
713 EFX_POPULATE_DWORD_2(dword,
714 ERF_DZ_TC_TIMER_MODE, mode,
715 ERF_DZ_TC_TIMER_VAL, ticks);
716 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
717 eep->ee_index, &dword, 0);
728 EFSYS_PROBE1(fail1, efx_rc_t, rc);
734 static __checkReturn boolean_t
737 __in efx_qword_t *eqp,
738 __in const efx_ev_callbacks_t *eecp,
741 efx_nic_t *enp = eep->ee_enp;
745 uint32_t eth_tag_class;
748 uint32_t next_read_lbits;
751 boolean_t should_abort;
752 efx_evq_rxq_state_t *eersp;
753 unsigned int desc_count;
754 unsigned int last_used_id;
756 EFX_EV_QSTAT_INCR(eep, EV_RX);
758 /* Discard events after RXQ/TXQ errors */
759 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
762 /* Basic packet information */
763 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
764 eersp = &eep->ee_rxq_state[label];
766 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
767 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
768 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
769 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
770 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
771 l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
772 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
774 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
775 /* Drop this event */
782 * This may be part of a scattered frame, or it may be a
783 * truncated frame if scatter is disabled on this RXQ.
784 * Overlength frames can be received if e.g. a VF is configured
785 * for 1500 MTU but connected to a port set to 9000 MTU
787 * FIXME: There is not yet any driver that supports scatter on
788 * Huntington. Scatter support is required for OSX.
790 flags |= EFX_PKT_CONT;
793 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
794 flags |= EFX_PKT_UNICAST;
796 /* Increment the count of descriptors read */
797 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
798 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
799 eersp->eers_rx_read_ptr += desc_count;
802 * FIXME: add error checking to make sure this a batched event.
803 * This could also be an aborted scatter, see Bug36629.
805 if (desc_count > 1) {
806 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
807 flags |= EFX_PKT_PREFIX_LEN;
810 /* Calculate the index of the last descriptor consumed */
811 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
813 /* Check for errors that invalidate checksum and L3/L4 fields */
814 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
815 /* RX frame truncated (error flag is misnamed) */
816 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
817 flags |= EFX_DISCARD;
820 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
821 /* Bad Ethernet frame CRC */
822 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
823 flags |= EFX_DISCARD;
826 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
828 * Hardware parse failed, due to malformed headers
829 * or headers that are too long for the parser.
830 * Headers and checksums must be validated by the host.
832 /* TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE); */
836 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
837 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
838 flags |= EFX_PKT_VLAN_TAGGED;
842 case ESE_DZ_L3_CLASS_IP4:
843 case ESE_DZ_L3_CLASS_IP4_FRAG:
844 flags |= EFX_PKT_IPV4;
845 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
846 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
848 flags |= EFX_CKSUM_IPV4;
851 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
852 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
853 flags |= EFX_PKT_TCP;
854 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
855 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
856 flags |= EFX_PKT_UDP;
858 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
862 case ESE_DZ_L3_CLASS_IP6:
863 case ESE_DZ_L3_CLASS_IP6_FRAG:
864 flags |= EFX_PKT_IPV6;
866 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
867 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
868 flags |= EFX_PKT_TCP;
869 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
870 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
871 flags |= EFX_PKT_UDP;
873 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
878 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
882 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
883 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
884 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
886 flags |= EFX_CKSUM_TCPUDP;
891 /* If we're not discarding the packet then it is ok */
892 if (~flags & EFX_DISCARD)
893 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
895 EFSYS_ASSERT(eecp->eec_rx != NULL);
896 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
898 return (should_abort);
901 static __checkReturn boolean_t
904 __in efx_qword_t *eqp,
905 __in const efx_ev_callbacks_t *eecp,
908 efx_nic_t *enp = eep->ee_enp;
911 boolean_t should_abort;
913 EFX_EV_QSTAT_INCR(eep, EV_TX);
915 /* Discard events after RXQ/TXQ errors */
916 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
919 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
920 /* Drop this event */
924 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
925 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
926 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
928 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
930 EFSYS_ASSERT(eecp->eec_tx != NULL);
931 should_abort = eecp->eec_tx(arg, label, id);
933 return (should_abort);
936 static __checkReturn boolean_t
939 __in efx_qword_t *eqp,
940 __in const efx_ev_callbacks_t *eecp,
944 boolean_t should_abort;
946 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
947 should_abort = B_FALSE;
949 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
951 case ESE_DZ_DRV_TIMER_EV: {
954 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
956 EFSYS_ASSERT(eecp->eec_timer != NULL);
957 should_abort = eecp->eec_timer(arg, id);
961 case ESE_DZ_DRV_WAKE_UP_EV: {
964 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
966 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
967 should_abort = eecp->eec_wake_up(arg, id);
971 case ESE_DZ_DRV_START_UP_EV:
972 EFSYS_ASSERT(eecp->eec_initialized != NULL);
973 should_abort = eecp->eec_initialized(arg);
977 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
978 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
979 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
983 return (should_abort);
986 static __checkReturn boolean_t
989 __in efx_qword_t *eqp,
990 __in const efx_ev_callbacks_t *eecp,
994 boolean_t should_abort;
996 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
997 should_abort = B_FALSE;
999 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
1000 if (data >= ((uint32_t)1 << 16)) {
1001 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1002 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1003 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1008 EFSYS_ASSERT(eecp->eec_software != NULL);
1009 should_abort = eecp->eec_software(arg, (uint16_t)data);
1011 return (should_abort);
1014 static __checkReturn boolean_t
1016 __in efx_evq_t *eep,
1017 __in efx_qword_t *eqp,
1018 __in const efx_ev_callbacks_t *eecp,
1021 efx_nic_t *enp = eep->ee_enp;
1023 boolean_t should_abort = B_FALSE;
1025 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1027 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1029 case MCDI_EVENT_CODE_BADSSERT:
1030 efx_mcdi_ev_death(enp, EINTR);
1033 case MCDI_EVENT_CODE_CMDDONE:
1034 efx_mcdi_ev_cpl(enp,
1035 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1036 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1037 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1040 #if EFSYS_OPT_MCDI_PROXY_AUTH
1041 case MCDI_EVENT_CODE_PROXY_RESPONSE:
1043 * This event notifies a function that an authorization request
1044 * has been processed. If the request was authorized then the
1045 * function can now re-send the original MCDI request.
1046 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
1048 efx_mcdi_ev_proxy_response(enp,
1049 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
1050 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
1052 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
1054 case MCDI_EVENT_CODE_LINKCHANGE: {
1055 efx_link_mode_t link_mode;
1057 ef10_phy_link_ev(enp, eqp, &link_mode);
1058 should_abort = eecp->eec_link_change(arg, link_mode);
1062 case MCDI_EVENT_CODE_SENSOREVT: {
1066 case MCDI_EVENT_CODE_SCHEDERR:
1067 /* Informational only */
1070 case MCDI_EVENT_CODE_REBOOT:
1071 /* Falcon/Siena only (should not been seen with Huntington). */
1072 efx_mcdi_ev_death(enp, EIO);
1075 case MCDI_EVENT_CODE_MC_REBOOT:
1076 /* MC_REBOOT event is used for Huntington (EF10) and later. */
1077 efx_mcdi_ev_death(enp, EIO);
1080 case MCDI_EVENT_CODE_MAC_STATS_DMA:
1083 case MCDI_EVENT_CODE_FWALERT: {
1084 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1086 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1087 should_abort = eecp->eec_exception(arg,
1088 EFX_EXCEPTION_FWALERT_SRAM,
1089 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1091 should_abort = eecp->eec_exception(arg,
1092 EFX_EXCEPTION_UNKNOWN_FWALERT,
1093 MCDI_EV_FIELD(eqp, DATA));
1097 case MCDI_EVENT_CODE_TX_ERR: {
1099 * After a TXQ error is detected, firmware sends a TX_ERR event.
1100 * This may be followed by TX completions (which we discard),
1101 * and then finally by a TX_FLUSH event. Firmware destroys the
1102 * TXQ automatically after sending the TX_FLUSH event.
1104 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
1106 EFSYS_PROBE2(tx_descq_err,
1107 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1108 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1110 /* Inform the driver that a reset is required. */
1111 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
1112 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
1116 case MCDI_EVENT_CODE_TX_FLUSH: {
1117 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
1120 * EF10 firmware sends two TX_FLUSH events: one to the txq's
1121 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
1122 * We want to wait for all completions, so ignore the events
1123 * with TX_FLUSH_TO_DRIVER.
1125 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
1126 should_abort = B_FALSE;
1130 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
1132 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
1134 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
1135 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
1139 case MCDI_EVENT_CODE_RX_ERR: {
1141 * After an RXQ error is detected, firmware sends an RX_ERR
1142 * event. This may be followed by RX events (which we discard),
1143 * and then finally by an RX_FLUSH event. Firmware destroys the
1144 * RXQ automatically after sending the RX_FLUSH event.
1146 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1148 EFSYS_PROBE2(rx_descq_err,
1149 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1150 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1152 /* Inform the driver that a reset is required. */
1153 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1154 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1158 case MCDI_EVENT_CODE_RX_FLUSH: {
1159 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1162 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1163 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1164 * We want to wait for all completions, so ignore the events
1165 * with RX_FLUSH_TO_DRIVER.
1167 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1168 should_abort = B_FALSE;
1172 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1174 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1176 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1177 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1182 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1183 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1184 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1188 return (should_abort);
1192 ef10_ev_rxlabel_init(
1193 __in efx_evq_t *eep,
1194 __in efx_rxq_t *erp,
1195 __in unsigned int label,
1196 __in boolean_t packed_stream)
1198 efx_evq_rxq_state_t *eersp;
1200 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1201 eersp = &eep->ee_rxq_state[label];
1203 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1205 eersp->eers_rx_read_ptr = 0;
1206 eersp->eers_rx_mask = erp->er_mask;
1207 EFSYS_ASSERT(!packed_stream);
1211 ef10_ev_rxlabel_fini(
1212 __in efx_evq_t *eep,
1213 __in unsigned int label)
1215 efx_evq_rxq_state_t *eersp;
1217 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1218 eersp = &eep->ee_rxq_state[label];
1220 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1222 eersp->eers_rx_read_ptr = 0;
1223 eersp->eers_rx_mask = 0;
1226 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */