2 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
35 #include "efx_check.h"
36 #include "efx_phy_ids.h"
42 #define EFX_STATIC_ASSERT(_cond) \
43 ((void)sizeof(char[(_cond) ? 1 : -1]))
45 #define EFX_ARRAY_SIZE(_array) \
46 (sizeof(_array) / sizeof((_array)[0]))
48 #define EFX_FIELD_OFFSET(_type, _field) \
49 ((size_t) &(((_type *)0)->_field))
53 typedef __success(return == 0) int efx_rc_t;
58 typedef enum efx_family_e {
60 EFX_FAMILY_FALCON, /* Obsolete and not supported */
62 EFX_FAMILY_HUNTINGTON,
67 extern __checkReturn efx_rc_t
71 __out efx_family_t *efp);
74 #define EFX_PCI_VENID_SFC 0x1924
76 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
78 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
79 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
80 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
82 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
83 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
84 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
86 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
87 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
89 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
90 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
91 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
100 EFX_ERR_BUFID_DC_OOB,
113 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
114 extern __checkReturn uint32_t
116 __in uint32_t crc_init,
117 __in_ecount(length) uint8_t const *input,
121 /* Type prototypes */
123 typedef struct efx_rxq_s efx_rxq_t;
127 typedef struct efx_nic_s efx_nic_t;
129 extern __checkReturn efx_rc_t
131 __in efx_family_t family,
132 __in efsys_identifier_t *esip,
133 __in efsys_bar_t *esbp,
134 __in efsys_lock_t *eslp,
135 __deref_out efx_nic_t **enpp);
137 extern __checkReturn efx_rc_t
139 __in efx_nic_t *enp);
141 extern __checkReturn efx_rc_t
143 __in efx_nic_t *enp);
145 extern __checkReturn efx_rc_t
147 __in efx_nic_t *enp);
151 __in efx_nic_t *enp);
155 __in efx_nic_t *enp);
159 __in efx_nic_t *enp);
161 #define EFX_PCIE_LINK_SPEED_GEN1 1
162 #define EFX_PCIE_LINK_SPEED_GEN2 2
163 #define EFX_PCIE_LINK_SPEED_GEN3 3
165 typedef enum efx_pcie_link_performance_e {
166 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
167 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
168 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
169 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
170 } efx_pcie_link_performance_t;
172 extern __checkReturn efx_rc_t
173 efx_nic_calculate_pcie_link_bandwidth(
174 __in uint32_t pcie_link_width,
175 __in uint32_t pcie_link_gen,
176 __out uint32_t *bandwidth_mbpsp);
178 extern __checkReturn efx_rc_t
179 efx_nic_check_pcie_link_speed(
181 __in uint32_t pcie_link_width,
182 __in uint32_t pcie_link_gen,
183 __out efx_pcie_link_performance_t *resultp);
187 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
188 /* Huntington and Medford require MCDIv2 commands */
189 #define WITH_MCDI_V2 1
192 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
194 typedef enum efx_mcdi_exception_e {
195 EFX_MCDI_EXCEPTION_MC_REBOOT,
196 EFX_MCDI_EXCEPTION_MC_BADASSERT,
197 } efx_mcdi_exception_t;
199 #if EFSYS_OPT_MCDI_LOGGING
200 typedef enum efx_log_msg_e {
202 EFX_LOG_MCDI_REQUEST,
203 EFX_LOG_MCDI_RESPONSE,
205 #endif /* EFSYS_OPT_MCDI_LOGGING */
207 typedef struct efx_mcdi_transport_s {
209 efsys_mem_t *emt_dma_mem;
210 void (*emt_execute)(void *, efx_mcdi_req_t *);
211 void (*emt_ev_cpl)(void *);
212 void (*emt_exception)(void *, efx_mcdi_exception_t);
213 #if EFSYS_OPT_MCDI_LOGGING
214 void (*emt_logger)(void *, efx_log_msg_t,
215 void *, size_t, void *, size_t);
216 #endif /* EFSYS_OPT_MCDI_LOGGING */
217 #if EFSYS_OPT_MCDI_PROXY_AUTH
218 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
219 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
220 } efx_mcdi_transport_t;
222 extern __checkReturn efx_rc_t
225 __in const efx_mcdi_transport_t *mtp);
227 extern __checkReturn efx_rc_t
229 __in efx_nic_t *enp);
233 __in efx_nic_t *enp);
236 efx_mcdi_get_timeout(
238 __in efx_mcdi_req_t *emrp,
239 __out uint32_t *usec_timeoutp);
242 efx_mcdi_request_start(
244 __in efx_mcdi_req_t *emrp,
245 __in boolean_t ev_cpl);
247 extern __checkReturn boolean_t
248 efx_mcdi_request_poll(
249 __in efx_nic_t *enp);
251 extern __checkReturn boolean_t
252 efx_mcdi_request_abort(
253 __in efx_nic_t *enp);
257 __in efx_nic_t *enp);
259 #endif /* EFSYS_OPT_MCDI */
263 #define EFX_NINTR_SIENA 1024
265 typedef enum efx_intr_type_e {
266 EFX_INTR_INVALID = 0,
272 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
274 extern __checkReturn efx_rc_t
277 __in efx_intr_type_t type,
278 __in efsys_mem_t *esmp);
282 __in efx_nic_t *enp);
286 __in efx_nic_t *enp);
289 efx_intr_disable_unlocked(
290 __in efx_nic_t *enp);
292 #define EFX_INTR_NEVQS 32
294 extern __checkReturn efx_rc_t
297 __in unsigned int level);
300 efx_intr_status_line(
302 __out boolean_t *fatalp,
303 __out uint32_t *maskp);
306 efx_intr_status_message(
308 __in unsigned int message,
309 __out boolean_t *fatalp);
313 __in efx_nic_t *enp);
317 __in efx_nic_t *enp);
321 typedef enum efx_link_mode_e {
322 EFX_LINK_UNKNOWN = 0,
335 #define EFX_MAC_ADDR_LEN 6
337 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
339 #define EFX_MAC_MULTICAST_LIST_MAX 256
341 #define EFX_MAC_SDU_MAX 9202
343 #define EFX_MAC_PDU_ADJUSTMENT \
347 + /* bug16011 */ 16) \
349 #define EFX_MAC_PDU(_sdu) \
350 P2ROUNDUP((_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
353 * Due to the P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
354 * the SDU rounded up slightly.
356 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
358 #define EFX_MAC_PDU_MIN 60
359 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
361 extern __checkReturn efx_rc_t
366 extern __checkReturn efx_rc_t
371 extern __checkReturn efx_rc_t
376 extern __checkReturn efx_rc_t
379 __in boolean_t all_unicst,
380 __in boolean_t mulcst,
381 __in boolean_t all_mulcst,
382 __in boolean_t brdcst);
384 extern __checkReturn efx_rc_t
385 efx_mac_multicast_list_set(
387 __in_ecount(6*count) uint8_t const *addrs,
390 extern __checkReturn efx_rc_t
391 efx_mac_filter_default_rxq_set(
394 __in boolean_t using_rss);
397 efx_mac_filter_default_rxq_clear(
398 __in efx_nic_t *enp);
400 extern __checkReturn efx_rc_t
403 __in boolean_t enabled);
405 extern __checkReturn efx_rc_t
408 __out boolean_t *mac_upp);
410 #define EFX_FCNTL_RESPOND 0x00000001
411 #define EFX_FCNTL_GENERATE 0x00000002
413 extern __checkReturn efx_rc_t
416 __in unsigned int fcntl,
417 __in boolean_t autoneg);
422 __out unsigned int *fcntl_wantedp,
423 __out unsigned int *fcntl_linkp);
428 typedef enum efx_mon_type_e {
440 __in efx_nic_t *enp);
442 #endif /* EFSYS_OPT_NAMES */
444 extern __checkReturn efx_rc_t
446 __in efx_nic_t *enp);
450 __in efx_nic_t *enp);
454 extern __checkReturn efx_rc_t
456 __in efx_nic_t *enp);
458 extern __checkReturn efx_rc_t
460 __in efx_nic_t *enp);
462 extern __checkReturn efx_rc_t
465 __out_opt efx_link_mode_t *link_modep);
469 __in efx_nic_t *enp);
471 typedef enum efx_phy_cap_type_e {
472 EFX_PHY_CAP_INVALID = 0,
479 EFX_PHY_CAP_10000FDX,
483 EFX_PHY_CAP_40000FDX,
485 } efx_phy_cap_type_t;
488 #define EFX_PHY_CAP_CURRENT 0x00000000
489 #define EFX_PHY_CAP_DEFAULT 0x00000001
490 #define EFX_PHY_CAP_PERM 0x00000002
496 __out uint32_t *maskp);
498 extern __checkReturn efx_rc_t
506 __out uint32_t *maskp);
508 extern __checkReturn efx_rc_t
511 __out uint32_t *ouip);
513 typedef enum efx_phy_media_type_e {
514 EFX_PHY_MEDIA_INVALID = 0,
519 EFX_PHY_MEDIA_SFP_PLUS,
520 EFX_PHY_MEDIA_BASE_T,
521 EFX_PHY_MEDIA_QSFP_PLUS,
523 } efx_phy_media_type_t;
525 /* Get the type of medium currently used. If the board has ports for
526 * modules, a module is present, and we recognise the media type of
527 * the module, then this will be the media type of the module.
528 * Otherwise it will be the media type of the port.
531 efx_phy_media_type_get(
533 __out efx_phy_media_type_t *typep);
536 efx_phy_module_get_info(
538 __in uint8_t dev_addr,
541 __out_bcount(len) uint8_t *data);
544 #define EFX_FEATURE_IPV6 0x00000001
545 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
546 #define EFX_FEATURE_LINK_EVENTS 0x00000004
547 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
548 #define EFX_FEATURE_MCDI 0x00000020
549 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
550 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
551 #define EFX_FEATURE_TURBO 0x00000100
552 #define EFX_FEATURE_MCDI_DMA 0x00000200
553 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
554 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
555 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
556 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
557 #define EFX_FEATURE_PACKED_STREAM 0x00004000
559 typedef struct efx_nic_cfg_s {
560 uint32_t enc_board_type;
561 uint32_t enc_phy_type;
563 char enc_phy_name[21];
565 char enc_phy_revision[21];
566 efx_mon_type_t enc_mon_type;
567 unsigned int enc_features;
568 uint8_t enc_mac_addr[6];
569 uint8_t enc_port; /* PHY port number */
570 uint32_t enc_intr_vec_base;
571 uint32_t enc_intr_limit;
572 uint32_t enc_evq_limit;
573 uint32_t enc_txq_limit;
574 uint32_t enc_rxq_limit;
575 uint32_t enc_txq_max_ndescs;
576 uint32_t enc_buftbl_limit;
577 uint32_t enc_piobuf_limit;
578 uint32_t enc_piobuf_size;
579 uint32_t enc_piobuf_min_alloc_size;
580 uint32_t enc_evq_timer_quantum_ns;
581 uint32_t enc_evq_timer_max_us;
582 uint32_t enc_clk_mult;
583 uint32_t enc_rx_prefix_size;
584 uint32_t enc_rx_buf_align_start;
585 uint32_t enc_rx_buf_align_end;
587 uint8_t enc_mcdi_mdio_channel;
588 #endif /* EFSYS_OPT_MCDI */
589 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
592 uint32_t enc_privilege_mask;
593 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
594 boolean_t enc_bug26807_workaround;
595 boolean_t enc_bug35388_workaround;
596 boolean_t enc_bug41750_workaround;
597 boolean_t enc_bug61265_workaround;
598 boolean_t enc_rx_batching_enabled;
599 /* Maximum number of descriptors completed in an rx event. */
600 uint32_t enc_rx_batch_max;
601 /* Number of rx descriptors the hardware requires for a push. */
602 uint32_t enc_rx_push_align;
604 * Maximum number of bytes into the packet the TCP header can start for
605 * the hardware to apply TSO packet edits.
607 uint32_t enc_tx_tso_tcp_header_offset_limit;
608 boolean_t enc_fw_assisted_tso_enabled;
609 boolean_t enc_fw_assisted_tso_v2_enabled;
610 /* Number of TSO contexts on the NIC (FATSOv2) */
611 uint32_t enc_fw_assisted_tso_v2_n_contexts;
612 boolean_t enc_hw_tx_insert_vlan_enabled;
613 /* Number of PFs on the NIC */
614 uint32_t enc_hw_pf_count;
615 /* Datapath firmware vadapter/vport/vswitch support */
616 boolean_t enc_datapath_cap_evb;
617 boolean_t enc_rx_disable_scatter_supported;
618 boolean_t enc_allow_set_mac_with_installed_filters;
619 boolean_t enc_enhanced_set_mac_supported;
620 boolean_t enc_init_evq_v2_supported;
621 boolean_t enc_rx_packed_stream_supported;
622 boolean_t enc_rx_var_packed_stream_supported;
623 boolean_t enc_pm_and_rxdp_counters;
624 boolean_t enc_mac_stats_40g_tx_size_bins;
625 /* External port identifier */
626 uint8_t enc_external_port;
627 uint32_t enc_mcdi_max_payload_length;
628 /* VPD may be per-PF or global */
629 boolean_t enc_vpd_is_global;
630 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
631 uint32_t enc_required_pcie_bandwidth_mbps;
632 uint32_t enc_max_pcie_link_gen;
633 /* Firmware verifies integrity of NVRAM updates */
634 uint32_t enc_fw_verified_nvram_update_required;
637 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
638 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
640 #define EFX_PCI_FUNCTION(_encp) \
641 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
643 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
645 extern const efx_nic_cfg_t *
647 __in efx_nic_t *enp);
649 /* Driver resource limits (minimum required/maximum usable). */
650 typedef struct efx_drv_limits_s {
651 uint32_t edl_min_evq_count;
652 uint32_t edl_max_evq_count;
654 uint32_t edl_min_rxq_count;
655 uint32_t edl_max_rxq_count;
657 uint32_t edl_min_txq_count;
658 uint32_t edl_max_txq_count;
660 /* PIO blocks (sub-allocated from piobuf) */
661 uint32_t edl_min_pio_alloc_size;
662 uint32_t edl_max_pio_alloc_count;
665 extern __checkReturn efx_rc_t
666 efx_nic_set_drv_limits(
667 __inout efx_nic_t *enp,
668 __in efx_drv_limits_t *edlp);
670 typedef enum efx_nic_region_e {
671 EFX_REGION_VI, /* Memory BAR UC mapping */
672 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
675 extern __checkReturn efx_rc_t
676 efx_nic_get_bar_region(
678 __in efx_nic_region_t region,
679 __out uint32_t *offsetp,
680 __out size_t *sizep);
682 extern __checkReturn efx_rc_t
685 __out uint32_t *evq_countp,
686 __out uint32_t *rxq_countp,
687 __out uint32_t *txq_countp);
692 extern __checkReturn efx_rc_t
693 efx_sram_buf_tbl_set(
696 __in efsys_mem_t *esmp,
700 efx_sram_buf_tbl_clear(
705 #define EFX_BUF_TBL_SIZE 0x20000
707 #define EFX_BUF_SIZE 4096
711 typedef struct efx_evq_s efx_evq_t;
713 extern __checkReturn efx_rc_t
715 __in efx_nic_t *enp);
719 __in efx_nic_t *enp);
721 #define EFX_EVQ_MAXNEVS 32768
722 #define EFX_EVQ_MINNEVS 512
724 #define EFX_EVQ_SIZE(_nevs) ((_nevs) * sizeof (efx_qword_t))
725 #define EFX_EVQ_NBUFS(_nevs) (EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
727 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
728 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
729 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
730 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
732 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
733 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
734 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
736 extern __checkReturn efx_rc_t
739 __in unsigned int index,
740 __in efsys_mem_t *esmp,
745 __deref_out efx_evq_t **eepp);
752 typedef __checkReturn boolean_t
753 (*efx_initialized_ev_t)(
756 #define EFX_PKT_UNICAST 0x0004
757 #define EFX_PKT_START 0x0008
759 #define EFX_PKT_VLAN_TAGGED 0x0010
760 #define EFX_CKSUM_TCPUDP 0x0020
761 #define EFX_CKSUM_IPV4 0x0040
762 #define EFX_PKT_CONT 0x0080
764 #define EFX_CHECK_VLAN 0x0100
765 #define EFX_PKT_TCP 0x0200
766 #define EFX_PKT_UDP 0x0400
767 #define EFX_PKT_IPV4 0x0800
769 #define EFX_PKT_IPV6 0x1000
770 #define EFX_PKT_PREFIX_LEN 0x2000
771 #define EFX_ADDR_MISMATCH 0x4000
772 #define EFX_DISCARD 0x8000
775 * The following flags are used only for packed stream
776 * mode. The values for the flags are reused to fit into 16 bit,
777 * since EFX_PKT_START and EFX_PKT_CONT are never used in
780 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
781 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
784 #define EFX_EV_RX_NLABELS 32
785 #define EFX_EV_TX_NLABELS 32
787 typedef __checkReturn boolean_t
793 __in uint16_t flags);
795 typedef __checkReturn boolean_t
801 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
802 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
803 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
804 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
805 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
806 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
807 #define EFX_EXCEPTION_RX_ERROR 0x00000007
808 #define EFX_EXCEPTION_TX_ERROR 0x00000008
809 #define EFX_EXCEPTION_EV_ERROR 0x00000009
811 typedef __checkReturn boolean_t
812 (*efx_exception_ev_t)(
817 typedef __checkReturn boolean_t
818 (*efx_rxq_flush_done_ev_t)(
820 __in uint32_t rxq_index);
822 typedef __checkReturn boolean_t
823 (*efx_rxq_flush_failed_ev_t)(
825 __in uint32_t rxq_index);
827 typedef __checkReturn boolean_t
828 (*efx_txq_flush_done_ev_t)(
830 __in uint32_t txq_index);
832 typedef __checkReturn boolean_t
833 (*efx_software_ev_t)(
835 __in uint16_t magic);
837 typedef __checkReturn boolean_t
842 #define EFX_SRAM_CLEAR 0
843 #define EFX_SRAM_UPDATE 1
844 #define EFX_SRAM_ILLEGAL_CLEAR 2
846 typedef __checkReturn boolean_t
849 __in uint32_t label);
851 typedef __checkReturn boolean_t
854 __in uint32_t label);
856 typedef __checkReturn boolean_t
857 (*efx_link_change_ev_t)(
859 __in efx_link_mode_t link_mode);
861 typedef struct efx_ev_callbacks_s {
862 efx_initialized_ev_t eec_initialized;
865 efx_exception_ev_t eec_exception;
866 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
867 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
868 efx_txq_flush_done_ev_t eec_txq_flush_done;
869 efx_software_ev_t eec_software;
870 efx_sram_ev_t eec_sram;
871 efx_wake_up_ev_t eec_wake_up;
872 efx_timer_ev_t eec_timer;
873 efx_link_change_ev_t eec_link_change;
874 } efx_ev_callbacks_t;
876 extern __checkReturn boolean_t
879 __in unsigned int count);
884 __inout unsigned int *countp,
885 __in const efx_ev_callbacks_t *eecp,
888 extern __checkReturn efx_rc_t
889 efx_ev_usecs_to_ticks(
891 __in unsigned int usecs,
892 __out unsigned int *ticksp);
894 extern __checkReturn efx_rc_t
897 __in unsigned int us);
899 extern __checkReturn efx_rc_t
902 __in unsigned int count);
906 __in efx_evq_t *eep);
910 extern __checkReturn efx_rc_t
912 __inout efx_nic_t *enp);
916 __in efx_nic_t *enp);
918 extern __checkReturn efx_rc_t
919 efx_pseudo_hdr_pkt_length_get(
921 __in uint8_t *buffer,
922 __out uint16_t *pkt_lengthp);
924 #define EFX_RXQ_MAXNDESCS 4096
925 #define EFX_RXQ_MINNDESCS 512
927 #define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
928 #define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
929 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
930 #define EFX_RXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
932 typedef enum efx_rxq_type_e {
933 EFX_RXQ_TYPE_DEFAULT,
934 EFX_RXQ_TYPE_SCATTER,
935 EFX_RXQ_TYPE_PACKED_STREAM_1M,
936 EFX_RXQ_TYPE_PACKED_STREAM_512K,
937 EFX_RXQ_TYPE_PACKED_STREAM_256K,
938 EFX_RXQ_TYPE_PACKED_STREAM_128K,
939 EFX_RXQ_TYPE_PACKED_STREAM_64K,
943 extern __checkReturn efx_rc_t
946 __in unsigned int index,
947 __in unsigned int label,
948 __in efx_rxq_type_t type,
949 __in efsys_mem_t *esmp,
953 __deref_out efx_rxq_t **erpp);
955 typedef struct efx_buffer_s {
956 efsys_dma_addr_t eb_addr;
961 typedef struct efx_desc_s {
968 __in_ecount(n) efsys_dma_addr_t *addrp,
971 __in unsigned int completed,
972 __in unsigned int added);
977 __in unsigned int added,
978 __inout unsigned int *pushedp);
980 extern __checkReturn efx_rc_t
982 __in efx_rxq_t *erp);
986 __in efx_rxq_t *erp);
990 __in efx_rxq_t *erp);
994 typedef struct efx_txq_s efx_txq_t;
996 extern __checkReturn efx_rc_t
998 __in efx_nic_t *enp);
1002 __in efx_nic_t *enp);
1004 #define EFX_TXQ_MINNDESCS 512
1006 #define EFX_TXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
1007 #define EFX_TXQ_NBUFS(_ndescs) (EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1008 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
1009 #define EFX_TXQ_DC_NDESCS(_dcsize) (8 << _dcsize)
1011 #define EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
1013 #define EFX_TXQ_CKSUM_IPV4 0x0001
1014 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
1015 #define EFX_TXQ_FATSOV2 0x0004
1017 extern __checkReturn efx_rc_t
1019 __in efx_nic_t *enp,
1020 __in unsigned int index,
1021 __in unsigned int label,
1022 __in efsys_mem_t *esmp,
1025 __in uint16_t flags,
1026 __in efx_evq_t *eep,
1027 __deref_out efx_txq_t **etpp,
1028 __out unsigned int *addedp);
1030 extern __checkReturn efx_rc_t
1032 __in efx_txq_t *etp,
1033 __in_ecount(n) efx_buffer_t *eb,
1034 __in unsigned int n,
1035 __in unsigned int completed,
1036 __inout unsigned int *addedp);
1038 extern __checkReturn efx_rc_t
1040 __in efx_txq_t *etp,
1041 __in unsigned int ns);
1045 __in efx_txq_t *etp,
1046 __in unsigned int added,
1047 __in unsigned int pushed);
1049 extern __checkReturn efx_rc_t
1051 __in efx_txq_t *etp);
1055 __in efx_txq_t *etp);
1057 extern __checkReturn efx_rc_t
1059 __in efx_txq_t *etp);
1062 efx_tx_qpio_disable(
1063 __in efx_txq_t *etp);
1065 extern __checkReturn efx_rc_t
1067 __in efx_txq_t *etp,
1068 __in_ecount(buf_length) uint8_t *buffer,
1069 __in size_t buf_length,
1070 __in size_t pio_buf_offset);
1072 extern __checkReturn efx_rc_t
1074 __in efx_txq_t *etp,
1075 __in size_t pkt_length,
1076 __in unsigned int completed,
1077 __inout unsigned int *addedp);
1079 extern __checkReturn efx_rc_t
1081 __in efx_txq_t *etp,
1082 __in_ecount(n) efx_desc_t *ed,
1083 __in unsigned int n,
1084 __in unsigned int completed,
1085 __inout unsigned int *addedp);
1088 efx_tx_qdesc_dma_create(
1089 __in efx_txq_t *etp,
1090 __in efsys_dma_addr_t addr,
1093 __out efx_desc_t *edp);
1096 efx_tx_qdesc_tso_create(
1097 __in efx_txq_t *etp,
1098 __in uint16_t ipv4_id,
1099 __in uint32_t tcp_seq,
1100 __in uint8_t tcp_flags,
1101 __out efx_desc_t *edp);
1103 /* Number of FATSOv2 option descriptors */
1104 #define EFX_TX_FATSOV2_OPT_NDESCS 2
1106 /* Maximum number of DMA segments per TSO packet (not superframe) */
1107 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
1110 efx_tx_qdesc_tso2_create(
1111 __in efx_txq_t *etp,
1112 __in uint16_t ipv4_id,
1113 __in uint32_t tcp_seq,
1114 __in uint16_t tcp_mss,
1115 __out_ecount(count) efx_desc_t *edp,
1119 efx_tx_qdesc_vlantci_create(
1120 __in efx_txq_t *etp,
1122 __out efx_desc_t *edp);
1126 __in efx_txq_t *etp);
1131 #if EFSYS_OPT_FILTER
1133 #define EFX_ETHER_TYPE_IPV4 0x0800
1134 #define EFX_ETHER_TYPE_IPV6 0x86DD
1136 #define EFX_IPPROTO_TCP 6
1137 #define EFX_IPPROTO_UDP 17
1139 /* Use RSS to spread across multiple queues */
1140 #define EFX_FILTER_FLAG_RX_RSS 0x01
1141 /* Enable RX scatter */
1142 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
1144 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
1145 * May only be set by the filter implementation for each type.
1146 * A removal request will restore the automatic filter in its place.
1148 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
1149 /* Filter is for RX */
1150 #define EFX_FILTER_FLAG_RX 0x08
1151 /* Filter is for TX */
1152 #define EFX_FILTER_FLAG_TX 0x10
1154 typedef unsigned int efx_filter_flags_t;
1156 typedef enum efx_filter_match_flags_e {
1157 EFX_FILTER_MATCH_REM_HOST = 0x0001, /* Match by remote IP host
1159 EFX_FILTER_MATCH_LOC_HOST = 0x0002, /* Match by local IP host
1161 EFX_FILTER_MATCH_REM_MAC = 0x0004, /* Match by remote MAC address */
1162 EFX_FILTER_MATCH_REM_PORT = 0x0008, /* Match by remote TCP/UDP port */
1163 EFX_FILTER_MATCH_LOC_MAC = 0x0010, /* Match by remote TCP/UDP port */
1164 EFX_FILTER_MATCH_LOC_PORT = 0x0020, /* Match by local TCP/UDP port */
1165 EFX_FILTER_MATCH_ETHER_TYPE = 0x0040, /* Match by Ether-type */
1166 EFX_FILTER_MATCH_INNER_VID = 0x0080, /* Match by inner VLAN ID */
1167 EFX_FILTER_MATCH_OUTER_VID = 0x0100, /* Match by outer VLAN ID */
1168 EFX_FILTER_MATCH_IP_PROTO = 0x0200, /* Match by IP transport
1170 EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400, /* Match by local MAC address
1171 * I/G bit. Used for RX default
1172 * unicast and multicast/
1173 * broadcast filters. */
1174 } efx_filter_match_flags_t;
1176 typedef enum efx_filter_priority_s {
1177 EFX_FILTER_PRI_HINT = 0, /* Performance hint */
1178 EFX_FILTER_PRI_AUTO, /* Automatic filter based on device
1179 * address list or hardware
1180 * requirements. This may only be used
1181 * by the filter implementation for
1183 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
1184 EFX_FILTER_PRI_REQUIRED, /* Required for correct behaviour of the
1185 * client (e.g. SR-IOV, HyperV VMQ etc.)
1187 } efx_filter_priority_t;
1190 * FIXME: All these fields are assumed to be in little-endian byte order.
1191 * It may be better for some to be big-endian. See bug42804.
1194 typedef struct efx_filter_spec_s {
1195 uint32_t efs_match_flags:12;
1196 uint32_t efs_priority:2;
1197 uint32_t efs_flags:6;
1198 uint32_t efs_dmaq_id:12;
1199 uint32_t efs_rss_context;
1200 uint16_t efs_outer_vid;
1201 uint16_t efs_inner_vid;
1202 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
1203 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
1204 uint16_t efs_ether_type;
1205 uint8_t efs_ip_proto;
1206 uint16_t efs_loc_port;
1207 uint16_t efs_rem_port;
1208 efx_oword_t efs_rem_host;
1209 efx_oword_t efs_loc_host;
1210 } efx_filter_spec_t;
1213 /* Default values for use in filter specifications */
1214 #define EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT 0xffffffff
1215 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
1216 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
1218 extern __checkReturn efx_rc_t
1220 __in efx_nic_t *enp);
1224 __in efx_nic_t *enp);
1226 extern __checkReturn efx_rc_t
1228 __in efx_nic_t *enp,
1229 __inout efx_filter_spec_t *spec);
1231 extern __checkReturn efx_rc_t
1233 __in efx_nic_t *enp,
1234 __inout efx_filter_spec_t *spec);
1236 extern __checkReturn efx_rc_t
1238 __in efx_nic_t *enp);
1240 extern __checkReturn efx_rc_t
1241 efx_filter_supported_filters(
1242 __in efx_nic_t *enp,
1243 __out uint32_t *list,
1244 __out size_t *length);
1247 efx_filter_spec_init_rx(
1248 __out efx_filter_spec_t *spec,
1249 __in efx_filter_priority_t priority,
1250 __in efx_filter_flags_t flags,
1251 __in efx_rxq_t *erp);
1254 efx_filter_spec_init_tx(
1255 __out efx_filter_spec_t *spec,
1256 __in efx_txq_t *etp);
1258 extern __checkReturn efx_rc_t
1259 efx_filter_spec_set_ipv4_local(
1260 __inout efx_filter_spec_t *spec,
1263 __in uint16_t port);
1265 extern __checkReturn efx_rc_t
1266 efx_filter_spec_set_ipv4_full(
1267 __inout efx_filter_spec_t *spec,
1269 __in uint32_t lhost,
1270 __in uint16_t lport,
1271 __in uint32_t rhost,
1272 __in uint16_t rport);
1274 extern __checkReturn efx_rc_t
1275 efx_filter_spec_set_eth_local(
1276 __inout efx_filter_spec_t *spec,
1278 __in const uint8_t *addr);
1280 extern __checkReturn efx_rc_t
1281 efx_filter_spec_set_uc_def(
1282 __inout efx_filter_spec_t *spec);
1284 extern __checkReturn efx_rc_t
1285 efx_filter_spec_set_mc_def(
1286 __inout efx_filter_spec_t *spec);
1288 #endif /* EFSYS_OPT_FILTER */
1292 extern __checkReturn uint32_t
1294 __in_ecount(count) uint32_t const *input,
1296 __in uint32_t init);
1298 extern __checkReturn uint32_t
1300 __in_ecount(length) uint8_t const *input,
1302 __in uint32_t init);
1310 #endif /* _SYS_EFX_H */