f1788cad25718dd5dd355161ec52ee311afd029d
[dpdk.git] / drivers / net / sfc / base / efx_ev.c
1 /* SPDX-License-Identifier: BSD-3-Clause
2  *
3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
4  * All rights reserved.
5  */
6
7 #include "efx.h"
8 #include "efx_impl.h"
9 #if EFSYS_OPT_MON_MCDI
10 #include "mcdi_mon.h"
11 #endif
12
13 #if EFSYS_OPT_QSTATS
14 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
15         do {                                                            \
16                 (_eep)->ee_stat[_stat]++;                               \
17         _NOTE(CONSTANTCONDITION)                                        \
18         } while (B_FALSE)
19 #else
20 #define EFX_EV_QSTAT_INCR(_eep, _stat)
21 #endif
22
23 #define EFX_EV_PRESENT(_qword)                                          \
24         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
25         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
26
27
28
29 #if EFSYS_OPT_SIENA
30
31 static  __checkReturn   efx_rc_t
32 siena_ev_init(
33         __in            efx_nic_t *enp);
34
35 static                  void
36 siena_ev_fini(
37         __in            efx_nic_t *enp);
38
39 static  __checkReturn   efx_rc_t
40 siena_ev_qcreate(
41         __in            efx_nic_t *enp,
42         __in            unsigned int index,
43         __in            efsys_mem_t *esmp,
44         __in            size_t ndescs,
45         __in            uint32_t id,
46         __in            uint32_t us,
47         __in            uint32_t flags,
48         __in            efx_evq_t *eep);
49
50 static                  void
51 siena_ev_qdestroy(
52         __in            efx_evq_t *eep);
53
54 static  __checkReturn   efx_rc_t
55 siena_ev_qprime(
56         __in            efx_evq_t *eep,
57         __in            unsigned int count);
58
59 static                  void
60 siena_ev_qpost(
61         __in    efx_evq_t *eep,
62         __in    uint16_t data);
63
64 static  __checkReturn   efx_rc_t
65 siena_ev_qmoderate(
66         __in            efx_evq_t *eep,
67         __in            unsigned int us);
68
69 #if EFSYS_OPT_QSTATS
70 static                  void
71 siena_ev_qstats_update(
72         __in                            efx_evq_t *eep,
73         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
74
75 #endif
76
77 #endif /* EFSYS_OPT_SIENA */
78
79 #if EFSYS_OPT_SIENA
80 static const efx_ev_ops_t       __efx_ev_siena_ops = {
81         siena_ev_init,                          /* eevo_init */
82         siena_ev_fini,                          /* eevo_fini */
83         siena_ev_qcreate,                       /* eevo_qcreate */
84         siena_ev_qdestroy,                      /* eevo_qdestroy */
85         siena_ev_qprime,                        /* eevo_qprime */
86         siena_ev_qpost,                         /* eevo_qpost */
87         siena_ev_qmoderate,                     /* eevo_qmoderate */
88 #if EFSYS_OPT_QSTATS
89         siena_ev_qstats_update,                 /* eevo_qstats_update */
90 #endif
91 };
92 #endif /* EFSYS_OPT_SIENA */
93
94 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
95 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
96         ef10_ev_init,                           /* eevo_init */
97         ef10_ev_fini,                           /* eevo_fini */
98         ef10_ev_qcreate,                        /* eevo_qcreate */
99         ef10_ev_qdestroy,                       /* eevo_qdestroy */
100         ef10_ev_qprime,                         /* eevo_qprime */
101         ef10_ev_qpost,                          /* eevo_qpost */
102         ef10_ev_qmoderate,                      /* eevo_qmoderate */
103 #if EFSYS_OPT_QSTATS
104         ef10_ev_qstats_update,                  /* eevo_qstats_update */
105 #endif
106 };
107 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
108
109
110         __checkReturn   efx_rc_t
111 efx_ev_init(
112         __in            efx_nic_t *enp)
113 {
114         const efx_ev_ops_t *eevop;
115         efx_rc_t rc;
116
117         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
118         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
119
120         if (enp->en_mod_flags & EFX_MOD_EV) {
121                 rc = EINVAL;
122                 goto fail1;
123         }
124
125         switch (enp->en_family) {
126 #if EFSYS_OPT_SIENA
127         case EFX_FAMILY_SIENA:
128                 eevop = &__efx_ev_siena_ops;
129                 break;
130 #endif /* EFSYS_OPT_SIENA */
131
132 #if EFSYS_OPT_HUNTINGTON
133         case EFX_FAMILY_HUNTINGTON:
134                 eevop = &__efx_ev_ef10_ops;
135                 break;
136 #endif /* EFSYS_OPT_HUNTINGTON */
137
138 #if EFSYS_OPT_MEDFORD
139         case EFX_FAMILY_MEDFORD:
140                 eevop = &__efx_ev_ef10_ops;
141                 break;
142 #endif /* EFSYS_OPT_MEDFORD */
143
144 #if EFSYS_OPT_MEDFORD2
145         case EFX_FAMILY_MEDFORD2:
146                 eevop = &__efx_ev_ef10_ops;
147                 break;
148 #endif /* EFSYS_OPT_MEDFORD2 */
149
150         default:
151                 EFSYS_ASSERT(0);
152                 rc = ENOTSUP;
153                 goto fail1;
154         }
155
156         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
157
158         if ((rc = eevop->eevo_init(enp)) != 0)
159                 goto fail2;
160
161         enp->en_eevop = eevop;
162         enp->en_mod_flags |= EFX_MOD_EV;
163         return (0);
164
165 fail2:
166         EFSYS_PROBE(fail2);
167
168 fail1:
169         EFSYS_PROBE1(fail1, efx_rc_t, rc);
170
171         enp->en_eevop = NULL;
172         enp->en_mod_flags &= ~EFX_MOD_EV;
173         return (rc);
174 }
175
176                 void
177 efx_ev_fini(
178         __in    efx_nic_t *enp)
179 {
180         const efx_ev_ops_t *eevop = enp->en_eevop;
181
182         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
183         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
184         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
185         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
186         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
187         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
188
189         eevop->eevo_fini(enp);
190
191         enp->en_eevop = NULL;
192         enp->en_mod_flags &= ~EFX_MOD_EV;
193 }
194
195
196         __checkReturn   efx_rc_t
197 efx_ev_qcreate(
198         __in            efx_nic_t *enp,
199         __in            unsigned int index,
200         __in            efsys_mem_t *esmp,
201         __in            size_t ndescs,
202         __in            uint32_t id,
203         __in            uint32_t us,
204         __in            uint32_t flags,
205         __deref_out     efx_evq_t **eepp)
206 {
207         const efx_ev_ops_t *eevop = enp->en_eevop;
208         efx_evq_t *eep;
209         efx_rc_t rc;
210
211         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
212         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
213
214         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
215             enp->en_nic_cfg.enc_evq_limit);
216
217         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
218         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
219                 break;
220         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
221                 if (us != 0) {
222                         rc = EINVAL;
223                         goto fail1;
224                 }
225                 break;
226         default:
227                 rc = EINVAL;
228                 goto fail2;
229         }
230
231         /* Allocate an EVQ object */
232         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
233         if (eep == NULL) {
234                 rc = ENOMEM;
235                 goto fail3;
236         }
237
238         eep->ee_magic = EFX_EVQ_MAGIC;
239         eep->ee_enp = enp;
240         eep->ee_index = index;
241         eep->ee_mask = ndescs - 1;
242         eep->ee_flags = flags;
243         eep->ee_esmp = esmp;
244
245         /*
246          * Set outputs before the queue is created because interrupts may be
247          * raised for events immediately after the queue is created, before the
248          * function call below returns. See bug58606.
249          *
250          * The eepp pointer passed in by the client must therefore point to data
251          * shared with the client's event processing context.
252          */
253         enp->en_ev_qcount++;
254         *eepp = eep;
255
256         if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
257             eep)) != 0)
258                 goto fail4;
259
260         return (0);
261
262 fail4:
263         EFSYS_PROBE(fail4);
264
265         *eepp = NULL;
266         enp->en_ev_qcount--;
267         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
268 fail3:
269         EFSYS_PROBE(fail3);
270 fail2:
271         EFSYS_PROBE(fail2);
272 fail1:
273         EFSYS_PROBE1(fail1, efx_rc_t, rc);
274         return (rc);
275 }
276
277                 void
278 efx_ev_qdestroy(
279         __in    efx_evq_t *eep)
280 {
281         efx_nic_t *enp = eep->ee_enp;
282         const efx_ev_ops_t *eevop = enp->en_eevop;
283
284         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
285
286         EFSYS_ASSERT(enp->en_ev_qcount != 0);
287         --enp->en_ev_qcount;
288
289         eevop->eevo_qdestroy(eep);
290
291         /* Free the EVQ object */
292         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
293 }
294
295         __checkReturn   efx_rc_t
296 efx_ev_qprime(
297         __in            efx_evq_t *eep,
298         __in            unsigned int count)
299 {
300         efx_nic_t *enp = eep->ee_enp;
301         const efx_ev_ops_t *eevop = enp->en_eevop;
302         efx_rc_t rc;
303
304         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
305
306         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
307                 rc = EINVAL;
308                 goto fail1;
309         }
310
311         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
312                 goto fail2;
313
314         return (0);
315
316 fail2:
317         EFSYS_PROBE(fail2);
318 fail1:
319         EFSYS_PROBE1(fail1, efx_rc_t, rc);
320         return (rc);
321 }
322
323         __checkReturn   boolean_t
324 efx_ev_qpending(
325         __in            efx_evq_t *eep,
326         __in            unsigned int count)
327 {
328         size_t offset;
329         efx_qword_t qword;
330
331         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
332
333         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
334         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
335
336         return (EFX_EV_PRESENT(qword));
337 }
338
339 #if EFSYS_OPT_EV_PREFETCH
340
341                         void
342 efx_ev_qprefetch(
343         __in            efx_evq_t *eep,
344         __in            unsigned int count)
345 {
346         unsigned int offset;
347
348         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
349
350         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
351         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
352 }
353
354 #endif  /* EFSYS_OPT_EV_PREFETCH */
355
356 #define EFX_EV_BATCH    8
357
358                         void
359 efx_ev_qpoll(
360         __in            efx_evq_t *eep,
361         __inout         unsigned int *countp,
362         __in            const efx_ev_callbacks_t *eecp,
363         __in_opt        void *arg)
364 {
365         efx_qword_t ev[EFX_EV_BATCH];
366         unsigned int batch;
367         unsigned int total;
368         unsigned int count;
369         unsigned int index;
370         size_t offset;
371
372         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
373         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
374         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
375
376         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
377         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
378         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
379         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
380             FSE_AZ_EV_CODE_DRV_GEN_EV);
381 #if EFSYS_OPT_MCDI
382         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
383             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
384 #endif
385
386         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
387         EFSYS_ASSERT(countp != NULL);
388         EFSYS_ASSERT(eecp != NULL);
389
390         count = *countp;
391         do {
392                 /* Read up until the end of the batch period */
393                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
394                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
395                 for (total = 0; total < batch; ++total) {
396                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
397
398                         if (!EFX_EV_PRESENT(ev[total]))
399                                 break;
400
401                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
402                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
403                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
404
405                         offset += sizeof (efx_qword_t);
406                 }
407
408 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
409                 /*
410                  * Prefetch the next batch when we get within PREFETCH_PERIOD
411                  * of a completed batch. If the batch is smaller, then prefetch
412                  * immediately.
413                  */
414                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
415                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
416 #endif  /* EFSYS_OPT_EV_PREFETCH */
417
418                 /* Process the batch of events */
419                 for (index = 0; index < total; ++index) {
420                         boolean_t should_abort;
421                         uint32_t code;
422
423 #if EFSYS_OPT_EV_PREFETCH
424                         /* Prefetch if we've now reached the batch period */
425                         if (total == batch &&
426                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
427                                 offset = (count + batch) & eep->ee_mask;
428                                 offset *= sizeof (efx_qword_t);
429
430                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
431                         }
432 #endif  /* EFSYS_OPT_EV_PREFETCH */
433
434                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
435
436                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
437                         switch (code) {
438                         case FSE_AZ_EV_CODE_RX_EV:
439                                 should_abort = eep->ee_rx(eep,
440                                     &(ev[index]), eecp, arg);
441                                 break;
442                         case FSE_AZ_EV_CODE_TX_EV:
443                                 should_abort = eep->ee_tx(eep,
444                                     &(ev[index]), eecp, arg);
445                                 break;
446                         case FSE_AZ_EV_CODE_DRIVER_EV:
447                                 should_abort = eep->ee_driver(eep,
448                                     &(ev[index]), eecp, arg);
449                                 break;
450                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
451                                 should_abort = eep->ee_drv_gen(eep,
452                                     &(ev[index]), eecp, arg);
453                                 break;
454 #if EFSYS_OPT_MCDI
455                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
456                                 should_abort = eep->ee_mcdi(eep,
457                                     &(ev[index]), eecp, arg);
458                                 break;
459 #endif
460                         case FSE_AZ_EV_CODE_GLOBAL_EV:
461                                 if (eep->ee_global) {
462                                         should_abort = eep->ee_global(eep,
463                                             &(ev[index]), eecp, arg);
464                                         break;
465                                 }
466                                 /* else fallthrough */
467                         default:
468                                 EFSYS_PROBE3(bad_event,
469                                     unsigned int, eep->ee_index,
470                                     uint32_t,
471                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
472                                     uint32_t,
473                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
474
475                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
476                                 (void) eecp->eec_exception(arg,
477                                         EFX_EXCEPTION_EV_ERROR, code);
478                                 should_abort = B_TRUE;
479                         }
480                         if (should_abort) {
481                                 /* Ignore subsequent events */
482                                 total = index + 1;
483
484                                 /*
485                                  * Poison batch to ensure the outer
486                                  * loop is broken out of.
487                                  */
488                                 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
489                                 batch += (EFX_EV_BATCH << 1);
490                                 EFSYS_ASSERT(total != batch);
491                                 break;
492                         }
493                 }
494
495                 /*
496                  * Now that the hardware has most likely moved onto dma'ing
497                  * into the next cache line, clear the processed events. Take
498                  * care to only clear out events that we've processed
499                  */
500                 EFX_SET_QWORD(ev[0]);
501                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
502                 for (index = 0; index < total; ++index) {
503                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
504                         offset += sizeof (efx_qword_t);
505                 }
506
507                 count += total;
508
509         } while (total == batch);
510
511         *countp = count;
512 }
513
514                         void
515 efx_ev_qpost(
516         __in    efx_evq_t *eep,
517         __in    uint16_t data)
518 {
519         efx_nic_t *enp = eep->ee_enp;
520         const efx_ev_ops_t *eevop = enp->en_eevop;
521
522         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
523
524         EFSYS_ASSERT(eevop != NULL &&
525             eevop->eevo_qpost != NULL);
526
527         eevop->eevo_qpost(eep, data);
528 }
529
530         __checkReturn   efx_rc_t
531 efx_ev_usecs_to_ticks(
532         __in            efx_nic_t *enp,
533         __in            unsigned int us,
534         __out           unsigned int *ticksp)
535 {
536         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
537         unsigned int ticks;
538
539         /* Convert microseconds to a timer tick count */
540         if (us == 0)
541                 ticks = 0;
542         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
543                 ticks = 1;      /* Never round down to zero */
544         else
545                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
546
547         *ticksp = ticks;
548         return (0);
549 }
550
551         __checkReturn   efx_rc_t
552 efx_ev_qmoderate(
553         __in            efx_evq_t *eep,
554         __in            unsigned int us)
555 {
556         efx_nic_t *enp = eep->ee_enp;
557         const efx_ev_ops_t *eevop = enp->en_eevop;
558         efx_rc_t rc;
559
560         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
561
562         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
563             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
564                 rc = EINVAL;
565                 goto fail1;
566         }
567
568         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
569                 goto fail2;
570
571         return (0);
572
573 fail2:
574         EFSYS_PROBE(fail2);
575 fail1:
576         EFSYS_PROBE1(fail1, efx_rc_t, rc);
577         return (rc);
578 }
579
580 #if EFSYS_OPT_QSTATS
581                                         void
582 efx_ev_qstats_update(
583         __in                            efx_evq_t *eep,
584         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
585
586 {       efx_nic_t *enp = eep->ee_enp;
587         const efx_ev_ops_t *eevop = enp->en_eevop;
588
589         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
590
591         eevop->eevo_qstats_update(eep, stat);
592 }
593
594 #endif  /* EFSYS_OPT_QSTATS */
595
596 #if EFSYS_OPT_SIENA
597
598 static  __checkReturn   efx_rc_t
599 siena_ev_init(
600         __in            efx_nic_t *enp)
601 {
602         efx_oword_t oword;
603
604         /*
605          * Program the event queue for receive and transmit queue
606          * flush events.
607          */
608         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
609         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
610         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
611
612         return (0);
613
614 }
615
616 static  __checkReturn   boolean_t
617 siena_ev_rx_not_ok(
618         __in            efx_evq_t *eep,
619         __in            efx_qword_t *eqp,
620         __in            uint32_t label,
621         __in            uint32_t id,
622         __inout         uint16_t *flagsp)
623 {
624         boolean_t ignore = B_FALSE;
625
626         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
627                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
628                 EFSYS_PROBE(tobe_disc);
629                 /*
630                  * Assume this is a unicast address mismatch, unless below
631                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
632                  * EV_RX_PAUSE_FRM_ERR is set.
633                  */
634                 (*flagsp) |= EFX_ADDR_MISMATCH;
635         }
636
637         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
638                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
639                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
640                 (*flagsp) |= EFX_DISCARD;
641
642 #if EFSYS_OPT_RX_SCATTER
643                 /*
644                  * Lookout for payload queue ran dry errors and ignore them.
645                  *
646                  * Sadly for the header/data split cases, the descriptor
647                  * pointer in this event refers to the header queue and
648                  * therefore cannot be easily detected as duplicate.
649                  * So we drop these and rely on the receive processing seeing
650                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
651                  * the partially received packet.
652                  */
653                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
654                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
655                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
656                         ignore = B_TRUE;
657 #endif  /* EFSYS_OPT_RX_SCATTER */
658         }
659
660         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
661                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
662                 EFSYS_PROBE(crc_err);
663                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
664                 (*flagsp) |= EFX_DISCARD;
665         }
666
667         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
668                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
669                 EFSYS_PROBE(pause_frm_err);
670                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
671                 (*flagsp) |= EFX_DISCARD;
672         }
673
674         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
675                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
676                 EFSYS_PROBE(owner_id_err);
677                 (*flagsp) |= EFX_DISCARD;
678         }
679
680         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
681                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
682                 EFSYS_PROBE(ipv4_err);
683                 (*flagsp) &= ~EFX_CKSUM_IPV4;
684         }
685
686         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
687                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
688                 EFSYS_PROBE(udp_chk_err);
689                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
690         }
691
692         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
693                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
694
695                 /*
696                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
697                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
698                  * condition.
699                  */
700                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
701         }
702
703         return (ignore);
704 }
705
706 static  __checkReturn   boolean_t
707 siena_ev_rx(
708         __in            efx_evq_t *eep,
709         __in            efx_qword_t *eqp,
710         __in            const efx_ev_callbacks_t *eecp,
711         __in_opt        void *arg)
712 {
713         uint32_t id;
714         uint32_t size;
715         uint32_t label;
716         boolean_t ok;
717 #if EFSYS_OPT_RX_SCATTER
718         boolean_t sop;
719         boolean_t jumbo_cont;
720 #endif  /* EFSYS_OPT_RX_SCATTER */
721         uint32_t hdr_type;
722         boolean_t is_v6;
723         uint16_t flags;
724         boolean_t ignore;
725         boolean_t should_abort;
726
727         EFX_EV_QSTAT_INCR(eep, EV_RX);
728
729         /* Basic packet information */
730         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
731         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
732         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
733         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
734
735 #if EFSYS_OPT_RX_SCATTER
736         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
737         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
738 #endif  /* EFSYS_OPT_RX_SCATTER */
739
740         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
741
742         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
743
744         /*
745          * If packet is marked as OK and packet type is TCP/IP or
746          * UDP/IP or other IP, then we can rely on the hardware checksums.
747          */
748         switch (hdr_type) {
749         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
750                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
751                 if (is_v6) {
752                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
753                         flags |= EFX_PKT_IPV6;
754                 } else {
755                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
756                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
757                 }
758                 break;
759
760         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
761                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
762                 if (is_v6) {
763                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
764                         flags |= EFX_PKT_IPV6;
765                 } else {
766                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
767                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
768                 }
769                 break;
770
771         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
772                 if (is_v6) {
773                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
774                         flags = EFX_PKT_IPV6;
775                 } else {
776                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
777                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
778                 }
779                 break;
780
781         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
782                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
783                 flags = 0;
784                 break;
785
786         default:
787                 EFSYS_ASSERT(B_FALSE);
788                 flags = 0;
789                 break;
790         }
791
792 #if EFSYS_OPT_RX_SCATTER
793         /* Report scatter and header/lookahead split buffer flags */
794         if (sop)
795                 flags |= EFX_PKT_START;
796         if (jumbo_cont)
797                 flags |= EFX_PKT_CONT;
798 #endif  /* EFSYS_OPT_RX_SCATTER */
799
800         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
801         if (!ok) {
802                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
803                 if (ignore) {
804                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
805                             uint32_t, size, uint16_t, flags);
806
807                         return (B_FALSE);
808                 }
809         }
810
811         /* If we're not discarding the packet then it is ok */
812         if (~flags & EFX_DISCARD)
813                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
814
815         /* Detect multicast packets that didn't match the filter */
816         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
817                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
818
819                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
820                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
821                 } else {
822                         EFSYS_PROBE(mcast_mismatch);
823                         flags |= EFX_ADDR_MISMATCH;
824                 }
825         } else {
826                 flags |= EFX_PKT_UNICAST;
827         }
828
829         /*
830          * The packet parser in Siena can abort parsing packets under
831          * certain error conditions, setting the PKT_NOT_PARSED bit
832          * (which clears PKT_OK). If this is set, then don't trust
833          * the PKT_TYPE field.
834          */
835         if (!ok) {
836                 uint32_t parse_err;
837
838                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
839                 if (parse_err != 0)
840                         flags |= EFX_CHECK_VLAN;
841         }
842
843         if (~flags & EFX_CHECK_VLAN) {
844                 uint32_t pkt_type;
845
846                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
847                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
848                         flags |= EFX_PKT_VLAN_TAGGED;
849         }
850
851         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
852             uint32_t, size, uint16_t, flags);
853
854         EFSYS_ASSERT(eecp->eec_rx != NULL);
855         should_abort = eecp->eec_rx(arg, label, id, size, flags);
856
857         return (should_abort);
858 }
859
860 static  __checkReturn   boolean_t
861 siena_ev_tx(
862         __in            efx_evq_t *eep,
863         __in            efx_qword_t *eqp,
864         __in            const efx_ev_callbacks_t *eecp,
865         __in_opt        void *arg)
866 {
867         uint32_t id;
868         uint32_t label;
869         boolean_t should_abort;
870
871         EFX_EV_QSTAT_INCR(eep, EV_TX);
872
873         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
874             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
875             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
876             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
877
878                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
879                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
880
881                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
882
883                 EFSYS_ASSERT(eecp->eec_tx != NULL);
884                 should_abort = eecp->eec_tx(arg, label, id);
885
886                 return (should_abort);
887         }
888
889         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
890                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
891                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
892                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
893
894         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
895                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
896
897         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
898                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
899
900         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
901                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
902
903         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
904         return (B_FALSE);
905 }
906
907 static  __checkReturn   boolean_t
908 siena_ev_global(
909         __in            efx_evq_t *eep,
910         __in            efx_qword_t *eqp,
911         __in            const efx_ev_callbacks_t *eecp,
912         __in_opt        void *arg)
913 {
914         _NOTE(ARGUNUSED(eqp, eecp, arg))
915
916         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
917
918         return (B_FALSE);
919 }
920
921 static  __checkReturn   boolean_t
922 siena_ev_driver(
923         __in            efx_evq_t *eep,
924         __in            efx_qword_t *eqp,
925         __in            const efx_ev_callbacks_t *eecp,
926         __in_opt        void *arg)
927 {
928         boolean_t should_abort;
929
930         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
931         should_abort = B_FALSE;
932
933         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
934         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
935                 uint32_t txq_index;
936
937                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
938
939                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
940
941                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
942
943                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
944                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
945
946                 break;
947         }
948         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
949                 uint32_t rxq_index;
950                 uint32_t failed;
951
952                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
953                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
954
955                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
956                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
957
958                 if (failed) {
959                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
960
961                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
962
963                         should_abort = eecp->eec_rxq_flush_failed(arg,
964                                                                     rxq_index);
965                 } else {
966                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
967
968                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
969
970                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
971                 }
972
973                 break;
974         }
975         case FSE_AZ_EVQ_INIT_DONE_EV:
976                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
977                 should_abort = eecp->eec_initialized(arg);
978
979                 break;
980
981         case FSE_AZ_EVQ_NOT_EN_EV:
982                 EFSYS_PROBE(evq_not_en);
983                 break;
984
985         case FSE_AZ_SRM_UPD_DONE_EV: {
986                 uint32_t code;
987
988                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
989
990                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
991
992                 EFSYS_ASSERT(eecp->eec_sram != NULL);
993                 should_abort = eecp->eec_sram(arg, code);
994
995                 break;
996         }
997         case FSE_AZ_WAKE_UP_EV: {
998                 uint32_t id;
999
1000                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1001
1002                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
1003                 should_abort = eecp->eec_wake_up(arg, id);
1004
1005                 break;
1006         }
1007         case FSE_AZ_TX_PKT_NON_TCP_UDP:
1008                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
1009                 break;
1010
1011         case FSE_AZ_TIMER_EV: {
1012                 uint32_t id;
1013
1014                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
1015
1016                 EFSYS_ASSERT(eecp->eec_timer != NULL);
1017                 should_abort = eecp->eec_timer(arg, id);
1018
1019                 break;
1020         }
1021         case FSE_AZ_RX_DSC_ERROR_EV:
1022                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
1023
1024                 EFSYS_PROBE(rx_dsc_error);
1025
1026                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1027                 should_abort = eecp->eec_exception(arg,
1028                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
1029
1030                 break;
1031
1032         case FSE_AZ_TX_DSC_ERROR_EV:
1033                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1034
1035                 EFSYS_PROBE(tx_dsc_error);
1036
1037                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1038                 should_abort = eecp->eec_exception(arg,
1039                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1040
1041                 break;
1042
1043         default:
1044                 break;
1045         }
1046
1047         return (should_abort);
1048 }
1049
1050 static  __checkReturn   boolean_t
1051 siena_ev_drv_gen(
1052         __in            efx_evq_t *eep,
1053         __in            efx_qword_t *eqp,
1054         __in            const efx_ev_callbacks_t *eecp,
1055         __in_opt        void *arg)
1056 {
1057         uint32_t data;
1058         boolean_t should_abort;
1059
1060         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1061
1062         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1063         if (data >= ((uint32_t)1 << 16)) {
1064                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1065                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1066                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1067                 return (B_TRUE);
1068         }
1069
1070         EFSYS_ASSERT(eecp->eec_software != NULL);
1071         should_abort = eecp->eec_software(arg, (uint16_t)data);
1072
1073         return (should_abort);
1074 }
1075
1076 #if EFSYS_OPT_MCDI
1077
1078 static  __checkReturn   boolean_t
1079 siena_ev_mcdi(
1080         __in            efx_evq_t *eep,
1081         __in            efx_qword_t *eqp,
1082         __in            const efx_ev_callbacks_t *eecp,
1083         __in_opt        void *arg)
1084 {
1085         efx_nic_t *enp = eep->ee_enp;
1086         unsigned int code;
1087         boolean_t should_abort = B_FALSE;
1088
1089         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1090
1091         if (enp->en_family != EFX_FAMILY_SIENA)
1092                 goto out;
1093
1094         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1095         EFSYS_ASSERT(eecp->eec_exception != NULL);
1096 #if EFSYS_OPT_MON_STATS
1097         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1098 #endif
1099
1100         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1101
1102         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1103         switch (code) {
1104         case MCDI_EVENT_CODE_BADSSERT:
1105                 efx_mcdi_ev_death(enp, EINTR);
1106                 break;
1107
1108         case MCDI_EVENT_CODE_CMDDONE:
1109                 efx_mcdi_ev_cpl(enp,
1110                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1111                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1112                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1113                 break;
1114
1115         case MCDI_EVENT_CODE_LINKCHANGE: {
1116                 efx_link_mode_t link_mode;
1117
1118                 siena_phy_link_ev(enp, eqp, &link_mode);
1119                 should_abort = eecp->eec_link_change(arg, link_mode);
1120                 break;
1121         }
1122         case MCDI_EVENT_CODE_SENSOREVT: {
1123 #if EFSYS_OPT_MON_STATS
1124                 efx_mon_stat_t id;
1125                 efx_mon_stat_value_t value;
1126                 efx_rc_t rc;
1127
1128                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1129                         should_abort = eecp->eec_monitor(arg, id, value);
1130                 else if (rc == ENOTSUP) {
1131                         should_abort = eecp->eec_exception(arg,
1132                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1133                                 MCDI_EV_FIELD(eqp, DATA));
1134                 } else
1135                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1136 #else
1137                 should_abort = B_FALSE;
1138 #endif
1139                 break;
1140         }
1141         case MCDI_EVENT_CODE_SCHEDERR:
1142                 /* Informational only */
1143                 break;
1144
1145         case MCDI_EVENT_CODE_REBOOT:
1146                 efx_mcdi_ev_death(enp, EIO);
1147                 break;
1148
1149         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1150 #if EFSYS_OPT_MAC_STATS
1151                 if (eecp->eec_mac_stats != NULL) {
1152                         eecp->eec_mac_stats(arg,
1153                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1154                 }
1155 #endif
1156                 break;
1157
1158         case MCDI_EVENT_CODE_FWALERT: {
1159                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1160
1161                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1162                         should_abort = eecp->eec_exception(arg,
1163                                 EFX_EXCEPTION_FWALERT_SRAM,
1164                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1165                 else
1166                         should_abort = eecp->eec_exception(arg,
1167                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1168                                 MCDI_EV_FIELD(eqp, DATA));
1169                 break;
1170         }
1171
1172         default:
1173                 EFSYS_PROBE1(mc_pcol_error, int, code);
1174                 break;
1175         }
1176
1177 out:
1178         return (should_abort);
1179 }
1180
1181 #endif  /* EFSYS_OPT_MCDI */
1182
1183 static  __checkReturn   efx_rc_t
1184 siena_ev_qprime(
1185         __in            efx_evq_t *eep,
1186         __in            unsigned int count)
1187 {
1188         efx_nic_t *enp = eep->ee_enp;
1189         uint32_t rptr;
1190         efx_dword_t dword;
1191
1192         rptr = count & eep->ee_mask;
1193
1194         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1195
1196         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1197                             &dword, B_FALSE);
1198
1199         return (0);
1200 }
1201
1202 static          void
1203 siena_ev_qpost(
1204         __in    efx_evq_t *eep,
1205         __in    uint16_t data)
1206 {
1207         efx_nic_t *enp = eep->ee_enp;
1208         efx_qword_t ev;
1209         efx_oword_t oword;
1210
1211         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1212             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1213
1214         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1215             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1216             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1217
1218         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1219 }
1220
1221 static  __checkReturn   efx_rc_t
1222 siena_ev_qmoderate(
1223         __in            efx_evq_t *eep,
1224         __in            unsigned int us)
1225 {
1226         efx_nic_t *enp = eep->ee_enp;
1227         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1228         unsigned int locked;
1229         efx_dword_t dword;
1230         efx_rc_t rc;
1231
1232         if (us > encp->enc_evq_timer_max_us) {
1233                 rc = EINVAL;
1234                 goto fail1;
1235         }
1236
1237         /* If the value is zero then disable the timer */
1238         if (us == 0) {
1239                 EFX_POPULATE_DWORD_2(dword,
1240                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1241                     FRF_CZ_TC_TIMER_VAL, 0);
1242         } else {
1243                 unsigned int ticks;
1244
1245                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1246                         goto fail2;
1247
1248                 EFSYS_ASSERT(ticks > 0);
1249                 EFX_POPULATE_DWORD_2(dword,
1250                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1251                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1252         }
1253
1254         locked = (eep->ee_index == 0) ? 1 : 0;
1255
1256         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1257             eep->ee_index, &dword, locked);
1258
1259         return (0);
1260
1261 fail2:
1262         EFSYS_PROBE(fail2);
1263 fail1:
1264         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1265
1266         return (rc);
1267 }
1268
1269 static  __checkReturn   efx_rc_t
1270 siena_ev_qcreate(
1271         __in            efx_nic_t *enp,
1272         __in            unsigned int index,
1273         __in            efsys_mem_t *esmp,
1274         __in            size_t ndescs,
1275         __in            uint32_t id,
1276         __in            uint32_t us,
1277         __in            uint32_t flags,
1278         __in            efx_evq_t *eep)
1279 {
1280         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1281         uint32_t size;
1282         efx_oword_t oword;
1283         efx_rc_t rc;
1284         boolean_t notify_mode;
1285
1286         _NOTE(ARGUNUSED(esmp))
1287
1288         EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
1289         EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
1290
1291         if (!ISP2(ndescs) ||
1292             (ndescs < encp->enc_evq_min_nevs) ||
1293             (ndescs > encp->enc_evq_max_nevs)) {
1294                 rc = EINVAL;
1295                 goto fail1;
1296         }
1297         if (index >= encp->enc_evq_limit) {
1298                 rc = EINVAL;
1299                 goto fail2;
1300         }
1301 #if EFSYS_OPT_RX_SCALE
1302         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1303             index >= EFX_MAXRSS_LEGACY) {
1304                 rc = EINVAL;
1305                 goto fail3;
1306         }
1307 #endif
1308         for (size = 0;
1309             (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1310             size++)
1311                 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1312                         break;
1313         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1314                 rc = EINVAL;
1315                 goto fail4;
1316         }
1317
1318         /* Set up the handler table */
1319         eep->ee_rx      = siena_ev_rx;
1320         eep->ee_tx      = siena_ev_tx;
1321         eep->ee_driver  = siena_ev_driver;
1322         eep->ee_global  = siena_ev_global;
1323         eep->ee_drv_gen = siena_ev_drv_gen;
1324 #if EFSYS_OPT_MCDI
1325         eep->ee_mcdi    = siena_ev_mcdi;
1326 #endif  /* EFSYS_OPT_MCDI */
1327
1328         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1329             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1330
1331         /* Set up the new event queue */
1332         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1333             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1334             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1335         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1336
1337         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1338             FRF_AZ_EVQ_BUF_BASE_ID, id);
1339
1340         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1341
1342         /* Set initial interrupt moderation */
1343         siena_ev_qmoderate(eep, us);
1344
1345         return (0);
1346
1347 fail4:
1348         EFSYS_PROBE(fail4);
1349 #if EFSYS_OPT_RX_SCALE
1350 fail3:
1351         EFSYS_PROBE(fail3);
1352 #endif
1353 fail2:
1354         EFSYS_PROBE(fail2);
1355 fail1:
1356         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1357
1358         return (rc);
1359 }
1360
1361 #endif /* EFSYS_OPT_SIENA */
1362
1363 #if EFSYS_OPT_QSTATS
1364 #if EFSYS_OPT_NAMES
1365 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock c0f3bc5083b40532 */
1366 static const char * const __efx_ev_qstat_name[] = {
1367         "all",
1368         "rx",
1369         "rx_ok",
1370         "rx_frm_trunc",
1371         "rx_tobe_disc",
1372         "rx_pause_frm_err",
1373         "rx_buf_owner_id_err",
1374         "rx_ipv4_hdr_chksum_err",
1375         "rx_tcp_udp_chksum_err",
1376         "rx_eth_crc_err",
1377         "rx_ip_frag_err",
1378         "rx_mcast_pkt",
1379         "rx_mcast_hash_match",
1380         "rx_tcp_ipv4",
1381         "rx_tcp_ipv6",
1382         "rx_udp_ipv4",
1383         "rx_udp_ipv6",
1384         "rx_other_ipv4",
1385         "rx_other_ipv6",
1386         "rx_non_ip",
1387         "rx_batch",
1388         "tx",
1389         "tx_wq_ff_full",
1390         "tx_pkt_err",
1391         "tx_pkt_too_big",
1392         "tx_unexpected",
1393         "global",
1394         "global_mnt",
1395         "driver",
1396         "driver_srm_upd_done",
1397         "driver_tx_descq_fls_done",
1398         "driver_rx_descq_fls_done",
1399         "driver_rx_descq_fls_failed",
1400         "driver_rx_dsc_error",
1401         "driver_tx_dsc_error",
1402         "drv_gen",
1403         "mcdi_response",
1404 };
1405 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1406
1407                 const char *
1408 efx_ev_qstat_name(
1409         __in    efx_nic_t *enp,
1410         __in    unsigned int id)
1411 {
1412         _NOTE(ARGUNUSED(enp))
1413
1414         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1415         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1416
1417         return (__efx_ev_qstat_name[id]);
1418 }
1419 #endif  /* EFSYS_OPT_NAMES */
1420 #endif  /* EFSYS_OPT_QSTATS */
1421
1422 #if EFSYS_OPT_SIENA
1423
1424 #if EFSYS_OPT_QSTATS
1425 static                                  void
1426 siena_ev_qstats_update(
1427         __in                            efx_evq_t *eep,
1428         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1429 {
1430         unsigned int id;
1431
1432         for (id = 0; id < EV_NQSTATS; id++) {
1433                 efsys_stat_t *essp = &stat[id];
1434
1435                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1436                 eep->ee_stat[id] = 0;
1437         }
1438 }
1439 #endif  /* EFSYS_OPT_QSTATS */
1440
1441 static          void
1442 siena_ev_qdestroy(
1443         __in    efx_evq_t *eep)
1444 {
1445         efx_nic_t *enp = eep->ee_enp;
1446         efx_oword_t oword;
1447
1448         /* Purge event queue */
1449         EFX_ZERO_OWORD(oword);
1450
1451         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1452             eep->ee_index, &oword, B_TRUE);
1453
1454         EFX_ZERO_OWORD(oword);
1455         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1456 }
1457
1458 static          void
1459 siena_ev_fini(
1460         __in    efx_nic_t *enp)
1461 {
1462         _NOTE(ARGUNUSED(enp))
1463 }
1464
1465 #endif /* EFSYS_OPT_SIENA */