drivers/net/sfc/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13
  14 /* FIXME: Add definition for driver generated software events */
  15 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  16 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  17 #endif
  18
  19
  20 #if EFSYS_OPT_SIENA
  21 #include "siena_impl.h"
  22 #endif  /* EFSYS_OPT_SIENA */
  23
  24 #if EFSYS_OPT_HUNTINGTON
  25 #include "hunt_impl.h"
  26 #endif  /* EFSYS_OPT_HUNTINGTON */
  27
  28 #if EFSYS_OPT_MEDFORD
  29 #include "medford_impl.h"
  30 #endif  /* EFSYS_OPT_MEDFORD */
  31
  32 #if EFSYS_OPT_MEDFORD2
  33 #include "medford2_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD2 */
  35
  36 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
  37 #include "ef10_impl.h"
  38 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
  39
  40 #ifdef  __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 #define EFX_MOD_MCDI            0x00000001
  45 #define EFX_MOD_PROBE           0x00000002
  46 #define EFX_MOD_NVRAM           0x00000004
  47 #define EFX_MOD_VPD             0x00000008
  48 #define EFX_MOD_NIC             0x00000010
  49 #define EFX_MOD_INTR            0x00000020
  50 #define EFX_MOD_EV              0x00000040
  51 #define EFX_MOD_RX              0x00000080
  52 #define EFX_MOD_TX              0x00000100
  53 #define EFX_MOD_PORT            0x00000200
  54 #define EFX_MOD_MON             0x00000400
  55 #define EFX_MOD_FILTER          0x00001000
  56 #define EFX_MOD_LIC             0x00002000
  57 #define EFX_MOD_TUNNEL          0x00004000
  58
  59 #define EFX_RESET_PHY           0x00000001
  60 #define EFX_RESET_RXQ_ERR       0x00000002
  61 #define EFX_RESET_TXQ_ERR       0x00000004
  62
  63 typedef enum efx_mac_type_e {
  64         EFX_MAC_INVALID = 0,
  65         EFX_MAC_SIENA,
  66         EFX_MAC_HUNTINGTON,
  67         EFX_MAC_MEDFORD,
  68         EFX_MAC_MEDFORD2,
  69         EFX_MAC_NTYPES
  70 } efx_mac_type_t;
  71
  72 typedef struct efx_ev_ops_s {
  73         efx_rc_t        (*eevo_init)(efx_nic_t *);
  74         void            (*eevo_fini)(efx_nic_t *);
  75         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  76                                           efsys_mem_t *, size_t, uint32_t,
  77                                           uint32_t, uint32_t, efx_evq_t *);
  78         void            (*eevo_qdestroy)(efx_evq_t *);
  79         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  80         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  81         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  82 #if EFSYS_OPT_QSTATS
  83         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  84 #endif
  85 } efx_ev_ops_t;
  86
  87 typedef struct efx_tx_ops_s {
  88         efx_rc_t        (*etxo_init)(efx_nic_t *);
  89         void            (*etxo_fini)(efx_nic_t *);
  90         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
  91                                         unsigned int, unsigned int,
  92                                         efsys_mem_t *, size_t,
  93                                         uint32_t, uint16_t,
  94                                         efx_evq_t *, efx_txq_t *,
  95                                         unsigned int *);
  96         void            (*etxo_qdestroy)(efx_txq_t *);
  97         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
  98                                       unsigned int, unsigned int,
  99                                       unsigned int *);
 100         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 101         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 102         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 103         void            (*etxo_qenable)(efx_txq_t *);
 104         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 105         void            (*etxo_qpio_disable)(efx_txq_t *);
 106         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 107                                            size_t);
 108         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 109                                            unsigned int *);
 110         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 111                                       unsigned int, unsigned int,
 112                                       unsigned int *);
 113         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 114                                                 size_t, boolean_t,
 115                                                 efx_desc_t *);
 116         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 117                                                 uint32_t, uint8_t,
 118                                                 efx_desc_t *);
 119         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 120                                                 uint32_t, uint16_t,
 121                                                 efx_desc_t *, int);
 122         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 123                                                 efx_desc_t *);
 124 #if EFSYS_OPT_QSTATS
 125         void            (*etxo_qstats_update)(efx_txq_t *,
 126                                               efsys_stat_t *);
 127 #endif
 128 } efx_tx_ops_t;
 129
 130 typedef struct efx_rx_ops_s {
 131         efx_rc_t        (*erxo_init)(efx_nic_t *);
 132         void            (*erxo_fini)(efx_nic_t *);
 133 #if EFSYS_OPT_RX_SCATTER
 134         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 135 #endif
 136 #if EFSYS_OPT_RX_SCALE
 137         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 138                                                     efx_rx_scale_context_type_t,
 139                                                     uint32_t, uint32_t *);
 140         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 141         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 142                                                efx_rx_hash_alg_t,
 143                                                efx_rx_hash_type_t, boolean_t);
 144         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 145                                               uint8_t *, size_t);
 146         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 147                                               unsigned int *, size_t);
 148         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 149                                             uint8_t *);
 150 #endif /* EFSYS_OPT_RX_SCALE */
 151         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 152                                               uint16_t *);
 153         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 154                                       unsigned int, unsigned int,
 155                                       unsigned int);
 156         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 157 #if EFSYS_OPT_RX_PACKED_STREAM
 158         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 159         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 160                                                 uint32_t, uint32_t,
 161                                                 uint16_t *, uint32_t *, uint32_t *);
 162 #endif
 163         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 164         void            (*erxo_qenable)(efx_rxq_t *);
 165         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 166                                         unsigned int, efx_rxq_type_t, uint32_t,
 167                                         efsys_mem_t *, size_t, uint32_t,
 168                                         unsigned int,
 169                                         efx_evq_t *, efx_rxq_t *);
 170         void            (*erxo_qdestroy)(efx_rxq_t *);
 171 } efx_rx_ops_t;
 172
 173 typedef struct efx_mac_ops_s {
 174         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 175         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 176         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 177         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 178         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 179         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 180         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 181         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 182                                                       efx_rxq_t *, boolean_t);
 183         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 184 #if EFSYS_OPT_LOOPBACK
 185         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 186                                             efx_loopback_type_t);
 187 #endif  /* EFSYS_OPT_LOOPBACK */
 188 #if EFSYS_OPT_MAC_STATS
 189         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 190         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 191         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 192         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 193                                               uint16_t, boolean_t);
 194         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 195                                             efsys_stat_t *, uint32_t *);
 196 #endif  /* EFSYS_OPT_MAC_STATS */
 197 } efx_mac_ops_t;
 198
 199 typedef struct efx_phy_ops_s {
 200         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 201         efx_rc_t        (*epo_reset)(efx_nic_t *);
 202         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 203         efx_rc_t        (*epo_verify)(efx_nic_t *);
 204         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 205 #if EFSYS_OPT_PHY_STATS
 206         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 207                                             uint32_t *);
 208 #endif  /* EFSYS_OPT_PHY_STATS */
 209 #if EFSYS_OPT_BIST
 210         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 211         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 212         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 213                                          efx_bist_result_t *, uint32_t *,
 214                                          unsigned long *, size_t);
 215         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 216 #endif  /* EFSYS_OPT_BIST */
 217 } efx_phy_ops_t;
 218
 219 #if EFSYS_OPT_FILTER
 220 typedef struct efx_filter_ops_s {
 221         efx_rc_t        (*efo_init)(efx_nic_t *);
 222         void            (*efo_fini)(efx_nic_t *);
 223         efx_rc_t        (*efo_restore)(efx_nic_t *);
 224         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 225                                    boolean_t may_replace);
 226         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 227         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 228                                    size_t, size_t *);
 229         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 230                                    boolean_t, boolean_t, boolean_t,
 231                                    uint8_t const *, uint32_t);
 232 } efx_filter_ops_t;
 233
 234 extern  __checkReturn   efx_rc_t
 235 efx_filter_reconfigure(
 236         __in                            efx_nic_t *enp,
 237         __in_ecount(6)                  uint8_t const *mac_addr,
 238         __in                            boolean_t all_unicst,
 239         __in                            boolean_t mulcst,
 240         __in                            boolean_t all_mulcst,
 241         __in                            boolean_t brdcst,
 242         __in_ecount(6*count)            uint8_t const *addrs,
 243         __in                            uint32_t count);
 244
 245 #endif /* EFSYS_OPT_FILTER */
 246
 247 #if EFSYS_OPT_TUNNEL
 248 typedef struct efx_tunnel_ops_s {
 249         boolean_t       (*eto_udp_encap_supported)(efx_nic_t *);
 250         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 251 } efx_tunnel_ops_t;
 252 #endif /* EFSYS_OPT_TUNNEL */
 253
 254 typedef struct efx_port_s {
 255         efx_mac_type_t          ep_mac_type;
 256         uint32_t                ep_phy_type;
 257         uint8_t                 ep_port;
 258         uint32_t                ep_mac_pdu;
 259         uint8_t                 ep_mac_addr[6];
 260         efx_link_mode_t         ep_link_mode;
 261         boolean_t               ep_all_unicst;
 262         boolean_t               ep_mulcst;
 263         boolean_t               ep_all_mulcst;
 264         boolean_t               ep_brdcst;
 265         unsigned int            ep_fcntl;
 266         boolean_t               ep_fcntl_autoneg;
 267         efx_oword_t             ep_multicst_hash[2];
 268         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 269                                                     EFX_MAC_MULTICAST_LIST_MAX];
 270         uint32_t                ep_mulcst_addr_count;
 271 #if EFSYS_OPT_LOOPBACK
 272         efx_loopback_type_t     ep_loopback_type;
 273         efx_link_mode_t         ep_loopback_link_mode;
 274 #endif  /* EFSYS_OPT_LOOPBACK */
 275 #if EFSYS_OPT_PHY_FLAGS
 276         uint32_t                ep_phy_flags;
 277 #endif  /* EFSYS_OPT_PHY_FLAGS */
 278 #if EFSYS_OPT_PHY_LED_CONTROL
 279         efx_phy_led_mode_t      ep_phy_led_mode;
 280 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 281         efx_phy_media_type_t    ep_fixed_port_type;
 282         efx_phy_media_type_t    ep_module_type;
 283         uint32_t                ep_adv_cap_mask;
 284         uint32_t                ep_lp_cap_mask;
 285         uint32_t                ep_default_adv_cap_mask;
 286         uint32_t                ep_phy_cap_mask;
 287         boolean_t               ep_mac_drain;
 288 #if EFSYS_OPT_BIST
 289         efx_bist_type_t         ep_current_bist;
 290 #endif
 291         const efx_mac_ops_t     *ep_emop;
 292         const efx_phy_ops_t     *ep_epop;
 293 } efx_port_t;
 294
 295 typedef struct efx_mon_ops_s {
 296 #if EFSYS_OPT_MON_STATS
 297         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 298                                             efx_mon_stat_value_t *);
 299 #endif  /* EFSYS_OPT_MON_STATS */
 300 } efx_mon_ops_t;
 301
 302 typedef struct efx_mon_s {
 303         efx_mon_type_t          em_type;
 304         const efx_mon_ops_t     *em_emop;
 305 } efx_mon_t;
 306
 307 typedef struct efx_intr_ops_s {
 308         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 309         void            (*eio_enable)(efx_nic_t *);
 310         void            (*eio_disable)(efx_nic_t *);
 311         void            (*eio_disable_unlocked)(efx_nic_t *);
 312         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 313         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 314         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 315                                  boolean_t *);
 316         void            (*eio_fatal)(efx_nic_t *);
 317         void            (*eio_fini)(efx_nic_t *);
 318 } efx_intr_ops_t;
 319
 320 typedef struct efx_intr_s {
 321         const efx_intr_ops_t    *ei_eiop;
 322         efsys_mem_t             *ei_esmp;
 323         efx_intr_type_t         ei_type;
 324         unsigned int            ei_level;
 325 } efx_intr_t;
 326
 327 typedef struct efx_nic_ops_s {
 328         efx_rc_t        (*eno_probe)(efx_nic_t *);
 329         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 330         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 331         efx_rc_t        (*eno_reset)(efx_nic_t *);
 332         efx_rc_t        (*eno_init)(efx_nic_t *);
 333         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 334         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 335                                         uint32_t *, size_t *);
 336 #if EFSYS_OPT_DIAG
 337         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 338 #endif  /* EFSYS_OPT_DIAG */
 339         void            (*eno_fini)(efx_nic_t *);
 340         void            (*eno_unprobe)(efx_nic_t *);
 341 } efx_nic_ops_t;
 342
 343 #ifndef EFX_TXQ_LIMIT_TARGET
 344 #define EFX_TXQ_LIMIT_TARGET 259
 345 #endif
 346 #ifndef EFX_RXQ_LIMIT_TARGET
 347 #define EFX_RXQ_LIMIT_TARGET 512
 348 #endif
 349
 350
 351 #if EFSYS_OPT_FILTER
 352
 353 #if EFSYS_OPT_SIENA
 354
 355 typedef struct siena_filter_spec_s {
 356         uint8_t         sfs_type;
 357         uint32_t        sfs_flags;
 358         uint32_t        sfs_dmaq_id;
 359         uint32_t        sfs_dword[3];
 360 } siena_filter_spec_t;
 361
 362 typedef enum siena_filter_type_e {
 363         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 364         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 365         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 366         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 367         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 368         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 369
 370         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 371         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 372         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 373         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 374         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 375         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 376
 377         EFX_SIENA_FILTER_NTYPES
 378 } siena_filter_type_t;
 379
 380 typedef enum siena_filter_tbl_id_e {
 381         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 382         EFX_SIENA_FILTER_TBL_RX_MAC,
 383         EFX_SIENA_FILTER_TBL_TX_IP,
 384         EFX_SIENA_FILTER_TBL_TX_MAC,
 385         EFX_SIENA_FILTER_NTBLS
 386 } siena_filter_tbl_id_t;
 387
 388 typedef struct siena_filter_tbl_s {
 389         int                     sft_size;       /* number of entries */
 390         int                     sft_used;       /* active count */
 391         uint32_t                *sft_bitmap;    /* active bitmap */
 392         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 393 } siena_filter_tbl_t;
 394
 395 typedef struct siena_filter_s {
 396         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 397         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 398 } siena_filter_t;
 399
 400 #endif  /* EFSYS_OPT_SIENA */
 401
 402 typedef struct efx_filter_s {
 403 #if EFSYS_OPT_SIENA
 404         siena_filter_t          *ef_siena_filter;
 405 #endif /* EFSYS_OPT_SIENA */
 406 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 407         ef10_filter_table_t     *ef_ef10_filter_table;
 408 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 409 } efx_filter_t;
 410
 411 #if EFSYS_OPT_SIENA
 412
 413 extern                  void
 414 siena_filter_tbl_clear(
 415         __in            efx_nic_t *enp,
 416         __in            siena_filter_tbl_id_t tbl);
 417
 418 #endif  /* EFSYS_OPT_SIENA */
 419
 420 #endif  /* EFSYS_OPT_FILTER */
 421
 422 #if EFSYS_OPT_MCDI
 423
 424 #define EFX_TUNNEL_MAXNENTRIES  (16)
 425
 426 #if EFSYS_OPT_TUNNEL
 427
 428 typedef struct efx_tunnel_udp_entry_s {
 429         uint16_t                        etue_port; /* host/cpu-endian */
 430         uint16_t                        etue_protocol;
 431 } efx_tunnel_udp_entry_t;
 432
 433 typedef struct efx_tunnel_cfg_s {
 434         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 435         unsigned int            etc_udp_entries_num;
 436 } efx_tunnel_cfg_t;
 437
 438 #endif /* EFSYS_OPT_TUNNEL */
 439
 440 typedef struct efx_mcdi_ops_s {
 441         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 442         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 443                                         void *, size_t);
 444         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 445         boolean_t       (*emco_poll_response)(efx_nic_t *);
 446         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 447         void            (*emco_fini)(efx_nic_t *);
 448         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 449                                             efx_mcdi_feature_id_t, boolean_t *);
 450         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 451                                             uint32_t *);
 452 } efx_mcdi_ops_t;
 453
 454 typedef struct efx_mcdi_s {
 455         const efx_mcdi_ops_t            *em_emcop;
 456         const efx_mcdi_transport_t      *em_emtp;
 457         efx_mcdi_iface_t                em_emip;
 458 } efx_mcdi_t;
 459
 460 #endif /* EFSYS_OPT_MCDI */
 461
 462 #if EFSYS_OPT_NVRAM
 463
 464 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 465 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 466
 467 typedef struct efx_nvram_ops_s {
 468 #if EFSYS_OPT_DIAG
 469         efx_rc_t        (*envo_test)(efx_nic_t *);
 470 #endif  /* EFSYS_OPT_DIAG */
 471         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 472                                             uint32_t *);
 473         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 474         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 475         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 476                                             unsigned int, caddr_t, size_t);
 477         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 478                                             unsigned int, caddr_t, size_t);
 479         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 480                                             unsigned int, size_t);
 481         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 482                                             unsigned int, caddr_t, size_t);
 483         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 484                                             uint32_t *);
 485         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 486                                             uint32_t *, uint16_t *);
 487         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 488                                             uint16_t *);
 489         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 490                                             caddr_t, size_t);
 491 } efx_nvram_ops_t;
 492 #endif /* EFSYS_OPT_NVRAM */
 493
 494 #if EFSYS_OPT_VPD
 495 typedef struct efx_vpd_ops_s {
 496         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 497         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 498         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 499         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 500         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 501         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 502                                         efx_vpd_value_t *);
 503         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 504                                         efx_vpd_value_t *);
 505         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 506                                         efx_vpd_value_t *, unsigned int *);
 507         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 508         void            (*evpdo_fini)(efx_nic_t *);
 509 } efx_vpd_ops_t;
 510 #endif  /* EFSYS_OPT_VPD */
 511
 512 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 513
 514         __checkReturn           efx_rc_t
 515 efx_mcdi_nvram_partitions(
 516         __in                    efx_nic_t *enp,
 517         __out_bcount(size)      caddr_t data,
 518         __in                    size_t size,
 519         __out                   unsigned int *npartnp);
 520
 521         __checkReturn           efx_rc_t
 522 efx_mcdi_nvram_metadata(
 523         __in                    efx_nic_t *enp,
 524         __in                    uint32_t partn,
 525         __out                   uint32_t *subtypep,
 526         __out_ecount(4)         uint16_t version[4],
 527         __out_bcount_opt(size)  char *descp,
 528         __in                    size_t size);
 529
 530         __checkReturn           efx_rc_t
 531 efx_mcdi_nvram_info(
 532         __in                    efx_nic_t *enp,
 533         __in                    uint32_t partn,
 534         __out_opt               size_t *sizep,
 535         __out_opt               uint32_t *addressp,
 536         __out_opt               uint32_t *erase_sizep,
 537         __out_opt               uint32_t *write_sizep);
 538
 539         __checkReturn           efx_rc_t
 540 efx_mcdi_nvram_update_start(
 541         __in                    efx_nic_t *enp,
 542         __in                    uint32_t partn);
 543
 544         __checkReturn           efx_rc_t
 545 efx_mcdi_nvram_read(
 546         __in                    efx_nic_t *enp,
 547         __in                    uint32_t partn,
 548         __in                    uint32_t offset,
 549         __out_bcount(size)      caddr_t data,
 550         __in                    size_t size,
 551         __in                    uint32_t mode);
 552
 553         __checkReturn           efx_rc_t
 554 efx_mcdi_nvram_erase(
 555         __in                    efx_nic_t *enp,
 556         __in                    uint32_t partn,
 557         __in                    uint32_t offset,
 558         __in                    size_t size);
 559
 560         __checkReturn           efx_rc_t
 561 efx_mcdi_nvram_write(
 562         __in                    efx_nic_t *enp,
 563         __in                    uint32_t partn,
 564         __in                    uint32_t offset,
 565         __out_bcount(size)      caddr_t data,
 566         __in                    size_t size);
 567
 568         __checkReturn           efx_rc_t
 569 efx_mcdi_nvram_update_finish(
 570         __in                    efx_nic_t *enp,
 571         __in                    uint32_t partn,
 572         __in                    boolean_t reboot,
 573         __out_opt               uint32_t *verify_resultp);
 574
 575 #if EFSYS_OPT_DIAG
 576
 577         __checkReturn           efx_rc_t
 578 efx_mcdi_nvram_test(
 579         __in                    efx_nic_t *enp,
 580         __in                    uint32_t partn);
 581
 582 #endif  /* EFSYS_OPT_DIAG */
 583
 584 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 585
 586 #if EFSYS_OPT_LICENSING
 587
 588 typedef struct efx_lic_ops_s {
 589         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 590         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 591         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 592         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 593                                       size_t *, uint8_t *);
 594         efx_rc_t        (*elo_find_start)
 595                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 596         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 597                                 uint32_t, uint32_t *);
 598         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 599                                 uint32_t, uint32_t *, uint32_t *);
 600         boolean_t       (*elo_validate_key)(efx_nic_t *,
 601                                 caddr_t, uint32_t);
 602         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 603                                 caddr_t, size_t, uint32_t, uint32_t,
 604                                 caddr_t, size_t, uint32_t *);
 605         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 606                                 caddr_t, size_t, uint32_t,
 607                                 caddr_t, uint32_t, uint32_t *);
 608         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 609                                 caddr_t, size_t, uint32_t,
 610                                 uint32_t, uint32_t, uint32_t *);
 611         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 612                                 caddr_t, size_t);
 613         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 614                                 caddr_t, size_t);
 615 } efx_lic_ops_t;
 616
 617 #endif
 618
 619 typedef struct efx_drv_cfg_s {
 620         uint32_t                edc_min_vi_count;
 621         uint32_t                edc_max_vi_count;
 622
 623         uint32_t                edc_max_piobuf_count;
 624         uint32_t                edc_pio_alloc_size;
 625 } efx_drv_cfg_t;
 626
 627 struct efx_nic_s {
 628         uint32_t                en_magic;
 629         efx_family_t            en_family;
 630         uint32_t                en_features;
 631         efsys_identifier_t      *en_esip;
 632         efsys_lock_t            *en_eslp;
 633         efsys_bar_t             *en_esbp;
 634         unsigned int            en_mod_flags;
 635         unsigned int            en_reset_flags;
 636         efx_nic_cfg_t           en_nic_cfg;
 637         efx_drv_cfg_t           en_drv_cfg;
 638         efx_port_t              en_port;
 639         efx_mon_t               en_mon;
 640         efx_intr_t              en_intr;
 641         uint32_t                en_ev_qcount;
 642         uint32_t                en_rx_qcount;
 643         uint32_t                en_tx_qcount;
 644         const efx_nic_ops_t     *en_enop;
 645         const efx_ev_ops_t      *en_eevop;
 646         const efx_tx_ops_t      *en_etxop;
 647         const efx_rx_ops_t      *en_erxop;
 648 #if EFSYS_OPT_FILTER
 649         efx_filter_t            en_filter;
 650         const efx_filter_ops_t  *en_efop;
 651 #endif  /* EFSYS_OPT_FILTER */
 652 #if EFSYS_OPT_TUNNEL
 653         efx_tunnel_cfg_t        en_tunnel_cfg;
 654         const efx_tunnel_ops_t  *en_etop;
 655 #endif /* EFSYS_OPT_TUNNEL */
 656 #if EFSYS_OPT_MCDI
 657         efx_mcdi_t              en_mcdi;
 658 #endif  /* EFSYS_OPT_MCDI */
 659 #if EFSYS_OPT_NVRAM
 660         uint32_t                en_nvram_partn_locked;
 661         const efx_nvram_ops_t   *en_envop;
 662 #endif  /* EFSYS_OPT_NVRAM */
 663 #if EFSYS_OPT_VPD
 664         const efx_vpd_ops_t     *en_evpdop;
 665 #endif  /* EFSYS_OPT_VPD */
 666 #if EFSYS_OPT_RX_SCALE
 667         efx_rx_hash_support_t           en_hash_support;
 668         efx_rx_scale_context_type_t     en_rss_context_type;
 669         uint32_t                        en_rss_context;
 670 #endif  /* EFSYS_OPT_RX_SCALE */
 671         uint32_t                en_vport_id;
 672 #if EFSYS_OPT_LICENSING
 673         const efx_lic_ops_t     *en_elop;
 674         boolean_t               en_licensing_supported;
 675 #endif
 676         union {
 677 #if EFSYS_OPT_SIENA
 678                 struct {
 679 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 680                         unsigned int            enu_partn_mask;
 681 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 682 #if EFSYS_OPT_VPD
 683                         caddr_t                 enu_svpd;
 684                         size_t                  enu_svpd_length;
 685 #endif  /* EFSYS_OPT_VPD */
 686                         int                     enu_unused;
 687                 } siena;
 688 #endif  /* EFSYS_OPT_SIENA */
 689                 int     enu_unused;
 690         } en_u;
 691 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2)
 692         union en_arch {
 693                 struct {
 694                         int                     ena_vi_base;
 695                         int                     ena_vi_count;
 696                         int                     ena_vi_shift;
 697 #if EFSYS_OPT_VPD
 698                         caddr_t                 ena_svpd;
 699                         size_t                  ena_svpd_length;
 700 #endif  /* EFSYS_OPT_VPD */
 701                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 702                         uint32_t                ena_piobuf_count;
 703                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 704                         uint32_t                ena_pio_write_vi_base;
 705                         /* Memory BAR mapping regions */
 706                         uint32_t                ena_uc_mem_map_offset;
 707                         size_t                  ena_uc_mem_map_size;
 708                         uint32_t                ena_wc_mem_map_offset;
 709                         size_t                  ena_wc_mem_map_size;
 710                 } ef10;
 711         } en_arch;
 712 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2) */
 713 };
 714
 715
 716 #define EFX_NIC_MAGIC   0x02121996
 717
 718 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 719     const efx_ev_callbacks_t *, void *);
 720
 721 typedef struct efx_evq_rxq_state_s {
 722         unsigned int                    eers_rx_read_ptr;
 723         unsigned int                    eers_rx_mask;
 724 #if EFSYS_OPT_RX_PACKED_STREAM
 725         unsigned int                    eers_rx_stream_npackets;
 726         boolean_t                       eers_rx_packed_stream;
 727         unsigned int                    eers_rx_packed_stream_credits;
 728 #endif
 729 } efx_evq_rxq_state_t;
 730
 731 struct efx_evq_s {
 732         uint32_t                        ee_magic;
 733         efx_nic_t                       *ee_enp;
 734         unsigned int                    ee_index;
 735         unsigned int                    ee_mask;
 736         efsys_mem_t                     *ee_esmp;
 737 #if EFSYS_OPT_QSTATS
 738         uint32_t                        ee_stat[EV_NQSTATS];
 739 #endif  /* EFSYS_OPT_QSTATS */
 740
 741         efx_ev_handler_t                ee_rx;
 742         efx_ev_handler_t                ee_tx;
 743         efx_ev_handler_t                ee_driver;
 744         efx_ev_handler_t                ee_global;
 745         efx_ev_handler_t                ee_drv_gen;
 746 #if EFSYS_OPT_MCDI
 747         efx_ev_handler_t                ee_mcdi;
 748 #endif  /* EFSYS_OPT_MCDI */
 749
 750         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 751
 752         uint32_t                        ee_flags;
 753 };
 754
 755 #define EFX_EVQ_MAGIC   0x08081997
 756
 757 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 758
 759 struct efx_rxq_s {
 760         uint32_t                        er_magic;
 761         efx_nic_t                       *er_enp;
 762         efx_evq_t                       *er_eep;
 763         unsigned int                    er_index;
 764         unsigned int                    er_label;
 765         unsigned int                    er_mask;
 766         efsys_mem_t                     *er_esmp;
 767         efx_evq_rxq_state_t             *er_ev_qstate;
 768 };
 769
 770 #define EFX_RXQ_MAGIC   0x15022005
 771
 772 struct efx_txq_s {
 773         uint32_t                        et_magic;
 774         efx_nic_t                       *et_enp;
 775         unsigned int                    et_index;
 776         unsigned int                    et_mask;
 777         efsys_mem_t                     *et_esmp;
 778 #if EFSYS_OPT_HUNTINGTON
 779         uint32_t                        et_pio_bufnum;
 780         uint32_t                        et_pio_blknum;
 781         uint32_t                        et_pio_write_offset;
 782         uint32_t                        et_pio_offset;
 783         size_t                          et_pio_size;
 784 #endif
 785 #if EFSYS_OPT_QSTATS
 786         uint32_t                        et_stat[TX_NQSTATS];
 787 #endif  /* EFSYS_OPT_QSTATS */
 788 };
 789
 790 #define EFX_TXQ_MAGIC   0x05092005
 791
 792 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 793         do {                                                            \
 794                 (_dst)[0] = (_src)[0];                                  \
 795                 (_dst)[1] = (_src)[1];                                  \
 796                 (_dst)[2] = (_src)[2];                                  \
 797                 (_dst)[3] = (_src)[3];                                  \
 798                 (_dst)[4] = (_src)[4];                                  \
 799                 (_dst)[5] = (_src)[5];                                  \
 800         _NOTE(CONSTANTCONDITION)                                        \
 801         } while (B_FALSE)
 802
 803 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 804         do {                                                            \
 805                 uint16_t *_d = (uint16_t *)(_dst);                      \
 806                 _d[0] = 0xffff;                                         \
 807                 _d[1] = 0xffff;                                         \
 808                 _d[2] = 0xffff;                                         \
 809         _NOTE(CONSTANTCONDITION)                                        \
 810         } while (B_FALSE)
 811
 812 #if EFSYS_OPT_CHECK_REG
 813 #define EFX_CHECK_REG(_enp, _reg)                                       \
 814         do {                                                            \
 815                 const char *name = #_reg;                               \
 816                 char min = name[4];                                     \
 817                 char max = name[5];                                     \
 818                 char rev;                                               \
 819                                                                         \
 820                 switch ((_enp)->en_family) {                            \
 821                 case EFX_FAMILY_SIENA:                                  \
 822                         rev = 'C';                                      \
 823                         break;                                          \
 824                                                                         \
 825                 case EFX_FAMILY_HUNTINGTON:                             \
 826                         rev = 'D';                                      \
 827                         break;                                          \
 828                                                                         \
 829                 case EFX_FAMILY_MEDFORD:                                \
 830                         rev = 'E';                                      \
 831                         break;                                          \
 832                                                                         \
 833                 case EFX_FAMILY_MEDFORD2:                               \
 834                         rev = 'F';                                      \
 835                         break;                                          \
 836                                                                         \
 837                 default:                                                \
 838                         rev = '?';                                      \
 839                         break;                                          \
 840                 }                                                       \
 841                                                                         \
 842                 EFSYS_ASSERT3S(rev, >=, min);                           \
 843                 EFSYS_ASSERT3S(rev, <=, max);                           \
 844                                                                         \
 845         _NOTE(CONSTANTCONDITION)                                        \
 846         } while (B_FALSE)
 847 #else
 848 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 849         _NOTE(CONSTANTCONDITION)                                        \
 850         } while (B_FALSE)
 851 #endif
 852
 853 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 854         do {                                                            \
 855                 EFX_CHECK_REG((_enp), (_reg));                          \
 856                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 857                     (_edp), (_lock));                                   \
 858                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 859                     uint32_t, _reg ## _OFST,                            \
 860                     uint32_t, (_edp)->ed_u32[0]);                       \
 861         _NOTE(CONSTANTCONDITION)                                        \
 862         } while (B_FALSE)
 863
 864 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 865         do {                                                            \
 866                 EFX_CHECK_REG((_enp), (_reg));                          \
 867                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 868                     uint32_t, _reg ## _OFST,                            \
 869                     uint32_t, (_edp)->ed_u32[0]);                       \
 870                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 871                     (_edp), (_lock));                                   \
 872         _NOTE(CONSTANTCONDITION)                                        \
 873         } while (B_FALSE)
 874
 875 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 876         do {                                                            \
 877                 EFX_CHECK_REG((_enp), (_reg));                          \
 878                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 879                     (_eqp));                                            \
 880                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 881                     uint32_t, _reg ## _OFST,                            \
 882                     uint32_t, (_eqp)->eq_u32[1],                        \
 883                     uint32_t, (_eqp)->eq_u32[0]);                       \
 884         _NOTE(CONSTANTCONDITION)                                        \
 885         } while (B_FALSE)
 886
 887 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 888         do {                                                            \
 889                 EFX_CHECK_REG((_enp), (_reg));                          \
 890                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 891                     uint32_t, _reg ## _OFST,                            \
 892                     uint32_t, (_eqp)->eq_u32[1],                        \
 893                     uint32_t, (_eqp)->eq_u32[0]);                       \
 894                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 895                     (_eqp));                                            \
 896         _NOTE(CONSTANTCONDITION)                                        \
 897         } while (B_FALSE)
 898
 899 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 900         do {                                                            \
 901                 EFX_CHECK_REG((_enp), (_reg));                          \
 902                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 903                     (_eop), B_TRUE);                                    \
 904                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 905                     uint32_t, _reg ## _OFST,                            \
 906                     uint32_t, (_eop)->eo_u32[3],                        \
 907                     uint32_t, (_eop)->eo_u32[2],                        \
 908                     uint32_t, (_eop)->eo_u32[1],                        \
 909                     uint32_t, (_eop)->eo_u32[0]);                       \
 910         _NOTE(CONSTANTCONDITION)                                        \
 911         } while (B_FALSE)
 912
 913 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 914         do {                                                            \
 915                 EFX_CHECK_REG((_enp), (_reg));                          \
 916                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 917                     uint32_t, _reg ## _OFST,                            \
 918                     uint32_t, (_eop)->eo_u32[3],                        \
 919                     uint32_t, (_eop)->eo_u32[2],                        \
 920                     uint32_t, (_eop)->eo_u32[1],                        \
 921                     uint32_t, (_eop)->eo_u32[0]);                       \
 922                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 923                     (_eop), B_TRUE);                                    \
 924         _NOTE(CONSTANTCONDITION)                                        \
 925         } while (B_FALSE)
 926
 927 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 928         do {                                                            \
 929                 EFX_CHECK_REG((_enp), (_reg));                          \
 930                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 931                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 932                     (_edp), (_lock));                                   \
 933                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 934                     uint32_t, (_index),                                 \
 935                     uint32_t, _reg ## _OFST,                            \
 936                     uint32_t, (_edp)->ed_u32[0]);                       \
 937         _NOTE(CONSTANTCONDITION)                                        \
 938         } while (B_FALSE)
 939
 940 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 941         do {                                                            \
 942                 EFX_CHECK_REG((_enp), (_reg));                          \
 943                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 944                     uint32_t, (_index),                                 \
 945                     uint32_t, _reg ## _OFST,                            \
 946                     uint32_t, (_edp)->ed_u32[0]);                       \
 947                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 948                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 949                     (_edp), (_lock));                                   \
 950         _NOTE(CONSTANTCONDITION)                                        \
 951         } while (B_FALSE)
 952
 953 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 954         do {                                                            \
 955                 EFX_CHECK_REG((_enp), (_reg));                          \
 956                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 957                     uint32_t, (_index),                                 \
 958                     uint32_t, _reg ## _OFST,                            \
 959                     uint32_t, (_edp)->ed_u32[0]);                       \
 960                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 961                     (_reg ## _OFST +                                    \
 962                     (2 * sizeof (efx_dword_t)) +                        \
 963                     ((_index) * _reg ## _STEP)),                        \
 964                     (_edp), (_lock));                                   \
 965         _NOTE(CONSTANTCONDITION)                                        \
 966         } while (B_FALSE)
 967
 968 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 969         do {                                                            \
 970                 EFX_CHECK_REG((_enp), (_reg));                          \
 971                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 972                     uint32_t, (_index),                                 \
 973                     uint32_t, _reg ## _OFST,                            \
 974                     uint32_t, (_edp)->ed_u32[0]);                       \
 975                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 976                     (_reg ## _OFST +                                    \
 977                     (3 * sizeof (efx_dword_t)) +                        \
 978                     ((_index) * _reg ## _STEP)),                        \
 979                     (_edp), (_lock));                                   \
 980         _NOTE(CONSTANTCONDITION)                                        \
 981         } while (B_FALSE)
 982
 983 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 984         do {                                                            \
 985                 EFX_CHECK_REG((_enp), (_reg));                          \
 986                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 987                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 988                     (_eqp));                                            \
 989                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 990                     uint32_t, (_index),                                 \
 991                     uint32_t, _reg ## _OFST,                            \
 992                     uint32_t, (_eqp)->eq_u32[1],                        \
 993                     uint32_t, (_eqp)->eq_u32[0]);                       \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 998         do {                                                            \
 999                 EFX_CHECK_REG((_enp), (_reg));                          \
1000                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1001                     uint32_t, (_index),                                 \
1002                     uint32_t, _reg ## _OFST,                            \
1003                     uint32_t, (_eqp)->eq_u32[1],                        \
1004                     uint32_t, (_eqp)->eq_u32[0]);                       \
1005                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1006                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1007                     (_eqp));                                            \
1008         _NOTE(CONSTANTCONDITION)                                        \
1009         } while (B_FALSE)
1010
1011 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1012         do {                                                            \
1013                 EFX_CHECK_REG((_enp), (_reg));                          \
1014                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1015                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1016                     (_eop), (_lock));                                   \
1017                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1018                     uint32_t, (_index),                                 \
1019                     uint32_t, _reg ## _OFST,                            \
1020                     uint32_t, (_eop)->eo_u32[3],                        \
1021                     uint32_t, (_eop)->eo_u32[2],                        \
1022                     uint32_t, (_eop)->eo_u32[1],                        \
1023                     uint32_t, (_eop)->eo_u32[0]);                       \
1024         _NOTE(CONSTANTCONDITION)                                        \
1025         } while (B_FALSE)
1026
1027 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1028         do {                                                            \
1029                 EFX_CHECK_REG((_enp), (_reg));                          \
1030                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1031                     uint32_t, (_index),                                 \
1032                     uint32_t, _reg ## _OFST,                            \
1033                     uint32_t, (_eop)->eo_u32[3],                        \
1034                     uint32_t, (_eop)->eo_u32[2],                        \
1035                     uint32_t, (_eop)->eo_u32[1],                        \
1036                     uint32_t, (_eop)->eo_u32[0]);                       \
1037                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1038                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1039                     (_eop), (_lock));                                   \
1040         _NOTE(CONSTANTCONDITION)                                        \
1041         } while (B_FALSE)
1042
1043 /*
1044  * Allow drivers to perform optimised 128-bit doorbell writes.
1045  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1046  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1047  * the need for locking in the host, and are the only ones known to be safe to
1048  * use 128-bites write with.
1049  */
1050 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1051         do {                                                            \
1052                 EFX_CHECK_REG((_enp), (_reg));                          \
1053                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1054                     const char *, #_reg,                                \
1055                     uint32_t, (_index),                                 \
1056                     uint32_t, _reg ## _OFST,                            \
1057                     uint32_t, (_eop)->eo_u32[3],                        \
1058                     uint32_t, (_eop)->eo_u32[2],                        \
1059                     uint32_t, (_eop)->eo_u32[1],                        \
1060                     uint32_t, (_eop)->eo_u32[0]);                       \
1061                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1062                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1063                     (_eop));                                            \
1064         _NOTE(CONSTANTCONDITION)                                        \
1065         } while (B_FALSE)
1066
1067 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1068         do {                                                            \
1069                 unsigned int _new = (_wptr);                            \
1070                 unsigned int _old = (_owptr);                           \
1071                                                                         \
1072                 if ((_new) >= (_old))                                   \
1073                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1074                             (_old) * sizeof (efx_desc_t),               \
1075                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1076                 else                                                    \
1077                         /*                                              \
1078                          * It is cheaper to sync entire map than sync   \
1079                          * two parts especially when offset/size are    \
1080                          * ignored and entire map is synced in any case.\
1081                          */                                             \
1082                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1083                             0,                                          \
1084                             (_entries) * sizeof (efx_desc_t));          \
1085         _NOTE(CONSTANTCONDITION)                                        \
1086         } while (B_FALSE)
1087
1088 extern  __checkReturn   efx_rc_t
1089 efx_mac_select(
1090         __in            efx_nic_t *enp);
1091
1092 extern  void
1093 efx_mac_multicast_hash_compute(
1094         __in_ecount(6*count)            uint8_t const *addrs,
1095         __in                            int count,
1096         __out                           efx_oword_t *hash_low,
1097         __out                           efx_oword_t *hash_high);
1098
1099 extern  __checkReturn   efx_rc_t
1100 efx_phy_probe(
1101         __in            efx_nic_t *enp);
1102
1103 extern                  void
1104 efx_phy_unprobe(
1105         __in            efx_nic_t *enp);
1106
1107 #if EFSYS_OPT_VPD
1108
1109 /* VPD utility functions */
1110
1111 extern  __checkReturn           efx_rc_t
1112 efx_vpd_hunk_length(
1113         __in_bcount(size)       caddr_t data,
1114         __in                    size_t size,
1115         __out                   size_t *lengthp);
1116
1117 extern  __checkReturn           efx_rc_t
1118 efx_vpd_hunk_verify(
1119         __in_bcount(size)       caddr_t data,
1120         __in                    size_t size,
1121         __out_opt               boolean_t *cksummedp);
1122
1123 extern  __checkReturn           efx_rc_t
1124 efx_vpd_hunk_reinit(
1125         __in_bcount(size)       caddr_t data,
1126         __in                    size_t size,
1127         __in                    boolean_t wantpid);
1128
1129 extern  __checkReturn           efx_rc_t
1130 efx_vpd_hunk_get(
1131         __in_bcount(size)       caddr_t data,
1132         __in                    size_t size,
1133         __in                    efx_vpd_tag_t tag,
1134         __in                    efx_vpd_keyword_t keyword,
1135         __out                   unsigned int *payloadp,
1136         __out                   uint8_t *paylenp);
1137
1138 extern  __checkReturn                   efx_rc_t
1139 efx_vpd_hunk_next(
1140         __in_bcount(size)               caddr_t data,
1141         __in                            size_t size,
1142         __out                           efx_vpd_tag_t *tagp,
1143         __out                           efx_vpd_keyword_t *keyword,
1144         __out_opt                       unsigned int *payloadp,
1145         __out_opt                       uint8_t *paylenp,
1146         __inout                         unsigned int *contp);
1147
1148 extern  __checkReturn           efx_rc_t
1149 efx_vpd_hunk_set(
1150         __in_bcount(size)       caddr_t data,
1151         __in                    size_t size,
1152         __in                    efx_vpd_value_t *evvp);
1153
1154 #endif  /* EFSYS_OPT_VPD */
1155
1156 #if EFSYS_OPT_MCDI
1157
1158 extern  __checkReturn           efx_rc_t
1159 efx_mcdi_set_workaround(
1160         __in                    efx_nic_t *enp,
1161         __in                    uint32_t type,
1162         __in                    boolean_t enabled,
1163         __out_opt               uint32_t *flagsp);
1164
1165 extern  __checkReturn           efx_rc_t
1166 efx_mcdi_get_workarounds(
1167         __in                    efx_nic_t *enp,
1168         __out_opt               uint32_t *implementedp,
1169         __out_opt               uint32_t *enabledp);
1170
1171 #endif /* EFSYS_OPT_MCDI */
1172
1173 #if EFSYS_OPT_MAC_STATS
1174
1175 /*
1176  * Closed range of stats (i.e. the first and the last are included).
1177  * The last must be greater or equal (if the range is one item only) to
1178  * the first.
1179  */
1180 struct efx_mac_stats_range {
1181         efx_mac_stat_t          first;
1182         efx_mac_stat_t          last;
1183 };
1184
1185 extern                                  efx_rc_t
1186 efx_mac_stats_mask_add_ranges(
1187         __inout_bcount(mask_size)       uint32_t *maskp,
1188         __in                            size_t mask_size,
1189         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1190         __in                            unsigned int rng_count);
1191
1192 #endif  /* EFSYS_OPT_MAC_STATS */
1193
1194 #ifdef  __cplusplus
1195 }
1196 #endif
1197
1198 #endif  /* _SYS_EFX_IMPL_H */