2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
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37 static __checkReturn efx_rc_t
40 __in efx_intr_type_t type,
41 __in efsys_mem_t *esmp);
52 siena_intr_disable_unlocked(
55 static __checkReturn efx_rc_t
58 __in unsigned int level);
65 siena_intr_status_line(
67 __out boolean_t *fatalp,
68 __out uint32_t *qmaskp);
71 siena_intr_status_message(
73 __in unsigned int message,
74 __out boolean_t *fatalp);
80 static __checkReturn boolean_t
81 siena_intr_check_fatal(
85 #endif /* EFSYS_OPT_SIENA */
89 static const efx_intr_ops_t __efx_intr_siena_ops = {
90 siena_intr_init, /* eio_init */
91 siena_intr_enable, /* eio_enable */
92 siena_intr_disable, /* eio_disable */
93 siena_intr_disable_unlocked, /* eio_disable_unlocked */
94 siena_intr_trigger, /* eio_trigger */
95 siena_intr_status_line, /* eio_status_line */
96 siena_intr_status_message, /* eio_status_message */
97 siena_intr_fatal, /* eio_fatal */
98 siena_intr_fini, /* eio_fini */
100 #endif /* EFSYS_OPT_SIENA */
102 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
103 static const efx_intr_ops_t __efx_intr_ef10_ops = {
104 ef10_intr_init, /* eio_init */
105 ef10_intr_enable, /* eio_enable */
106 ef10_intr_disable, /* eio_disable */
107 ef10_intr_disable_unlocked, /* eio_disable_unlocked */
108 ef10_intr_trigger, /* eio_trigger */
109 ef10_intr_status_line, /* eio_status_line */
110 ef10_intr_status_message, /* eio_status_message */
111 ef10_intr_fatal, /* eio_fatal */
112 ef10_intr_fini, /* eio_fini */
114 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
116 __checkReturn efx_rc_t
119 __in efx_intr_type_t type,
120 __in efsys_mem_t *esmp)
122 efx_intr_t *eip = &(enp->en_intr);
123 const efx_intr_ops_t *eiop;
126 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
127 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
129 if (enp->en_mod_flags & EFX_MOD_INTR) {
138 enp->en_mod_flags |= EFX_MOD_INTR;
140 switch (enp->en_family) {
142 case EFX_FAMILY_SIENA:
143 eiop = &__efx_intr_siena_ops;
145 #endif /* EFSYS_OPT_SIENA */
147 #if EFSYS_OPT_HUNTINGTON
148 case EFX_FAMILY_HUNTINGTON:
149 eiop = &__efx_intr_ef10_ops;
151 #endif /* EFSYS_OPT_HUNTINGTON */
154 EFSYS_ASSERT(B_FALSE);
159 if ((rc = eiop->eio_init(enp, type, esmp)) != 0)
171 EFSYS_PROBE1(fail1, efx_rc_t, rc);
180 efx_intr_t *eip = &(enp->en_intr);
181 const efx_intr_ops_t *eiop = eip->ei_eiop;
183 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
184 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
185 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
189 enp->en_mod_flags &= ~EFX_MOD_INTR;
196 efx_intr_t *eip = &(enp->en_intr);
197 const efx_intr_ops_t *eiop = eip->ei_eiop;
199 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
200 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
202 eiop->eio_enable(enp);
209 efx_intr_t *eip = &(enp->en_intr);
210 const efx_intr_ops_t *eiop = eip->ei_eiop;
212 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
213 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
215 eiop->eio_disable(enp);
219 efx_intr_disable_unlocked(
222 efx_intr_t *eip = &(enp->en_intr);
223 const efx_intr_ops_t *eiop = eip->ei_eiop;
225 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
226 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
228 eiop->eio_disable_unlocked(enp);
232 __checkReturn efx_rc_t
235 __in unsigned int level)
237 efx_intr_t *eip = &(enp->en_intr);
238 const efx_intr_ops_t *eiop = eip->ei_eiop;
240 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
241 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
243 return (eiop->eio_trigger(enp, level));
247 efx_intr_status_line(
249 __out boolean_t *fatalp,
250 __out uint32_t *qmaskp)
252 efx_intr_t *eip = &(enp->en_intr);
253 const efx_intr_ops_t *eiop = eip->ei_eiop;
255 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
256 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
258 eiop->eio_status_line(enp, fatalp, qmaskp);
262 efx_intr_status_message(
264 __in unsigned int message,
265 __out boolean_t *fatalp)
267 efx_intr_t *eip = &(enp->en_intr);
268 const efx_intr_ops_t *eiop = eip->ei_eiop;
270 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
271 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
273 eiop->eio_status_message(enp, message, fatalp);
280 efx_intr_t *eip = &(enp->en_intr);
281 const efx_intr_ops_t *eiop = eip->ei_eiop;
283 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
284 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
286 eiop->eio_fatal(enp);
290 /* ************************************************************************* */
291 /* ************************************************************************* */
292 /* ************************************************************************* */
296 static __checkReturn efx_rc_t
299 __in efx_intr_type_t type,
300 __in efsys_mem_t *esmp)
302 efx_intr_t *eip = &(enp->en_intr);
306 * bug17213 workaround.
308 * Under legacy interrupts, don't share a level between fatal
309 * interrupts and event queue interrupts. Under MSI-X, they
310 * must share, or we won't get an interrupt.
312 if (enp->en_family == EFX_FAMILY_SIENA &&
313 eip->ei_type == EFX_INTR_LINE)
314 eip->ei_level = 0x1f;
318 /* Enable all the genuinely fatal interrupts */
319 EFX_SET_OWORD(oword);
320 EFX_SET_OWORD_FIELD(oword, FRF_AZ_ILL_ADR_INT_KER_EN, 0);
321 EFX_SET_OWORD_FIELD(oword, FRF_AZ_RBUF_OWN_INT_KER_EN, 0);
322 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TBUF_OWN_INT_KER_EN, 0);
323 if (enp->en_family >= EFX_FAMILY_SIENA)
324 EFX_SET_OWORD_FIELD(oword, FRF_CZ_SRAM_PERR_INT_P_KER_EN, 0);
325 EFX_BAR_WRITEO(enp, FR_AZ_FATAL_INTR_REG_KER, &oword);
327 /* Set up the interrupt address register */
328 EFX_POPULATE_OWORD_3(oword,
329 FRF_AZ_NORM_INT_VEC_DIS_KER, (type == EFX_INTR_MESSAGE) ? 1 : 0,
330 FRF_AZ_INT_ADR_KER_DW0, EFSYS_MEM_ADDR(esmp) & 0xffffffff,
331 FRF_AZ_INT_ADR_KER_DW1, EFSYS_MEM_ADDR(esmp) >> 32);
332 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
341 efx_intr_t *eip = &(enp->en_intr);
344 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
346 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
347 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 1);
348 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
357 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
358 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
359 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
365 siena_intr_disable_unlocked(
370 EFSYS_BAR_READO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
372 EFX_SET_OWORD_FIELD(oword, FRF_AZ_DRV_INT_EN_KER, 0);
373 EFSYS_BAR_WRITEO(enp->en_esbp, FR_AZ_INT_EN_REG_KER_OFST,
377 static __checkReturn efx_rc_t
380 __in unsigned int level)
382 efx_intr_t *eip = &(enp->en_intr);
388 /* bug16757: No event queues can be initialized */
389 EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
391 if (level >= EFX_NINTR_SIENA) {
396 if (level > EFX_MASK32(FRF_AZ_KER_INT_LEVE_SEL))
397 return (ENOTSUP); /* avoid EFSYS_PROBE() */
401 /* Trigger a test interrupt */
402 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
403 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, sel);
404 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER, 1);
405 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
408 * Wait up to 100ms for the interrupt to be raised before restoring
409 * KER_INT_LEVE_SEL. Ignore a failure to raise (the caller will
410 * observe this soon enough anyway), but always reset KER_INT_LEVE_SEL
414 EFSYS_SPIN(100); /* 100us */
416 EFX_BAR_READO(enp, FR_AZ_INT_EN_REG_KER, &oword);
417 } while (EFX_OWORD_FIELD(oword, FRF_AZ_KER_INT_KER) && ++count < 1000);
419 EFX_SET_OWORD_FIELD(oword, FRF_AZ_KER_INT_LEVE_SEL, eip->ei_level);
420 EFX_BAR_WRITEO(enp, FR_AZ_INT_EN_REG_KER, &oword);
425 EFSYS_PROBE1(fail1, efx_rc_t, rc);
430 static __checkReturn boolean_t
431 siena_intr_check_fatal(
434 efx_intr_t *eip = &(enp->en_intr);
435 efsys_mem_t *esmp = eip->ei_esmp;
438 /* Read the syndrome */
439 EFSYS_MEM_READO(esmp, 0, &oword);
441 if (EFX_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT) != 0) {
444 /* Clear the fatal interrupt condition */
445 EFX_SET_OWORD_FIELD(oword, FSF_AZ_NET_IVEC_FATAL_INT, 0);
446 EFSYS_MEM_WRITEO(esmp, 0, &oword);
455 siena_intr_status_line(
457 __out boolean_t *fatalp,
458 __out uint32_t *qmaskp)
460 efx_intr_t *eip = &(enp->en_intr);
463 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
464 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
467 * Read the queue mask and implicitly acknowledge the
470 EFX_BAR_READD(enp, FR_BZ_INT_ISR0_REG, &dword, B_FALSE);
471 *qmaskp = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
473 EFSYS_PROBE1(qmask, uint32_t, *qmaskp);
475 if (*qmaskp & (1U << eip->ei_level))
476 *fatalp = siena_intr_check_fatal(enp);
482 siena_intr_status_message(
484 __in unsigned int message,
485 __out boolean_t *fatalp)
487 efx_intr_t *eip = &(enp->en_intr);
489 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
490 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
492 if (message == eip->ei_level)
493 *fatalp = siena_intr_check_fatal(enp);
503 #if EFSYS_OPT_DECODE_INTR_FATAL
507 EFX_BAR_READO(enp, FR_AZ_FATAL_INTR_REG_KER, &fatal);
508 EFX_ZERO_OWORD(mem_per);
510 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0 ||
511 EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
512 EFX_BAR_READO(enp, FR_AZ_MEM_STAT_REG, &mem_per);
514 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRAM_OOB_INT_KER) != 0)
515 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_OOB, 0, 0);
517 if (EFX_OWORD_FIELD(fatal, FRF_AZ_BUFID_DC_OOB_INT_KER) != 0)
518 EFSYS_ERR(enp->en_esip, EFX_ERR_BUFID_DC_OOB, 0, 0);
520 if (EFX_OWORD_FIELD(fatal, FRF_AZ_MEM_PERR_INT_KER) != 0)
521 EFSYS_ERR(enp->en_esip, EFX_ERR_MEM_PERR,
522 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
523 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
525 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RBUF_OWN_INT_KER) != 0)
526 EFSYS_ERR(enp->en_esip, EFX_ERR_RBUF_OWN, 0, 0);
528 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TBUF_OWN_INT_KER) != 0)
529 EFSYS_ERR(enp->en_esip, EFX_ERR_TBUF_OWN, 0, 0);
531 if (EFX_OWORD_FIELD(fatal, FRF_AZ_RDESCQ_OWN_INT_KER) != 0)
532 EFSYS_ERR(enp->en_esip, EFX_ERR_RDESQ_OWN, 0, 0);
534 if (EFX_OWORD_FIELD(fatal, FRF_AZ_TDESCQ_OWN_INT_KER) != 0)
535 EFSYS_ERR(enp->en_esip, EFX_ERR_TDESQ_OWN, 0, 0);
537 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVQ_OWN_INT_KER) != 0)
538 EFSYS_ERR(enp->en_esip, EFX_ERR_EVQ_OWN, 0, 0);
540 if (EFX_OWORD_FIELD(fatal, FRF_AZ_EVF_OFLO_INT_KER) != 0)
541 EFSYS_ERR(enp->en_esip, EFX_ERR_EVFF_OFLO, 0, 0);
543 if (EFX_OWORD_FIELD(fatal, FRF_AZ_ILL_ADR_INT_KER) != 0)
544 EFSYS_ERR(enp->en_esip, EFX_ERR_ILL_ADDR, 0, 0);
546 if (EFX_OWORD_FIELD(fatal, FRF_AZ_SRM_PERR_INT_KER) != 0)
547 EFSYS_ERR(enp->en_esip, EFX_ERR_SRAM_PERR,
548 EFX_OWORD_FIELD(mem_per, EFX_DWORD_0),
549 EFX_OWORD_FIELD(mem_per, EFX_DWORD_1));
561 /* Clear the interrupt address register */
562 EFX_ZERO_OWORD(oword);
563 EFX_BAR_WRITEO(enp, FR_AZ_INT_ADR_REG_KER, &oword);
566 #endif /* EFSYS_OPT_SIENA */