drivers/net/sfc/base/efx_rx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2007-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_SIENA
  12
  13 static  __checkReturn   efx_rc_t
  14 siena_rx_init(
  15         __in            efx_nic_t *enp);
  16
  17 static                  void
  18 siena_rx_fini(
  19         __in            efx_nic_t *enp);
  20
  21 #if EFSYS_OPT_RX_SCATTER
  22 static  __checkReturn   efx_rc_t
  23 siena_rx_scatter_enable(
  24         __in            efx_nic_t *enp,
  25         __in            unsigned int buf_size);
  26 #endif /* EFSYS_OPT_RX_SCATTER */
  27
  28 #if EFSYS_OPT_RX_SCALE
  29 static  __checkReturn   efx_rc_t
  30 siena_rx_scale_mode_set(
  31         __in            efx_nic_t *enp,
  32         __in            uint32_t rss_context,
  33         __in            efx_rx_hash_alg_t alg,
  34         __in            efx_rx_hash_type_t type,
  35         __in            boolean_t insert);
  36
  37 static  __checkReturn   efx_rc_t
  38 siena_rx_scale_key_set(
  39         __in            efx_nic_t *enp,
  40         __in            uint32_t rss_context,
  41         __in_ecount(n)  uint8_t *key,
  42         __in            size_t n);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_rx_scale_tbl_set(
  46         __in            efx_nic_t *enp,
  47         __in            uint32_t rss_context,
  48         __in_ecount(n)  unsigned int *table,
  49         __in            size_t n);
  50
  51 static  __checkReturn   uint32_t
  52 siena_rx_prefix_hash(
  53         __in            efx_nic_t *enp,
  54         __in            efx_rx_hash_alg_t func,
  55         __in            uint8_t *buffer);
  56
  57 #endif /* EFSYS_OPT_RX_SCALE */
  58
  59 static  __checkReturn   efx_rc_t
  60 siena_rx_prefix_pktlen(
  61         __in            efx_nic_t *enp,
  62         __in            uint8_t *buffer,
  63         __out           uint16_t *lengthp);
  64
  65 static                          void
  66 siena_rx_qpost(
  67         __in                    efx_rxq_t *erp,
  68         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
  69         __in                    size_t size,
  70         __in                    unsigned int ndescs,
  71         __in                    unsigned int completed,
  72         __in                    unsigned int added);
  73
  74 static                  void
  75 siena_rx_qpush(
  76         __in            efx_rxq_t *erp,
  77         __in            unsigned int added,
  78         __inout         unsigned int *pushedp);
  79
  80 #if EFSYS_OPT_RX_PACKED_STREAM
  81 static          void
  82 siena_rx_qpush_ps_credits(
  83         __in            efx_rxq_t *erp);
  84
  85 static  __checkReturn   uint8_t *
  86 siena_rx_qps_packet_info(
  87         __in            efx_rxq_t *erp,
  88         __in            uint8_t *buffer,
  89         __in            uint32_t buffer_length,
  90         __in            uint32_t current_offset,
  91         __out           uint16_t *lengthp,
  92         __out           uint32_t *next_offsetp,
  93         __out           uint32_t *timestamp);
  94 #endif
  95
  96 static  __checkReturn   efx_rc_t
  97 siena_rx_qflush(
  98         __in            efx_rxq_t *erp);
  99
 100 static                  void
 101 siena_rx_qenable(
 102         __in            efx_rxq_t *erp);
 103
 104 static  __checkReturn   efx_rc_t
 105 siena_rx_qcreate(
 106         __in            efx_nic_t *enp,
 107         __in            unsigned int index,
 108         __in            unsigned int label,
 109         __in            efx_rxq_type_t type,
 110         __in_opt        const efx_rxq_type_data_t *type_data,
 111         __in            efsys_mem_t *esmp,
 112         __in            size_t ndescs,
 113         __in            uint32_t id,
 114         __in            unsigned int flags,
 115         __in            efx_evq_t *eep,
 116         __in            efx_rxq_t *erp);
 117
 118 static                  void
 119 siena_rx_qdestroy(
 120         __in            efx_rxq_t *erp);
 121
 122 #endif /* EFSYS_OPT_SIENA */
 123
 124
 125 #if EFSYS_OPT_SIENA
 126 static const efx_rx_ops_t __efx_rx_siena_ops = {
 127         siena_rx_init,                          /* erxo_init */
 128         siena_rx_fini,                          /* erxo_fini */
 129 #if EFSYS_OPT_RX_SCATTER
 130         siena_rx_scatter_enable,                /* erxo_scatter_enable */
 131 #endif
 132 #if EFSYS_OPT_RX_SCALE
 133         NULL,                                   /* erxo_scale_context_alloc */
 134         NULL,                                   /* erxo_scale_context_free */
 135         siena_rx_scale_mode_set,                /* erxo_scale_mode_set */
 136         siena_rx_scale_key_set,                 /* erxo_scale_key_set */
 137         siena_rx_scale_tbl_set,                 /* erxo_scale_tbl_set */
 138         siena_rx_prefix_hash,                   /* erxo_prefix_hash */
 139 #endif
 140         siena_rx_prefix_pktlen,                 /* erxo_prefix_pktlen */
 141         siena_rx_qpost,                         /* erxo_qpost */
 142         siena_rx_qpush,                         /* erxo_qpush */
 143 #if EFSYS_OPT_RX_PACKED_STREAM
 144         siena_rx_qpush_ps_credits,              /* erxo_qpush_ps_credits */
 145         siena_rx_qps_packet_info,               /* erxo_qps_packet_info */
 146 #endif
 147         siena_rx_qflush,                        /* erxo_qflush */
 148         siena_rx_qenable,                       /* erxo_qenable */
 149         siena_rx_qcreate,                       /* erxo_qcreate */
 150         siena_rx_qdestroy,                      /* erxo_qdestroy */
 151 };
 152 #endif  /* EFSYS_OPT_SIENA */
 153
 154 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2
 155 static const efx_rx_ops_t __efx_rx_ef10_ops = {
 156         ef10_rx_init,                           /* erxo_init */
 157         ef10_rx_fini,                           /* erxo_fini */
 158 #if EFSYS_OPT_RX_SCATTER
 159         ef10_rx_scatter_enable,                 /* erxo_scatter_enable */
 160 #endif
 161 #if EFSYS_OPT_RX_SCALE
 162         ef10_rx_scale_context_alloc,            /* erxo_scale_context_alloc */
 163         ef10_rx_scale_context_free,             /* erxo_scale_context_free */
 164         ef10_rx_scale_mode_set,                 /* erxo_scale_mode_set */
 165         ef10_rx_scale_key_set,                  /* erxo_scale_key_set */
 166         ef10_rx_scale_tbl_set,                  /* erxo_scale_tbl_set */
 167         ef10_rx_prefix_hash,                    /* erxo_prefix_hash */
 168 #endif
 169         ef10_rx_prefix_pktlen,                  /* erxo_prefix_pktlen */
 170         ef10_rx_qpost,                          /* erxo_qpost */
 171         ef10_rx_qpush,                          /* erxo_qpush */
 172 #if EFSYS_OPT_RX_PACKED_STREAM
 173         ef10_rx_qpush_ps_credits,               /* erxo_qpush_ps_credits */
 174         ef10_rx_qps_packet_info,                /* erxo_qps_packet_info */
 175 #endif
 176         ef10_rx_qflush,                         /* erxo_qflush */
 177         ef10_rx_qenable,                        /* erxo_qenable */
 178         ef10_rx_qcreate,                        /* erxo_qcreate */
 179         ef10_rx_qdestroy,                       /* erxo_qdestroy */
 180 };
 181 #endif  /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD || EFSYS_OPT_MEDFORD2 */
 182
 183
 184         __checkReturn   efx_rc_t
 185 efx_rx_init(
 186         __inout         efx_nic_t *enp)
 187 {
 188         const efx_rx_ops_t *erxop;
 189         efx_rc_t rc;
 190
 191         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 192         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 193
 194         if (!(enp->en_mod_flags & EFX_MOD_EV)) {
 195                 rc = EINVAL;
 196                 goto fail1;
 197         }
 198
 199         if (enp->en_mod_flags & EFX_MOD_RX) {
 200                 rc = EINVAL;
 201                 goto fail2;
 202         }
 203
 204         switch (enp->en_family) {
 205 #if EFSYS_OPT_SIENA
 206         case EFX_FAMILY_SIENA:
 207                 erxop = &__efx_rx_siena_ops;
 208                 break;
 209 #endif /* EFSYS_OPT_SIENA */
 210
 211 #if EFSYS_OPT_HUNTINGTON
 212         case EFX_FAMILY_HUNTINGTON:
 213                 erxop = &__efx_rx_ef10_ops;
 214                 break;
 215 #endif /* EFSYS_OPT_HUNTINGTON */
 216
 217 #if EFSYS_OPT_MEDFORD
 218         case EFX_FAMILY_MEDFORD:
 219                 erxop = &__efx_rx_ef10_ops;
 220                 break;
 221 #endif /* EFSYS_OPT_MEDFORD */
 222
 223 #if EFSYS_OPT_MEDFORD2
 224         case EFX_FAMILY_MEDFORD2:
 225                 erxop = &__efx_rx_ef10_ops;
 226                 break;
 227 #endif /* EFSYS_OPT_MEDFORD2 */
 228
 229         default:
 230                 EFSYS_ASSERT(0);
 231                 rc = ENOTSUP;
 232                 goto fail3;
 233         }
 234
 235         if ((rc = erxop->erxo_init(enp)) != 0)
 236                 goto fail4;
 237
 238         enp->en_erxop = erxop;
 239         enp->en_mod_flags |= EFX_MOD_RX;
 240         return (0);
 241
 242 fail4:
 243         EFSYS_PROBE(fail4);
 244 fail3:
 245         EFSYS_PROBE(fail3);
 246 fail2:
 247         EFSYS_PROBE(fail2);
 248 fail1:
 249         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 250
 251         enp->en_erxop = NULL;
 252         enp->en_mod_flags &= ~EFX_MOD_RX;
 253         return (rc);
 254 }
 255
 256                         void
 257 efx_rx_fini(
 258         __in            efx_nic_t *enp)
 259 {
 260         const efx_rx_ops_t *erxop = enp->en_erxop;
 261
 262         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 263         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 264         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 265         EFSYS_ASSERT3U(enp->en_rx_qcount, ==, 0);
 266
 267         erxop->erxo_fini(enp);
 268
 269         enp->en_erxop = NULL;
 270         enp->en_mod_flags &= ~EFX_MOD_RX;
 271 }
 272
 273 #if EFSYS_OPT_RX_SCATTER
 274         __checkReturn   efx_rc_t
 275 efx_rx_scatter_enable(
 276         __in            efx_nic_t *enp,
 277         __in            unsigned int buf_size)
 278 {
 279         const efx_rx_ops_t *erxop = enp->en_erxop;
 280         efx_rc_t rc;
 281
 282         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 283         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 284
 285         if ((rc = erxop->erxo_scatter_enable(enp, buf_size)) != 0)
 286                 goto fail1;
 287
 288         return (0);
 289
 290 fail1:
 291         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 292         return (rc);
 293 }
 294 #endif  /* EFSYS_OPT_RX_SCATTER */
 295
 296 #if EFSYS_OPT_RX_SCALE
 297         __checkReturn                           efx_rc_t
 298 efx_rx_scale_hash_flags_get(
 299         __in                                    efx_nic_t *enp,
 300         __in                                    efx_rx_hash_alg_t hash_alg,
 301         __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
 302         __in                                    unsigned int max_nflags,
 303         __out                                   unsigned int *nflagsp)
 304 {
 305         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 306         unsigned int nflags = 0;
 307         efx_rc_t rc;
 308
 309         if (flagsp == NULL || nflagsp == NULL) {
 310                 rc = EINVAL;
 311                 goto fail1;
 312         }
 313
 314         if ((encp->enc_rx_scale_hash_alg_mask & (1U << hash_alg)) == 0) {
 315                 nflags = 0;
 316                 goto done;
 317         }
 318
 319         /* Helper to add flags word to flags array without buffer overflow */
 320 #define INSERT_FLAGS(_flags)                    \
 321         do {                                    \
 322                 if (nflags >= max_nflags) {     \
 323                         rc = E2BIG;             \
 324                         goto fail2;             \
 325                 }                               \
 326                 *(flagsp + nflags) = (_flags);  \
 327                 nflags++;                       \
 328                                                 \
 329                 _NOTE(CONSTANTCONDITION)        \
 330         } while (B_FALSE)
 331
 332         if (encp->enc_rx_scale_l4_hash_supported != B_FALSE) {
 333                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 4TUPLE));
 334                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 4TUPLE));
 335         }
 336
 337         if ((encp->enc_rx_scale_l4_hash_supported != B_FALSE) &&
 338             (encp->enc_rx_scale_additional_modes_supported != B_FALSE)) {
 339                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_DST));
 340                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE_SRC));
 341
 342                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_DST));
 343                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE_SRC));
 344
 345                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 4TUPLE));
 346                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_DST));
 347                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE_SRC));
 348
 349                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 4TUPLE));
 350                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_DST));
 351                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE_SRC));
 352         }
 353
 354         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 2TUPLE));
 355         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 2TUPLE));
 356
 357         INSERT_FLAGS(EFX_RX_HASH(IPV4, 2TUPLE));
 358         INSERT_FLAGS(EFX_RX_HASH(IPV6, 2TUPLE));
 359
 360         if (encp->enc_rx_scale_additional_modes_supported != B_FALSE) {
 361                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_DST));
 362                 INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, 1TUPLE_SRC));
 363
 364                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_DST));
 365                 INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, 1TUPLE_SRC));
 366
 367                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 2TUPLE));
 368                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_DST));
 369                 INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, 1TUPLE_SRC));
 370
 371                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 2TUPLE));
 372                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_DST));
 373                 INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, 1TUPLE_SRC));
 374
 375                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_DST));
 376                 INSERT_FLAGS(EFX_RX_HASH(IPV4, 1TUPLE_SRC));
 377
 378                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_DST));
 379                 INSERT_FLAGS(EFX_RX_HASH(IPV6, 1TUPLE_SRC));
 380         }
 381
 382         INSERT_FLAGS(EFX_RX_HASH(IPV4_TCP, DISABLE));
 383         INSERT_FLAGS(EFX_RX_HASH(IPV6_TCP, DISABLE));
 384
 385         INSERT_FLAGS(EFX_RX_HASH(IPV4_UDP, DISABLE));
 386         INSERT_FLAGS(EFX_RX_HASH(IPV6_UDP, DISABLE));
 387
 388         INSERT_FLAGS(EFX_RX_HASH(IPV4, DISABLE));
 389         INSERT_FLAGS(EFX_RX_HASH(IPV6, DISABLE));
 390
 391 #undef INSERT_FLAGS
 392
 393 done:
 394         *nflagsp = nflags;
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401
 402         return (rc);
 403 }
 404
 405         __checkReturn   efx_rc_t
 406 efx_rx_hash_default_support_get(
 407         __in            efx_nic_t *enp,
 408         __out           efx_rx_hash_support_t *supportp)
 409 {
 410         efx_rc_t rc;
 411
 412         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 413         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 414
 415         if (supportp == NULL) {
 416                 rc = EINVAL;
 417                 goto fail1;
 418         }
 419
 420         /*
 421          * Report the hashing support the client gets by default if it
 422          * does not allocate an RSS context itself.
 423          */
 424         *supportp = enp->en_hash_support;
 425
 426         return (0);
 427
 428 fail1:
 429         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 430
 431         return (rc);
 432 }
 433
 434         __checkReturn   efx_rc_t
 435 efx_rx_scale_default_support_get(
 436         __in            efx_nic_t *enp,
 437         __out           efx_rx_scale_context_type_t *typep)
 438 {
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 443
 444         if (typep == NULL) {
 445                 rc = EINVAL;
 446                 goto fail1;
 447         }
 448
 449         /*
 450          * Report the RSS support the client gets by default if it
 451          * does not allocate an RSS context itself.
 452          */
 453         *typep = enp->en_rss_context_type;
 454
 455         return (0);
 456
 457 fail1:
 458         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 459
 460         return (rc);
 461 }
 462 #endif  /* EFSYS_OPT_RX_SCALE */
 463
 464 #if EFSYS_OPT_RX_SCALE
 465         __checkReturn   efx_rc_t
 466 efx_rx_scale_context_alloc(
 467         __in            efx_nic_t *enp,
 468         __in            efx_rx_scale_context_type_t type,
 469         __in            uint32_t num_queues,
 470         __out           uint32_t *rss_contextp)
 471 {
 472         const efx_rx_ops_t *erxop = enp->en_erxop;
 473         efx_rc_t rc;
 474
 475         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 476         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 477
 478         if (erxop->erxo_scale_context_alloc == NULL) {
 479                 rc = ENOTSUP;
 480                 goto fail1;
 481         }
 482         if ((rc = erxop->erxo_scale_context_alloc(enp, type,
 483                             num_queues, rss_contextp)) != 0) {
 484                 goto fail2;
 485         }
 486
 487         return (0);
 488
 489 fail2:
 490         EFSYS_PROBE(fail2);
 491 fail1:
 492         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 493         return (rc);
 494 }
 495 #endif  /* EFSYS_OPT_RX_SCALE */
 496
 497 #if EFSYS_OPT_RX_SCALE
 498         __checkReturn   efx_rc_t
 499 efx_rx_scale_context_free(
 500         __in            efx_nic_t *enp,
 501         __in            uint32_t rss_context)
 502 {
 503         const efx_rx_ops_t *erxop = enp->en_erxop;
 504         efx_rc_t rc;
 505
 506         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 507         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 508
 509         if (erxop->erxo_scale_context_free == NULL) {
 510                 rc = ENOTSUP;
 511                 goto fail1;
 512         }
 513         if ((rc = erxop->erxo_scale_context_free(enp, rss_context)) != 0)
 514                 goto fail2;
 515
 516         return (0);
 517
 518 fail2:
 519         EFSYS_PROBE(fail2);
 520 fail1:
 521         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 522         return (rc);
 523 }
 524 #endif  /* EFSYS_OPT_RX_SCALE */
 525
 526 #if EFSYS_OPT_RX_SCALE
 527         __checkReturn   efx_rc_t
 528 efx_rx_scale_mode_set(
 529         __in            efx_nic_t *enp,
 530         __in            uint32_t rss_context,
 531         __in            efx_rx_hash_alg_t alg,
 532         __in            efx_rx_hash_type_t type,
 533         __in            boolean_t insert)
 534 {
 535         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 536         const efx_rx_ops_t *erxop = enp->en_erxop;
 537         efx_rx_hash_type_t type_check;
 538         unsigned int i;
 539         efx_rc_t rc;
 540
 541         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 542         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 543
 544         /*
 545          * Legacy flags and modern bits cannot be
 546          * used at the same time in the hash type.
 547          */
 548         if ((type & EFX_RX_HASH_LEGACY_MASK) &&
 549             (type & ~EFX_RX_HASH_LEGACY_MASK)) {
 550                 rc = EINVAL;
 551                 goto fail1;
 552         }
 553
 554         /*
 555          * If RSS hash type is represented by additional bits
 556          * in the value, the latter need to be verified since
 557          * not all bit combinations are valid RSS modes. Also,
 558          * depending on the firmware, some valid combinations
 559          * may be unsupported. Discern additional bits in the
 560          * type value and try to recognise valid combinations.
 561          * If some bits remain unrecognised, report the error.
 562          */
 563         type_check = type & ~EFX_RX_HASH_LEGACY_MASK;
 564         if (type_check != 0) {
 565                 unsigned int type_flags[EFX_RX_HASH_NFLAGS];
 566                 unsigned int type_nflags;
 567
 568                 rc = efx_rx_scale_hash_flags_get(enp, alg, type_flags,
 569                                     EFX_ARRAY_SIZE(type_flags), &type_nflags);
 570                 if (rc != 0)
 571                         goto fail2;
 572
 573                 for (i = 0; i < type_nflags; ++i) {
 574                         if ((type_check & type_flags[i]) == type_flags[i])
 575                                 type_check &= ~(type_flags[i]);
 576                 }
 577
 578                 if (type_check != 0) {
 579                         rc = EINVAL;
 580                         goto fail3;
 581                 }
 582         }
 583
 584         /*
 585          * Translate EFX_RX_HASH() flags to their legacy counterparts
 586          * provided that the FW claims no support for additional modes.
 587          */
 588         if (encp->enc_rx_scale_additional_modes_supported == B_FALSE) {
 589                 efx_rx_hash_type_t t_ipv4 = EFX_RX_HASH(IPV4, 2TUPLE) |
 590                                             EFX_RX_HASH(IPV4_TCP, 2TUPLE);
 591                 efx_rx_hash_type_t t_ipv6 = EFX_RX_HASH(IPV6, 2TUPLE) |
 592                                             EFX_RX_HASH(IPV6_TCP, 2TUPLE);
 593                 efx_rx_hash_type_t t_ipv4_tcp = EFX_RX_HASH(IPV4_TCP, 4TUPLE);
 594                 efx_rx_hash_type_t t_ipv6_tcp = EFX_RX_HASH(IPV6_TCP, 4TUPLE);
 595
 596                 if ((type & t_ipv4) == t_ipv4)
 597                         type |= EFX_RX_HASH_IPV4;
 598                 if ((type & t_ipv6) == t_ipv6)
 599                         type |= EFX_RX_HASH_IPV6;
 600
 601                 if (encp->enc_rx_scale_l4_hash_supported == B_TRUE) {
 602                         if ((type & t_ipv4_tcp) == t_ipv4_tcp)
 603                                 type |= EFX_RX_HASH_TCPIPV4;
 604                         if ((type & t_ipv6_tcp) == t_ipv6_tcp)
 605                                 type |= EFX_RX_HASH_TCPIPV6;
 606                 }
 607
 608                 type &= EFX_RX_HASH_LEGACY_MASK;
 609         }
 610
 611         if (erxop->erxo_scale_mode_set != NULL) {
 612                 if ((rc = erxop->erxo_scale_mode_set(enp, rss_context, alg,
 613                             type, insert)) != 0)
 614                         goto fail4;
 615         }
 616
 617         return (0);
 618
 619 fail4:
 620         EFSYS_PROBE(fail4);
 621 fail3:
 622         EFSYS_PROBE(fail3);
 623 fail2:
 624         EFSYS_PROBE(fail2);
 625 fail1:
 626         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 627         return (rc);
 628 }
 629 #endif  /* EFSYS_OPT_RX_SCALE */
 630
 631 #if EFSYS_OPT_RX_SCALE
 632         __checkReturn   efx_rc_t
 633 efx_rx_scale_key_set(
 634         __in            efx_nic_t *enp,
 635         __in            uint32_t rss_context,
 636         __in_ecount(n)  uint8_t *key,
 637         __in            size_t n)
 638 {
 639         const efx_rx_ops_t *erxop = enp->en_erxop;
 640         efx_rc_t rc;
 641
 642         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 643         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 644
 645         if ((rc = erxop->erxo_scale_key_set(enp, rss_context, key, n)) != 0)
 646                 goto fail1;
 647
 648         return (0);
 649
 650 fail1:
 651         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 652
 653         return (rc);
 654 }
 655 #endif  /* EFSYS_OPT_RX_SCALE */
 656
 657 #if EFSYS_OPT_RX_SCALE
 658         __checkReturn   efx_rc_t
 659 efx_rx_scale_tbl_set(
 660         __in            efx_nic_t *enp,
 661         __in            uint32_t rss_context,
 662         __in_ecount(n)  unsigned int *table,
 663         __in            size_t n)
 664 {
 665         const efx_rx_ops_t *erxop = enp->en_erxop;
 666         efx_rc_t rc;
 667
 668         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 669         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 670
 671         if ((rc = erxop->erxo_scale_tbl_set(enp, rss_context, table, n)) != 0)
 672                 goto fail1;
 673
 674         return (0);
 675
 676 fail1:
 677         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 678
 679         return (rc);
 680 }
 681 #endif  /* EFSYS_OPT_RX_SCALE */
 682
 683                                 void
 684 efx_rx_qpost(
 685         __in                    efx_rxq_t *erp,
 686         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
 687         __in                    size_t size,
 688         __in                    unsigned int ndescs,
 689         __in                    unsigned int completed,
 690         __in                    unsigned int added)
 691 {
 692         efx_nic_t *enp = erp->er_enp;
 693         const efx_rx_ops_t *erxop = enp->en_erxop;
 694
 695         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 696
 697         erxop->erxo_qpost(erp, addrp, size, ndescs, completed, added);
 698 }
 699
 700 #if EFSYS_OPT_RX_PACKED_STREAM
 701
 702                         void
 703 efx_rx_qpush_ps_credits(
 704         __in            efx_rxq_t *erp)
 705 {
 706         efx_nic_t *enp = erp->er_enp;
 707         const efx_rx_ops_t *erxop = enp->en_erxop;
 708
 709         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 710
 711         erxop->erxo_qpush_ps_credits(erp);
 712 }
 713
 714         __checkReturn   uint8_t *
 715 efx_rx_qps_packet_info(
 716         __in            efx_rxq_t *erp,
 717         __in            uint8_t *buffer,
 718         __in            uint32_t buffer_length,
 719         __in            uint32_t current_offset,
 720         __out           uint16_t *lengthp,
 721         __out           uint32_t *next_offsetp,
 722         __out           uint32_t *timestamp)
 723 {
 724         efx_nic_t *enp = erp->er_enp;
 725         const efx_rx_ops_t *erxop = enp->en_erxop;
 726
 727         return (erxop->erxo_qps_packet_info(erp, buffer,
 728                 buffer_length, current_offset, lengthp,
 729                 next_offsetp, timestamp));
 730 }
 731
 732 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
 733
 734                         void
 735 efx_rx_qpush(
 736         __in            efx_rxq_t *erp,
 737         __in            unsigned int added,
 738         __inout         unsigned int *pushedp)
 739 {
 740         efx_nic_t *enp = erp->er_enp;
 741         const efx_rx_ops_t *erxop = enp->en_erxop;
 742
 743         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 744
 745         erxop->erxo_qpush(erp, added, pushedp);
 746 }
 747
 748         __checkReturn   efx_rc_t
 749 efx_rx_qflush(
 750         __in            efx_rxq_t *erp)
 751 {
 752         efx_nic_t *enp = erp->er_enp;
 753         const efx_rx_ops_t *erxop = enp->en_erxop;
 754         efx_rc_t rc;
 755
 756         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 757
 758         if ((rc = erxop->erxo_qflush(erp)) != 0)
 759                 goto fail1;
 760
 761         return (0);
 762
 763 fail1:
 764         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 765
 766         return (rc);
 767 }
 768
 769         __checkReturn   size_t
 770 efx_rxq_size(
 771         __in    const efx_nic_t *enp,
 772         __in    unsigned int ndescs)
 773 {
 774         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 775
 776         return (ndescs * encp->enc_rx_desc_size);
 777 }
 778
 779         __checkReturn   unsigned int
 780 efx_rxq_nbufs(
 781         __in    const efx_nic_t *enp,
 782         __in    unsigned int ndescs)
 783 {
 784         return (EFX_DIV_ROUND_UP(efx_rxq_size(enp, ndescs), EFX_BUF_SIZE));
 785 }
 786
 787                         void
 788 efx_rx_qenable(
 789         __in            efx_rxq_t *erp)
 790 {
 791         efx_nic_t *enp = erp->er_enp;
 792         const efx_rx_ops_t *erxop = enp->en_erxop;
 793
 794         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 795
 796         erxop->erxo_qenable(erp);
 797 }
 798
 799 static  __checkReturn   efx_rc_t
 800 efx_rx_qcreate_internal(
 801         __in            efx_nic_t *enp,
 802         __in            unsigned int index,
 803         __in            unsigned int label,
 804         __in            efx_rxq_type_t type,
 805         __in_opt        const efx_rxq_type_data_t *type_data,
 806         __in            efsys_mem_t *esmp,
 807         __in            size_t ndescs,
 808         __in            uint32_t id,
 809         __in            unsigned int flags,
 810         __in            efx_evq_t *eep,
 811         __deref_out     efx_rxq_t **erpp)
 812 {
 813         const efx_rx_ops_t *erxop = enp->en_erxop;
 814         efx_rxq_t *erp;
 815         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 816         efx_rc_t rc;
 817
 818         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 819         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_RX);
 820
 821         EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
 822         EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
 823
 824         if (!ISP2(ndescs) ||
 825             ndescs < encp->enc_rxq_min_ndescs ||
 826             ndescs > encp->enc_rxq_max_ndescs) {
 827                 rc = EINVAL;
 828                 goto fail1;
 829         }
 830
 831         /* Allocate an RXQ object */
 832         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_rxq_t), erp);
 833
 834         if (erp == NULL) {
 835                 rc = ENOMEM;
 836                 goto fail2;
 837         }
 838
 839         erp->er_magic = EFX_RXQ_MAGIC;
 840         erp->er_enp = enp;
 841         erp->er_index = index;
 842         erp->er_mask = ndescs - 1;
 843         erp->er_esmp = esmp;
 844
 845         if ((rc = erxop->erxo_qcreate(enp, index, label, type, type_data, esmp,
 846             ndescs, id, flags, eep, erp)) != 0)
 847                 goto fail3;
 848
 849         enp->en_rx_qcount++;
 850         *erpp = erp;
 851
 852         return (0);
 853
 854 fail3:
 855         EFSYS_PROBE(fail3);
 856
 857         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
 858 fail2:
 859         EFSYS_PROBE(fail2);
 860 fail1:
 861         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 862
 863         return (rc);
 864 }
 865
 866         __checkReturn   efx_rc_t
 867 efx_rx_qcreate(
 868         __in            efx_nic_t *enp,
 869         __in            unsigned int index,
 870         __in            unsigned int label,
 871         __in            efx_rxq_type_t type,
 872         __in            efsys_mem_t *esmp,
 873         __in            size_t ndescs,
 874         __in            uint32_t id,
 875         __in            unsigned int flags,
 876         __in            efx_evq_t *eep,
 877         __deref_out     efx_rxq_t **erpp)
 878 {
 879         return efx_rx_qcreate_internal(enp, index, label, type, NULL,
 880             esmp, ndescs, id, flags, eep, erpp);
 881 }
 882
 883 #if EFSYS_OPT_RX_PACKED_STREAM
 884
 885         __checkReturn   efx_rc_t
 886 efx_rx_qcreate_packed_stream(
 887         __in            efx_nic_t *enp,
 888         __in            unsigned int index,
 889         __in            unsigned int label,
 890         __in            uint32_t ps_buf_size,
 891         __in            efsys_mem_t *esmp,
 892         __in            size_t ndescs,
 893         __in            efx_evq_t *eep,
 894         __deref_out     efx_rxq_t **erpp)
 895 {
 896         efx_rxq_type_data_t type_data;
 897
 898         memset(&type_data, 0, sizeof (type_data));
 899
 900         type_data.ertd_packed_stream.eps_buf_size = ps_buf_size;
 901
 902         return efx_rx_qcreate_internal(enp, index, label,
 903             EFX_RXQ_TYPE_PACKED_STREAM, &type_data, esmp, ndescs,
 904             0 /* id unused on EF10 */, EFX_RXQ_FLAG_NONE, eep, erpp);
 905 }
 906
 907 #endif
 908
 909 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 910
 911         __checkReturn   efx_rc_t
 912 efx_rx_qcreate_es_super_buffer(
 913         __in            efx_nic_t *enp,
 914         __in            unsigned int index,
 915         __in            unsigned int label,
 916         __in            uint32_t n_bufs_per_desc,
 917         __in            uint32_t max_dma_len,
 918         __in            uint32_t buf_stride,
 919         __in            uint32_t hol_block_timeout,
 920         __in            efsys_mem_t *esmp,
 921         __in            size_t ndescs,
 922         __in            unsigned int flags,
 923         __in            efx_evq_t *eep,
 924         __deref_out     efx_rxq_t **erpp)
 925 {
 926         efx_rc_t rc;
 927         efx_rxq_type_data_t type_data;
 928
 929         if (hol_block_timeout > EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX) {
 930                 rc = EINVAL;
 931                 goto fail1;
 932         }
 933
 934         memset(&type_data, 0, sizeof (type_data));
 935
 936         type_data.ertd_es_super_buffer.eessb_bufs_per_desc = n_bufs_per_desc;
 937         type_data.ertd_es_super_buffer.eessb_max_dma_len = max_dma_len;
 938         type_data.ertd_es_super_buffer.eessb_buf_stride = buf_stride;
 939         type_data.ertd_es_super_buffer.eessb_hol_block_timeout =
 940             hol_block_timeout;
 941
 942         rc = efx_rx_qcreate_internal(enp, index, label,
 943             EFX_RXQ_TYPE_ES_SUPER_BUFFER, &type_data, esmp, ndescs,
 944             0 /* id unused on EF10 */, flags, eep, erpp);
 945         if (rc != 0)
 946                 goto fail2;
 947
 948         return (0);
 949
 950 fail2:
 951         EFSYS_PROBE(fail2);
 952 fail1:
 953         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 954
 955         return (rc);
 956 }
 957
 958 #endif
 959
 960
 961                         void
 962 efx_rx_qdestroy(
 963         __in            efx_rxq_t *erp)
 964 {
 965         efx_nic_t *enp = erp->er_enp;
 966         const efx_rx_ops_t *erxop = enp->en_erxop;
 967
 968         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 969
 970         erxop->erxo_qdestroy(erp);
 971 }
 972
 973         __checkReturn   efx_rc_t
 974 efx_pseudo_hdr_pkt_length_get(
 975         __in            efx_rxq_t *erp,
 976         __in            uint8_t *buffer,
 977         __out           uint16_t *lengthp)
 978 {
 979         efx_nic_t *enp = erp->er_enp;
 980         const efx_rx_ops_t *erxop = enp->en_erxop;
 981
 982         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 983
 984         return (erxop->erxo_prefix_pktlen(enp, buffer, lengthp));
 985 }
 986
 987 #if EFSYS_OPT_RX_SCALE
 988         __checkReturn   uint32_t
 989 efx_pseudo_hdr_hash_get(
 990         __in            efx_rxq_t *erp,
 991         __in            efx_rx_hash_alg_t func,
 992         __in            uint8_t *buffer)
 993 {
 994         efx_nic_t *enp = erp->er_enp;
 995         const efx_rx_ops_t *erxop = enp->en_erxop;
 996
 997         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
 998
 999         EFSYS_ASSERT3U(enp->en_hash_support, ==, EFX_RX_HASH_AVAILABLE);
1000         return (erxop->erxo_prefix_hash(enp, func, buffer));
1001 }
1002 #endif  /* EFSYS_OPT_RX_SCALE */
1003
1004 #if EFSYS_OPT_SIENA
1005
1006 static  __checkReturn   efx_rc_t
1007 siena_rx_init(
1008         __in            efx_nic_t *enp)
1009 {
1010         efx_oword_t oword;
1011         unsigned int index;
1012
1013         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1014
1015         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_DESC_PUSH_EN, 0);
1016         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);
1017         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);
1018         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);
1019         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR, 0);
1020         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, 0x3000 / 32);
1021         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1022
1023         /* Zero the RSS table */
1024         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS;
1025             index++) {
1026                 EFX_ZERO_OWORD(oword);
1027                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1028                                     index, &oword, B_TRUE);
1029         }
1030
1031 #if EFSYS_OPT_RX_SCALE
1032         /* The RSS key and indirection table are writable. */
1033         enp->en_rss_context_type = EFX_RX_SCALE_EXCLUSIVE;
1034
1035         /* Hardware can insert RX hash with/without RSS */
1036         enp->en_hash_support = EFX_RX_HASH_AVAILABLE;
1037 #endif  /* EFSYS_OPT_RX_SCALE */
1038
1039         return (0);
1040 }
1041
1042 #if EFSYS_OPT_RX_SCATTER
1043 static  __checkReturn   efx_rc_t
1044 siena_rx_scatter_enable(
1045         __in            efx_nic_t *enp,
1046         __in            unsigned int buf_size)
1047 {
1048         unsigned int nbuf32;
1049         efx_oword_t oword;
1050         efx_rc_t rc;
1051
1052         nbuf32 = buf_size / 32;
1053         if ((nbuf32 == 0) ||
1054             (nbuf32 >= (1 << FRF_BZ_RX_USR_BUF_SIZE_WIDTH)) ||
1055             ((buf_size % 32) != 0)) {
1056                 rc = EINVAL;
1057                 goto fail1;
1058         }
1059
1060         if (enp->en_rx_qcount > 0) {
1061                 rc = EBUSY;
1062                 goto fail2;
1063         }
1064
1065         /* Set scatter buffer size */
1066         EFX_BAR_READO(enp, FR_AZ_RX_CFG_REG, &oword);
1067         EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_USR_BUF_SIZE, nbuf32);
1068         EFX_BAR_WRITEO(enp, FR_AZ_RX_CFG_REG, &oword);
1069
1070         /* Enable scatter for packets not matching a filter */
1071         EFX_BAR_READO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1072         EFX_SET_OWORD_FIELD(oword, FRF_BZ_SCATTER_ENBL_NO_MATCH_Q, 1);
1073         EFX_BAR_WRITEO(enp, FR_AZ_RX_FILTER_CTL_REG, &oword);
1074
1075         return (0);
1076
1077 fail2:
1078         EFSYS_PROBE(fail2);
1079 fail1:
1080         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1081
1082         return (rc);
1083 }
1084 #endif  /* EFSYS_OPT_RX_SCATTER */
1085
1086
1087 #define EFX_RX_LFSR_HASH(_enp, _insert)                                 \
1088         do {                                                            \
1089                 efx_oword_t oword;                                      \
1090                                                                         \
1091                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1092                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 0);      \
1093                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH, 0);       \
1094                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP, 0);       \
1095                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1096                     (_insert) ? 1 : 0);                                 \
1097                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1098                                                                         \
1099                 if ((_enp)->en_family == EFX_FAMILY_SIENA) {            \
1100                         EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3,   \
1101                             &oword);                                    \
1102                         EFX_SET_OWORD_FIELD(oword,                      \
1103                             FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 0);        \
1104                         EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3,  \
1105                             &oword);                                    \
1106                 }                                                       \
1107                                                                         \
1108                 _NOTE(CONSTANTCONDITION)                                \
1109         } while (B_FALSE)
1110
1111 #define EFX_RX_TOEPLITZ_IPV4_HASH(_enp, _insert, _ip, _tcp)             \
1112         do {                                                            \
1113                 efx_oword_t oword;                                      \
1114                                                                         \
1115                 EFX_BAR_READO((_enp), FR_AZ_RX_CFG_REG, &oword);        \
1116                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_ALG, 1);      \
1117                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_IP_HASH,           \
1118                     (_ip) ? 1 : 0);                                     \
1119                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_TCP_SUP,           \
1120                     (_tcp) ? 0 : 1);                                    \
1121                 EFX_SET_OWORD_FIELD(oword, FRF_BZ_RX_HASH_INSRT_HDR,    \
1122                     (_insert) ? 1 : 0);                                 \
1123                 EFX_BAR_WRITEO((_enp), FR_AZ_RX_CFG_REG, &oword);       \
1124                                                                         \
1125                 _NOTE(CONSTANTCONDITION)                                \
1126         } while (B_FALSE)
1127
1128 #define EFX_RX_TOEPLITZ_IPV6_HASH(_enp, _ip, _tcp, _rc)                 \
1129         do {                                                            \
1130                 efx_oword_t oword;                                      \
1131                                                                         \
1132                 EFX_BAR_READO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword);  \
1133                 EFX_SET_OWORD_FIELD(oword,                              \
1134                     FRF_CZ_RX_RSS_IPV6_THASH_ENABLE, 1);                \
1135                 EFX_SET_OWORD_FIELD(oword,                              \
1136                     FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE, (_ip) ? 1 : 0); \
1137                 EFX_SET_OWORD_FIELD(oword,                              \
1138                     FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS, (_tcp) ? 0 : 1);   \
1139                 EFX_BAR_WRITEO((_enp), FR_CZ_RX_RSS_IPV6_REG3, &oword); \
1140                                                                         \
1141                 (_rc) = 0;                                              \
1142                                                                         \
1143                 _NOTE(CONSTANTCONDITION)                                \
1144         } while (B_FALSE)
1145
1146
1147 #if EFSYS_OPT_RX_SCALE
1148
1149 static  __checkReturn   efx_rc_t
1150 siena_rx_scale_mode_set(
1151         __in            efx_nic_t *enp,
1152         __in            uint32_t rss_context,
1153         __in            efx_rx_hash_alg_t alg,
1154         __in            efx_rx_hash_type_t type,
1155         __in            boolean_t insert)
1156 {
1157         efx_rc_t rc;
1158
1159         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1160                 rc = EINVAL;
1161                 goto fail1;
1162         }
1163
1164         switch (alg) {
1165         case EFX_RX_HASHALG_LFSR:
1166                 EFX_RX_LFSR_HASH(enp, insert);
1167                 break;
1168
1169         case EFX_RX_HASHALG_TOEPLITZ:
1170                 EFX_RX_TOEPLITZ_IPV4_HASH(enp, insert,
1171                     (type & EFX_RX_HASH_IPV4) ? B_TRUE : B_FALSE,
1172                     (type & EFX_RX_HASH_TCPIPV4) ? B_TRUE : B_FALSE);
1173
1174                 EFX_RX_TOEPLITZ_IPV6_HASH(enp,
1175                     (type & EFX_RX_HASH_IPV6) ? B_TRUE : B_FALSE,
1176                     (type & EFX_RX_HASH_TCPIPV6) ? B_TRUE : B_FALSE,
1177                     rc);
1178                 if (rc != 0)
1179                         goto fail2;
1180
1181                 break;
1182
1183         default:
1184                 rc = EINVAL;
1185                 goto fail3;
1186         }
1187
1188         return (0);
1189
1190 fail3:
1191         EFSYS_PROBE(fail3);
1192 fail2:
1193         EFSYS_PROBE(fail2);
1194 fail1:
1195         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1196
1197         EFX_RX_LFSR_HASH(enp, B_FALSE);
1198
1199         return (rc);
1200 }
1201 #endif
1202
1203 #if EFSYS_OPT_RX_SCALE
1204 static  __checkReturn   efx_rc_t
1205 siena_rx_scale_key_set(
1206         __in            efx_nic_t *enp,
1207         __in            uint32_t rss_context,
1208         __in_ecount(n)  uint8_t *key,
1209         __in            size_t n)
1210 {
1211         efx_oword_t oword;
1212         unsigned int byte;
1213         unsigned int offset;
1214         efx_rc_t rc;
1215
1216         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1217                 rc = EINVAL;
1218                 goto fail1;
1219         }
1220
1221         byte = 0;
1222
1223         /* Write Toeplitz IPv4 hash key */
1224         EFX_ZERO_OWORD(oword);
1225         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1226             offset > 0 && byte < n;
1227             --offset)
1228                 oword.eo_u8[offset - 1] = key[byte++];
1229
1230         EFX_BAR_WRITEO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1231
1232         byte = 0;
1233
1234         /* Verify Toeplitz IPv4 hash key */
1235         EFX_BAR_READO(enp, FR_BZ_RX_RSS_TKEY_REG, &oword);
1236         for (offset = (FRF_BZ_RX_RSS_TKEY_LBN + FRF_BZ_RX_RSS_TKEY_WIDTH) / 8;
1237             offset > 0 && byte < n;
1238             --offset) {
1239                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1240                         rc = EFAULT;
1241                         goto fail2;
1242                 }
1243         }
1244
1245         if ((enp->en_features & EFX_FEATURE_IPV6) == 0)
1246                 goto done;
1247
1248         byte = 0;
1249
1250         /* Write Toeplitz IPv6 hash key 3 */
1251         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1252         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1253             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1254             offset > 0 && byte < n;
1255             --offset)
1256                 oword.eo_u8[offset - 1] = key[byte++];
1257
1258         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1259
1260         /* Write Toeplitz IPv6 hash key 2 */
1261         EFX_ZERO_OWORD(oword);
1262         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1263             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1264             offset > 0 && byte < n;
1265             --offset)
1266                 oword.eo_u8[offset - 1] = key[byte++];
1267
1268         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1269
1270         /* Write Toeplitz IPv6 hash key 1 */
1271         EFX_ZERO_OWORD(oword);
1272         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1273             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1274             offset > 0 && byte < n;
1275             --offset)
1276                 oword.eo_u8[offset - 1] = key[byte++];
1277
1278         EFX_BAR_WRITEO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1279
1280         byte = 0;
1281
1282         /* Verify Toeplitz IPv6 hash key 3 */
1283         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG3, &oword);
1284         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN +
1285             FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH) / 8;
1286             offset > 0 && byte < n;
1287             --offset) {
1288                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1289                         rc = EFAULT;
1290                         goto fail3;
1291                 }
1292         }
1293
1294         /* Verify Toeplitz IPv6 hash key 2 */
1295         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG2, &oword);
1296         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN +
1297             FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH) / 8;
1298             offset > 0 && byte < n;
1299             --offset) {
1300                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1301                         rc = EFAULT;
1302                         goto fail4;
1303                 }
1304         }
1305
1306         /* Verify Toeplitz IPv6 hash key 1 */
1307         EFX_BAR_READO(enp, FR_CZ_RX_RSS_IPV6_REG1, &oword);
1308         for (offset = (FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN +
1309             FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH) / 8;
1310             offset > 0 && byte < n;
1311             --offset) {
1312                 if (oword.eo_u8[offset - 1] != key[byte++]) {
1313                         rc = EFAULT;
1314                         goto fail5;
1315                 }
1316         }
1317
1318 done:
1319         return (0);
1320
1321 fail5:
1322         EFSYS_PROBE(fail5);
1323 fail4:
1324         EFSYS_PROBE(fail4);
1325 fail3:
1326         EFSYS_PROBE(fail3);
1327 fail2:
1328         EFSYS_PROBE(fail2);
1329 fail1:
1330         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1331
1332         return (rc);
1333 }
1334 #endif
1335
1336 #if EFSYS_OPT_RX_SCALE
1337 static  __checkReturn   efx_rc_t
1338 siena_rx_scale_tbl_set(
1339         __in            efx_nic_t *enp,
1340         __in            uint32_t rss_context,
1341         __in_ecount(n)  unsigned int *table,
1342         __in            size_t n)
1343 {
1344         efx_oword_t oword;
1345         int index;
1346         efx_rc_t rc;
1347
1348         EFX_STATIC_ASSERT(EFX_RSS_TBL_SIZE == FR_BZ_RX_INDIRECTION_TBL_ROWS);
1349         EFX_STATIC_ASSERT(EFX_MAXRSS == (1 << FRF_BZ_IT_QUEUE_WIDTH));
1350
1351         if (rss_context != EFX_RSS_CONTEXT_DEFAULT) {
1352                 rc = EINVAL;
1353                 goto fail1;
1354         }
1355
1356         if (n > FR_BZ_RX_INDIRECTION_TBL_ROWS) {
1357                 rc = EINVAL;
1358                 goto fail2;
1359         }
1360
1361         for (index = 0; index < FR_BZ_RX_INDIRECTION_TBL_ROWS; index++) {
1362                 uint32_t byte;
1363
1364                 /* Calculate the entry to place in the table */
1365                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1366
1367                 EFSYS_PROBE2(table, int, index, uint32_t, byte);
1368
1369                 EFX_POPULATE_OWORD_1(oword, FRF_BZ_IT_QUEUE, byte);
1370
1371                 /* Write the table */
1372                 EFX_BAR_TBL_WRITEO(enp, FR_BZ_RX_INDIRECTION_TBL,
1373                                     index, &oword, B_TRUE);
1374         }
1375
1376         for (index = FR_BZ_RX_INDIRECTION_TBL_ROWS - 1; index >= 0; --index) {
1377                 uint32_t byte;
1378
1379                 /* Determine if we're starting a new batch */
1380                 byte = (n > 0) ? (uint32_t)table[index % n] : 0;
1381
1382                 /* Read the table */
1383                 EFX_BAR_TBL_READO(enp, FR_BZ_RX_INDIRECTION_TBL,
1384                                     index, &oword, B_TRUE);
1385
1386                 /* Verify the entry */
1387                 if (EFX_OWORD_FIELD(oword, FRF_BZ_IT_QUEUE) != byte) {
1388                         rc = EFAULT;
1389                         goto fail3;
1390                 }
1391         }
1392
1393         return (0);
1394
1395 fail3:
1396         EFSYS_PROBE(fail3);
1397 fail2:
1398         EFSYS_PROBE(fail2);
1399 fail1:
1400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1401
1402         return (rc);
1403 }
1404 #endif
1405
1406 /*
1407  * Falcon/Siena pseudo-header
1408  * --------------------------
1409  *
1410  * Receive packets are prefixed by an optional 16 byte pseudo-header.
1411  * The pseudo-header is a byte array of one of the forms:
1412  *
1413  *  0  1  2  3  4  5  6  7  8  9 10 11 12 13 14 15
1414  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.TT.TT.TT.TT
1415  * xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.xx.LL.LL
1416  *
1417  * where:
1418  *   TT.TT.TT.TT   Toeplitz hash (32-bit big-endian)
1419  *   LL.LL         LFSR hash     (16-bit big-endian)
1420  */
1421
1422 #if EFSYS_OPT_RX_SCALE
1423 static  __checkReturn   uint32_t
1424 siena_rx_prefix_hash(
1425         __in            efx_nic_t *enp,
1426         __in            efx_rx_hash_alg_t func,
1427         __in            uint8_t *buffer)
1428 {
1429         _NOTE(ARGUNUSED(enp))
1430
1431         switch (func) {
1432         case EFX_RX_HASHALG_TOEPLITZ:
1433                 return ((buffer[12] << 24) |
1434                     (buffer[13] << 16) |
1435                     (buffer[14] <<  8) |
1436                     buffer[15]);
1437
1438         case EFX_RX_HASHALG_LFSR:
1439                 return ((buffer[14] << 8) | buffer[15]);
1440
1441         default:
1442                 EFSYS_ASSERT(0);
1443                 return (0);
1444         }
1445 }
1446 #endif /* EFSYS_OPT_RX_SCALE */
1447
1448 static  __checkReturn   efx_rc_t
1449 siena_rx_prefix_pktlen(
1450         __in            efx_nic_t *enp,
1451         __in            uint8_t *buffer,
1452         __out           uint16_t *lengthp)
1453 {
1454         _NOTE(ARGUNUSED(enp, buffer, lengthp))
1455
1456         /* Not supported by Falcon/Siena hardware */
1457         EFSYS_ASSERT(0);
1458         return (ENOTSUP);
1459 }
1460
1461
1462 static                          void
1463 siena_rx_qpost(
1464         __in                    efx_rxq_t *erp,
1465         __in_ecount(ndescs)     efsys_dma_addr_t *addrp,
1466         __in                    size_t size,
1467         __in                    unsigned int ndescs,
1468         __in                    unsigned int completed,
1469         __in                    unsigned int added)
1470 {
1471         efx_qword_t qword;
1472         unsigned int i;
1473         unsigned int offset;
1474         unsigned int id;
1475
1476         /* The client driver must not overfill the queue */
1477         EFSYS_ASSERT3U(added - completed + ndescs, <=,
1478             EFX_RXQ_LIMIT(erp->er_mask + 1));
1479
1480         id = added & (erp->er_mask);
1481         for (i = 0; i < ndescs; i++) {
1482                 EFSYS_PROBE4(rx_post, unsigned int, erp->er_index,
1483                     unsigned int, id, efsys_dma_addr_t, addrp[i],
1484                     size_t, size);
1485
1486                 EFX_POPULATE_QWORD_3(qword,
1487                     FSF_AZ_RX_KER_BUF_SIZE, (uint32_t)(size),
1488                     FSF_AZ_RX_KER_BUF_ADDR_DW0,
1489                     (uint32_t)(addrp[i] & 0xffffffff),
1490                     FSF_AZ_RX_KER_BUF_ADDR_DW1,
1491                     (uint32_t)(addrp[i] >> 32));
1492
1493                 offset = id * sizeof (efx_qword_t);
1494                 EFSYS_MEM_WRITEQ(erp->er_esmp, offset, &qword);
1495
1496                 id = (id + 1) & (erp->er_mask);
1497         }
1498 }
1499
1500 static                  void
1501 siena_rx_qpush(
1502         __in    efx_rxq_t *erp,
1503         __in    unsigned int added,
1504         __inout unsigned int *pushedp)
1505 {
1506         efx_nic_t *enp = erp->er_enp;
1507         unsigned int pushed = *pushedp;
1508         uint32_t wptr;
1509         efx_oword_t oword;
1510         efx_dword_t dword;
1511
1512         /* All descriptors are pushed */
1513         *pushedp = added;
1514
1515         /* Push the populated descriptors out */
1516         wptr = added & erp->er_mask;
1517
1518         EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DESC_WPTR, wptr);
1519
1520         /* Only write the third DWORD */
1521         EFX_POPULATE_DWORD_1(dword,
1522             EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
1523
1524         /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
1525         EFX_DMA_SYNC_QUEUE_FOR_DEVICE(erp->er_esmp, erp->er_mask + 1,
1526             wptr, pushed & erp->er_mask);
1527         EFSYS_PIO_WRITE_BARRIER();
1528         EFX_BAR_TBL_WRITED3(enp, FR_BZ_RX_DESC_UPD_REGP0,
1529                             erp->er_index, &dword, B_FALSE);
1530 }
1531
1532 #if EFSYS_OPT_RX_PACKED_STREAM
1533 static          void
1534 siena_rx_qpush_ps_credits(
1535         __in            efx_rxq_t *erp)
1536 {
1537         /* Not supported by Siena hardware */
1538         EFSYS_ASSERT(0);
1539 }
1540
1541 static          uint8_t *
1542 siena_rx_qps_packet_info(
1543         __in            efx_rxq_t *erp,
1544         __in            uint8_t *buffer,
1545         __in            uint32_t buffer_length,
1546         __in            uint32_t current_offset,
1547         __out           uint16_t *lengthp,
1548         __out           uint32_t *next_offsetp,
1549         __out           uint32_t *timestamp)
1550 {
1551         /* Not supported by Siena hardware */
1552         EFSYS_ASSERT(0);
1553
1554         return (NULL);
1555 }
1556 #endif /* EFSYS_OPT_RX_PACKED_STREAM */
1557
1558 static  __checkReturn   efx_rc_t
1559 siena_rx_qflush(
1560         __in    efx_rxq_t *erp)
1561 {
1562         efx_nic_t *enp = erp->er_enp;
1563         efx_oword_t oword;
1564         uint32_t label;
1565
1566         label = erp->er_index;
1567
1568         /* Flush the queue */
1569         EFX_POPULATE_OWORD_2(oword, FRF_AZ_RX_FLUSH_DESCQ_CMD, 1,
1570             FRF_AZ_RX_FLUSH_DESCQ, label);
1571         EFX_BAR_WRITEO(enp, FR_AZ_RX_FLUSH_DESCQ_REG, &oword);
1572
1573         return (0);
1574 }
1575
1576 static          void
1577 siena_rx_qenable(
1578         __in    efx_rxq_t *erp)
1579 {
1580         efx_nic_t *enp = erp->er_enp;
1581         efx_oword_t oword;
1582
1583         EFSYS_ASSERT3U(erp->er_magic, ==, EFX_RXQ_MAGIC);
1584
1585         EFX_BAR_TBL_READO(enp, FR_AZ_RX_DESC_PTR_TBL,
1586                             erp->er_index, &oword, B_TRUE);
1587
1588         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DC_HW_RPTR, 0);
1589         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_HW_RPTR, 0);
1590         EFX_SET_OWORD_FIELD(oword, FRF_AZ_RX_DESCQ_EN, 1);
1591
1592         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1593                             erp->er_index, &oword, B_TRUE);
1594 }
1595
1596 static  __checkReturn   efx_rc_t
1597 siena_rx_qcreate(
1598         __in            efx_nic_t *enp,
1599         __in            unsigned int index,
1600         __in            unsigned int label,
1601         __in            efx_rxq_type_t type,
1602         __in_opt        const efx_rxq_type_data_t *type_data,
1603         __in            efsys_mem_t *esmp,
1604         __in            size_t ndescs,
1605         __in            uint32_t id,
1606         __in            unsigned int flags,
1607         __in            efx_evq_t *eep,
1608         __in            efx_rxq_t *erp)
1609 {
1610         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1611         efx_oword_t oword;
1612         uint32_t size;
1613         boolean_t jumbo = B_FALSE;
1614         efx_rc_t rc;
1615
1616         _NOTE(ARGUNUSED(esmp))
1617         _NOTE(ARGUNUSED(type_data))
1618
1619         EFX_STATIC_ASSERT(EFX_EV_RX_NLABELS ==
1620             (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH));
1621         EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
1622         EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
1623
1624         if (index >= encp->enc_rxq_limit) {
1625                 rc = EINVAL;
1626                 goto fail1;
1627         }
1628         for (size = 0;
1629             (1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;
1630             size++)
1631                 if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)
1632                         break;
1633         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1634                 rc = EINVAL;
1635                 goto fail2;
1636         }
1637
1638         switch (type) {
1639         case EFX_RXQ_TYPE_DEFAULT:
1640                 break;
1641
1642         default:
1643                 rc = EINVAL;
1644                 goto fail3;
1645         }
1646
1647         if (flags & EFX_RXQ_FLAG_SCATTER) {
1648 #if EFSYS_OPT_RX_SCATTER
1649                 jumbo = B_TRUE;
1650 #else
1651                 rc = EINVAL;
1652                 goto fail4;
1653 #endif  /* EFSYS_OPT_RX_SCATTER */
1654         }
1655
1656         /* Set up the new descriptor queue */
1657         EFX_POPULATE_OWORD_7(oword,
1658             FRF_AZ_RX_DESCQ_BUF_BASE_ID, id,
1659             FRF_AZ_RX_DESCQ_EVQ_ID, eep->ee_index,
1660             FRF_AZ_RX_DESCQ_OWNER_ID, 0,
1661             FRF_AZ_RX_DESCQ_LABEL, label,
1662             FRF_AZ_RX_DESCQ_SIZE, size,
1663             FRF_AZ_RX_DESCQ_TYPE, 0,
1664             FRF_AZ_RX_DESCQ_JUMBO, jumbo);
1665
1666         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1667                             erp->er_index, &oword, B_TRUE);
1668
1669         return (0);
1670
1671 #if !EFSYS_OPT_RX_SCATTER
1672 fail4:
1673         EFSYS_PROBE(fail4);
1674 #endif
1675 fail3:
1676         EFSYS_PROBE(fail3);
1677 fail2:
1678         EFSYS_PROBE(fail2);
1679 fail1:
1680         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1681
1682         return (rc);
1683 }
1684
1685 static          void
1686 siena_rx_qdestroy(
1687         __in    efx_rxq_t *erp)
1688 {
1689         efx_nic_t *enp = erp->er_enp;
1690         efx_oword_t oword;
1691
1692         EFSYS_ASSERT(enp->en_rx_qcount != 0);
1693         --enp->en_rx_qcount;
1694
1695         /* Purge descriptor queue */
1696         EFX_ZERO_OWORD(oword);
1697
1698         EFX_BAR_TBL_WRITEO(enp, FR_AZ_RX_DESC_PTR_TBL,
1699                             erp->er_index, &oword, B_TRUE);
1700
1701         /* Free the RXQ object */
1702         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_rxq_t), erp);
1703 }
1704
1705 static          void
1706 siena_rx_fini(
1707         __in    efx_nic_t *enp)
1708 {
1709         _NOTE(ARGUNUSED(enp))
1710 }
1711
1712 #endif /* EFSYS_OPT_SIENA */