2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
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28 * policies, either expressed or implied, of the FreeBSD Project.
35 #define EFX_TX_QSTAT_INCR(_etp, _stat) \
37 (_etp)->et_stat[_stat]++; \
38 _NOTE(CONSTANTCONDITION) \
41 #define EFX_TX_QSTAT_INCR(_etp, _stat)
46 static __checkReturn efx_rc_t
54 static __checkReturn efx_rc_t
57 __in unsigned int index,
58 __in unsigned int label,
59 __in efsys_mem_t *esmp,
65 __out unsigned int *addedp);
71 static __checkReturn efx_rc_t
74 __in_ecount(n) efx_buffer_t *eb,
76 __in unsigned int completed,
77 __inout unsigned int *addedp);
82 __in unsigned int added,
83 __in unsigned int pushed);
85 static __checkReturn efx_rc_t
88 __in unsigned int ns);
90 static __checkReturn efx_rc_t
98 __checkReturn efx_rc_t
101 __in_ecount(n) efx_desc_t *ed,
103 __in unsigned int completed,
104 __inout unsigned int *addedp);
107 siena_tx_qdesc_dma_create(
109 __in efsys_dma_addr_t addr,
112 __out efx_desc_t *edp);
116 siena_tx_qstats_update(
118 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
121 #endif /* EFSYS_OPT_SIENA */
125 static const efx_tx_ops_t __efx_tx_siena_ops = {
126 siena_tx_init, /* etxo_init */
127 siena_tx_fini, /* etxo_fini */
128 siena_tx_qcreate, /* etxo_qcreate */
129 siena_tx_qdestroy, /* etxo_qdestroy */
130 siena_tx_qpost, /* etxo_qpost */
131 siena_tx_qpush, /* etxo_qpush */
132 siena_tx_qpace, /* etxo_qpace */
133 siena_tx_qflush, /* etxo_qflush */
134 siena_tx_qenable, /* etxo_qenable */
135 NULL, /* etxo_qpio_enable */
136 NULL, /* etxo_qpio_disable */
137 NULL, /* etxo_qpio_write */
138 NULL, /* etxo_qpio_post */
139 siena_tx_qdesc_post, /* etxo_qdesc_post */
140 siena_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
141 NULL, /* etxo_qdesc_tso_create */
142 NULL, /* etxo_qdesc_tso2_create */
143 NULL, /* etxo_qdesc_vlantci_create */
145 siena_tx_qstats_update, /* etxo_qstats_update */
148 #endif /* EFSYS_OPT_SIENA */
150 #if EFSYS_OPT_HUNTINGTON
151 static const efx_tx_ops_t __efx_tx_hunt_ops = {
152 ef10_tx_init, /* etxo_init */
153 ef10_tx_fini, /* etxo_fini */
154 ef10_tx_qcreate, /* etxo_qcreate */
155 ef10_tx_qdestroy, /* etxo_qdestroy */
156 ef10_tx_qpost, /* etxo_qpost */
157 ef10_tx_qpush, /* etxo_qpush */
158 ef10_tx_qpace, /* etxo_qpace */
159 ef10_tx_qflush, /* etxo_qflush */
160 ef10_tx_qenable, /* etxo_qenable */
161 ef10_tx_qpio_enable, /* etxo_qpio_enable */
162 ef10_tx_qpio_disable, /* etxo_qpio_disable */
163 ef10_tx_qpio_write, /* etxo_qpio_write */
164 ef10_tx_qpio_post, /* etxo_qpio_post */
165 ef10_tx_qdesc_post, /* etxo_qdesc_post */
166 ef10_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
167 ef10_tx_qdesc_tso_create, /* etxo_qdesc_tso_create */
168 ef10_tx_qdesc_tso2_create, /* etxo_qdesc_tso2_create */
169 ef10_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */
171 ef10_tx_qstats_update, /* etxo_qstats_update */
174 #endif /* EFSYS_OPT_HUNTINGTON */
176 #if EFSYS_OPT_MEDFORD
177 static const efx_tx_ops_t __efx_tx_medford_ops = {
178 ef10_tx_init, /* etxo_init */
179 ef10_tx_fini, /* etxo_fini */
180 ef10_tx_qcreate, /* etxo_qcreate */
181 ef10_tx_qdestroy, /* etxo_qdestroy */
182 ef10_tx_qpost, /* etxo_qpost */
183 ef10_tx_qpush, /* etxo_qpush */
184 ef10_tx_qpace, /* etxo_qpace */
185 ef10_tx_qflush, /* etxo_qflush */
186 ef10_tx_qenable, /* etxo_qenable */
187 ef10_tx_qpio_enable, /* etxo_qpio_enable */
188 ef10_tx_qpio_disable, /* etxo_qpio_disable */
189 ef10_tx_qpio_write, /* etxo_qpio_write */
190 ef10_tx_qpio_post, /* etxo_qpio_post */
191 ef10_tx_qdesc_post, /* etxo_qdesc_post */
192 ef10_tx_qdesc_dma_create, /* etxo_qdesc_dma_create */
193 NULL, /* etxo_qdesc_tso_create */
194 ef10_tx_qdesc_tso2_create, /* etxo_qdesc_tso2_create */
195 ef10_tx_qdesc_vlantci_create, /* etxo_qdesc_vlantci_create */
197 ef10_tx_qstats_update, /* etxo_qstats_update */
200 #endif /* EFSYS_OPT_MEDFORD */
202 __checkReturn efx_rc_t
206 const efx_tx_ops_t *etxop;
209 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
210 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
212 if (!(enp->en_mod_flags & EFX_MOD_EV)) {
217 if (enp->en_mod_flags & EFX_MOD_TX) {
222 switch (enp->en_family) {
224 case EFX_FAMILY_SIENA:
225 etxop = &__efx_tx_siena_ops;
227 #endif /* EFSYS_OPT_SIENA */
229 #if EFSYS_OPT_HUNTINGTON
230 case EFX_FAMILY_HUNTINGTON:
231 etxop = &__efx_tx_hunt_ops;
233 #endif /* EFSYS_OPT_HUNTINGTON */
235 #if EFSYS_OPT_MEDFORD
236 case EFX_FAMILY_MEDFORD:
237 etxop = &__efx_tx_medford_ops;
239 #endif /* EFSYS_OPT_MEDFORD */
247 EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
249 if ((rc = etxop->etxo_init(enp)) != 0)
252 enp->en_etxop = etxop;
253 enp->en_mod_flags |= EFX_MOD_TX;
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
265 enp->en_etxop = NULL;
266 enp->en_mod_flags &= ~EFX_MOD_TX;
274 const efx_tx_ops_t *etxop = enp->en_etxop;
276 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
277 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
278 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
279 EFSYS_ASSERT3U(enp->en_tx_qcount, ==, 0);
281 etxop->etxo_fini(enp);
283 enp->en_etxop = NULL;
284 enp->en_mod_flags &= ~EFX_MOD_TX;
287 __checkReturn efx_rc_t
290 __in unsigned int index,
291 __in unsigned int label,
292 __in efsys_mem_t *esmp,
297 __deref_out efx_txq_t **etpp,
298 __out unsigned int *addedp)
300 const efx_tx_ops_t *etxop = enp->en_etxop;
301 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
305 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
306 EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_TX);
308 EFSYS_ASSERT3U(enp->en_tx_qcount + 1, <, encp->enc_txq_limit);
310 /* Allocate an TXQ object */
311 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_txq_t), etp);
318 etp->et_magic = EFX_TXQ_MAGIC;
320 etp->et_index = index;
321 etp->et_mask = n - 1;
324 /* Initial descriptor index may be modified by etxo_qcreate */
327 if ((rc = etxop->etxo_qcreate(enp, index, label, esmp,
328 n, id, flags, eep, etp, addedp)) != 0)
338 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
340 EFSYS_PROBE1(fail1, efx_rc_t, rc);
348 efx_nic_t *enp = etp->et_enp;
349 const efx_tx_ops_t *etxop = enp->en_etxop;
351 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
353 EFSYS_ASSERT(enp->en_tx_qcount != 0);
356 etxop->etxo_qdestroy(etp);
358 /* Free the TXQ object */
359 EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_txq_t), etp);
362 __checkReturn efx_rc_t
365 __in_ecount(n) efx_buffer_t *eb,
367 __in unsigned int completed,
368 __inout unsigned int *addedp)
370 efx_nic_t *enp = etp->et_enp;
371 const efx_tx_ops_t *etxop = enp->en_etxop;
374 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
376 if ((rc = etxop->etxo_qpost(etp, eb,
377 n, completed, addedp)) != 0)
383 EFSYS_PROBE1(fail1, efx_rc_t, rc);
390 __in unsigned int added,
391 __in unsigned int pushed)
393 efx_nic_t *enp = etp->et_enp;
394 const efx_tx_ops_t *etxop = enp->en_etxop;
396 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
398 etxop->etxo_qpush(etp, added, pushed);
401 __checkReturn efx_rc_t
404 __in unsigned int ns)
406 efx_nic_t *enp = etp->et_enp;
407 const efx_tx_ops_t *etxop = enp->en_etxop;
410 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
412 if ((rc = etxop->etxo_qpace(etp, ns)) != 0)
418 EFSYS_PROBE1(fail1, efx_rc_t, rc);
422 __checkReturn efx_rc_t
426 efx_nic_t *enp = etp->et_enp;
427 const efx_tx_ops_t *etxop = enp->en_etxop;
430 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
432 if ((rc = etxop->etxo_qflush(etp)) != 0)
438 EFSYS_PROBE1(fail1, efx_rc_t, rc);
446 efx_nic_t *enp = etp->et_enp;
447 const efx_tx_ops_t *etxop = enp->en_etxop;
449 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
451 etxop->etxo_qenable(etp);
454 __checkReturn efx_rc_t
458 efx_nic_t *enp = etp->et_enp;
459 const efx_tx_ops_t *etxop = enp->en_etxop;
462 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
464 if (~enp->en_features & EFX_FEATURE_PIO_BUFFERS) {
468 if (etxop->etxo_qpio_enable == NULL) {
472 if ((rc = etxop->etxo_qpio_enable(etp)) != 0)
482 EFSYS_PROBE1(fail1, efx_rc_t, rc);
490 efx_nic_t *enp = etp->et_enp;
491 const efx_tx_ops_t *etxop = enp->en_etxop;
493 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
495 if (etxop->etxo_qpio_disable != NULL)
496 etxop->etxo_qpio_disable(etp);
499 __checkReturn efx_rc_t
502 __in_ecount(buf_length) uint8_t *buffer,
503 __in size_t buf_length,
504 __in size_t pio_buf_offset)
506 efx_nic_t *enp = etp->et_enp;
507 const efx_tx_ops_t *etxop = enp->en_etxop;
510 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
512 if (etxop->etxo_qpio_write != NULL) {
513 if ((rc = etxop->etxo_qpio_write(etp, buffer, buf_length,
514 pio_buf_offset)) != 0)
522 EFSYS_PROBE1(fail1, efx_rc_t, rc);
526 __checkReturn efx_rc_t
529 __in size_t pkt_length,
530 __in unsigned int completed,
531 __inout unsigned int *addedp)
533 efx_nic_t *enp = etp->et_enp;
534 const efx_tx_ops_t *etxop = enp->en_etxop;
537 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
539 if (etxop->etxo_qpio_post != NULL) {
540 if ((rc = etxop->etxo_qpio_post(etp, pkt_length, completed,
549 EFSYS_PROBE1(fail1, efx_rc_t, rc);
553 __checkReturn efx_rc_t
556 __in_ecount(n) efx_desc_t *ed,
558 __in unsigned int completed,
559 __inout unsigned int *addedp)
561 efx_nic_t *enp = etp->et_enp;
562 const efx_tx_ops_t *etxop = enp->en_etxop;
565 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
567 if ((rc = etxop->etxo_qdesc_post(etp, ed,
568 n, completed, addedp)) != 0)
574 EFSYS_PROBE1(fail1, efx_rc_t, rc);
579 efx_tx_qdesc_dma_create(
581 __in efsys_dma_addr_t addr,
584 __out efx_desc_t *edp)
586 efx_nic_t *enp = etp->et_enp;
587 const efx_tx_ops_t *etxop = enp->en_etxop;
589 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
590 EFSYS_ASSERT(etxop->etxo_qdesc_dma_create != NULL);
592 etxop->etxo_qdesc_dma_create(etp, addr, size, eop, edp);
596 efx_tx_qdesc_tso_create(
598 __in uint16_t ipv4_id,
599 __in uint32_t tcp_seq,
600 __in uint8_t tcp_flags,
601 __out efx_desc_t *edp)
603 efx_nic_t *enp = etp->et_enp;
604 const efx_tx_ops_t *etxop = enp->en_etxop;
606 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
607 EFSYS_ASSERT(etxop->etxo_qdesc_tso_create != NULL);
609 etxop->etxo_qdesc_tso_create(etp, ipv4_id, tcp_seq, tcp_flags, edp);
613 efx_tx_qdesc_tso2_create(
615 __in uint16_t ipv4_id,
616 __in uint32_t tcp_seq,
618 __out_ecount(count) efx_desc_t *edp,
621 efx_nic_t *enp = etp->et_enp;
622 const efx_tx_ops_t *etxop = enp->en_etxop;
624 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
625 EFSYS_ASSERT(etxop->etxo_qdesc_tso2_create != NULL);
627 etxop->etxo_qdesc_tso2_create(etp, ipv4_id, tcp_seq, mss, edp, count);
631 efx_tx_qdesc_vlantci_create(
634 __out efx_desc_t *edp)
636 efx_nic_t *enp = etp->et_enp;
637 const efx_tx_ops_t *etxop = enp->en_etxop;
639 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
640 EFSYS_ASSERT(etxop->etxo_qdesc_vlantci_create != NULL);
642 etxop->etxo_qdesc_vlantci_create(etp, tci, edp);
648 efx_tx_qstats_update(
650 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
652 efx_nic_t *enp = etp->et_enp;
653 const efx_tx_ops_t *etxop = enp->en_etxop;
655 EFSYS_ASSERT3U(etp->et_magic, ==, EFX_TXQ_MAGIC);
657 etxop->etxo_qstats_update(etp, stat);
664 static __checkReturn efx_rc_t
671 * Disable the timer-based TX DMA backoff and allow TX DMA to be
672 * controlled by the RX FIFO fill level (although always allow a
675 EFX_BAR_READO(enp, FR_AZ_TX_RESERVED_REG, &oword);
676 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER, 0xfe);
677 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_RX_SPACER_EN, 1);
678 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_ONE_PKT_PER_Q, 1);
679 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PUSH_EN, 0);
680 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DIS_NON_IP_EV, 1);
681 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_THRESHOLD, 2);
682 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_PREF_WD_TMR, 0x3fffff);
685 * Filter all packets less than 14 bytes to avoid parsing
688 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
689 EFX_BAR_WRITEO(enp, FR_AZ_TX_RESERVED_REG, &oword);
692 * Do not set TX_NO_EOP_DISC_EN, since it limits packets to 16
693 * descriptors (which is bad).
695 EFX_BAR_READO(enp, FR_AZ_TX_CFG_REG, &oword);
696 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
697 EFX_BAR_WRITEO(enp, FR_AZ_TX_CFG_REG, &oword);
702 #define EFX_TX_DESC(_etp, _addr, _size, _eop, _added) \
708 id = (_added)++ & (_etp)->et_mask; \
709 offset = id * sizeof (efx_qword_t); \
711 EFSYS_PROBE5(tx_post, unsigned int, (_etp)->et_index, \
712 unsigned int, id, efsys_dma_addr_t, (_addr), \
713 size_t, (_size), boolean_t, (_eop)); \
715 EFX_POPULATE_QWORD_4(qword, \
716 FSF_AZ_TX_KER_CONT, (_eop) ? 0 : 1, \
717 FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)(_size), \
718 FSF_AZ_TX_KER_BUF_ADDR_DW0, \
719 (uint32_t)((_addr) & 0xffffffff), \
720 FSF_AZ_TX_KER_BUF_ADDR_DW1, \
721 (uint32_t)((_addr) >> 32)); \
722 EFSYS_MEM_WRITEQ((_etp)->et_esmp, offset, &qword); \
724 _NOTE(CONSTANTCONDITION) \
727 static __checkReturn efx_rc_t
730 __in_ecount(n) efx_buffer_t *eb,
732 __in unsigned int completed,
733 __inout unsigned int *addedp)
735 unsigned int added = *addedp;
739 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1))
742 for (i = 0; i < n; i++) {
743 efx_buffer_t *ebp = &eb[i];
744 efsys_dma_addr_t start = ebp->eb_addr;
745 size_t size = ebp->eb_size;
746 efsys_dma_addr_t end = start + size;
748 /* Fragments must not span 4k boundaries. */
749 EFSYS_ASSERT(P2ROUNDUP(start + 1, 4096) >= end);
751 EFX_TX_DESC(etp, start, size, ebp->eb_eop, added);
754 EFX_TX_QSTAT_INCR(etp, TX_POST);
760 EFSYS_PROBE1(fail1, efx_rc_t, rc);
768 __in unsigned int added,
769 __in unsigned int pushed)
771 efx_nic_t *enp = etp->et_enp;
776 /* Push the populated descriptors out */
777 wptr = added & etp->et_mask;
779 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DESC_WPTR, wptr);
781 /* Only write the third DWORD */
782 EFX_POPULATE_DWORD_1(dword,
783 EFX_DWORD_0, EFX_OWORD_FIELD(oword, EFX_DWORD_3));
785 /* Guarantee ordering of memory (descriptors) and PIO (doorbell) */
786 EFX_DMA_SYNC_QUEUE_FOR_DEVICE(etp->et_esmp, etp->et_mask + 1,
787 wptr, pushed & etp->et_mask);
788 EFSYS_PIO_WRITE_BARRIER();
789 EFX_BAR_TBL_WRITED3(enp, FR_BZ_TX_DESC_UPD_REGP0,
790 etp->et_index, &dword, B_FALSE);
793 #define EFX_MAX_PACE_VALUE 20
795 static __checkReturn efx_rc_t
798 __in unsigned int ns)
800 efx_nic_t *enp = etp->et_enp;
801 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
803 unsigned int pace_val;
804 unsigned int timer_period;
811 * The pace_val to write into the table is s.t
812 * ns <= timer_period * (2 ^ pace_val)
814 timer_period = 104 / encp->enc_clk_mult;
815 for (pace_val = 1; pace_val <= EFX_MAX_PACE_VALUE; pace_val++) {
816 if ((timer_period << pace_val) >= ns)
820 if (pace_val > EFX_MAX_PACE_VALUE) {
825 /* Update the pacing table */
826 EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_PACE, pace_val);
827 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_PACE_TBL, etp->et_index,
833 EFSYS_PROBE1(fail1, efx_rc_t, rc);
838 static __checkReturn efx_rc_t
842 efx_nic_t *enp = etp->et_enp;
846 efx_tx_qpace(etp, 0);
848 label = etp->et_index;
850 /* Flush the queue */
851 EFX_POPULATE_OWORD_2(oword, FRF_AZ_TX_FLUSH_DESCQ_CMD, 1,
852 FRF_AZ_TX_FLUSH_DESCQ, label);
853 EFX_BAR_WRITEO(enp, FR_AZ_TX_FLUSH_DESCQ_REG, &oword);
862 efx_nic_t *enp = etp->et_enp;
865 EFX_BAR_TBL_READO(enp, FR_AZ_TX_DESC_PTR_TBL,
866 etp->et_index, &oword, B_TRUE);
868 EFSYS_PROBE5(tx_descq_ptr, unsigned int, etp->et_index,
869 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_3),
870 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_2),
871 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_1),
872 uint32_t, EFX_OWORD_FIELD(oword, EFX_DWORD_0));
874 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DC_HW_RPTR, 0);
875 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_HW_RPTR, 0);
876 EFX_SET_OWORD_FIELD(oword, FRF_AZ_TX_DESCQ_EN, 1);
878 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
879 etp->et_index, &oword, B_TRUE);
882 static __checkReturn efx_rc_t
885 __in unsigned int index,
886 __in unsigned int label,
887 __in efsys_mem_t *esmp,
893 __out unsigned int *addedp)
895 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
900 _NOTE(ARGUNUSED(esmp))
902 EFX_STATIC_ASSERT(EFX_EV_TX_NLABELS ==
903 (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH));
904 EFSYS_ASSERT3U(label, <, EFX_EV_TX_NLABELS);
906 EFSYS_ASSERT(ISP2(encp->enc_txq_max_ndescs));
907 EFX_STATIC_ASSERT(ISP2(EFX_TXQ_MINNDESCS));
909 if (!ISP2(n) || (n < EFX_TXQ_MINNDESCS) || (n > EFX_EVQ_MAXNEVS)) {
913 if (index >= encp->enc_txq_limit) {
918 (1 << size) <= (int)(encp->enc_txq_max_ndescs / EFX_TXQ_MINNDESCS);
920 if ((1 << size) == (int)(n / EFX_TXQ_MINNDESCS))
922 if (id + (1 << size) >= encp->enc_buftbl_limit) {
927 /* Set up the new descriptor queue */
930 EFX_POPULATE_OWORD_6(oword,
931 FRF_AZ_TX_DESCQ_BUF_BASE_ID, id,
932 FRF_AZ_TX_DESCQ_EVQ_ID, eep->ee_index,
933 FRF_AZ_TX_DESCQ_OWNER_ID, 0,
934 FRF_AZ_TX_DESCQ_LABEL, label,
935 FRF_AZ_TX_DESCQ_SIZE, size,
936 FRF_AZ_TX_DESCQ_TYPE, 0);
938 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_NON_IP_DROP_DIS, 1);
939 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_IP_CHKSM_DIS,
940 (flags & EFX_TXQ_CKSUM_IPV4) ? 0 : 1);
941 EFX_SET_OWORD_FIELD(oword, FRF_BZ_TX_TCP_CHKSM_DIS,
942 (flags & EFX_TXQ_CKSUM_TCPUDP) ? 0 : 1);
944 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
945 etp->et_index, &oword, B_TRUE);
954 EFSYS_PROBE1(fail1, efx_rc_t, rc);
959 __checkReturn efx_rc_t
962 __in_ecount(n) efx_desc_t *ed,
964 __in unsigned int completed,
965 __inout unsigned int *addedp)
967 unsigned int added = *addedp;
971 if (added - completed + n > EFX_TXQ_LIMIT(etp->et_mask + 1)) {
976 for (i = 0; i < n; i++) {
977 efx_desc_t *edp = &ed[i];
981 id = added++ & etp->et_mask;
982 offset = id * sizeof (efx_desc_t);
984 EFSYS_MEM_WRITEQ(etp->et_esmp, offset, &edp->ed_eq);
987 EFSYS_PROBE3(tx_desc_post, unsigned int, etp->et_index,
988 unsigned int, added, unsigned int, n);
990 EFX_TX_QSTAT_INCR(etp, TX_POST);
996 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1001 siena_tx_qdesc_dma_create(
1002 __in efx_txq_t *etp,
1003 __in efsys_dma_addr_t addr,
1006 __out efx_desc_t *edp)
1008 /* Fragments must not span 4k boundaries. */
1009 EFSYS_ASSERT(P2ROUNDUP(addr + 1, 4096) >= addr + size);
1011 EFSYS_PROBE4(tx_desc_dma_create, unsigned int, etp->et_index,
1012 efsys_dma_addr_t, addr,
1013 size_t, size, boolean_t, eop);
1015 EFX_POPULATE_QWORD_4(edp->ed_eq,
1016 FSF_AZ_TX_KER_CONT, eop ? 0 : 1,
1017 FSF_AZ_TX_KER_BYTE_COUNT, (uint32_t)size,
1018 FSF_AZ_TX_KER_BUF_ADDR_DW0,
1019 (uint32_t)(addr & 0xffffffff),
1020 FSF_AZ_TX_KER_BUF_ADDR_DW1,
1021 (uint32_t)(addr >> 32));
1024 #endif /* EFSYS_OPT_SIENA */
1026 #if EFSYS_OPT_QSTATS
1028 /* START MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock 2866874ecd7a363b */
1029 static const char * const __efx_tx_qstat_name[] = {
1033 /* END MKCONFIG GENERATED EfxTransmitQueueStatNamesBlock */
1037 __in efx_nic_t *enp,
1038 __in unsigned int id)
1040 _NOTE(ARGUNUSED(enp))
1041 EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1042 EFSYS_ASSERT3U(id, <, TX_NQSTATS);
1044 return (__efx_tx_qstat_name[id]);
1046 #endif /* EFSYS_OPT_NAMES */
1047 #endif /* EFSYS_OPT_QSTATS */
1051 #if EFSYS_OPT_QSTATS
1053 siena_tx_qstats_update(
1054 __in efx_txq_t *etp,
1055 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat)
1059 for (id = 0; id < TX_NQSTATS; id++) {
1060 efsys_stat_t *essp = &stat[id];
1062 EFSYS_STAT_INCR(essp, etp->et_stat[id]);
1063 etp->et_stat[id] = 0;
1066 #endif /* EFSYS_OPT_QSTATS */
1070 __in efx_txq_t *etp)
1072 efx_nic_t *enp = etp->et_enp;
1075 /* Purge descriptor queue */
1076 EFX_ZERO_OWORD(oword);
1078 EFX_BAR_TBL_WRITEO(enp, FR_AZ_TX_DESC_PTR_TBL,
1079 etp->et_index, &oword, B_TRUE);
1084 __in efx_nic_t *enp)
1086 _NOTE(ARGUNUSED(enp))
1089 #endif /* EFSYS_OPT_SIENA */