4 * Copyright (c) 2016 Solarflare Communications Inc.
7 * This software was jointly developed between OKTET Labs (under contract
8 * for Solarflare) and Solarflare Communications, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
29 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 /* EF10 native datapath implementation */
36 #include <rte_byteorder.h>
37 #include <rte_mbuf_ptype.h>
42 #include "efx_types.h"
44 #include "efx_regs_ef10.h"
46 #include "sfc_tweak.h"
47 #include "sfc_dp_rx.h"
48 #include "sfc_kvargs.h"
51 #define sfc_ef10_rx_err(dpq, ...) \
52 SFC_DP_LOG(SFC_KVARG_DATAPATH_EF10, ERR, dpq, __VA_ARGS__)
55 * Alignment requirement for value written to RX WPTR:
56 * the WPTR must be aligned to an 8 descriptor boundary.
58 #define SFC_EF10_RX_WPTR_ALIGN 8
61 * Maximum number of descriptors/buffers in the Rx ring.
62 * It should guarantee that corresponding event queue never overfill.
63 * EF10 native datapath uses event queue of the same size as Rx queue.
64 * Maximum number of events on datapath can be estimated as number of
65 * Rx queue entries (one event per Rx buffer in the worst case) plus
66 * Rx error and flush events.
68 #define SFC_EF10_RXQ_LIMIT(_ndesc) \
69 ((_ndesc) - 1 /* head must not step on tail */ - \
70 (SFC_EF10_EV_PER_CACHE_LINE - 1) /* max unused EvQ entries */ - \
71 1 /* Rx error */ - 1 /* flush */)
73 struct sfc_ef10_rx_sw_desc {
74 struct rte_mbuf *mbuf;
78 /* Used on data path */
80 #define SFC_EF10_RXQ_STARTED 0x1
81 #define SFC_EF10_RXQ_NOT_RUNNING 0x2
82 #define SFC_EF10_RXQ_EXCEPTION 0x4
83 #define SFC_EF10_RXQ_RSS_HASH 0x8
84 unsigned int ptr_mask;
85 unsigned int prepared;
86 unsigned int completed;
87 unsigned int evq_read_ptr;
88 efx_qword_t *evq_hw_ring;
89 struct sfc_ef10_rx_sw_desc *sw_ring;
96 unsigned int refill_threshold;
97 struct rte_mempool *refill_mb_pool;
98 efx_qword_t *rxq_hw_ring;
99 volatile void *doorbell;
101 /* Datapath receive queue anchor */
102 struct sfc_dp_rxq dp;
105 static inline struct sfc_ef10_rxq *
106 sfc_ef10_rxq_by_dp_rxq(struct sfc_dp_rxq *dp_rxq)
108 return container_of(dp_rxq, struct sfc_ef10_rxq, dp);
112 sfc_ef10_rx_qpush(struct sfc_ef10_rxq *rxq)
116 /* Hardware has alignment restriction for WPTR */
117 RTE_BUILD_BUG_ON(SFC_RX_REFILL_BULK % SFC_EF10_RX_WPTR_ALIGN != 0);
118 SFC_ASSERT(RTE_ALIGN(rxq->added, SFC_EF10_RX_WPTR_ALIGN) == rxq->added);
120 EFX_POPULATE_DWORD_1(dword, ERF_DZ_RX_DESC_WPTR,
121 rxq->added & rxq->ptr_mask);
123 /* DMA sync to device is not required */
126 * rte_write32() has rte_io_wmb() which guarantees that the STORE
127 * operations (i.e. Rx and event descriptor updates) that precede
128 * the rte_io_wmb() call are visible to NIC before the STORE
129 * operations that follow it (i.e. doorbell write).
131 rte_write32(dword.ed_u32[0], rxq->doorbell);
135 sfc_ef10_rx_qrefill(struct sfc_ef10_rxq *rxq)
137 const unsigned int ptr_mask = rxq->ptr_mask;
138 const uint32_t buf_size = rxq->buf_size;
139 unsigned int free_space;
141 void *objs[SFC_RX_REFILL_BULK];
142 unsigned int added = rxq->added;
144 free_space = SFC_EF10_RXQ_LIMIT(ptr_mask + 1) -
145 (added - rxq->completed);
147 if (free_space < rxq->refill_threshold)
150 bulks = free_space / RTE_DIM(objs);
151 /* refill_threshold guarantees that bulks is positive */
152 SFC_ASSERT(bulks > 0);
158 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
159 RTE_DIM(objs)) < 0)) {
160 struct rte_eth_dev_data *dev_data =
161 rte_eth_devices[rxq->dp.dpq.port_id].data;
164 * It is hardly a safe way to increment counter
165 * from different contexts, but all PMDs do it.
167 dev_data->rx_mbuf_alloc_failed += RTE_DIM(objs);
168 /* Return if we have posted nothing yet */
169 if (added == rxq->added)
175 for (i = 0, id = added & ptr_mask;
178 struct rte_mbuf *m = objs[i];
179 struct sfc_ef10_rx_sw_desc *rxd;
180 rte_iova_t phys_addr;
182 SFC_ASSERT((id & ~ptr_mask) == 0);
183 rxd = &rxq->sw_ring[id];
187 * Avoid writing to mbuf. It is cheaper to do it
188 * when we receive packet and fill in nearby
192 phys_addr = rte_mbuf_data_iova_default(m);
193 EFX_POPULATE_QWORD_2(rxq->rxq_hw_ring[id],
194 ESF_DZ_RX_KER_BYTE_CNT, buf_size,
195 ESF_DZ_RX_KER_BUF_ADDR, phys_addr);
198 added += RTE_DIM(objs);
199 } while (--bulks > 0);
201 SFC_ASSERT(rxq->added != added);
203 sfc_ef10_rx_qpush(rxq);
207 sfc_ef10_rx_prefetch_next(struct sfc_ef10_rxq *rxq, unsigned int next_id)
209 struct rte_mbuf *next_mbuf;
211 /* Prefetch next bunch of software descriptors */
212 if ((next_id % (RTE_CACHE_LINE_SIZE / sizeof(rxq->sw_ring[0]))) == 0)
213 rte_prefetch0(&rxq->sw_ring[next_id]);
216 * It looks strange to prefetch depending on previous prefetch
217 * data, but measurements show that it is really efficient and
218 * increases packet rate.
220 next_mbuf = rxq->sw_ring[next_id].mbuf;
221 if (likely(next_mbuf != NULL)) {
222 /* Prefetch the next mbuf structure */
223 rte_mbuf_prefetch_part1(next_mbuf);
225 /* Prefetch pseudo header of the next packet */
226 /* data_off is not filled in yet */
227 /* Yes, data could be not ready yet, but we hope */
228 rte_prefetch0((uint8_t *)next_mbuf->buf_addr +
229 RTE_PKTMBUF_HEADROOM);
234 sfc_ef10_rx_prepared(struct sfc_ef10_rxq *rxq, struct rte_mbuf **rx_pkts,
237 uint16_t n_rx_pkts = RTE_MIN(nb_pkts, rxq->prepared);
238 unsigned int completed = rxq->completed;
241 rxq->prepared -= n_rx_pkts;
242 rxq->completed = completed + n_rx_pkts;
244 for (i = 0; i < n_rx_pkts; ++i, ++completed)
245 rx_pkts[i] = rxq->sw_ring[completed & rxq->ptr_mask].mbuf;
251 sfc_ef10_rx_ev_to_offloads(struct sfc_ef10_rxq *rxq, const efx_qword_t rx_ev,
254 uint32_t tun_ptype = 0;
255 uint32_t l2_ptype = 0;
256 uint32_t l3_ptype = 0;
257 uint32_t l4_ptype = 0;
258 uint64_t ol_flags = 0;
260 if (unlikely(EFX_TEST_QWORD_BIT(rx_ev, ESF_DZ_RX_PARSE_INCOMPLETE_LBN)))
263 switch (EFX_QWORD_FIELD(rx_ev, ESF_EZ_RX_ENCAP_HDR)) {
265 /* Unexpected encapsulation tag class */
268 case ESE_EZ_ENCAP_HDR_NONE:
270 case ESE_EZ_ENCAP_HDR_VXLAN:
272 * It is definitely UDP, but we have no information
273 * about IPv4 vs IPv6 and VLAN tagging.
275 tun_ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP;
277 case ESE_EZ_ENCAP_HDR_GRE:
279 * We have no information about IPv4 vs IPv6 and VLAN tagging.
281 tun_ptype = RTE_PTYPE_TUNNEL_NVGRE;
285 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_ETH_TAG_CLASS)) {
286 case ESE_DZ_ETH_TAG_CLASS_NONE:
287 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER :
288 RTE_PTYPE_INNER_L2_ETHER;
290 case ESE_DZ_ETH_TAG_CLASS_VLAN1:
291 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_VLAN :
292 RTE_PTYPE_INNER_L2_ETHER_VLAN;
294 case ESE_DZ_ETH_TAG_CLASS_VLAN2:
295 l2_ptype = (tun_ptype == 0) ? RTE_PTYPE_L2_ETHER_QINQ :
296 RTE_PTYPE_INNER_L2_ETHER_QINQ;
299 /* Unexpected Eth tag class */
303 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L3_CLASS)) {
304 case ESE_DZ_L3_CLASS_IP4_FRAG:
305 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
306 RTE_PTYPE_INNER_L4_FRAG;
308 case ESE_DZ_L3_CLASS_IP4:
309 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV4_EXT_UNKNOWN :
310 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
311 ol_flags |= PKT_RX_RSS_HASH |
312 ((EFX_TEST_QWORD_BIT(rx_ev,
313 ESF_DZ_RX_IPCKSUM_ERR_LBN)) ?
314 PKT_RX_IP_CKSUM_BAD : PKT_RX_IP_CKSUM_GOOD);
316 case ESE_DZ_L3_CLASS_IP6_FRAG:
317 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_FRAG :
318 RTE_PTYPE_INNER_L4_FRAG;
320 case ESE_DZ_L3_CLASS_IP6:
321 l3_ptype = (tun_ptype == 0) ? RTE_PTYPE_L3_IPV6_EXT_UNKNOWN :
322 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
323 ol_flags |= PKT_RX_RSS_HASH;
325 case ESE_DZ_L3_CLASS_ARP:
326 /* Override Layer 2 packet type */
327 /* There is no ARP classification for inner packets */
329 l2_ptype = RTE_PTYPE_L2_ETHER_ARP;
332 /* Unexpected Layer 3 class */
336 switch (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_L4_CLASS)) {
337 case ESE_DZ_L4_CLASS_TCP:
338 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_TCP :
339 RTE_PTYPE_INNER_L4_TCP;
341 (EFX_TEST_QWORD_BIT(rx_ev,
342 ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN)) ?
343 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
345 case ESE_DZ_L4_CLASS_UDP:
346 l4_ptype = (tun_ptype == 0) ? RTE_PTYPE_L4_UDP :
347 RTE_PTYPE_INNER_L4_UDP;
349 (EFX_TEST_QWORD_BIT(rx_ev,
350 ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN)) ?
351 PKT_RX_L4_CKSUM_BAD : PKT_RX_L4_CKSUM_GOOD;
353 case ESE_DZ_L4_CLASS_UNKNOWN:
356 /* Unexpected Layer 4 class */
360 /* Remove RSS hash offload flag if RSS is not enabled */
361 if (~rxq->flags & SFC_EF10_RXQ_RSS_HASH)
362 ol_flags &= ~PKT_RX_RSS_HASH;
365 m->ol_flags = ol_flags;
366 m->packet_type = tun_ptype | l2_ptype | l3_ptype | l4_ptype;
370 sfc_ef10_rx_pseudo_hdr_get_len(const uint8_t *pseudo_hdr)
372 return rte_le_to_cpu_16(*(const uint16_t *)&pseudo_hdr[8]);
376 sfc_ef10_rx_pseudo_hdr_get_hash(const uint8_t *pseudo_hdr)
378 return rte_le_to_cpu_32(*(const uint32_t *)pseudo_hdr);
382 sfc_ef10_rx_process_event(struct sfc_ef10_rxq *rxq, efx_qword_t rx_ev,
383 struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
385 const unsigned int ptr_mask = rxq->ptr_mask;
386 unsigned int completed = rxq->completed;
388 struct sfc_ef10_rx_sw_desc *rxd;
392 const uint8_t *pseudo_hdr;
395 ready = (EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_DSC_PTR_LBITS) - completed) &
396 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
397 SFC_ASSERT(ready > 0);
399 if (rx_ev.eq_u64[0] &
400 rte_cpu_to_le_64((1ull << ESF_DZ_RX_ECC_ERR_LBN) |
401 (1ull << ESF_DZ_RX_ECRC_ERR_LBN))) {
402 SFC_ASSERT(rxq->prepared == 0);
403 rxq->completed += ready;
404 while (ready-- > 0) {
405 rxd = &rxq->sw_ring[completed++ & ptr_mask];
406 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
411 n_rx_pkts = RTE_MIN(ready, nb_pkts);
412 rxq->prepared = ready - n_rx_pkts;
413 rxq->completed += n_rx_pkts;
415 rxd = &rxq->sw_ring[completed++ & ptr_mask];
417 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
423 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) != sizeof(rxq->rearm_data));
424 m->rearm_data[0] = rxq->rearm_data;
426 /* Classify packet based on Rx event */
427 sfc_ef10_rx_ev_to_offloads(rxq, rx_ev, m);
429 /* data_off already moved past pseudo header */
430 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
433 * Always get RSS hash from pseudo header to avoid
434 * condition/branching. If it is valid or not depends on
435 * PKT_RX_RSS_HASH in m->ol_flags.
437 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
440 pkt_len = EFX_QWORD_FIELD(rx_ev, ESF_DZ_RX_BYTES) -
443 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
444 SFC_ASSERT(pkt_len > 0);
445 rte_pktmbuf_data_len(m) = pkt_len;
446 rte_pktmbuf_pkt_len(m) = pkt_len;
448 SFC_ASSERT(m->next == NULL);
450 /* Remember mbuf to copy offload flags and packet type from */
452 for (--ready; ready > 0; --ready) {
453 rxd = &rxq->sw_ring[completed++ & ptr_mask];
455 sfc_ef10_rx_prefetch_next(rxq, completed & ptr_mask);
459 if (ready > rxq->prepared)
462 RTE_BUILD_BUG_ON(sizeof(m->rearm_data[0]) !=
463 sizeof(rxq->rearm_data));
464 m->rearm_data[0] = rxq->rearm_data;
466 /* Event-dependent information is the same */
467 m->ol_flags = m0->ol_flags;
468 m->packet_type = m0->packet_type;
470 /* data_off already moved past pseudo header */
471 pseudo_hdr = (uint8_t *)m->buf_addr + RTE_PKTMBUF_HEADROOM;
474 * Always get RSS hash from pseudo header to avoid
475 * condition/branching. If it is valid or not depends on
476 * PKT_RX_RSS_HASH in m->ol_flags.
478 m->hash.rss = sfc_ef10_rx_pseudo_hdr_get_hash(pseudo_hdr);
480 pkt_len = sfc_ef10_rx_pseudo_hdr_get_len(pseudo_hdr);
481 SFC_ASSERT(pkt_len > 0);
482 rte_pktmbuf_data_len(m) = pkt_len;
483 rte_pktmbuf_pkt_len(m) = pkt_len;
485 SFC_ASSERT(m->next == NULL);
492 sfc_ef10_rx_get_event(struct sfc_ef10_rxq *rxq, efx_qword_t *rx_ev)
494 *rx_ev = rxq->evq_hw_ring[rxq->evq_read_ptr & rxq->ptr_mask];
496 if (!sfc_ef10_ev_present(*rx_ev))
499 if (unlikely(EFX_QWORD_FIELD(*rx_ev, FSF_AZ_EV_CODE) !=
500 FSE_AZ_EV_CODE_RX_EV)) {
502 * Do not move read_ptr to keep the event for exception
503 * handling by the control path.
505 rxq->flags |= SFC_EF10_RXQ_EXCEPTION;
506 sfc_ef10_rx_err(&rxq->dp.dpq,
507 "RxQ exception at EvQ read ptr %#x",
517 sfc_ef10_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
519 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(rx_queue);
520 unsigned int evq_old_read_ptr;
524 if (unlikely(rxq->flags &
525 (SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION)))
528 n_rx_pkts = sfc_ef10_rx_prepared(rxq, rx_pkts, nb_pkts);
530 evq_old_read_ptr = rxq->evq_read_ptr;
531 while (n_rx_pkts != nb_pkts && sfc_ef10_rx_get_event(rxq, &rx_ev)) {
533 * DROP_EVENT is an internal to the NIC, software should
534 * never see it and, therefore, may ignore it.
537 n_rx_pkts += sfc_ef10_rx_process_event(rxq, rx_ev,
539 nb_pkts - n_rx_pkts);
542 sfc_ef10_ev_qclear(rxq->evq_hw_ring, rxq->ptr_mask, evq_old_read_ptr,
545 /* It is not a problem if we refill in the case of exception */
546 sfc_ef10_rx_qrefill(rxq);
551 static const uint32_t *
552 sfc_ef10_supported_ptypes_get(uint32_t tunnel_encaps)
554 static const uint32_t ef10_native_ptypes[] = {
556 RTE_PTYPE_L2_ETHER_ARP,
557 RTE_PTYPE_L2_ETHER_VLAN,
558 RTE_PTYPE_L2_ETHER_QINQ,
559 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
560 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
566 static const uint32_t ef10_overlay_ptypes[] = {
568 RTE_PTYPE_L2_ETHER_ARP,
569 RTE_PTYPE_L2_ETHER_VLAN,
570 RTE_PTYPE_L2_ETHER_QINQ,
571 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
572 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
576 RTE_PTYPE_TUNNEL_VXLAN,
577 RTE_PTYPE_TUNNEL_NVGRE,
578 RTE_PTYPE_INNER_L2_ETHER,
579 RTE_PTYPE_INNER_L2_ETHER_VLAN,
580 RTE_PTYPE_INNER_L2_ETHER_QINQ,
581 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
582 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
583 RTE_PTYPE_INNER_L4_FRAG,
584 RTE_PTYPE_INNER_L4_TCP,
585 RTE_PTYPE_INNER_L4_UDP,
590 * The function returns static set of supported packet types,
591 * so we can't build it dynamically based on supported tunnel
592 * encapsulations and should limit to known sets.
594 switch (tunnel_encaps) {
595 case (1u << EFX_TUNNEL_PROTOCOL_VXLAN |
596 1u << EFX_TUNNEL_PROTOCOL_GENEVE |
597 1u << EFX_TUNNEL_PROTOCOL_NVGRE):
598 return ef10_overlay_ptypes;
601 "Unexpected set of supported tunnel encapsulations: %#x\n",
605 return ef10_native_ptypes;
609 static sfc_dp_rx_qdesc_npending_t sfc_ef10_rx_qdesc_npending;
611 sfc_ef10_rx_qdesc_npending(__rte_unused struct sfc_dp_rxq *dp_rxq)
614 * Correct implementation requires EvQ polling and events
615 * processing (keeping all ready mbufs in prepared).
620 static sfc_dp_rx_qdesc_status_t sfc_ef10_rx_qdesc_status;
622 sfc_ef10_rx_qdesc_status(__rte_unused struct sfc_dp_rxq *dp_rxq,
623 __rte_unused uint16_t offset)
630 sfc_ef10_mk_mbuf_rearm_data(uint16_t port_id, uint16_t prefix_size)
634 memset(&m, 0, sizeof(m));
636 rte_mbuf_refcnt_set(&m, 1);
637 m.data_off = RTE_PKTMBUF_HEADROOM + prefix_size;
641 /* rearm_data covers structure members filled in above */
642 rte_compiler_barrier();
643 RTE_BUILD_BUG_ON(sizeof(m.rearm_data[0]) != sizeof(uint64_t));
644 return m.rearm_data[0];
647 static sfc_dp_rx_qcreate_t sfc_ef10_rx_qcreate;
649 sfc_ef10_rx_qcreate(uint16_t port_id, uint16_t queue_id,
650 const struct rte_pci_addr *pci_addr, int socket_id,
651 const struct sfc_dp_rx_qcreate_info *info,
652 struct sfc_dp_rxq **dp_rxqp)
654 struct sfc_ef10_rxq *rxq;
658 if (info->rxq_entries != info->evq_entries)
662 rxq = rte_zmalloc_socket("sfc-ef10-rxq", sizeof(*rxq),
663 RTE_CACHE_LINE_SIZE, socket_id);
667 sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
670 rxq->sw_ring = rte_calloc_socket("sfc-ef10-rxq-sw_ring",
672 sizeof(*rxq->sw_ring),
673 RTE_CACHE_LINE_SIZE, socket_id);
674 if (rxq->sw_ring == NULL)
675 goto fail_desc_alloc;
677 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
678 if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
679 rxq->flags |= SFC_EF10_RXQ_RSS_HASH;
680 rxq->ptr_mask = info->rxq_entries - 1;
681 rxq->evq_hw_ring = info->evq_hw_ring;
682 rxq->refill_threshold = info->refill_threshold;
684 sfc_ef10_mk_mbuf_rearm_data(port_id, info->prefix_size);
685 rxq->prefix_size = info->prefix_size;
686 rxq->buf_size = info->buf_size;
687 rxq->refill_mb_pool = info->refill_mb_pool;
688 rxq->rxq_hw_ring = info->rxq_hw_ring;
689 rxq->doorbell = (volatile uint8_t *)info->mem_bar +
690 ER_DZ_RX_DESC_UPD_REG_OFST +
691 info->hw_index * ER_DZ_RX_DESC_UPD_REG_STEP;
704 static sfc_dp_rx_qdestroy_t sfc_ef10_rx_qdestroy;
706 sfc_ef10_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
708 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
710 rte_free(rxq->sw_ring);
714 static sfc_dp_rx_qstart_t sfc_ef10_rx_qstart;
716 sfc_ef10_rx_qstart(struct sfc_dp_rxq *dp_rxq, unsigned int evq_read_ptr)
718 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
721 rxq->completed = rxq->added = 0;
723 sfc_ef10_rx_qrefill(rxq);
725 rxq->evq_read_ptr = evq_read_ptr;
727 rxq->flags |= SFC_EF10_RXQ_STARTED;
728 rxq->flags &= ~(SFC_EF10_RXQ_NOT_RUNNING | SFC_EF10_RXQ_EXCEPTION);
733 static sfc_dp_rx_qstop_t sfc_ef10_rx_qstop;
735 sfc_ef10_rx_qstop(struct sfc_dp_rxq *dp_rxq, unsigned int *evq_read_ptr)
737 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
739 rxq->flags |= SFC_EF10_RXQ_NOT_RUNNING;
741 *evq_read_ptr = rxq->evq_read_ptr;
744 static sfc_dp_rx_qrx_ev_t sfc_ef10_rx_qrx_ev;
746 sfc_ef10_rx_qrx_ev(struct sfc_dp_rxq *dp_rxq, __rte_unused unsigned int id)
748 __rte_unused struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
750 SFC_ASSERT(rxq->flags & SFC_EF10_RXQ_NOT_RUNNING);
753 * It is safe to ignore Rx event since we free all mbufs on
754 * queue purge anyway.
760 static sfc_dp_rx_qpurge_t sfc_ef10_rx_qpurge;
762 sfc_ef10_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
764 struct sfc_ef10_rxq *rxq = sfc_ef10_rxq_by_dp_rxq(dp_rxq);
766 struct sfc_ef10_rx_sw_desc *rxd;
768 for (i = rxq->completed; i != rxq->added; ++i) {
769 rxd = &rxq->sw_ring[i & rxq->ptr_mask];
770 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
774 rxq->flags &= ~SFC_EF10_RXQ_STARTED;
777 struct sfc_dp_rx sfc_ef10_rx = {
779 .name = SFC_KVARG_DATAPATH_EF10,
781 .hw_fw_caps = SFC_DP_HW_FW_CAP_EF10,
783 .features = SFC_DP_RX_FEAT_MULTI_PROCESS |
784 SFC_DP_RX_FEAT_TUNNELS,
785 .qcreate = sfc_ef10_rx_qcreate,
786 .qdestroy = sfc_ef10_rx_qdestroy,
787 .qstart = sfc_ef10_rx_qstart,
788 .qstop = sfc_ef10_rx_qstop,
789 .qrx_ev = sfc_ef10_rx_qrx_ev,
790 .qpurge = sfc_ef10_rx_qpurge,
791 .supported_ptypes_get = sfc_ef10_supported_ptypes_get,
792 .qdesc_npending = sfc_ef10_rx_qdesc_npending,
793 .qdesc_status = sfc_ef10_rx_qdesc_status,
794 .pkt_burst = sfc_ef10_recv_pkts,