drivers/net/sfc/sfc_rx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  * Copyright (c) 2016-2017 Solarflare Communications Inc.
   5  * All rights reserved.
   6  *
   7  * This software was jointly developed between OKTET Labs (under contract
   8  * for Solarflare) and Solarflare Communications, Inc.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are met:
  12  *
  13  * 1. Redistributions of source code must retain the above copyright notice,
  14  *    this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright notice,
  16  *    this list of conditions and the following disclaimer in the documentation
  17  *    and/or other materials provided with the distribution.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  21  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  22  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  23  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  24  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  25  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  26  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  27  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  28  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  29  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include <rte_mempool.h>
  33
  34 #include "efx.h"
  35
  36 #include "sfc.h"
  37 #include "sfc_debug.h"
  38 #include "sfc_log.h"
  39 #include "sfc_ev.h"
  40 #include "sfc_rx.h"
  41 #include "sfc_kvargs.h"
  42 #include "sfc_tweak.h"
  43
  44 /*
  45  * Maximum number of Rx queue flush attempt in the case of failure or
  46  * flush timeout
  47  */
  48 #define SFC_RX_QFLUSH_ATTEMPTS          (3)
  49
  50 /*
  51  * Time to wait between event queue polling attempts when waiting for Rx
  52  * queue flush done or failed events.
  53  */
  54 #define SFC_RX_QFLUSH_POLL_WAIT_MS      (1)
  55
  56 /*
  57  * Maximum number of event queue polling attempts when waiting for Rx queue
  58  * flush done or failed events. It defines Rx queue flush attempt timeout
  59  * together with SFC_RX_QFLUSH_POLL_WAIT_MS.
  60  */
  61 #define SFC_RX_QFLUSH_POLL_ATTEMPTS     (2000)
  62
  63 void
  64 sfc_rx_qflush_done(struct sfc_rxq *rxq)
  65 {
  66         rxq->state |= SFC_RXQ_FLUSHED;
  67         rxq->state &= ~SFC_RXQ_FLUSHING;
  68 }
  69
  70 void
  71 sfc_rx_qflush_failed(struct sfc_rxq *rxq)
  72 {
  73         rxq->state |= SFC_RXQ_FLUSH_FAILED;
  74         rxq->state &= ~SFC_RXQ_FLUSHING;
  75 }
  76
  77 static void
  78 sfc_efx_rx_qrefill(struct sfc_efx_rxq *rxq)
  79 {
  80         unsigned int free_space;
  81         unsigned int bulks;
  82         void *objs[SFC_RX_REFILL_BULK];
  83         efsys_dma_addr_t addr[RTE_DIM(objs)];
  84         unsigned int added = rxq->added;
  85         unsigned int id;
  86         unsigned int i;
  87         struct sfc_efx_rx_sw_desc *rxd;
  88         struct rte_mbuf *m;
  89         uint16_t port_id = rxq->dp.dpq.port_id;
  90
  91         free_space = EFX_RXQ_LIMIT(rxq->ptr_mask + 1) -
  92                 (added - rxq->completed);
  93
  94         if (free_space < rxq->refill_threshold)
  95                 return;
  96
  97         bulks = free_space / RTE_DIM(objs);
  98         /* refill_threshold guarantees that bulks is positive */
  99         SFC_ASSERT(bulks > 0);
 100
 101         id = added & rxq->ptr_mask;
 102         do {
 103                 if (unlikely(rte_mempool_get_bulk(rxq->refill_mb_pool, objs,
 104                                                   RTE_DIM(objs)) < 0)) {
 105                         /*
 106                          * It is hardly a safe way to increment counter
 107                          * from different contexts, but all PMDs do it.
 108                          */
 109                         rxq->evq->sa->eth_dev->data->rx_mbuf_alloc_failed +=
 110                                 RTE_DIM(objs);
 111                         /* Return if we have posted nothing yet */
 112                         if (added == rxq->added)
 113                                 return;
 114                         /* Push posted */
 115                         break;
 116                 }
 117
 118                 for (i = 0; i < RTE_DIM(objs);
 119                      ++i, id = (id + 1) & rxq->ptr_mask) {
 120                         m = objs[i];
 121
 122                         rxd = &rxq->sw_desc[id];
 123                         rxd->mbuf = m;
 124
 125                         rte_mbuf_refcnt_set(m, 1);
 126                         m->data_off = RTE_PKTMBUF_HEADROOM;
 127                         m->next = NULL;
 128                         m->nb_segs = 1;
 129                         m->port = port_id;
 130
 131                         addr[i] = rte_pktmbuf_mtophys(m);
 132                 }
 133
 134                 efx_rx_qpost(rxq->common, addr, rxq->buf_size,
 135                              RTE_DIM(objs), rxq->completed, added);
 136                 added += RTE_DIM(objs);
 137         } while (--bulks > 0);
 138
 139         SFC_ASSERT(added != rxq->added);
 140         rxq->added = added;
 141         efx_rx_qpush(rxq->common, added, &rxq->pushed);
 142 }
 143
 144 static uint64_t
 145 sfc_efx_rx_desc_flags_to_offload_flags(const unsigned int desc_flags)
 146 {
 147         uint64_t mbuf_flags = 0;
 148
 149         switch (desc_flags & (EFX_PKT_IPV4 | EFX_CKSUM_IPV4)) {
 150         case (EFX_PKT_IPV4 | EFX_CKSUM_IPV4):
 151                 mbuf_flags |= PKT_RX_IP_CKSUM_GOOD;
 152                 break;
 153         case EFX_PKT_IPV4:
 154                 mbuf_flags |= PKT_RX_IP_CKSUM_BAD;
 155                 break;
 156         default:
 157                 RTE_BUILD_BUG_ON(PKT_RX_IP_CKSUM_UNKNOWN != 0);
 158                 SFC_ASSERT((mbuf_flags & PKT_RX_IP_CKSUM_MASK) ==
 159                            PKT_RX_IP_CKSUM_UNKNOWN);
 160                 break;
 161         }
 162
 163         switch ((desc_flags &
 164                  (EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP))) {
 165         case (EFX_PKT_TCP | EFX_CKSUM_TCPUDP):
 166         case (EFX_PKT_UDP | EFX_CKSUM_TCPUDP):
 167                 mbuf_flags |= PKT_RX_L4_CKSUM_GOOD;
 168                 break;
 169         case EFX_PKT_TCP:
 170         case EFX_PKT_UDP:
 171                 mbuf_flags |= PKT_RX_L4_CKSUM_BAD;
 172                 break;
 173         default:
 174                 RTE_BUILD_BUG_ON(PKT_RX_L4_CKSUM_UNKNOWN != 0);
 175                 SFC_ASSERT((mbuf_flags & PKT_RX_L4_CKSUM_MASK) ==
 176                            PKT_RX_L4_CKSUM_UNKNOWN);
 177                 break;
 178         }
 179
 180         return mbuf_flags;
 181 }
 182
 183 static uint32_t
 184 sfc_efx_rx_desc_flags_to_packet_type(const unsigned int desc_flags)
 185 {
 186         return RTE_PTYPE_L2_ETHER |
 187                 ((desc_flags & EFX_PKT_IPV4) ?
 188                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN : 0) |
 189                 ((desc_flags & EFX_PKT_IPV6) ?
 190                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN : 0) |
 191                 ((desc_flags & EFX_PKT_TCP) ? RTE_PTYPE_L4_TCP : 0) |
 192                 ((desc_flags & EFX_PKT_UDP) ? RTE_PTYPE_L4_UDP : 0);
 193 }
 194
 195 static const uint32_t *
 196 sfc_efx_supported_ptypes_get(void)
 197 {
 198         static const uint32_t ptypes[] = {
 199                 RTE_PTYPE_L2_ETHER,
 200                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
 201                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
 202                 RTE_PTYPE_L4_TCP,
 203                 RTE_PTYPE_L4_UDP,
 204                 RTE_PTYPE_UNKNOWN
 205         };
 206
 207         return ptypes;
 208 }
 209
 210 static void
 211 sfc_efx_rx_set_rss_hash(struct sfc_efx_rxq *rxq, unsigned int flags,
 212                         struct rte_mbuf *m)
 213 {
 214 #if EFSYS_OPT_RX_SCALE
 215         uint8_t *mbuf_data;
 216
 217
 218         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RSS_HASH) == 0)
 219                 return;
 220
 221         mbuf_data = rte_pktmbuf_mtod(m, uint8_t *);
 222
 223         if (flags & (EFX_PKT_IPV4 | EFX_PKT_IPV6)) {
 224                 m->hash.rss = efx_pseudo_hdr_hash_get(rxq->common,
 225                                                       EFX_RX_HASHALG_TOEPLITZ,
 226                                                       mbuf_data);
 227
 228                 m->ol_flags |= PKT_RX_RSS_HASH;
 229         }
 230 #endif
 231 }
 232
 233 static uint16_t
 234 sfc_efx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 235 {
 236         struct sfc_dp_rxq *dp_rxq = rx_queue;
 237         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 238         unsigned int completed;
 239         unsigned int prefix_size = rxq->prefix_size;
 240         unsigned int done_pkts = 0;
 241         boolean_t discard_next = B_FALSE;
 242         struct rte_mbuf *scatter_pkt = NULL;
 243
 244         if (unlikely((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0))
 245                 return 0;
 246
 247         sfc_ev_qpoll(rxq->evq);
 248
 249         completed = rxq->completed;
 250         while (completed != rxq->pending && done_pkts < nb_pkts) {
 251                 unsigned int id;
 252                 struct sfc_efx_rx_sw_desc *rxd;
 253                 struct rte_mbuf *m;
 254                 unsigned int seg_len;
 255                 unsigned int desc_flags;
 256
 257                 id = completed++ & rxq->ptr_mask;
 258                 rxd = &rxq->sw_desc[id];
 259                 m = rxd->mbuf;
 260                 desc_flags = rxd->flags;
 261
 262                 if (discard_next)
 263                         goto discard;
 264
 265                 if (desc_flags & (EFX_ADDR_MISMATCH | EFX_DISCARD))
 266                         goto discard;
 267
 268                 if (desc_flags & EFX_PKT_PREFIX_LEN) {
 269                         uint16_t tmp_size;
 270                         int rc __rte_unused;
 271
 272                         rc = efx_pseudo_hdr_pkt_length_get(rxq->common,
 273                                 rte_pktmbuf_mtod(m, uint8_t *), &tmp_size);
 274                         SFC_ASSERT(rc == 0);
 275                         seg_len = tmp_size;
 276                 } else {
 277                         seg_len = rxd->size - prefix_size;
 278                 }
 279
 280                 rte_pktmbuf_data_len(m) = seg_len;
 281                 rte_pktmbuf_pkt_len(m) = seg_len;
 282
 283                 if (scatter_pkt != NULL) {
 284                         if (rte_pktmbuf_chain(scatter_pkt, m) != 0) {
 285                                 rte_mempool_put(rxq->refill_mb_pool,
 286                                                 scatter_pkt);
 287                                 goto discard;
 288                         }
 289                         /* The packet to deliver */
 290                         m = scatter_pkt;
 291                 }
 292
 293                 if (desc_flags & EFX_PKT_CONT) {
 294                         /* The packet is scattered, more fragments to come */
 295                         scatter_pkt = m;
 296                         /* Futher fragments have no prefix */
 297                         prefix_size = 0;
 298                         continue;
 299                 }
 300
 301                 /* Scattered packet is done */
 302                 scatter_pkt = NULL;
 303                 /* The first fragment of the packet has prefix */
 304                 prefix_size = rxq->prefix_size;
 305
 306                 m->ol_flags =
 307                         sfc_efx_rx_desc_flags_to_offload_flags(desc_flags);
 308                 m->packet_type =
 309                         sfc_efx_rx_desc_flags_to_packet_type(desc_flags);
 310
 311                 /*
 312                  * Extract RSS hash from the packet prefix and
 313                  * set the corresponding field (if needed and possible)
 314                  */
 315                 sfc_efx_rx_set_rss_hash(rxq, desc_flags, m);
 316
 317                 m->data_off += prefix_size;
 318
 319                 *rx_pkts++ = m;
 320                 done_pkts++;
 321                 continue;
 322
 323 discard:
 324                 discard_next = ((desc_flags & EFX_PKT_CONT) != 0);
 325                 rte_mempool_put(rxq->refill_mb_pool, m);
 326                 rxd->mbuf = NULL;
 327         }
 328
 329         /* pending is only moved when entire packet is received */
 330         SFC_ASSERT(scatter_pkt == NULL);
 331
 332         rxq->completed = completed;
 333
 334         sfc_efx_rx_qrefill(rxq);
 335
 336         return done_pkts;
 337 }
 338
 339 static sfc_dp_rx_qdesc_npending_t sfc_efx_rx_qdesc_npending;
 340 static unsigned int
 341 sfc_efx_rx_qdesc_npending(struct sfc_dp_rxq *dp_rxq)
 342 {
 343         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 344
 345         if ((rxq->flags & SFC_EFX_RXQ_FLAG_RUNNING) == 0)
 346                 return 0;
 347
 348         sfc_ev_qpoll(rxq->evq);
 349
 350         return rxq->pending - rxq->completed;
 351 }
 352
 353 struct sfc_rxq *
 354 sfc_rxq_by_dp_rxq(const struct sfc_dp_rxq *dp_rxq)
 355 {
 356         const struct sfc_dp_queue *dpq = &dp_rxq->dpq;
 357         struct rte_eth_dev *eth_dev;
 358         struct sfc_adapter *sa;
 359         struct sfc_rxq *rxq;
 360
 361         SFC_ASSERT(rte_eth_dev_is_valid_port(dpq->port_id));
 362         eth_dev = &rte_eth_devices[dpq->port_id];
 363
 364         sa = eth_dev->data->dev_private;
 365
 366         SFC_ASSERT(dpq->queue_id < sa->rxq_count);
 367         rxq = sa->rxq_info[dpq->queue_id].rxq;
 368
 369         SFC_ASSERT(rxq != NULL);
 370         return rxq;
 371 }
 372
 373 static sfc_dp_rx_qcreate_t sfc_efx_rx_qcreate;
 374 static int
 375 sfc_efx_rx_qcreate(uint16_t port_id, uint16_t queue_id,
 376                    const struct rte_pci_addr *pci_addr, int socket_id,
 377                    const struct sfc_dp_rx_qcreate_info *info,
 378                    struct sfc_dp_rxq **dp_rxqp)
 379 {
 380         struct sfc_efx_rxq *rxq;
 381         int rc;
 382
 383         rc = ENOMEM;
 384         rxq = rte_zmalloc_socket("sfc-efx-rxq", sizeof(*rxq),
 385                                  RTE_CACHE_LINE_SIZE, socket_id);
 386         if (rxq == NULL)
 387                 goto fail_rxq_alloc;
 388
 389         sfc_dp_queue_init(&rxq->dp.dpq, port_id, queue_id, pci_addr);
 390
 391         rc = ENOMEM;
 392         rxq->sw_desc = rte_calloc_socket("sfc-efx-rxq-sw_desc",
 393                                          info->rxq_entries,
 394                                          sizeof(*rxq->sw_desc),
 395                                          RTE_CACHE_LINE_SIZE, socket_id);
 396         if (rxq->sw_desc == NULL)
 397                 goto fail_desc_alloc;
 398
 399         /* efx datapath is bound to efx control path */
 400         rxq->evq = sfc_rxq_by_dp_rxq(&rxq->dp)->evq;
 401         if (info->flags & SFC_RXQ_FLAG_RSS_HASH)
 402                 rxq->flags |= SFC_EFX_RXQ_FLAG_RSS_HASH;
 403         rxq->ptr_mask = info->rxq_entries - 1;
 404         rxq->batch_max = info->batch_max;
 405         rxq->prefix_size = info->prefix_size;
 406         rxq->refill_threshold = info->refill_threshold;
 407         rxq->buf_size = info->buf_size;
 408         rxq->refill_mb_pool = info->refill_mb_pool;
 409
 410         *dp_rxqp = &rxq->dp;
 411         return 0;
 412
 413 fail_desc_alloc:
 414         rte_free(rxq);
 415
 416 fail_rxq_alloc:
 417         return rc;
 418 }
 419
 420 static sfc_dp_rx_qdestroy_t sfc_efx_rx_qdestroy;
 421 static void
 422 sfc_efx_rx_qdestroy(struct sfc_dp_rxq *dp_rxq)
 423 {
 424         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 425
 426         rte_free(rxq->sw_desc);
 427         rte_free(rxq);
 428 }
 429
 430 static sfc_dp_rx_qstart_t sfc_efx_rx_qstart;
 431 static int
 432 sfc_efx_rx_qstart(struct sfc_dp_rxq *dp_rxq,
 433                   __rte_unused unsigned int evq_read_ptr)
 434 {
 435         /* libefx-based datapath is specific to libefx-based PMD */
 436         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 437         struct sfc_rxq *crxq = sfc_rxq_by_dp_rxq(dp_rxq);
 438
 439         rxq->common = crxq->common;
 440
 441         rxq->pending = rxq->completed = rxq->added = rxq->pushed = 0;
 442
 443         sfc_efx_rx_qrefill(rxq);
 444
 445         rxq->flags |= (SFC_EFX_RXQ_FLAG_STARTED | SFC_EFX_RXQ_FLAG_RUNNING);
 446
 447         return 0;
 448 }
 449
 450 static sfc_dp_rx_qstop_t sfc_efx_rx_qstop;
 451 static void
 452 sfc_efx_rx_qstop(struct sfc_dp_rxq *dp_rxq,
 453                  __rte_unused unsigned int *evq_read_ptr)
 454 {
 455         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 456
 457         rxq->flags &= ~SFC_EFX_RXQ_FLAG_RUNNING;
 458
 459         /* libefx-based datapath is bound to libefx-based PMD and uses
 460          * event queue structure directly. So, there is no necessity to
 461          * return EvQ read pointer.
 462          */
 463 }
 464
 465 static sfc_dp_rx_qpurge_t sfc_efx_rx_qpurge;
 466 static void
 467 sfc_efx_rx_qpurge(struct sfc_dp_rxq *dp_rxq)
 468 {
 469         struct sfc_efx_rxq *rxq = sfc_efx_rxq_by_dp_rxq(dp_rxq);
 470         unsigned int i;
 471         struct sfc_efx_rx_sw_desc *rxd;
 472
 473         for (i = rxq->completed; i != rxq->added; ++i) {
 474                 rxd = &rxq->sw_desc[i & rxq->ptr_mask];
 475                 rte_mempool_put(rxq->refill_mb_pool, rxd->mbuf);
 476                 rxd->mbuf = NULL;
 477                 /* Packed stream relies on 0 in inactive SW desc.
 478                  * Rx queue stop is not performance critical, so
 479                  * there is no harm to do it always.
 480                  */
 481                 rxd->flags = 0;
 482                 rxd->size = 0;
 483         }
 484
 485         rxq->flags &= ~SFC_EFX_RXQ_FLAG_STARTED;
 486 }
 487
 488 struct sfc_dp_rx sfc_efx_rx = {
 489         .dp = {
 490                 .name           = SFC_KVARG_DATAPATH_EFX,
 491                 .type           = SFC_DP_RX,
 492                 .hw_fw_caps     = 0,
 493         },
 494         .features               = SFC_DP_RX_FEAT_SCATTER,
 495         .qcreate                = sfc_efx_rx_qcreate,
 496         .qdestroy               = sfc_efx_rx_qdestroy,
 497         .qstart                 = sfc_efx_rx_qstart,
 498         .qstop                  = sfc_efx_rx_qstop,
 499         .qpurge                 = sfc_efx_rx_qpurge,
 500         .supported_ptypes_get   = sfc_efx_supported_ptypes_get,
 501         .qdesc_npending         = sfc_efx_rx_qdesc_npending,
 502         .pkt_burst              = sfc_efx_recv_pkts,
 503 };
 504
 505 unsigned int
 506 sfc_rx_qdesc_npending(struct sfc_adapter *sa, unsigned int sw_index)
 507 {
 508         struct sfc_rxq *rxq;
 509
 510         SFC_ASSERT(sw_index < sa->rxq_count);
 511         rxq = sa->rxq_info[sw_index].rxq;
 512
 513         if (rxq == NULL || (rxq->state & SFC_RXQ_STARTED) == 0)
 514                 return 0;
 515
 516         return sa->dp_rx->qdesc_npending(rxq->dp);
 517 }
 518
 519 int
 520 sfc_rx_qdesc_done(struct sfc_dp_rxq *dp_rxq, unsigned int offset)
 521 {
 522         struct sfc_rxq *rxq = sfc_rxq_by_dp_rxq(dp_rxq);
 523
 524         return offset < rxq->evq->sa->dp_rx->qdesc_npending(dp_rxq);
 525 }
 526
 527 static void
 528 sfc_rx_qflush(struct sfc_adapter *sa, unsigned int sw_index)
 529 {
 530         struct sfc_rxq *rxq;
 531         unsigned int retry_count;
 532         unsigned int wait_count;
 533
 534         rxq = sa->rxq_info[sw_index].rxq;
 535         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 536
 537         /*
 538          * Retry Rx queue flushing in the case of flush failed or
 539          * timeout. In the worst case it can delay for 6 seconds.
 540          */
 541         for (retry_count = 0;
 542              ((rxq->state & SFC_RXQ_FLUSHED) == 0) &&
 543              (retry_count < SFC_RX_QFLUSH_ATTEMPTS);
 544              ++retry_count) {
 545                 if (efx_rx_qflush(rxq->common) != 0) {
 546                         rxq->state |= SFC_RXQ_FLUSH_FAILED;
 547                         break;
 548                 }
 549                 rxq->state &= ~SFC_RXQ_FLUSH_FAILED;
 550                 rxq->state |= SFC_RXQ_FLUSHING;
 551
 552                 /*
 553                  * Wait for Rx queue flush done or failed event at least
 554                  * SFC_RX_QFLUSH_POLL_WAIT_MS milliseconds and not more
 555                  * than 2 seconds (SFC_RX_QFLUSH_POLL_WAIT_MS multiplied
 556                  * by SFC_RX_QFLUSH_POLL_ATTEMPTS).
 557                  */
 558                 wait_count = 0;
 559                 do {
 560                         rte_delay_ms(SFC_RX_QFLUSH_POLL_WAIT_MS);
 561                         sfc_ev_qpoll(rxq->evq);
 562                 } while ((rxq->state & SFC_RXQ_FLUSHING) &&
 563                          (wait_count++ < SFC_RX_QFLUSH_POLL_ATTEMPTS));
 564
 565                 if (rxq->state & SFC_RXQ_FLUSHING)
 566                         sfc_err(sa, "RxQ %u flush timed out", sw_index);
 567
 568                 if (rxq->state & SFC_RXQ_FLUSH_FAILED)
 569                         sfc_err(sa, "RxQ %u flush failed", sw_index);
 570
 571                 if (rxq->state & SFC_RXQ_FLUSHED)
 572                         sfc_info(sa, "RxQ %u flushed", sw_index);
 573         }
 574
 575         sa->dp_rx->qpurge(rxq->dp);
 576 }
 577
 578 static int
 579 sfc_rx_default_rxq_set_filter(struct sfc_adapter *sa, struct sfc_rxq *rxq)
 580 {
 581         boolean_t rss = (sa->rss_channels > 1) ? B_TRUE : B_FALSE;
 582         struct sfc_port *port = &sa->port;
 583         int rc;
 584
 585         /*
 586          * If promiscuous or all-multicast mode has been requested, setting
 587          * filter for the default Rx queue might fail, in particular, while
 588          * running over PCI function which is not a member of corresponding
 589          * privilege groups; if this occurs, few iterations will be made to
 590          * repeat this step without promiscuous and all-multicast flags set
 591          */
 592 retry:
 593         rc = efx_mac_filter_default_rxq_set(sa->nic, rxq->common, rss);
 594         if (rc == 0)
 595                 return 0;
 596         else if (rc != EOPNOTSUPP)
 597                 return rc;
 598
 599         if (port->promisc) {
 600                 sfc_warn(sa, "promiscuous mode has been requested, "
 601                              "but the HW rejects it");
 602                 sfc_warn(sa, "promiscuous mode will be disabled");
 603
 604                 port->promisc = B_FALSE;
 605                 rc = sfc_set_rx_mode(sa);
 606                 if (rc != 0)
 607                         return rc;
 608
 609                 goto retry;
 610         }
 611
 612         if (port->allmulti) {
 613                 sfc_warn(sa, "all-multicast mode has been requested, "
 614                              "but the HW rejects it");
 615                 sfc_warn(sa, "all-multicast mode will be disabled");
 616
 617                 port->allmulti = B_FALSE;
 618                 rc = sfc_set_rx_mode(sa);
 619                 if (rc != 0)
 620                         return rc;
 621
 622                 goto retry;
 623         }
 624
 625         return rc;
 626 }
 627
 628 int
 629 sfc_rx_qstart(struct sfc_adapter *sa, unsigned int sw_index)
 630 {
 631         struct sfc_rxq_info *rxq_info;
 632         struct sfc_rxq *rxq;
 633         struct sfc_evq *evq;
 634         int rc;
 635
 636         sfc_log_init(sa, "sw_index=%u", sw_index);
 637
 638         SFC_ASSERT(sw_index < sa->rxq_count);
 639
 640         rxq_info = &sa->rxq_info[sw_index];
 641         rxq = rxq_info->rxq;
 642         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
 643
 644         evq = rxq->evq;
 645
 646         rc = sfc_ev_qstart(sa, evq->evq_index);
 647         if (rc != 0)
 648                 goto fail_ev_qstart;
 649
 650         rc = efx_rx_qcreate(sa->nic, rxq->hw_index, 0, rxq_info->type,
 651                             &rxq->mem, rxq_info->entries,
 652                             0 /* not used on EF10 */, evq->common,
 653                             &rxq->common);
 654         if (rc != 0)
 655                 goto fail_rx_qcreate;
 656
 657         efx_rx_qenable(rxq->common);
 658
 659         rc = sa->dp_rx->qstart(rxq->dp, evq->read_ptr);
 660         if (rc != 0)
 661                 goto fail_dp_qstart;
 662
 663         rxq->state |= SFC_RXQ_STARTED;
 664
 665         if (sw_index == 0) {
 666                 rc = sfc_rx_default_rxq_set_filter(sa, rxq);
 667                 if (rc != 0)
 668                         goto fail_mac_filter_default_rxq_set;
 669         }
 670
 671         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 672         sa->eth_dev->data->rx_queue_state[sw_index] =
 673                 RTE_ETH_QUEUE_STATE_STARTED;
 674
 675         return 0;
 676
 677 fail_mac_filter_default_rxq_set:
 678         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 679
 680 fail_dp_qstart:
 681         sfc_rx_qflush(sa, sw_index);
 682
 683 fail_rx_qcreate:
 684         sfc_ev_qstop(sa, evq->evq_index);
 685
 686 fail_ev_qstart:
 687         return rc;
 688 }
 689
 690 void
 691 sfc_rx_qstop(struct sfc_adapter *sa, unsigned int sw_index)
 692 {
 693         struct sfc_rxq_info *rxq_info;
 694         struct sfc_rxq *rxq;
 695
 696         sfc_log_init(sa, "sw_index=%u", sw_index);
 697
 698         SFC_ASSERT(sw_index < sa->rxq_count);
 699
 700         rxq_info = &sa->rxq_info[sw_index];
 701         rxq = rxq_info->rxq;
 702
 703         if (rxq->state == SFC_RXQ_INITIALIZED)
 704                 return;
 705         SFC_ASSERT(rxq->state & SFC_RXQ_STARTED);
 706
 707         /* It seems to be used by DPDK for debug purposes only ('rte_ether') */
 708         sa->eth_dev->data->rx_queue_state[sw_index] =
 709                 RTE_ETH_QUEUE_STATE_STOPPED;
 710
 711         sa->dp_rx->qstop(rxq->dp, &rxq->evq->read_ptr);
 712
 713         if (sw_index == 0)
 714                 efx_mac_filter_default_rxq_clear(sa->nic);
 715
 716         sfc_rx_qflush(sa, sw_index);
 717
 718         rxq->state = SFC_RXQ_INITIALIZED;
 719
 720         efx_rx_qdestroy(rxq->common);
 721
 722         sfc_ev_qstop(sa, rxq->evq->evq_index);
 723 }
 724
 725 static int
 726 sfc_rx_qcheck_conf(struct sfc_adapter *sa, uint16_t nb_rx_desc,
 727                    const struct rte_eth_rxconf *rx_conf)
 728 {
 729         const uint16_t rx_free_thresh_max = EFX_RXQ_LIMIT(nb_rx_desc);
 730         int rc = 0;
 731
 732         if (rx_conf->rx_thresh.pthresh != 0 ||
 733             rx_conf->rx_thresh.hthresh != 0 ||
 734             rx_conf->rx_thresh.wthresh != 0) {
 735                 sfc_err(sa,
 736                         "RxQ prefetch/host/writeback thresholds are not supported");
 737                 rc = EINVAL;
 738         }
 739
 740         if (rx_conf->rx_free_thresh > rx_free_thresh_max) {
 741                 sfc_err(sa,
 742                         "RxQ free threshold too large: %u vs maximum %u",
 743                         rx_conf->rx_free_thresh, rx_free_thresh_max);
 744                 rc = EINVAL;
 745         }
 746
 747         if (rx_conf->rx_drop_en == 0) {
 748                 sfc_err(sa, "RxQ drop disable is not supported");
 749                 rc = EINVAL;
 750         }
 751
 752         return rc;
 753 }
 754
 755 static unsigned int
 756 sfc_rx_mbuf_data_alignment(struct rte_mempool *mb_pool)
 757 {
 758         uint32_t data_off;
 759         uint32_t order;
 760
 761         /* The mbuf object itself is always cache line aligned */
 762         order = rte_bsf32(RTE_CACHE_LINE_SIZE);
 763
 764         /* Data offset from mbuf object start */
 765         data_off = sizeof(struct rte_mbuf) + rte_pktmbuf_priv_size(mb_pool) +
 766                 RTE_PKTMBUF_HEADROOM;
 767
 768         order = MIN(order, rte_bsf32(data_off));
 769
 770         return 1u << (order - 1);
 771 }
 772
 773 static uint16_t
 774 sfc_rx_mb_pool_buf_size(struct sfc_adapter *sa, struct rte_mempool *mb_pool)
 775 {
 776         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 777         const uint32_t nic_align_start = MAX(1, encp->enc_rx_buf_align_start);
 778         const uint32_t nic_align_end = MAX(1, encp->enc_rx_buf_align_end);
 779         uint16_t buf_size;
 780         unsigned int buf_aligned;
 781         unsigned int start_alignment;
 782         unsigned int end_padding_alignment;
 783
 784         /* Below it is assumed that both alignments are power of 2 */
 785         SFC_ASSERT(rte_is_power_of_2(nic_align_start));
 786         SFC_ASSERT(rte_is_power_of_2(nic_align_end));
 787
 788         /*
 789          * mbuf is always cache line aligned, double-check
 790          * that it meets rx buffer start alignment requirements.
 791          */
 792
 793         /* Start from mbuf pool data room size */
 794         buf_size = rte_pktmbuf_data_room_size(mb_pool);
 795
 796         /* Remove headroom */
 797         if (buf_size <= RTE_PKTMBUF_HEADROOM) {
 798                 sfc_err(sa,
 799                         "RxQ mbuf pool %s object data room size %u is smaller than headroom %u",
 800                         mb_pool->name, buf_size, RTE_PKTMBUF_HEADROOM);
 801                 return 0;
 802         }
 803         buf_size -= RTE_PKTMBUF_HEADROOM;
 804
 805         /* Calculate guaranteed data start alignment */
 806         buf_aligned = sfc_rx_mbuf_data_alignment(mb_pool);
 807
 808         /* Reserve space for start alignment */
 809         if (buf_aligned < nic_align_start) {
 810                 start_alignment = nic_align_start - buf_aligned;
 811                 if (buf_size <= start_alignment) {
 812                         sfc_err(sa,
 813                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u and buffer start alignment %u required by NIC",
 814                                 mb_pool->name,
 815                                 rte_pktmbuf_data_room_size(mb_pool),
 816                                 RTE_PKTMBUF_HEADROOM, start_alignment);
 817                         return 0;
 818                 }
 819                 buf_aligned = nic_align_start;
 820                 buf_size -= start_alignment;
 821         } else {
 822                 start_alignment = 0;
 823         }
 824
 825         /* Make sure that end padding does not write beyond the buffer */
 826         if (buf_aligned < nic_align_end) {
 827                 /*
 828                  * Estimate space which can be lost. If guarnteed buffer
 829                  * size is odd, lost space is (nic_align_end - 1). More
 830                  * accurate formula is below.
 831                  */
 832                 end_padding_alignment = nic_align_end -
 833                         MIN(buf_aligned, 1u << (rte_bsf32(buf_size) - 1));
 834                 if (buf_size <= end_padding_alignment) {
 835                         sfc_err(sa,
 836                                 "RxQ mbuf pool %s object data room size %u is insufficient for headroom %u, buffer start alignment %u and end padding alignment %u required by NIC",
 837                                 mb_pool->name,
 838                                 rte_pktmbuf_data_room_size(mb_pool),
 839                                 RTE_PKTMBUF_HEADROOM, start_alignment,
 840                                 end_padding_alignment);
 841                         return 0;
 842                 }
 843                 buf_size -= end_padding_alignment;
 844         } else {
 845                 /*
 846                  * Start is aligned the same or better than end,
 847                  * just align length.
 848                  */
 849                 buf_size = P2ALIGN(buf_size, nic_align_end);
 850         }
 851
 852         return buf_size;
 853 }
 854
 855 int
 856 sfc_rx_qinit(struct sfc_adapter *sa, unsigned int sw_index,
 857              uint16_t nb_rx_desc, unsigned int socket_id,
 858              const struct rte_eth_rxconf *rx_conf,
 859              struct rte_mempool *mb_pool)
 860 {
 861         const efx_nic_cfg_t *encp = efx_nic_cfg_get(sa->nic);
 862         int rc;
 863         uint16_t buf_size;
 864         struct sfc_rxq_info *rxq_info;
 865         unsigned int evq_index;
 866         struct sfc_evq *evq;
 867         struct sfc_rxq *rxq;
 868         struct sfc_dp_rx_qcreate_info info;
 869
 870         rc = sfc_rx_qcheck_conf(sa, nb_rx_desc, rx_conf);
 871         if (rc != 0)
 872                 goto fail_bad_conf;
 873
 874         buf_size = sfc_rx_mb_pool_buf_size(sa, mb_pool);
 875         if (buf_size == 0) {
 876                 sfc_err(sa, "RxQ %u mbuf pool object size is too small",
 877                         sw_index);
 878                 rc = EINVAL;
 879                 goto fail_bad_conf;
 880         }
 881
 882         if ((buf_size < sa->port.pdu + encp->enc_rx_prefix_size) &&
 883             !sa->eth_dev->data->dev_conf.rxmode.enable_scatter) {
 884                 sfc_err(sa, "Rx scatter is disabled and RxQ %u mbuf pool "
 885                         "object size is too small", sw_index);
 886                 sfc_err(sa, "RxQ %u calculated Rx buffer size is %u vs "
 887                         "PDU size %u plus Rx prefix %u bytes",
 888                         sw_index, buf_size, (unsigned int)sa->port.pdu,
 889                         encp->enc_rx_prefix_size);
 890                 rc = EINVAL;
 891                 goto fail_bad_conf;
 892         }
 893
 894         SFC_ASSERT(sw_index < sa->rxq_count);
 895         rxq_info = &sa->rxq_info[sw_index];
 896
 897         SFC_ASSERT(nb_rx_desc <= rxq_info->max_entries);
 898         rxq_info->entries = nb_rx_desc;
 899         rxq_info->type =
 900                 sa->eth_dev->data->dev_conf.rxmode.enable_scatter ?
 901                 EFX_RXQ_TYPE_SCATTER : EFX_RXQ_TYPE_DEFAULT;
 902
 903         evq_index = sfc_evq_index_by_rxq_sw_index(sa, sw_index);
 904
 905         rc = sfc_ev_qinit(sa, evq_index, rxq_info->entries, socket_id);
 906         if (rc != 0)
 907                 goto fail_ev_qinit;
 908
 909         evq = sa->evq_info[evq_index].evq;
 910
 911         rc = ENOMEM;
 912         rxq = rte_zmalloc_socket("sfc-rxq", sizeof(*rxq), RTE_CACHE_LINE_SIZE,
 913                                  socket_id);
 914         if (rxq == NULL)
 915                 goto fail_rxq_alloc;
 916
 917         rxq_info->rxq = rxq;
 918
 919         rxq->evq = evq;
 920         rxq->hw_index = sw_index;
 921         rxq->refill_threshold =
 922                 RTE_MAX(rx_conf->rx_free_thresh, SFC_RX_REFILL_BULK);
 923         rxq->refill_mb_pool = mb_pool;
 924
 925         rc = sfc_dma_alloc(sa, "rxq", sw_index, EFX_RXQ_SIZE(rxq_info->entries),
 926                            socket_id, &rxq->mem);
 927         if (rc != 0)
 928                 goto fail_dma_alloc;
 929
 930         memset(&info, 0, sizeof(info));
 931         info.refill_mb_pool = rxq->refill_mb_pool;
 932         info.refill_threshold = rxq->refill_threshold;
 933         info.buf_size = buf_size;
 934         info.batch_max = encp->enc_rx_batch_max;
 935         info.prefix_size = encp->enc_rx_prefix_size;
 936
 937 #if EFSYS_OPT_RX_SCALE
 938         if (sa->hash_support == EFX_RX_HASH_AVAILABLE)
 939                 info.flags |= SFC_RXQ_FLAG_RSS_HASH;
 940 #endif
 941
 942         info.rxq_entries = rxq_info->entries;
 943         info.rxq_hw_ring = rxq->mem.esm_base;
 944         info.evq_entries = rxq_info->entries;
 945         info.evq_hw_ring = evq->mem.esm_base;
 946         info.hw_index = rxq->hw_index;
 947         info.mem_bar = sa->mem_bar.esb_base;
 948
 949         rc = sa->dp_rx->qcreate(sa->eth_dev->data->port_id, sw_index,
 950                                 &SFC_DEV_TO_PCI(sa->eth_dev)->addr,
 951                                 socket_id, &info, &rxq->dp);
 952         if (rc != 0)
 953                 goto fail_dp_rx_qcreate;
 954
 955         evq->dp_rxq = rxq->dp;
 956
 957         rxq->state = SFC_RXQ_INITIALIZED;
 958
 959         rxq_info->deferred_start = (rx_conf->rx_deferred_start != 0);
 960
 961         return 0;
 962
 963 fail_dp_rx_qcreate:
 964         sfc_dma_free(sa, &rxq->mem);
 965
 966 fail_dma_alloc:
 967         rxq_info->rxq = NULL;
 968         rte_free(rxq);
 969
 970 fail_rxq_alloc:
 971         sfc_ev_qfini(sa, evq_index);
 972
 973 fail_ev_qinit:
 974         rxq_info->entries = 0;
 975
 976 fail_bad_conf:
 977         sfc_log_init(sa, "failed %d", rc);
 978         return rc;
 979 }
 980
 981 void
 982 sfc_rx_qfini(struct sfc_adapter *sa, unsigned int sw_index)
 983 {
 984         struct sfc_rxq_info *rxq_info;
 985         struct sfc_rxq *rxq;
 986
 987         SFC_ASSERT(sw_index < sa->rxq_count);
 988
 989         rxq_info = &sa->rxq_info[sw_index];
 990
 991         rxq = rxq_info->rxq;
 992         SFC_ASSERT(rxq->state == SFC_RXQ_INITIALIZED);
 993
 994         sa->dp_rx->qdestroy(rxq->dp);
 995         rxq->dp = NULL;
 996
 997         rxq_info->rxq = NULL;
 998         rxq_info->entries = 0;
 999
1000         sfc_dma_free(sa, &rxq->mem);
1001         rte_free(rxq);
1002 }
1003
1004 #if EFSYS_OPT_RX_SCALE
1005 efx_rx_hash_type_t
1006 sfc_rte_to_efx_hash_type(uint64_t rss_hf)
1007 {
1008         efx_rx_hash_type_t efx_hash_types = 0;
1009
1010         if ((rss_hf & (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
1011                        ETH_RSS_NONFRAG_IPV4_OTHER)) != 0)
1012                 efx_hash_types |= EFX_RX_HASH_IPV4;
1013
1014         if ((rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) != 0)
1015                 efx_hash_types |= EFX_RX_HASH_TCPIPV4;
1016
1017         if ((rss_hf & (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
1018                         ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_IPV6_EX)) != 0)
1019                 efx_hash_types |= EFX_RX_HASH_IPV6;
1020
1021         if ((rss_hf & (ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX)) != 0)
1022                 efx_hash_types |= EFX_RX_HASH_TCPIPV6;
1023
1024         return efx_hash_types;
1025 }
1026
1027 uint64_t
1028 sfc_efx_to_rte_hash_type(efx_rx_hash_type_t efx_hash_types)
1029 {
1030         uint64_t rss_hf = 0;
1031
1032         if ((efx_hash_types & EFX_RX_HASH_IPV4) != 0)
1033                 rss_hf |= (ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 |
1034                            ETH_RSS_NONFRAG_IPV4_OTHER);
1035
1036         if ((efx_hash_types & EFX_RX_HASH_TCPIPV4) != 0)
1037                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
1038
1039         if ((efx_hash_types & EFX_RX_HASH_IPV6) != 0)
1040                 rss_hf |= (ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 |
1041                            ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_IPV6_EX);
1042
1043         if ((efx_hash_types & EFX_RX_HASH_TCPIPV6) != 0)
1044                 rss_hf |= (ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_IPV6_TCP_EX);
1045
1046         return rss_hf;
1047 }
1048 #endif
1049
1050 static int
1051 sfc_rx_rss_config(struct sfc_adapter *sa)
1052 {
1053         int rc = 0;
1054
1055 #if EFSYS_OPT_RX_SCALE
1056         if (sa->rss_channels > 1) {
1057                 rc = efx_rx_scale_mode_set(sa->nic, EFX_RX_HASHALG_TOEPLITZ,
1058                                            sa->rss_hash_types, B_TRUE);
1059                 if (rc != 0)
1060                         goto finish;
1061
1062                 rc = efx_rx_scale_key_set(sa->nic, sa->rss_key,
1063                                           sizeof(sa->rss_key));
1064                 if (rc != 0)
1065                         goto finish;
1066
1067                 rc = efx_rx_scale_tbl_set(sa->nic, sa->rss_tbl,
1068                                           sizeof(sa->rss_tbl));
1069         }
1070
1071 finish:
1072 #endif
1073         return rc;
1074 }
1075
1076 int
1077 sfc_rx_start(struct sfc_adapter *sa)
1078 {
1079         unsigned int sw_index;
1080         int rc;
1081
1082         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1083
1084         rc = efx_rx_init(sa->nic);
1085         if (rc != 0)
1086                 goto fail_rx_init;
1087
1088         rc = sfc_rx_rss_config(sa);
1089         if (rc != 0)
1090                 goto fail_rss_config;
1091
1092         for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1093                 if ((!sa->rxq_info[sw_index].deferred_start ||
1094                      sa->rxq_info[sw_index].deferred_started)) {
1095                         rc = sfc_rx_qstart(sa, sw_index);
1096                         if (rc != 0)
1097                                 goto fail_rx_qstart;
1098                 }
1099         }
1100
1101         return 0;
1102
1103 fail_rx_qstart:
1104         while (sw_index-- > 0)
1105                 sfc_rx_qstop(sa, sw_index);
1106
1107 fail_rss_config:
1108         efx_rx_fini(sa->nic);
1109
1110 fail_rx_init:
1111         sfc_log_init(sa, "failed %d", rc);
1112         return rc;
1113 }
1114
1115 void
1116 sfc_rx_stop(struct sfc_adapter *sa)
1117 {
1118         unsigned int sw_index;
1119
1120         sfc_log_init(sa, "rxq_count=%u", sa->rxq_count);
1121
1122         sw_index = sa->rxq_count;
1123         while (sw_index-- > 0) {
1124                 if (sa->rxq_info[sw_index].rxq != NULL)
1125                         sfc_rx_qstop(sa, sw_index);
1126         }
1127
1128         efx_rx_fini(sa->nic);
1129 }
1130
1131 static int
1132 sfc_rx_qinit_info(struct sfc_adapter *sa, unsigned int sw_index)
1133 {
1134         struct sfc_rxq_info *rxq_info = &sa->rxq_info[sw_index];
1135         unsigned int max_entries;
1136
1137         max_entries = EFX_RXQ_MAXNDESCS;
1138         SFC_ASSERT(rte_is_power_of_2(max_entries));
1139
1140         rxq_info->max_entries = max_entries;
1141
1142         return 0;
1143 }
1144
1145 static int
1146 sfc_rx_check_mode(struct sfc_adapter *sa, struct rte_eth_rxmode *rxmode)
1147 {
1148         int rc = 0;
1149
1150         switch (rxmode->mq_mode) {
1151         case ETH_MQ_RX_NONE:
1152                 /* No special checks are required */
1153                 break;
1154 #if EFSYS_OPT_RX_SCALE
1155         case ETH_MQ_RX_RSS:
1156                 if (sa->rss_support == EFX_RX_SCALE_UNAVAILABLE) {
1157                         sfc_err(sa, "RSS is not available");
1158                         rc = EINVAL;
1159                 }
1160                 break;
1161 #endif
1162         default:
1163                 sfc_err(sa, "Rx multi-queue mode %u not supported",
1164                         rxmode->mq_mode);
1165                 rc = EINVAL;
1166         }
1167
1168         if (rxmode->header_split) {
1169                 sfc_err(sa, "Header split on Rx not supported");
1170                 rc = EINVAL;
1171         }
1172
1173         if (rxmode->hw_vlan_filter) {
1174                 sfc_err(sa, "HW VLAN filtering not supported");
1175                 rc = EINVAL;
1176         }
1177
1178         if (rxmode->hw_vlan_strip) {
1179                 sfc_err(sa, "HW VLAN stripping not supported");
1180                 rc = EINVAL;
1181         }
1182
1183         if (rxmode->hw_vlan_extend) {
1184                 sfc_err(sa,
1185                         "Q-in-Q HW VLAN stripping not supported");
1186                 rc = EINVAL;
1187         }
1188
1189         if (!rxmode->hw_strip_crc) {
1190                 sfc_warn(sa,
1191                          "FCS stripping control not supported - always stripped");
1192                 rxmode->hw_strip_crc = 1;
1193         }
1194
1195         if (rxmode->enable_scatter &&
1196             (~sa->dp_rx->features & SFC_DP_RX_FEAT_SCATTER)) {
1197                 sfc_err(sa, "Rx scatter not supported by %s datapath",
1198                         sa->dp_rx->dp.name);
1199                 rc = EINVAL;
1200         }
1201
1202         if (rxmode->enable_lro) {
1203                 sfc_err(sa, "LRO not supported");
1204                 rc = EINVAL;
1205         }
1206
1207         return rc;
1208 }
1209
1210 /**
1211  * Initialize Rx subsystem.
1212  *
1213  * Called at device configuration stage when number of receive queues is
1214  * specified together with other device level receive configuration.
1215  *
1216  * It should be used to allocate NUMA-unaware resources.
1217  */
1218 int
1219 sfc_rx_init(struct sfc_adapter *sa)
1220 {
1221         struct rte_eth_conf *dev_conf = &sa->eth_dev->data->dev_conf;
1222         unsigned int sw_index;
1223         int rc;
1224
1225         rc = sfc_rx_check_mode(sa, &dev_conf->rxmode);
1226         if (rc != 0)
1227                 goto fail_check_mode;
1228
1229         sa->rxq_count = sa->eth_dev->data->nb_rx_queues;
1230
1231         rc = ENOMEM;
1232         sa->rxq_info = rte_calloc_socket("sfc-rxqs", sa->rxq_count,
1233                                          sizeof(struct sfc_rxq_info), 0,
1234                                          sa->socket_id);
1235         if (sa->rxq_info == NULL)
1236                 goto fail_rxqs_alloc;
1237
1238         for (sw_index = 0; sw_index < sa->rxq_count; ++sw_index) {
1239                 rc = sfc_rx_qinit_info(sa, sw_index);
1240                 if (rc != 0)
1241                         goto fail_rx_qinit_info;
1242         }
1243
1244 #if EFSYS_OPT_RX_SCALE
1245         sa->rss_channels = (dev_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) ?
1246                            MIN(sa->rxq_count, EFX_MAXRSS) : 1;
1247
1248         if (sa->rss_channels > 1) {
1249                 for (sw_index = 0; sw_index < EFX_RSS_TBL_SIZE; ++sw_index)
1250                         sa->rss_tbl[sw_index] = sw_index % sa->rss_channels;
1251         }
1252 #endif
1253
1254         return 0;
1255
1256 fail_rx_qinit_info:
1257         rte_free(sa->rxq_info);
1258         sa->rxq_info = NULL;
1259
1260 fail_rxqs_alloc:
1261         sa->rxq_count = 0;
1262 fail_check_mode:
1263         sfc_log_init(sa, "failed %d", rc);
1264         return rc;
1265 }
1266
1267 /**
1268  * Shutdown Rx subsystem.
1269  *
1270  * Called at device close stage, for example, before device
1271  * reconfiguration or shutdown.
1272  */
1273 void
1274 sfc_rx_fini(struct sfc_adapter *sa)
1275 {
1276         unsigned int sw_index;
1277
1278         sw_index = sa->rxq_count;
1279         while (sw_index-- > 0) {
1280                 if (sa->rxq_info[sw_index].rxq != NULL)
1281                         sfc_rx_qfini(sa, sw_index);
1282         }
1283
1284         rte_free(sa->rxq_info);
1285         sa->rxq_info = NULL;
1286         sa->rxq_count = 0;
1287 }