drivers/net/thunderx/nicvf_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016 Cavium, Inc
   3  */
   4
   5 #include <assert.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15 #include <sys/queue.h>
  16
  17 #include <rte_alarm.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_cycles.h>
  22 #include <rte_debug.h>
  23 #include <rte_dev.h>
  24 #include <rte_eal.h>
  25 #include <rte_ether.h>
  26 #include <rte_ethdev_driver.h>
  27 #include <rte_ethdev_pci.h>
  28 #include <rte_interrupts.h>
  29 #include <rte_log.h>
  30 #include <rte_memory.h>
  31 #include <rte_memzone.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_pci.h>
  35 #include <rte_bus_pci.h>
  36 #include <rte_tailq.h>
  37 #include <rte_devargs.h>
  38 #include <rte_kvargs.h>
  39
  40 #include "base/nicvf_plat.h"
  41
  42 #include "nicvf_ethdev.h"
  43 #include "nicvf_rxtx.h"
  44 #include "nicvf_svf.h"
  45 #include "nicvf_logs.h"
  46
  47 int nicvf_logtype_mbox;
  48 int nicvf_logtype_init;
  49 int nicvf_logtype_driver;
  50
  51 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  54                           bool cleanup);
  55 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
  56 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  57
  58 RTE_INIT(nicvf_init_log)
  59 {
  60         nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox");
  61         if (nicvf_logtype_mbox >= 0)
  62                 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
  63
  64         nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init");
  65         if (nicvf_logtype_init >= 0)
  66                 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
  67
  68         nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver");
  69         if (nicvf_logtype_driver >= 0)
  70                 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
  71 }
  72
  73 static void
  74 nicvf_link_status_update(struct nicvf *nic,
  75                          struct rte_eth_link *link)
  76 {
  77         memset(link, 0, sizeof(*link));
  78
  79         link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
  80
  81         if (nic->duplex == NICVF_HALF_DUPLEX)
  82                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  83         else if (nic->duplex == NICVF_FULL_DUPLEX)
  84                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  85         link->link_speed = nic->speed;
  86         link->link_autoneg = ETH_LINK_AUTONEG;
  87 }
  88
  89 static void
  90 nicvf_interrupt(void *arg)
  91 {
  92         struct rte_eth_dev *dev = arg;
  93         struct nicvf *nic = nicvf_pmd_priv(dev);
  94         struct rte_eth_link link;
  95
  96         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
  97                 if (dev->data->dev_conf.intr_conf.lsc) {
  98                         nicvf_link_status_update(nic, &link);
  99                         rte_eth_linkstatus_set(dev, &link);
 100
 101                         _rte_eth_dev_callback_process(dev,
 102                                                       RTE_ETH_EVENT_INTR_LSC,
 103                                                       NULL);
 104                 }
 105         }
 106
 107         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 108                                 nicvf_interrupt, dev);
 109 }
 110
 111 static void
 112 nicvf_vf_interrupt(void *arg)
 113 {
 114         struct nicvf *nic = arg;
 115
 116         nicvf_reg_poll_interrupts(nic);
 117
 118         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 119                                 nicvf_vf_interrupt, nic);
 120 }
 121
 122 static int
 123 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 124 {
 125         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 126 }
 127
 128 static int
 129 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 130 {
 131         return rte_eal_alarm_cancel(fn, arg);
 132 }
 133
 134 /*
 135  * Return 0 means link status changed, -1 means not changed
 136  */
 137 static int
 138 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 139 {
 140 #define CHECK_INTERVAL 100  /* 100ms */
 141 #define MAX_CHECK_TIME 90   /* 9s (90 * 100ms) in total */
 142         struct rte_eth_link link;
 143         struct nicvf *nic = nicvf_pmd_priv(dev);
 144         int i;
 145
 146         PMD_INIT_FUNC_TRACE();
 147
 148         if (wait_to_complete) {
 149                 /* rte_eth_link_get() might need to wait up to 9 seconds */
 150                 for (i = 0; i < MAX_CHECK_TIME; i++) {
 151                         nicvf_link_status_update(nic, &link);
 152                         if (link.link_status == ETH_LINK_UP)
 153                                 break;
 154                         rte_delay_ms(CHECK_INTERVAL);
 155                 }
 156         } else {
 157                 nicvf_link_status_update(nic, &link);
 158         }
 159
 160         return rte_eth_linkstatus_set(dev, &link);
 161 }
 162
 163 static int
 164 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 165 {
 166         struct nicvf *nic = nicvf_pmd_priv(dev);
 167         uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
 168         size_t i;
 169         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 170
 171         PMD_INIT_FUNC_TRACE();
 172
 173         if (frame_size > NIC_HW_MAX_FRS)
 174                 return -EINVAL;
 175
 176         if (frame_size < NIC_HW_MIN_FRS)
 177                 return -EINVAL;
 178
 179         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 180
 181         /*
 182          * Refuse mtu that requires the support of scattered packets
 183          * when this feature has not been enabled before.
 184          */
 185         if (dev->data->dev_started && !dev->data->scattered_rx &&
 186                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 187                 return -EINVAL;
 188
 189         /* check <seg size> * <max_seg>  >= max_frame */
 190         if (dev->data->scattered_rx &&
 191                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 192                 return -EINVAL;
 193
 194         if (frame_size > RTE_ETHER_MAX_LEN)
 195                 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 196         else
 197                 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 198
 199         if (nicvf_mbox_update_hw_max_frs(nic, mtu))
 200                 return -EINVAL;
 201
 202         /* Update max_rx_pkt_len */
 203         rxmode->max_rx_pkt_len = mtu + RTE_ETHER_HDR_LEN;
 204         nic->mtu = mtu;
 205
 206         for (i = 0; i < nic->sqs_count; i++)
 207                 nic->snicvf[i]->mtu = mtu;
 208
 209         return 0;
 210 }
 211
 212 static int
 213 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 214 {
 215         uint64_t *data = regs->data;
 216         struct nicvf *nic = nicvf_pmd_priv(dev);
 217
 218         if (data == NULL) {
 219                 regs->length = nicvf_reg_get_count();
 220                 regs->width = THUNDERX_REG_BYTES;
 221                 return 0;
 222         }
 223
 224         /* Support only full register dump */
 225         if ((regs->length == 0) ||
 226                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 227                 regs->version = nic->vendor_id << 16 | nic->device_id;
 228                 nicvf_reg_dump(nic, data);
 229                 return 0;
 230         }
 231         return -ENOTSUP;
 232 }
 233
 234 static int
 235 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 236 {
 237         uint16_t qidx;
 238         struct nicvf_hw_rx_qstats rx_qstats;
 239         struct nicvf_hw_tx_qstats tx_qstats;
 240         struct nicvf_hw_stats port_stats;
 241         struct nicvf *nic = nicvf_pmd_priv(dev);
 242         uint16_t rx_start, rx_end;
 243         uint16_t tx_start, tx_end;
 244         size_t i;
 245
 246         /* RX queue indices for the first VF */
 247         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 248
 249         /* Reading per RX ring stats */
 250         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 251                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 252                         break;
 253
 254                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 255                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 256                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 257         }
 258
 259         /* TX queue indices for the first VF */
 260         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 261
 262         /* Reading per TX ring stats */
 263         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 264                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 265                         break;
 266
 267                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 268                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 269                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 270         }
 271
 272         for (i = 0; i < nic->sqs_count; i++) {
 273                 struct nicvf *snic = nic->snicvf[i];
 274
 275                 if (snic == NULL)
 276                         break;
 277
 278                 /* RX queue indices for a secondary VF */
 279                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 280
 281                 /* Reading per RX ring stats */
 282                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 283                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 284                                 break;
 285
 286                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 287                                                qidx % MAX_RCV_QUEUES_PER_QS);
 288                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 289                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 290                 }
 291
 292                 /* TX queue indices for a secondary VF */
 293                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 294                 /* Reading per TX ring stats */
 295                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 296                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 297                                 break;
 298
 299                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 300                                                qidx % MAX_SND_QUEUES_PER_QS);
 301                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 302                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 303                 }
 304         }
 305
 306         nicvf_hw_get_stats(nic, &port_stats);
 307         stats->ibytes = port_stats.rx_bytes;
 308         stats->ipackets = port_stats.rx_ucast_frames;
 309         stats->ipackets += port_stats.rx_bcast_frames;
 310         stats->ipackets += port_stats.rx_mcast_frames;
 311         stats->ierrors = port_stats.rx_l2_errors;
 312         stats->imissed = port_stats.rx_drop_red;
 313         stats->imissed += port_stats.rx_drop_overrun;
 314         stats->imissed += port_stats.rx_drop_bcast;
 315         stats->imissed += port_stats.rx_drop_mcast;
 316         stats->imissed += port_stats.rx_drop_l3_bcast;
 317         stats->imissed += port_stats.rx_drop_l3_mcast;
 318
 319         stats->obytes = port_stats.tx_bytes_ok;
 320         stats->opackets = port_stats.tx_ucast_frames_ok;
 321         stats->opackets += port_stats.tx_bcast_frames_ok;
 322         stats->opackets += port_stats.tx_mcast_frames_ok;
 323         stats->oerrors = port_stats.tx_drops;
 324
 325         return 0;
 326 }
 327
 328 static const uint32_t *
 329 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 330 {
 331         size_t copied;
 332         static uint32_t ptypes[32];
 333         struct nicvf *nic = nicvf_pmd_priv(dev);
 334         static const uint32_t ptypes_common[] = {
 335                 RTE_PTYPE_L3_IPV4,
 336                 RTE_PTYPE_L3_IPV4_EXT,
 337                 RTE_PTYPE_L3_IPV6,
 338                 RTE_PTYPE_L3_IPV6_EXT,
 339                 RTE_PTYPE_L4_TCP,
 340                 RTE_PTYPE_L4_UDP,
 341                 RTE_PTYPE_L4_FRAG,
 342         };
 343         static const uint32_t ptypes_tunnel[] = {
 344                 RTE_PTYPE_TUNNEL_GRE,
 345                 RTE_PTYPE_TUNNEL_GENEVE,
 346                 RTE_PTYPE_TUNNEL_VXLAN,
 347                 RTE_PTYPE_TUNNEL_NVGRE,
 348         };
 349         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 350
 351         copied = sizeof(ptypes_common);
 352         memcpy(ptypes, ptypes_common, copied);
 353         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 354                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 355                         sizeof(ptypes_tunnel));
 356                 copied += sizeof(ptypes_tunnel);
 357         }
 358
 359         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 360
 361         /* All Ptypes are supported in all Rx functions. */
 362         return ptypes;
 363 }
 364
 365 static int
 366 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 367 {
 368         int i;
 369         uint16_t rxqs = 0, txqs = 0;
 370         struct nicvf *nic = nicvf_pmd_priv(dev);
 371         uint16_t rx_start, rx_end;
 372         uint16_t tx_start, tx_end;
 373         int ret;
 374
 375         /* Reset all primary nic counters */
 376         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 377         for (i = rx_start; i <= rx_end; i++)
 378                 rxqs |= (0x3 << (i * 2));
 379
 380         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 381         for (i = tx_start; i <= tx_end; i++)
 382                 txqs |= (0x3 << (i * 2));
 383
 384         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 385         if (ret != 0)
 386                 return ret;
 387
 388         /* Reset secondary nic queue counters */
 389         for (i = 0; i < nic->sqs_count; i++) {
 390                 struct nicvf *snic = nic->snicvf[i];
 391                 if (snic == NULL)
 392                         break;
 393
 394                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 395                 for (i = rx_start; i <= rx_end; i++)
 396                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 397
 398                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 399                 for (i = tx_start; i <= tx_end; i++)
 400                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 401
 402                 ret = nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 403                 if (ret != 0)
 404                         return ret;
 405         }
 406
 407         return 0;
 408 }
 409
 410 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 411 static int
 412 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 413 {
 414         return 0;
 415 }
 416
 417 static inline uint64_t
 418 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 419 {
 420         uint64_t nic_rss = 0;
 421
 422         if (ethdev_rss & ETH_RSS_IPV4)
 423                 nic_rss |= RSS_IP_ENA;
 424
 425         if (ethdev_rss & ETH_RSS_IPV6)
 426                 nic_rss |= RSS_IP_ENA;
 427
 428         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 429                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 430
 431         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 432                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 433
 434         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 435                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 436
 437         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 438                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 439
 440         if (ethdev_rss & ETH_RSS_PORT)
 441                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 442
 443         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 444                 if (ethdev_rss & ETH_RSS_VXLAN)
 445                         nic_rss |= RSS_TUN_VXLAN_ENA;
 446
 447                 if (ethdev_rss & ETH_RSS_GENEVE)
 448                         nic_rss |= RSS_TUN_GENEVE_ENA;
 449
 450                 if (ethdev_rss & ETH_RSS_NVGRE)
 451                         nic_rss |= RSS_TUN_NVGRE_ENA;
 452         }
 453
 454         return nic_rss;
 455 }
 456
 457 static inline uint64_t
 458 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 459 {
 460         uint64_t ethdev_rss = 0;
 461
 462         if (nic_rss & RSS_IP_ENA)
 463                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 464
 465         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 466                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 467                                 ETH_RSS_NONFRAG_IPV6_TCP);
 468
 469         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 470                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 471                                 ETH_RSS_NONFRAG_IPV6_UDP);
 472
 473         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 474                 ethdev_rss |= ETH_RSS_PORT;
 475
 476         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 477                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 478                         ethdev_rss |= ETH_RSS_VXLAN;
 479
 480                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 481                         ethdev_rss |= ETH_RSS_GENEVE;
 482
 483                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 484                         ethdev_rss |= ETH_RSS_NVGRE;
 485         }
 486         return ethdev_rss;
 487 }
 488
 489 static int
 490 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 491                      struct rte_eth_rss_reta_entry64 *reta_conf,
 492                      uint16_t reta_size)
 493 {
 494         struct nicvf *nic = nicvf_pmd_priv(dev);
 495         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 496         int ret, i, j;
 497
 498         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 499                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 500                         "(%d) doesn't match the number hardware can supported "
 501                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 502                 return -EINVAL;
 503         }
 504
 505         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 506         if (ret)
 507                 return ret;
 508
 509         /* Copy RETA table */
 510         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 511                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 512                         if ((reta_conf[i].mask >> j) & 0x01)
 513                                 reta_conf[i].reta[j] = tbl[j];
 514         }
 515
 516         return 0;
 517 }
 518
 519 static int
 520 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 521                       struct rte_eth_rss_reta_entry64 *reta_conf,
 522                       uint16_t reta_size)
 523 {
 524         struct nicvf *nic = nicvf_pmd_priv(dev);
 525         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 526         int ret, i, j;
 527
 528         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 529                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 530                         "(%d) doesn't match the number hardware can supported "
 531                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 532                 return -EINVAL;
 533         }
 534
 535         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 536         if (ret)
 537                 return ret;
 538
 539         /* Copy RETA table */
 540         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 541                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 542                         if ((reta_conf[i].mask >> j) & 0x01)
 543                                 tbl[j] = reta_conf[i].reta[j];
 544         }
 545
 546         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 547 }
 548
 549 static int
 550 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 551                             struct rte_eth_rss_conf *rss_conf)
 552 {
 553         struct nicvf *nic = nicvf_pmd_priv(dev);
 554
 555         if (rss_conf->rss_key)
 556                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 557
 558         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 559         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 560         return 0;
 561 }
 562
 563 static int
 564 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 565                           struct rte_eth_rss_conf *rss_conf)
 566 {
 567         struct nicvf *nic = nicvf_pmd_priv(dev);
 568         uint64_t nic_rss;
 569
 570         if (rss_conf->rss_key &&
 571                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 572                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 573                                 rss_conf->rss_key_len);
 574                 return -EINVAL;
 575         }
 576
 577         if (rss_conf->rss_key)
 578                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 579
 580         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 581         nicvf_rss_set_cfg(nic, nic_rss);
 582         return 0;
 583 }
 584
 585 static int
 586 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 587                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 588 {
 589         const struct rte_memzone *rz;
 590         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 591
 592         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 593                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 594                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 595         if (rz == NULL) {
 596                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 597                 return -ENOMEM;
 598         }
 599
 600         memset(rz->addr, 0, ring_size);
 601
 602         rxq->phys = rz->iova;
 603         rxq->desc = rz->addr;
 604         rxq->qlen_mask = desc_cnt - 1;
 605
 606         return 0;
 607 }
 608
 609 static int
 610 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 611                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 612 {
 613         const struct rte_memzone *rz;
 614         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 615
 616         rz = rte_eth_dma_zone_reserve(dev, "sq",
 617                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 618                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 619         if (rz == NULL) {
 620                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 621                 return -ENOMEM;
 622         }
 623
 624         memset(rz->addr, 0, ring_size);
 625
 626         sq->phys = rz->iova;
 627         sq->desc = rz->addr;
 628         sq->qlen_mask = desc_cnt - 1;
 629
 630         return 0;
 631 }
 632
 633 static int
 634 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 635                       uint32_t desc_cnt, uint32_t buffsz)
 636 {
 637         struct nicvf_rbdr *rbdr;
 638         const struct rte_memzone *rz;
 639         uint32_t ring_size;
 640
 641         assert(nic->rbdr == NULL);
 642         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 643                                   RTE_CACHE_LINE_SIZE, nic->node);
 644         if (rbdr == NULL) {
 645                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 646                 return -ENOMEM;
 647         }
 648
 649         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 650         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 651                                       nicvf_netdev_qidx(nic, 0), ring_size,
 652                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 653         if (rz == NULL) {
 654                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 655                 return -ENOMEM;
 656         }
 657
 658         memset(rz->addr, 0, ring_size);
 659
 660         rbdr->phys = rz->iova;
 661         rbdr->tail = 0;
 662         rbdr->next_tail = 0;
 663         rbdr->desc = rz->addr;
 664         rbdr->buffsz = buffsz;
 665         rbdr->qlen_mask = desc_cnt - 1;
 666         rbdr->rbdr_status =
 667                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 668         rbdr->rbdr_door =
 669                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 670
 671         nic->rbdr = rbdr;
 672         return 0;
 673 }
 674
 675 static void
 676 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 677                         nicvf_iova_addr_t phy)
 678 {
 679         uint16_t qidx;
 680         void *obj;
 681         struct nicvf_rxq *rxq;
 682         uint16_t rx_start, rx_end;
 683
 684         /* Get queue ranges for this VF */
 685         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 686
 687         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 688                 rxq = dev->data->rx_queues[qidx];
 689                 if (rxq->precharge_cnt) {
 690                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 691                                                            rxq->mbuf_phys_off);
 692                         rte_mempool_put(rxq->pool, obj);
 693                         rxq->precharge_cnt--;
 694                         break;
 695                 }
 696         }
 697 }
 698
 699 static inline void
 700 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 701 {
 702         uint32_t qlen_mask, head;
 703         struct rbdr_entry_t *entry;
 704         struct nicvf_rbdr *rbdr = nic->rbdr;
 705
 706         qlen_mask = rbdr->qlen_mask;
 707         head = rbdr->head;
 708         while (head != rbdr->tail) {
 709                 entry = rbdr->desc + head;
 710                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 711                 head++;
 712                 head = head & qlen_mask;
 713         }
 714 }
 715
 716 static inline void
 717 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 718 {
 719         uint32_t head;
 720
 721         head = txq->head;
 722         while (head != txq->tail) {
 723                 if (txq->txbuffs[head]) {
 724                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 725                         txq->txbuffs[head] = NULL;
 726                 }
 727                 head++;
 728                 head = head & txq->qlen_mask;
 729         }
 730 }
 731
 732 static void
 733 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 734 {
 735         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 736
 737         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 738         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 739         txq->tail = 0;
 740         txq->head = 0;
 741         txq->xmit_bufs = 0;
 742 }
 743
 744 static inline int
 745 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 746                         uint16_t qidx)
 747 {
 748         struct nicvf_txq *txq;
 749         int ret;
 750
 751         assert(qidx < MAX_SND_QUEUES_PER_QS);
 752
 753         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 754                 RTE_ETH_QUEUE_STATE_STARTED)
 755                 return 0;
 756
 757         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 758         txq->pool = NULL;
 759         ret = nicvf_qset_sq_config(nic, qidx, txq);
 760         if (ret) {
 761                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 762                              nic->vf_id, qidx, ret);
 763                 goto config_sq_error;
 764         }
 765
 766         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 767                 RTE_ETH_QUEUE_STATE_STARTED;
 768         return ret;
 769
 770 config_sq_error:
 771         nicvf_qset_sq_reclaim(nic, qidx);
 772         return ret;
 773 }
 774
 775 static inline int
 776 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 777                        uint16_t qidx)
 778 {
 779         struct nicvf_txq *txq;
 780         int ret;
 781
 782         assert(qidx < MAX_SND_QUEUES_PER_QS);
 783
 784         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 785                 RTE_ETH_QUEUE_STATE_STOPPED)
 786                 return 0;
 787
 788         ret = nicvf_qset_sq_reclaim(nic, qidx);
 789         if (ret)
 790                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 791                              nic->vf_id, qidx, ret);
 792
 793         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 794         nicvf_tx_queue_release_mbufs(txq);
 795         nicvf_tx_queue_reset(txq);
 796
 797         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 798                 RTE_ETH_QUEUE_STATE_STOPPED;
 799         return ret;
 800 }
 801
 802 static inline int
 803 nicvf_configure_cpi(struct rte_eth_dev *dev)
 804 {
 805         struct nicvf *nic = nicvf_pmd_priv(dev);
 806         uint16_t qidx, qcnt;
 807         int ret;
 808
 809         /* Count started rx queues */
 810         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 811                 if (dev->data->rx_queue_state[qidx] ==
 812                     RTE_ETH_QUEUE_STATE_STARTED)
 813                         qcnt++;
 814
 815         nic->cpi_alg = CPI_ALG_NONE;
 816         ret = nicvf_mbox_config_cpi(nic, qcnt);
 817         if (ret)
 818                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 819
 820         return ret;
 821 }
 822
 823 static inline int
 824 nicvf_configure_rss(struct rte_eth_dev *dev)
 825 {
 826         struct nicvf *nic = nicvf_pmd_priv(dev);
 827         uint64_t rsshf;
 828         int ret = -EINVAL;
 829
 830         rsshf = nicvf_rss_ethdev_to_nic(nic,
 831                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 832         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 833                     dev->data->dev_conf.rxmode.mq_mode,
 834                     dev->data->nb_rx_queues,
 835                     dev->data->dev_conf.lpbk_mode, rsshf);
 836
 837         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 838                 ret = nicvf_rss_term(nic);
 839         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 840                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 841         if (ret)
 842                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 843
 844         return ret;
 845 }
 846
 847 static int
 848 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 849 {
 850         struct nicvf *nic = nicvf_pmd_priv(dev);
 851         unsigned int idx, qmap_size;
 852         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 853         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 854
 855         if (nic->cpi_alg != CPI_ALG_NONE)
 856                 return -EINVAL;
 857
 858         /* Prepare queue map */
 859         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 860                 if (dev->data->rx_queue_state[idx] ==
 861                                 RTE_ETH_QUEUE_STATE_STARTED)
 862                         qmap[qmap_size++] = idx;
 863         }
 864
 865         /* Update default RSS RETA */
 866         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 867                 default_reta[idx] = qmap[idx % qmap_size];
 868
 869         return nicvf_rss_reta_update(nic, default_reta,
 870                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 871 }
 872
 873 static void
 874 nicvf_dev_tx_queue_release(void *sq)
 875 {
 876         struct nicvf_txq *txq;
 877
 878         PMD_INIT_FUNC_TRACE();
 879
 880         txq = (struct nicvf_txq *)sq;
 881         if (txq) {
 882                 if (txq->txbuffs != NULL) {
 883                         nicvf_tx_queue_release_mbufs(txq);
 884                         rte_free(txq->txbuffs);
 885                         txq->txbuffs = NULL;
 886                 }
 887                 rte_free(txq);
 888         }
 889 }
 890
 891 static void
 892 nicvf_set_tx_function(struct rte_eth_dev *dev)
 893 {
 894         struct nicvf_txq *txq = NULL;
 895         size_t i;
 896         bool multiseg = false;
 897
 898         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 899                 txq = dev->data->tx_queues[i];
 900                 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
 901                         multiseg = true;
 902                         break;
 903                 }
 904         }
 905
 906         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 907         if (multiseg) {
 908                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 909                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 910         } else {
 911                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 912                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 913         }
 914
 915         if (!txq)
 916                 return;
 917
 918         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 919                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 920         else
 921                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 922 }
 923
 924 static void
 925 nicvf_set_rx_function(struct rte_eth_dev *dev)
 926 {
 927         struct nicvf *nic = nicvf_pmd_priv(dev);
 928
 929         const eth_rx_burst_t rx_burst_func[2][2][2] = {
 930         /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */
 931                 [0][0][0] = nicvf_recv_pkts_no_offload,
 932                 [0][0][1] = nicvf_recv_pkts_vlan_strip,
 933                 [0][1][0] = nicvf_recv_pkts_cksum,
 934                 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip,
 935                 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload,
 936                 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip,
 937                 [1][1][0] = nicvf_recv_pkts_multiseg_cksum,
 938                 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip,
 939         };
 940
 941         dev->rx_pkt_burst =
 942                 rx_burst_func[dev->data->scattered_rx]
 943                         [nic->offload_cksum][nic->vlan_strip];
 944 }
 945
 946 static int
 947 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 948                          uint16_t nb_desc, unsigned int socket_id,
 949                          const struct rte_eth_txconf *tx_conf)
 950 {
 951         uint16_t tx_free_thresh;
 952         bool is_single_pool;
 953         struct nicvf_txq *txq;
 954         struct nicvf *nic = nicvf_pmd_priv(dev);
 955         uint64_t offloads;
 956
 957         PMD_INIT_FUNC_TRACE();
 958
 959         if (qidx >= MAX_SND_QUEUES_PER_QS)
 960                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 961
 962         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 963
 964         /* Socket id check */
 965         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 966                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 967                 socket_id, nic->node);
 968
 969         /* Tx deferred start is not supported */
 970         if (tx_conf->tx_deferred_start) {
 971                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 972                 return -EINVAL;
 973         }
 974
 975         /* Roundup nb_desc to available qsize and validate max number of desc */
 976         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 977         if (nb_desc == 0) {
 978                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 979                 return -EINVAL;
 980         }
 981
 982         /* Validate tx_free_thresh */
 983         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 984                                 tx_conf->tx_free_thresh :
 985                                 NICVF_DEFAULT_TX_FREE_THRESH);
 986
 987         if (tx_free_thresh > (nb_desc) ||
 988                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 989                 PMD_INIT_LOG(ERR,
 990                         "tx_free_thresh must be less than the number of TX "
 991                         "descriptors. (tx_free_thresh=%u port=%d "
 992                         "queue=%d)", (unsigned int)tx_free_thresh,
 993                         (int)dev->data->port_id, (int)qidx);
 994                 return -EINVAL;
 995         }
 996
 997         /* Free memory prior to re-allocation if needed. */
 998         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 999                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1000                                 nicvf_netdev_qidx(nic, qidx));
1001                 nicvf_dev_tx_queue_release(
1002                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
1003                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1004         }
1005
1006         /* Allocating tx queue data structure */
1007         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
1008                                         RTE_CACHE_LINE_SIZE, nic->node);
1009         if (txq == NULL) {
1010                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
1011                              nicvf_netdev_qidx(nic, qidx));
1012                 return -ENOMEM;
1013         }
1014
1015         txq->nic = nic;
1016         txq->queue_id = qidx;
1017         txq->tx_free_thresh = tx_free_thresh;
1018         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1019         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1020         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1021         txq->offloads = offloads;
1022
1023         is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);
1024
1025         /* Choose optimum free threshold value for multipool case */
1026         if (!is_single_pool) {
1027                 txq->tx_free_thresh = (uint16_t)
1028                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1029                                 NICVF_TX_FREE_MPOOL_THRESH :
1030                                 tx_conf->tx_free_thresh);
1031                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1032         } else {
1033                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1034         }
1035
1036         /* Allocate software ring */
1037         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1038                                 nb_desc * sizeof(struct rte_mbuf *),
1039                                 RTE_CACHE_LINE_SIZE, nic->node);
1040
1041         if (txq->txbuffs == NULL) {
1042                 nicvf_dev_tx_queue_release(txq);
1043                 return -ENOMEM;
1044         }
1045
1046         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1047                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1048                 nicvf_dev_tx_queue_release(txq);
1049                 return -ENOMEM;
1050         }
1051
1052         nicvf_tx_queue_reset(txq);
1053
1054         PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p"
1055                         " phys=0x%" PRIx64 " offloads=0x%" PRIx64,
1056                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1057                         txq->phys, txq->offloads);
1058
1059         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1060         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1061                 RTE_ETH_QUEUE_STATE_STOPPED;
1062         return 0;
1063 }
1064
1065 static inline void
1066 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1067 {
1068         uint32_t rxq_cnt;
1069         uint32_t nb_pkts, released_pkts = 0;
1070         uint32_t refill_cnt = 0;
1071         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1072
1073         if (dev->rx_pkt_burst == NULL)
1074                 return;
1075
1076         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1077                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1078                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1079                                         NICVF_MAX_RX_FREE_THRESH);
1080                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1081                 while (nb_pkts) {
1082                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1083                         released_pkts++;
1084                 }
1085         }
1086
1087
1088         refill_cnt += nicvf_dev_rbdr_refill(dev,
1089                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1090
1091         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1092                     released_pkts, refill_cnt);
1093 }
1094
1095 static void
1096 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1097 {
1098         rxq->head = 0;
1099         rxq->available_space = 0;
1100         rxq->recv_buffers = 0;
1101 }
1102
1103 static inline int
1104 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1105                         uint16_t qidx)
1106 {
1107         struct nicvf_rxq *rxq;
1108         int ret;
1109
1110         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1111
1112         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1113                 RTE_ETH_QUEUE_STATE_STARTED)
1114                 return 0;
1115
1116         /* Update rbdr pointer to all rxq */
1117         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1118         rxq->shared_rbdr = nic->rbdr;
1119
1120         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1121         if (ret) {
1122                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1123                              nic->vf_id, qidx, ret);
1124                 goto config_rq_error;
1125         }
1126         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1127         if (ret) {
1128                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1129                              nic->vf_id, qidx, ret);
1130                 goto config_cq_error;
1131         }
1132
1133         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1134                 RTE_ETH_QUEUE_STATE_STARTED;
1135         return 0;
1136
1137 config_cq_error:
1138         nicvf_qset_cq_reclaim(nic, qidx);
1139 config_rq_error:
1140         nicvf_qset_rq_reclaim(nic, qidx);
1141         return ret;
1142 }
1143
1144 static inline int
1145 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1146                        uint16_t qidx)
1147 {
1148         struct nicvf_rxq *rxq;
1149         int ret, other_error;
1150
1151         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1152                 RTE_ETH_QUEUE_STATE_STOPPED)
1153                 return 0;
1154
1155         ret = nicvf_qset_rq_reclaim(nic, qidx);
1156         if (ret)
1157                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1158                              nic->vf_id, qidx, ret);
1159
1160         other_error = ret;
1161         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1162         nicvf_rx_queue_release_mbufs(dev, rxq);
1163         nicvf_rx_queue_reset(rxq);
1164
1165         ret = nicvf_qset_cq_reclaim(nic, qidx);
1166         if (ret)
1167                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1168                              nic->vf_id, qidx, ret);
1169
1170         other_error |= ret;
1171         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1172                 RTE_ETH_QUEUE_STATE_STOPPED;
1173         return other_error;
1174 }
1175
1176 static void
1177 nicvf_dev_rx_queue_release(void *rx_queue)
1178 {
1179         PMD_INIT_FUNC_TRACE();
1180
1181         rte_free(rx_queue);
1182 }
1183
1184 static int
1185 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1186 {
1187         struct nicvf *nic = nicvf_pmd_priv(dev);
1188         int ret;
1189
1190         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1191                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1192
1193         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1194
1195         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1196         if (ret)
1197                 return ret;
1198
1199         ret = nicvf_configure_cpi(dev);
1200         if (ret)
1201                 return ret;
1202
1203         return nicvf_configure_rss_reta(dev);
1204 }
1205
1206 static int
1207 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1208 {
1209         int ret;
1210         struct nicvf *nic = nicvf_pmd_priv(dev);
1211
1212         if (qidx >= MAX_SND_QUEUES_PER_QS)
1213                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1214
1215         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1216
1217         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1218         ret |= nicvf_configure_cpi(dev);
1219         ret |= nicvf_configure_rss_reta(dev);
1220         return ret;
1221 }
1222
1223 static int
1224 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1225 {
1226         struct nicvf *nic = nicvf_pmd_priv(dev);
1227
1228         if (qidx >= MAX_SND_QUEUES_PER_QS)
1229                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1230
1231         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1232
1233         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1234 }
1235
1236 static int
1237 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1238 {
1239         struct nicvf *nic = nicvf_pmd_priv(dev);
1240
1241         if (qidx >= MAX_SND_QUEUES_PER_QS)
1242                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1243
1244         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1245
1246         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1247 }
1248
1249 static inline void
1250 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1251 {
1252         uintptr_t p;
1253         struct rte_mbuf mb_def;
1254         struct nicvf *nic = rxq->nic;
1255
1256         RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1257         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1258         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1259                                 offsetof(struct rte_mbuf, data_off) != 2);
1260         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1261                                 offsetof(struct rte_mbuf, data_off) != 4);
1262         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1263                                 offsetof(struct rte_mbuf, data_off) != 6);
1264         RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) -
1265                                 offsetof(struct nicvf_rxq,
1266                                         rxq_fastpath_data_start) > 128);
1267         mb_def.nb_segs = 1;
1268         mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes);
1269         mb_def.port = rxq->port_id;
1270         rte_mbuf_refcnt_set(&mb_def, 1);
1271
1272         /* Prevent compiler reordering: rearm_data covers previous fields */
1273         rte_compiler_barrier();
1274         p = (uintptr_t)&mb_def.rearm_data;
1275         rxq->mbuf_initializer.value = *(uint64_t *)p;
1276 }
1277
1278 static int
1279 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1280                          uint16_t nb_desc, unsigned int socket_id,
1281                          const struct rte_eth_rxconf *rx_conf,
1282                          struct rte_mempool *mp)
1283 {
1284         uint16_t rx_free_thresh;
1285         struct nicvf_rxq *rxq;
1286         struct nicvf *nic = nicvf_pmd_priv(dev);
1287         uint64_t offloads;
1288         uint32_t buffsz;
1289         struct rte_pktmbuf_pool_private *mbp_priv;
1290
1291         PMD_INIT_FUNC_TRACE();
1292
1293         /* First skip check */
1294         mbp_priv = rte_mempool_get_priv(mp);
1295         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1296         if (buffsz < (uint32_t)(nic->skip_bytes)) {
1297                 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size");
1298                 return -EINVAL;
1299         }
1300
1301         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1302                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1303
1304         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1305
1306         /* Socket id check */
1307         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1308                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1309                 socket_id, nic->node);
1310
1311         /* Mempool memory must be contiguous, so must be one memory segment*/
1312         if (mp->nb_mem_chunks != 1) {
1313                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1314                 return -EINVAL;
1315         }
1316
1317         /* Mempool memory must be physically contiguous */
1318         if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) {
1319                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1320                 return -EINVAL;
1321         }
1322
1323         /* Rx deferred start is not supported */
1324         if (rx_conf->rx_deferred_start) {
1325                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1326                 return -EINVAL;
1327         }
1328
1329         /* Roundup nb_desc to available qsize and validate max number of desc */
1330         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1331         if (nb_desc == 0) {
1332                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1333                 return -EINVAL;
1334         }
1335
1336
1337         /* Check rx_free_thresh upper bound */
1338         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1339                                 rx_conf->rx_free_thresh :
1340                                 NICVF_DEFAULT_RX_FREE_THRESH);
1341         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1342                 rx_free_thresh >= nb_desc * .75) {
1343                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1344                                 rx_free_thresh);
1345                 return -EINVAL;
1346         }
1347
1348         /* Free memory prior to re-allocation if needed */
1349         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1350                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1351                                 nicvf_netdev_qidx(nic, qidx));
1352                 nicvf_dev_rx_queue_release(
1353                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1354                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1355         }
1356
1357         /* Allocate rxq memory */
1358         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1359                                         RTE_CACHE_LINE_SIZE, nic->node);
1360         if (rxq == NULL) {
1361                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1362                              nicvf_netdev_qidx(nic, qidx));
1363                 return -ENOMEM;
1364         }
1365
1366         rxq->nic = nic;
1367         rxq->pool = mp;
1368         rxq->queue_id = qidx;
1369         rxq->port_id = dev->data->port_id;
1370         rxq->rx_free_thresh = rx_free_thresh;
1371         rxq->rx_drop_en = rx_conf->rx_drop_en;
1372         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1373         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1374         rxq->precharge_cnt = 0;
1375
1376         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1377                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1378         else
1379                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1380
1381         nicvf_rxq_mbuf_setup(rxq);
1382
1383         /* Alloc completion queue */
1384         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1385                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1386                 nicvf_dev_rx_queue_release(rxq);
1387                 return -ENOMEM;
1388         }
1389
1390         nicvf_rx_queue_reset(rxq);
1391
1392         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1393         PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)"
1394                         " phy=0x%" PRIx64 " offloads=0x%" PRIx64,
1395                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1396                         rte_mempool_avail_count(mp), rxq->phys, offloads);
1397
1398         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1399         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1400                 RTE_ETH_QUEUE_STATE_STOPPED;
1401         return 0;
1402 }
1403
1404 static int
1405 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1406 {
1407         struct nicvf *nic = nicvf_pmd_priv(dev);
1408         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1409
1410         PMD_INIT_FUNC_TRACE();
1411
1412         /* Autonegotiation may be disabled */
1413         dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1414         dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1415                                  ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1416         if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1417                 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1418
1419         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1420         dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN;
1421         dev_info->max_rx_queues =
1422                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1423         dev_info->max_tx_queues =
1424                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1425         dev_info->max_mac_addrs = 1;
1426         dev_info->max_vfs = pci_dev->max_vfs;
1427
1428         dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1429         dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1430         dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1431         dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1432
1433         dev_info->reta_size = nic->rss_info.rss_size;
1434         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1435         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1436         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1437                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1438
1439         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1440                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1441                 .rx_drop_en = 0,
1442         };
1443
1444         dev_info->default_txconf = (struct rte_eth_txconf) {
1445                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1446                 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE |
1447                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM   |
1448                         DEV_TX_OFFLOAD_UDP_CKSUM          |
1449                         DEV_TX_OFFLOAD_TCP_CKSUM,
1450         };
1451
1452         return 0;
1453 }
1454
1455 static nicvf_iova_addr_t
1456 rbdr_rte_mempool_get(void *dev, void *opaque)
1457 {
1458         uint16_t qidx;
1459         uintptr_t mbuf;
1460         struct nicvf_rxq *rxq;
1461         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1462         struct nicvf *nic = (struct nicvf *)opaque;
1463         uint16_t rx_start, rx_end;
1464
1465         /* Get queue ranges for this VF */
1466         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1467
1468         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1469                 rxq = eth_dev->data->rx_queues[qidx];
1470                 /* Maintain equal buffer count across all pools */
1471                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1472                         continue;
1473                 rxq->precharge_cnt++;
1474                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1475                 if (mbuf)
1476                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1477         }
1478         return 0;
1479 }
1480
1481 static int
1482 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1483 {
1484         int ret;
1485         uint16_t qidx, data_off;
1486         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1487         uint64_t mbuf_phys_off = 0;
1488         struct nicvf_rxq *rxq;
1489         struct rte_mbuf *mbuf;
1490         uint16_t rx_start, rx_end;
1491         uint16_t tx_start, tx_end;
1492         int mask;
1493
1494         PMD_INIT_FUNC_TRACE();
1495
1496         /* Userspace process exited without proper shutdown in last run */
1497         if (nicvf_qset_rbdr_active(nic, 0))
1498                 nicvf_vf_stop(dev, nic, false);
1499
1500         /* Get queue ranges for this VF */
1501         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1502
1503         /*
1504          * Thunderx nicvf PMD can support more than one pool per port only when
1505          * 1) Data payload size is same across all the pools in given port
1506          * AND
1507          * 2) All mbuffs in the pools are from the same hugepage
1508          * AND
1509          * 3) Mbuff metadata size is same across all the pools in given port
1510          *
1511          * This is to support existing application that uses multiple pool/port.
1512          * But, the purpose of using multipool for QoS will not be addressed.
1513          *
1514          */
1515
1516         /* Validate mempool attributes */
1517         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1518                 rxq = dev->data->rx_queues[qidx];
1519                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1520                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1521                 if (mbuf == NULL) {
1522                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1523                                      "pool=%s",
1524                                      nic->vf_id, qidx, rxq->pool->name);
1525                         return -ENOMEM;
1526                 }
1527                 data_off = nicvf_mbuff_meta_length(mbuf);
1528                 data_off += RTE_PKTMBUF_HEADROOM;
1529                 rte_pktmbuf_free(mbuf);
1530
1531                 if (data_off % RTE_CACHE_LINE_SIZE) {
1532                         PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1533                                 rxq->pool->name, data_off,
1534                                 data_off % RTE_CACHE_LINE_SIZE);
1535                         return -EINVAL;
1536                 }
1537                 rxq->mbuf_phys_off -= data_off;
1538                 rxq->mbuf_phys_off -= nic->skip_bytes;
1539
1540                 if (mbuf_phys_off == 0)
1541                         mbuf_phys_off = rxq->mbuf_phys_off;
1542                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1543                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1544                                      PRIx64, rxq->pool->name, nic->vf_id,
1545                                      mbuf_phys_off);
1546                         return -EINVAL;
1547                 }
1548         }
1549
1550         /* Check the level of buffers in the pool */
1551         total_rxq_desc = 0;
1552         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1553                 rxq = dev->data->rx_queues[qidx];
1554                 /* Count total numbers of rxq descs */
1555                 total_rxq_desc += rxq->qlen_mask + 1;
1556                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1557                 exp_buffs *= dev->data->nb_rx_queues;
1558                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1559                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1560                                      rxq->pool->name,
1561                                      rte_mempool_avail_count(rxq->pool),
1562                                      exp_buffs);
1563                         return -ENOENT;
1564                 }
1565         }
1566
1567         /* Check RBDR desc overflow */
1568         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1569         if (ret == 0) {
1570                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1571                              "VF%d", nic->vf_id);
1572                 return -ENOMEM;
1573         }
1574
1575         /* Enable qset */
1576         ret = nicvf_qset_config(nic);
1577         if (ret) {
1578                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1579                              nic->vf_id);
1580                 return ret;
1581         }
1582
1583         /* Allocate RBDR and RBDR ring desc */
1584         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1585         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1586         if (ret) {
1587                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1588                              "VF%d", nic->vf_id);
1589                 goto qset_reclaim;
1590         }
1591
1592         /* Enable and configure RBDR registers */
1593         ret = nicvf_qset_rbdr_config(nic, 0);
1594         if (ret) {
1595                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1596                              nic->vf_id);
1597                 goto qset_rbdr_free;
1598         }
1599
1600         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1601         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1602                                         total_rxq_desc);
1603         if (ret) {
1604                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1605                              nic->vf_id);
1606                 goto qset_rbdr_reclaim;
1607         }
1608
1609         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1610                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1611
1612         /* Configure VLAN Strip */
1613         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1614                 ETH_VLAN_EXTEND_MASK;
1615         ret = nicvf_vlan_offload_config(dev, mask);
1616
1617         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1618          * to the 64bit memory address.
1619          * The alignment creates a hole in mbuf(between the end of headroom and
1620          * packet data start). The new revision of the HW provides an option to
1621          * disable the L3 alignment feature and make mbuf layout looks
1622          * more like other NICs. For better application compatibility, disabling
1623          * l3 alignment feature on the hardware revisions it supports
1624          */
1625         nicvf_apad_config(nic, false);
1626
1627         /* Get queue ranges for this VF */
1628         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1629
1630         /* Configure TX queues */
1631         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1632                 ret = nicvf_vf_start_tx_queue(dev, nic,
1633                         qidx % MAX_SND_QUEUES_PER_QS);
1634                 if (ret)
1635                         goto start_txq_error;
1636         }
1637
1638         /* Configure RX queues */
1639         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1640                 ret = nicvf_vf_start_rx_queue(dev, nic,
1641                         qidx % MAX_RCV_QUEUES_PER_QS);
1642                 if (ret)
1643                         goto start_rxq_error;
1644         }
1645
1646         if (!nic->sqs_mode) {
1647                 /* Configure CPI algorithm */
1648                 ret = nicvf_configure_cpi(dev);
1649                 if (ret)
1650                         goto start_txq_error;
1651
1652                 ret = nicvf_mbox_get_rss_size(nic);
1653                 if (ret) {
1654                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1655                         goto qset_rss_error;
1656                 }
1657
1658                 /* Configure RSS */
1659                 ret = nicvf_configure_rss(dev);
1660                 if (ret)
1661                         goto qset_rss_error;
1662         }
1663
1664         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1665         nicvf_mbox_cfg_done(nic);
1666         return 0;
1667
1668 qset_rss_error:
1669         nicvf_rss_term(nic);
1670 start_rxq_error:
1671         for (qidx = rx_start; qidx <= rx_end; qidx++)
1672                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1673 start_txq_error:
1674         for (qidx = tx_start; qidx <= tx_end; qidx++)
1675                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1676 qset_rbdr_reclaim:
1677         nicvf_qset_rbdr_reclaim(nic, 0);
1678         nicvf_rbdr_release_mbufs(dev, nic);
1679 qset_rbdr_free:
1680         if (nic->rbdr) {
1681                 rte_free(nic->rbdr);
1682                 nic->rbdr = NULL;
1683         }
1684 qset_reclaim:
1685         nicvf_qset_reclaim(nic);
1686         return ret;
1687 }
1688
1689 static int
1690 nicvf_dev_start(struct rte_eth_dev *dev)
1691 {
1692         uint16_t qidx;
1693         int ret;
1694         size_t i;
1695         struct nicvf *nic = nicvf_pmd_priv(dev);
1696         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1697         uint16_t mtu;
1698         uint32_t buffsz = 0, rbdrsz = 0;
1699         struct rte_pktmbuf_pool_private *mbp_priv;
1700         struct nicvf_rxq *rxq;
1701
1702         PMD_INIT_FUNC_TRACE();
1703
1704         /* This function must be called for a primary device */
1705         assert_primary(nic);
1706
1707         /* Validate RBDR buff size */
1708         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1709                 rxq = dev->data->rx_queues[qidx];
1710                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1711                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1712                 if (buffsz % 128) {
1713                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1714                         return -EINVAL;
1715                 }
1716                 if (rbdrsz == 0)
1717                         rbdrsz = buffsz;
1718                 if (rbdrsz != buffsz) {
1719                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1720                                      qidx, rbdrsz, buffsz);
1721                         return -EINVAL;
1722                 }
1723         }
1724
1725         /* Configure loopback */
1726         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1727         if (ret) {
1728                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1729                 return ret;
1730         }
1731
1732         /* Reset all statistics counters attached to this port */
1733         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1734         if (ret) {
1735                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1736                 return ret;
1737         }
1738
1739         /* Setup scatter mode if needed by jumbo */
1740         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1741                                             2 * VLAN_TAG_SIZE > buffsz)
1742                 dev->data->scattered_rx = 1;
1743         if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0)
1744                 dev->data->scattered_rx = 1;
1745
1746         /* Setup MTU based on max_rx_pkt_len or default */
1747         mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ?
1748                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1749                         -  RTE_ETHER_HDR_LEN : RTE_ETHER_MTU;
1750
1751         if (nicvf_dev_set_mtu(dev, mtu)) {
1752                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1753                 return -EBUSY;
1754         }
1755
1756         ret = nicvf_vf_start(dev, nic, rbdrsz);
1757         if (ret != 0)
1758                 return ret;
1759
1760         for (i = 0; i < nic->sqs_count; i++) {
1761                 assert(nic->snicvf[i]);
1762
1763                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1764                 if (ret != 0)
1765                         return ret;
1766         }
1767
1768         /* Configure callbacks based on offloads */
1769         nicvf_set_tx_function(dev);
1770         nicvf_set_rx_function(dev);
1771
1772         return 0;
1773 }
1774
1775 static void
1776 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1777 {
1778         size_t i;
1779         int ret;
1780         struct nicvf *nic = nicvf_pmd_priv(dev);
1781
1782         PMD_INIT_FUNC_TRACE();
1783
1784         /* Teardown secondary vf first */
1785         for (i = 0; i < nic->sqs_count; i++) {
1786                 if (!nic->snicvf[i])
1787                         continue;
1788
1789                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1790         }
1791
1792         /* Stop the primary VF now */
1793         nicvf_vf_stop(dev, nic, cleanup);
1794
1795         /* Disable loopback */
1796         ret = nicvf_loopback_config(nic, 0);
1797         if (ret)
1798                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1799
1800         /* Reclaim CPI configuration */
1801         ret = nicvf_mbox_config_cpi(nic, 0);
1802         if (ret)
1803                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1804 }
1805
1806 static void
1807 nicvf_dev_stop(struct rte_eth_dev *dev)
1808 {
1809         PMD_INIT_FUNC_TRACE();
1810
1811         nicvf_dev_stop_cleanup(dev, false);
1812 }
1813
1814 static void
1815 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1816 {
1817         int ret;
1818         uint16_t qidx;
1819         uint16_t tx_start, tx_end;
1820         uint16_t rx_start, rx_end;
1821
1822         PMD_INIT_FUNC_TRACE();
1823
1824         if (cleanup) {
1825                 /* Let PF make the BGX's RX and TX switches to OFF position */
1826                 nicvf_mbox_shutdown(nic);
1827         }
1828
1829         /* Disable VLAN Strip */
1830         nicvf_vlan_hw_strip(nic, 0);
1831
1832         /* Get queue ranges for this VF */
1833         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1834
1835         for (qidx = tx_start; qidx <= tx_end; qidx++)
1836                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1837
1838         /* Get queue ranges for this VF */
1839         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1840
1841         /* Reclaim rq */
1842         for (qidx = rx_start; qidx <= rx_end; qidx++)
1843                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1844
1845         /* Reclaim RBDR */
1846         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1847         if (ret)
1848                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1849
1850         /* Move all charged buffers in RBDR back to pool */
1851         if (nic->rbdr != NULL)
1852                 nicvf_rbdr_release_mbufs(dev, nic);
1853
1854         /* Disable qset */
1855         ret = nicvf_qset_reclaim(nic);
1856         if (ret)
1857                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1858
1859         /* Disable all interrupts */
1860         nicvf_disable_all_interrupts(nic);
1861
1862         /* Free RBDR SW structure */
1863         if (nic->rbdr) {
1864                 rte_free(nic->rbdr);
1865                 nic->rbdr = NULL;
1866         }
1867 }
1868
1869 static void
1870 nicvf_dev_close(struct rte_eth_dev *dev)
1871 {
1872         size_t i;
1873         struct nicvf *nic = nicvf_pmd_priv(dev);
1874
1875         PMD_INIT_FUNC_TRACE();
1876
1877         nicvf_dev_stop_cleanup(dev, true);
1878         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1879
1880         for (i = 0; i < nic->sqs_count; i++) {
1881                 if (!nic->snicvf[i])
1882                         continue;
1883
1884                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1885         }
1886 }
1887
1888 static int
1889 nicvf_request_sqs(struct nicvf *nic)
1890 {
1891         size_t i;
1892
1893         assert_primary(nic);
1894         assert(nic->sqs_count > 0);
1895         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1896
1897         /* Set no of Rx/Tx queues in each of the SQsets */
1898         for (i = 0; i < nic->sqs_count; i++) {
1899                 if (nicvf_svf_empty())
1900                         rte_panic("Cannot assign sufficient number of "
1901                                   "secondary queues to primary VF%" PRIu8 "\n",
1902                                   nic->vf_id);
1903
1904                 nic->snicvf[i] = nicvf_svf_pop();
1905                 nic->snicvf[i]->sqs_id = i;
1906         }
1907
1908         return nicvf_mbox_request_sqs(nic);
1909 }
1910
1911 static int
1912 nicvf_dev_configure(struct rte_eth_dev *dev)
1913 {
1914         struct rte_eth_dev_data *data = dev->data;
1915         struct rte_eth_conf *conf = &data->dev_conf;
1916         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1917         struct rte_eth_txmode *txmode = &conf->txmode;
1918         struct nicvf *nic = nicvf_pmd_priv(dev);
1919         uint8_t cqcount;
1920
1921         PMD_INIT_FUNC_TRACE();
1922
1923         if (rxmode->mq_mode & ETH_MQ_RX_RSS_FLAG)
1924                 rxmode->offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1925
1926         if (!rte_eal_has_hugepages()) {
1927                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1928                 return -EINVAL;
1929         }
1930
1931         if (txmode->mq_mode) {
1932                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1933                 return -EINVAL;
1934         }
1935
1936         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1937                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1938                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1939                 return -EINVAL;
1940         }
1941
1942         if (rxmode->split_hdr_size) {
1943                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1944                 return -EINVAL;
1945         }
1946
1947         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1948                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1949                 return -EINVAL;
1950         }
1951
1952         if (conf->dcb_capability_en) {
1953                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1954                 return -EINVAL;
1955         }
1956
1957         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1958                 PMD_INIT_LOG(INFO, "Flow director not supported");
1959                 return -EINVAL;
1960         }
1961
1962         assert_primary(nic);
1963         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1964         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1965         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1966                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1967                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1968         } else {
1969                 nic->sqs_count = 0;
1970         }
1971
1972         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1973
1974         if (nic->sqs_count > 0) {
1975                 if (nicvf_request_sqs(nic)) {
1976                         rte_panic("Cannot assign sufficient number of "
1977                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1978                                   dev->data->port_id, nic->vf_id);
1979                 }
1980         }
1981
1982         if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
1983                 nic->offload_cksum = 1;
1984
1985         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1986                 dev->data->port_id, nicvf_hw_cap(nic));
1987
1988         return 0;
1989 }
1990
1991 static int
1992 nicvf_dev_set_link_up(struct rte_eth_dev *dev)
1993 {
1994         struct nicvf *nic = nicvf_pmd_priv(dev);
1995         int rc, i;
1996
1997         rc = nicvf_mbox_set_link_up_down(nic, true);
1998         if (rc)
1999                 goto done;
2000
2001         /* Start tx queues  */
2002         for (i = 0; i < dev->data->nb_tx_queues; i++)
2003                 nicvf_dev_tx_queue_start(dev, i);
2004
2005 done:
2006         return rc;
2007 }
2008
2009 static int
2010 nicvf_dev_set_link_down(struct rte_eth_dev *dev)
2011 {
2012         struct nicvf *nic = nicvf_pmd_priv(dev);
2013         int i;
2014
2015         /* Stop tx queues  */
2016         for (i = 0; i < dev->data->nb_tx_queues; i++)
2017                 nicvf_dev_tx_queue_stop(dev, i);
2018
2019         return nicvf_mbox_set_link_up_down(nic, false);
2020 }
2021
2022 /* Initialize and register driver with DPDK Application */
2023 static const struct eth_dev_ops nicvf_eth_dev_ops = {
2024         .dev_configure            = nicvf_dev_configure,
2025         .dev_start                = nicvf_dev_start,
2026         .dev_stop                 = nicvf_dev_stop,
2027         .link_update              = nicvf_dev_link_update,
2028         .dev_close                = nicvf_dev_close,
2029         .stats_get                = nicvf_dev_stats_get,
2030         .stats_reset              = nicvf_dev_stats_reset,
2031         .promiscuous_enable       = nicvf_dev_promisc_enable,
2032         .dev_infos_get            = nicvf_dev_info_get,
2033         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
2034         .mtu_set                  = nicvf_dev_set_mtu,
2035         .vlan_offload_set         = nicvf_vlan_offload_set,
2036         .reta_update              = nicvf_dev_reta_update,
2037         .reta_query               = nicvf_dev_reta_query,
2038         .rss_hash_update          = nicvf_dev_rss_hash_update,
2039         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
2040         .rx_queue_start           = nicvf_dev_rx_queue_start,
2041         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
2042         .tx_queue_start           = nicvf_dev_tx_queue_start,
2043         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
2044         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
2045         .rx_queue_release         = nicvf_dev_rx_queue_release,
2046         .rx_queue_count           = nicvf_dev_rx_queue_count,
2047         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
2048         .tx_queue_release         = nicvf_dev_tx_queue_release,
2049         .dev_set_link_up          = nicvf_dev_set_link_up,
2050         .dev_set_link_down        = nicvf_dev_set_link_down,
2051         .get_reg                  = nicvf_dev_get_regs,
2052 };
2053
2054 static int
2055 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2056 {
2057         struct rte_eth_rxmode *rxmode;
2058         struct nicvf *nic = nicvf_pmd_priv(dev);
2059         rxmode = &dev->data->dev_conf.rxmode;
2060         if (mask & ETH_VLAN_STRIP_MASK) {
2061                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2062                         nicvf_vlan_hw_strip(nic, true);
2063                 else
2064                         nicvf_vlan_hw_strip(nic, false);
2065         }
2066
2067         return 0;
2068 }
2069
2070 static int
2071 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2072 {
2073         nicvf_vlan_offload_config(dev, mask);
2074
2075         return 0;
2076 }
2077
2078 static inline int
2079 nicvf_set_first_skip(struct rte_eth_dev *dev)
2080 {
2081         int bytes_to_skip = 0;
2082         int ret = 0;
2083         unsigned int i;
2084         struct rte_kvargs *kvlist;
2085         static const char *const skip[] = {
2086                 SKIP_DATA_BYTES,
2087                 NULL};
2088         struct nicvf *nic = nicvf_pmd_priv(dev);
2089
2090         if (!dev->device->devargs) {
2091                 nicvf_first_skip_config(nic, 0);
2092                 return ret;
2093         }
2094
2095         kvlist = rte_kvargs_parse(dev->device->devargs->args, skip);
2096         if (!kvlist)
2097                 return -EINVAL;
2098
2099         if (kvlist->count == 0)
2100                 goto exit;
2101
2102         for (i = 0; i != kvlist->count; ++i) {
2103                 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
2104
2105                 if (!strcmp(pair->key, SKIP_DATA_BYTES))
2106                         bytes_to_skip = atoi(pair->value);
2107         }
2108
2109         /*128 bytes amounts to one cache line*/
2110         if (bytes_to_skip >= 0 && bytes_to_skip < 128) {
2111                 if (!(bytes_to_skip % 8)) {
2112                         nicvf_first_skip_config(nic, (bytes_to_skip / 8));
2113                         nic->skip_bytes = bytes_to_skip;
2114                         goto kvlist_free;
2115                 } else {
2116                         PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8");
2117                         ret = -EINVAL;
2118                         goto exit;
2119                 }
2120         } else {
2121                 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128");
2122                 ret = -EINVAL;
2123                 goto exit;
2124         }
2125 exit:
2126         nicvf_first_skip_config(nic, 0);
2127 kvlist_free:
2128         rte_kvargs_free(kvlist);
2129         return ret;
2130 }
2131 static int
2132 nicvf_eth_dev_uninit(struct rte_eth_dev *dev)
2133 {
2134         PMD_INIT_FUNC_TRACE();
2135
2136         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2137                 nicvf_dev_close(dev);
2138
2139         return 0;
2140 }
2141 static int
2142 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2143 {
2144         int ret;
2145         struct rte_pci_device *pci_dev;
2146         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2147
2148         PMD_INIT_FUNC_TRACE();
2149
2150         eth_dev->dev_ops = &nicvf_eth_dev_ops;
2151
2152         /* For secondary processes, the primary has done all the work */
2153         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2154                 if (nic) {
2155                         /* Setup callbacks for secondary process */
2156                         nicvf_set_tx_function(eth_dev);
2157                         nicvf_set_rx_function(eth_dev);
2158                         return 0;
2159                 } else {
2160                         /* If nic == NULL than it is secondary function
2161                          * so ethdev need to be released by caller */
2162                         return ENOTSUP;
2163                 }
2164         }
2165
2166         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2167         rte_eth_copy_pci_info(eth_dev, pci_dev);
2168
2169         nic->device_id = pci_dev->id.device_id;
2170         nic->vendor_id = pci_dev->id.vendor_id;
2171         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2172         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2173
2174         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2175                         pci_dev->id.vendor_id, pci_dev->id.device_id,
2176                         pci_dev->addr.domain, pci_dev->addr.bus,
2177                         pci_dev->addr.devid, pci_dev->addr.function);
2178
2179         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2180         if (!nic->reg_base) {
2181                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2182                 ret = -ENODEV;
2183                 goto fail;
2184         }
2185
2186         nicvf_disable_all_interrupts(nic);
2187
2188         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2189         if (ret) {
2190                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2191                 goto fail;
2192         }
2193
2194         ret = nicvf_mbox_check_pf_ready(nic);
2195         if (ret) {
2196                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2197                 goto alarm_fail;
2198         } else {
2199                 PMD_INIT_LOG(INFO,
2200                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2201                         nic->node, nic->vf_id,
2202                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2203                         nic->sqs_mode ? "true" : "false",
2204                         nic->loopback_supported ? "true" : "false"
2205                         );
2206         }
2207
2208         ret = nicvf_base_init(nic);
2209         if (ret) {
2210                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2211                 goto malloc_fail;
2212         }
2213
2214         if (nic->sqs_mode) {
2215                 /* Push nic to stack of secondary vfs */
2216                 nicvf_svf_push(nic);
2217
2218                 /* Steal nic pointer from the device for further reuse */
2219                 eth_dev->data->dev_private = NULL;
2220
2221                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2222                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2223                 if (ret) {
2224                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2225                         goto fail;
2226                 }
2227
2228                 /* Detach port by returning positive error number */
2229                 return ENOTSUP;
2230         }
2231
2232         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2233                                         RTE_ETHER_ADDR_LEN, 0);
2234         if (eth_dev->data->mac_addrs == NULL) {
2235                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2236                 ret = -ENOMEM;
2237                 goto alarm_fail;
2238         }
2239         if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr))
2240                 rte_eth_random_addr(&nic->mac_addr[0]);
2241
2242         rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr,
2243                         &eth_dev->data->mac_addrs[0]);
2244
2245         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2246         if (ret) {
2247                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2248                 goto malloc_fail;
2249         }
2250
2251         ret = nicvf_set_first_skip(eth_dev);
2252         if (ret) {
2253                 PMD_INIT_LOG(ERR, "Failed to configure first skip");
2254                 goto malloc_fail;
2255         }
2256         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2257                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2258                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2259                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2260
2261         return 0;
2262
2263 malloc_fail:
2264         rte_free(eth_dev->data->mac_addrs);
2265         eth_dev->data->mac_addrs = NULL;
2266 alarm_fail:
2267         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2268 fail:
2269         return ret;
2270 }
2271
2272 static const struct rte_pci_id pci_id_nicvf_map[] = {
2273         {
2274                 .class_id = RTE_CLASS_ANY_ID,
2275                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2276                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2277                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2278                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2279         },
2280         {
2281                 .class_id = RTE_CLASS_ANY_ID,
2282                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2283                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2284                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2285                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2286         },
2287         {
2288                 .class_id = RTE_CLASS_ANY_ID,
2289                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2290                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2291                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2292                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2293         },
2294         {
2295                 .class_id = RTE_CLASS_ANY_ID,
2296                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2297                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2298                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2299                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2300         },
2301         {
2302                 .vendor_id = 0,
2303         },
2304 };
2305
2306 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2307         struct rte_pci_device *pci_dev)
2308 {
2309         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2310                 nicvf_eth_dev_init);
2311 }
2312
2313 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2314 {
2315         return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit);
2316 }
2317
2318 static struct rte_pci_driver rte_nicvf_pmd = {
2319         .id_table = pci_id_nicvf_map,
2320         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2321                         RTE_PCI_DRV_INTR_LSC,
2322         .probe = nicvf_eth_pci_probe,
2323         .remove = nicvf_eth_pci_remove,
2324 };
2325
2326 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2327 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2328 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");
2329 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>");