drivers/net/thunderx/nicvf_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016 Cavium, Inc
   3  */
   4
   5 #include <assert.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15 #include <sys/queue.h>
  16
  17 #include <rte_alarm.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_cycles.h>
  22 #include <rte_debug.h>
  23 #include <rte_dev.h>
  24 #include <rte_eal.h>
  25 #include <rte_ether.h>
  26 #include <rte_ethdev_driver.h>
  27 #include <rte_ethdev_pci.h>
  28 #include <rte_interrupts.h>
  29 #include <rte_log.h>
  30 #include <rte_memory.h>
  31 #include <rte_memzone.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_pci.h>
  35 #include <rte_bus_pci.h>
  36 #include <rte_tailq.h>
  37 #include <rte_devargs.h>
  38 #include <rte_kvargs.h>
  39
  40 #include "base/nicvf_plat.h"
  41
  42 #include "nicvf_ethdev.h"
  43 #include "nicvf_rxtx.h"
  44 #include "nicvf_svf.h"
  45 #include "nicvf_logs.h"
  46
  47 int nicvf_logtype_mbox;
  48 int nicvf_logtype_init;
  49 int nicvf_logtype_driver;
  50
  51 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  54                           bool cleanup);
  55 static int nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask);
  56 static int nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  57
  58 RTE_INIT(nicvf_init_log)
  59 {
  60         nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox");
  61         if (nicvf_logtype_mbox >= 0)
  62                 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
  63
  64         nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init");
  65         if (nicvf_logtype_init >= 0)
  66                 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
  67
  68         nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver");
  69         if (nicvf_logtype_driver >= 0)
  70                 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
  71 }
  72
  73 static void
  74 nicvf_link_status_update(struct nicvf *nic,
  75                          struct rte_eth_link *link)
  76 {
  77         memset(link, 0, sizeof(*link));
  78
  79         link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
  80
  81         if (nic->duplex == NICVF_HALF_DUPLEX)
  82                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  83         else if (nic->duplex == NICVF_FULL_DUPLEX)
  84                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  85         link->link_speed = nic->speed;
  86         link->link_autoneg = ETH_LINK_AUTONEG;
  87 }
  88
  89 static void
  90 nicvf_interrupt(void *arg)
  91 {
  92         struct rte_eth_dev *dev = arg;
  93         struct nicvf *nic = nicvf_pmd_priv(dev);
  94         struct rte_eth_link link;
  95
  96         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
  97                 if (dev->data->dev_conf.intr_conf.lsc) {
  98                         nicvf_link_status_update(nic, &link);
  99                         rte_eth_linkstatus_set(dev, &link);
 100
 101                         _rte_eth_dev_callback_process(dev,
 102                                                       RTE_ETH_EVENT_INTR_LSC,
 103                                                       NULL);
 104                 }
 105         }
 106
 107         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 108                                 nicvf_interrupt, dev);
 109 }
 110
 111 static void
 112 nicvf_vf_interrupt(void *arg)
 113 {
 114         struct nicvf *nic = arg;
 115
 116         nicvf_reg_poll_interrupts(nic);
 117
 118         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 119                                 nicvf_vf_interrupt, nic);
 120 }
 121
 122 static int
 123 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 124 {
 125         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 126 }
 127
 128 static int
 129 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 130 {
 131         return rte_eal_alarm_cancel(fn, arg);
 132 }
 133
 134 /*
 135  * Return 0 means link status changed, -1 means not changed
 136  */
 137 static int
 138 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 139 {
 140 #define CHECK_INTERVAL 100  /* 100ms */
 141 #define MAX_CHECK_TIME 90   /* 9s (90 * 100ms) in total */
 142         struct rte_eth_link link;
 143         struct nicvf *nic = nicvf_pmd_priv(dev);
 144         int i;
 145
 146         PMD_INIT_FUNC_TRACE();
 147
 148         if (wait_to_complete) {
 149                 /* rte_eth_link_get() might need to wait up to 9 seconds */
 150                 for (i = 0; i < MAX_CHECK_TIME; i++) {
 151                         nicvf_link_status_update(nic, &link);
 152                         if (link.link_status == ETH_LINK_UP)
 153                                 break;
 154                         rte_delay_ms(CHECK_INTERVAL);
 155                 }
 156         } else {
 157                 nicvf_link_status_update(nic, &link);
 158         }
 159
 160         return rte_eth_linkstatus_set(dev, &link);
 161 }
 162
 163 static int
 164 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 165 {
 166         struct nicvf *nic = nicvf_pmd_priv(dev);
 167         uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
 168         size_t i;
 169         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 170
 171         PMD_INIT_FUNC_TRACE();
 172
 173         if (frame_size > NIC_HW_MAX_FRS)
 174                 return -EINVAL;
 175
 176         if (frame_size < NIC_HW_MIN_FRS)
 177                 return -EINVAL;
 178
 179         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 180
 181         /*
 182          * Refuse mtu that requires the support of scattered packets
 183          * when this feature has not been enabled before.
 184          */
 185         if (dev->data->dev_started && !dev->data->scattered_rx &&
 186                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 187                 return -EINVAL;
 188
 189         /* check <seg size> * <max_seg>  >= max_frame */
 190         if (dev->data->scattered_rx &&
 191                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 192                 return -EINVAL;
 193
 194         if (frame_size > RTE_ETHER_MAX_LEN)
 195                 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 196         else
 197                 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 198
 199         if (nicvf_mbox_update_hw_max_frs(nic, mtu))
 200                 return -EINVAL;
 201
 202         /* Update max_rx_pkt_len */
 203         rxmode->max_rx_pkt_len = mtu + RTE_ETHER_HDR_LEN;
 204         nic->mtu = mtu;
 205
 206         for (i = 0; i < nic->sqs_count; i++)
 207                 nic->snicvf[i]->mtu = mtu;
 208
 209         return 0;
 210 }
 211
 212 static int
 213 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 214 {
 215         uint64_t *data = regs->data;
 216         struct nicvf *nic = nicvf_pmd_priv(dev);
 217
 218         if (data == NULL) {
 219                 regs->length = nicvf_reg_get_count();
 220                 regs->width = THUNDERX_REG_BYTES;
 221                 return 0;
 222         }
 223
 224         /* Support only full register dump */
 225         if ((regs->length == 0) ||
 226                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 227                 regs->version = nic->vendor_id << 16 | nic->device_id;
 228                 nicvf_reg_dump(nic, data);
 229                 return 0;
 230         }
 231         return -ENOTSUP;
 232 }
 233
 234 static int
 235 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 236 {
 237         uint16_t qidx;
 238         struct nicvf_hw_rx_qstats rx_qstats;
 239         struct nicvf_hw_tx_qstats tx_qstats;
 240         struct nicvf_hw_stats port_stats;
 241         struct nicvf *nic = nicvf_pmd_priv(dev);
 242         uint16_t rx_start, rx_end;
 243         uint16_t tx_start, tx_end;
 244         size_t i;
 245
 246         /* RX queue indices for the first VF */
 247         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 248
 249         /* Reading per RX ring stats */
 250         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 251                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 252                         break;
 253
 254                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 255                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 256                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 257         }
 258
 259         /* TX queue indices for the first VF */
 260         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 261
 262         /* Reading per TX ring stats */
 263         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 264                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 265                         break;
 266
 267                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 268                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 269                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 270         }
 271
 272         for (i = 0; i < nic->sqs_count; i++) {
 273                 struct nicvf *snic = nic->snicvf[i];
 274
 275                 if (snic == NULL)
 276                         break;
 277
 278                 /* RX queue indices for a secondary VF */
 279                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 280
 281                 /* Reading per RX ring stats */
 282                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 283                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 284                                 break;
 285
 286                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 287                                                qidx % MAX_RCV_QUEUES_PER_QS);
 288                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 289                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 290                 }
 291
 292                 /* TX queue indices for a secondary VF */
 293                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 294                 /* Reading per TX ring stats */
 295                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 296                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 297                                 break;
 298
 299                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 300                                                qidx % MAX_SND_QUEUES_PER_QS);
 301                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 302                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 303                 }
 304         }
 305
 306         nicvf_hw_get_stats(nic, &port_stats);
 307         stats->ibytes = port_stats.rx_bytes;
 308         stats->ipackets = port_stats.rx_ucast_frames;
 309         stats->ipackets += port_stats.rx_bcast_frames;
 310         stats->ipackets += port_stats.rx_mcast_frames;
 311         stats->ierrors = port_stats.rx_l2_errors;
 312         stats->imissed = port_stats.rx_drop_red;
 313         stats->imissed += port_stats.rx_drop_overrun;
 314         stats->imissed += port_stats.rx_drop_bcast;
 315         stats->imissed += port_stats.rx_drop_mcast;
 316         stats->imissed += port_stats.rx_drop_l3_bcast;
 317         stats->imissed += port_stats.rx_drop_l3_mcast;
 318
 319         stats->obytes = port_stats.tx_bytes_ok;
 320         stats->opackets = port_stats.tx_ucast_frames_ok;
 321         stats->opackets += port_stats.tx_bcast_frames_ok;
 322         stats->opackets += port_stats.tx_mcast_frames_ok;
 323         stats->oerrors = port_stats.tx_drops;
 324
 325         return 0;
 326 }
 327
 328 static const uint32_t *
 329 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 330 {
 331         size_t copied;
 332         static uint32_t ptypes[32];
 333         struct nicvf *nic = nicvf_pmd_priv(dev);
 334         static const uint32_t ptypes_common[] = {
 335                 RTE_PTYPE_L3_IPV4,
 336                 RTE_PTYPE_L3_IPV4_EXT,
 337                 RTE_PTYPE_L3_IPV6,
 338                 RTE_PTYPE_L3_IPV6_EXT,
 339                 RTE_PTYPE_L4_TCP,
 340                 RTE_PTYPE_L4_UDP,
 341                 RTE_PTYPE_L4_FRAG,
 342         };
 343         static const uint32_t ptypes_tunnel[] = {
 344                 RTE_PTYPE_TUNNEL_GRE,
 345                 RTE_PTYPE_TUNNEL_GENEVE,
 346                 RTE_PTYPE_TUNNEL_VXLAN,
 347                 RTE_PTYPE_TUNNEL_NVGRE,
 348         };
 349         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 350
 351         copied = sizeof(ptypes_common);
 352         memcpy(ptypes, ptypes_common, copied);
 353         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 354                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 355                         sizeof(ptypes_tunnel));
 356                 copied += sizeof(ptypes_tunnel);
 357         }
 358
 359         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 360
 361         /* All Ptypes are supported in all Rx functions. */
 362         return ptypes;
 363 }
 364
 365 static void
 366 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 367 {
 368         int i;
 369         uint16_t rxqs = 0, txqs = 0;
 370         struct nicvf *nic = nicvf_pmd_priv(dev);
 371         uint16_t rx_start, rx_end;
 372         uint16_t tx_start, tx_end;
 373
 374         /* Reset all primary nic counters */
 375         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 376         for (i = rx_start; i <= rx_end; i++)
 377                 rxqs |= (0x3 << (i * 2));
 378
 379         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 380         for (i = tx_start; i <= tx_end; i++)
 381                 txqs |= (0x3 << (i * 2));
 382
 383         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 384
 385         /* Reset secondary nic queue counters */
 386         for (i = 0; i < nic->sqs_count; i++) {
 387                 struct nicvf *snic = nic->snicvf[i];
 388                 if (snic == NULL)
 389                         break;
 390
 391                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 392                 for (i = rx_start; i <= rx_end; i++)
 393                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 394
 395                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 396                 for (i = tx_start; i <= tx_end; i++)
 397                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 398
 399                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 400         }
 401 }
 402
 403 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 404 static int
 405 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 406 {
 407         return 0;
 408 }
 409
 410 static inline uint64_t
 411 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 412 {
 413         uint64_t nic_rss = 0;
 414
 415         if (ethdev_rss & ETH_RSS_IPV4)
 416                 nic_rss |= RSS_IP_ENA;
 417
 418         if (ethdev_rss & ETH_RSS_IPV6)
 419                 nic_rss |= RSS_IP_ENA;
 420
 421         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 422                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 423
 424         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 425                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 426
 427         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 428                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 429
 430         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 431                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 432
 433         if (ethdev_rss & ETH_RSS_PORT)
 434                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 435
 436         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 437                 if (ethdev_rss & ETH_RSS_VXLAN)
 438                         nic_rss |= RSS_TUN_VXLAN_ENA;
 439
 440                 if (ethdev_rss & ETH_RSS_GENEVE)
 441                         nic_rss |= RSS_TUN_GENEVE_ENA;
 442
 443                 if (ethdev_rss & ETH_RSS_NVGRE)
 444                         nic_rss |= RSS_TUN_NVGRE_ENA;
 445         }
 446
 447         return nic_rss;
 448 }
 449
 450 static inline uint64_t
 451 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 452 {
 453         uint64_t ethdev_rss = 0;
 454
 455         if (nic_rss & RSS_IP_ENA)
 456                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 457
 458         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 459                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 460                                 ETH_RSS_NONFRAG_IPV6_TCP);
 461
 462         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 463                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 464                                 ETH_RSS_NONFRAG_IPV6_UDP);
 465
 466         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 467                 ethdev_rss |= ETH_RSS_PORT;
 468
 469         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 470                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 471                         ethdev_rss |= ETH_RSS_VXLAN;
 472
 473                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 474                         ethdev_rss |= ETH_RSS_GENEVE;
 475
 476                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 477                         ethdev_rss |= ETH_RSS_NVGRE;
 478         }
 479         return ethdev_rss;
 480 }
 481
 482 static int
 483 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 484                      struct rte_eth_rss_reta_entry64 *reta_conf,
 485                      uint16_t reta_size)
 486 {
 487         struct nicvf *nic = nicvf_pmd_priv(dev);
 488         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 489         int ret, i, j;
 490
 491         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 492                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 493                         "(%d) doesn't match the number hardware can supported "
 494                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 495                 return -EINVAL;
 496         }
 497
 498         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 499         if (ret)
 500                 return ret;
 501
 502         /* Copy RETA table */
 503         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 504                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 505                         if ((reta_conf[i].mask >> j) & 0x01)
 506                                 reta_conf[i].reta[j] = tbl[j];
 507         }
 508
 509         return 0;
 510 }
 511
 512 static int
 513 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 514                       struct rte_eth_rss_reta_entry64 *reta_conf,
 515                       uint16_t reta_size)
 516 {
 517         struct nicvf *nic = nicvf_pmd_priv(dev);
 518         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 519         int ret, i, j;
 520
 521         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 522                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 523                         "(%d) doesn't match the number hardware can supported "
 524                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 525                 return -EINVAL;
 526         }
 527
 528         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 529         if (ret)
 530                 return ret;
 531
 532         /* Copy RETA table */
 533         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 534                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 535                         if ((reta_conf[i].mask >> j) & 0x01)
 536                                 tbl[j] = reta_conf[i].reta[j];
 537         }
 538
 539         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 540 }
 541
 542 static int
 543 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 544                             struct rte_eth_rss_conf *rss_conf)
 545 {
 546         struct nicvf *nic = nicvf_pmd_priv(dev);
 547
 548         if (rss_conf->rss_key)
 549                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 550
 551         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 552         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 553         return 0;
 554 }
 555
 556 static int
 557 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 558                           struct rte_eth_rss_conf *rss_conf)
 559 {
 560         struct nicvf *nic = nicvf_pmd_priv(dev);
 561         uint64_t nic_rss;
 562
 563         if (rss_conf->rss_key &&
 564                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 565                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 566                                 rss_conf->rss_key_len);
 567                 return -EINVAL;
 568         }
 569
 570         if (rss_conf->rss_key)
 571                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 572
 573         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 574         nicvf_rss_set_cfg(nic, nic_rss);
 575         return 0;
 576 }
 577
 578 static int
 579 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 580                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 581 {
 582         const struct rte_memzone *rz;
 583         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 584
 585         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 586                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 587                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 588         if (rz == NULL) {
 589                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 590                 return -ENOMEM;
 591         }
 592
 593         memset(rz->addr, 0, ring_size);
 594
 595         rxq->phys = rz->iova;
 596         rxq->desc = rz->addr;
 597         rxq->qlen_mask = desc_cnt - 1;
 598
 599         return 0;
 600 }
 601
 602 static int
 603 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 604                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 605 {
 606         const struct rte_memzone *rz;
 607         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 608
 609         rz = rte_eth_dma_zone_reserve(dev, "sq",
 610                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 611                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 612         if (rz == NULL) {
 613                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 614                 return -ENOMEM;
 615         }
 616
 617         memset(rz->addr, 0, ring_size);
 618
 619         sq->phys = rz->iova;
 620         sq->desc = rz->addr;
 621         sq->qlen_mask = desc_cnt - 1;
 622
 623         return 0;
 624 }
 625
 626 static int
 627 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 628                       uint32_t desc_cnt, uint32_t buffsz)
 629 {
 630         struct nicvf_rbdr *rbdr;
 631         const struct rte_memzone *rz;
 632         uint32_t ring_size;
 633
 634         assert(nic->rbdr == NULL);
 635         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 636                                   RTE_CACHE_LINE_SIZE, nic->node);
 637         if (rbdr == NULL) {
 638                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 639                 return -ENOMEM;
 640         }
 641
 642         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 643         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 644                                       nicvf_netdev_qidx(nic, 0), ring_size,
 645                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 646         if (rz == NULL) {
 647                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 648                 return -ENOMEM;
 649         }
 650
 651         memset(rz->addr, 0, ring_size);
 652
 653         rbdr->phys = rz->iova;
 654         rbdr->tail = 0;
 655         rbdr->next_tail = 0;
 656         rbdr->desc = rz->addr;
 657         rbdr->buffsz = buffsz;
 658         rbdr->qlen_mask = desc_cnt - 1;
 659         rbdr->rbdr_status =
 660                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 661         rbdr->rbdr_door =
 662                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 663
 664         nic->rbdr = rbdr;
 665         return 0;
 666 }
 667
 668 static void
 669 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 670                         nicvf_iova_addr_t phy)
 671 {
 672         uint16_t qidx;
 673         void *obj;
 674         struct nicvf_rxq *rxq;
 675         uint16_t rx_start, rx_end;
 676
 677         /* Get queue ranges for this VF */
 678         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 679
 680         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 681                 rxq = dev->data->rx_queues[qidx];
 682                 if (rxq->precharge_cnt) {
 683                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 684                                                            rxq->mbuf_phys_off);
 685                         rte_mempool_put(rxq->pool, obj);
 686                         rxq->precharge_cnt--;
 687                         break;
 688                 }
 689         }
 690 }
 691
 692 static inline void
 693 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 694 {
 695         uint32_t qlen_mask, head;
 696         struct rbdr_entry_t *entry;
 697         struct nicvf_rbdr *rbdr = nic->rbdr;
 698
 699         qlen_mask = rbdr->qlen_mask;
 700         head = rbdr->head;
 701         while (head != rbdr->tail) {
 702                 entry = rbdr->desc + head;
 703                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 704                 head++;
 705                 head = head & qlen_mask;
 706         }
 707 }
 708
 709 static inline void
 710 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 711 {
 712         uint32_t head;
 713
 714         head = txq->head;
 715         while (head != txq->tail) {
 716                 if (txq->txbuffs[head]) {
 717                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 718                         txq->txbuffs[head] = NULL;
 719                 }
 720                 head++;
 721                 head = head & txq->qlen_mask;
 722         }
 723 }
 724
 725 static void
 726 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 727 {
 728         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 729
 730         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 731         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 732         txq->tail = 0;
 733         txq->head = 0;
 734         txq->xmit_bufs = 0;
 735 }
 736
 737 static inline int
 738 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 739                         uint16_t qidx)
 740 {
 741         struct nicvf_txq *txq;
 742         int ret;
 743
 744         assert(qidx < MAX_SND_QUEUES_PER_QS);
 745
 746         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 747                 RTE_ETH_QUEUE_STATE_STARTED)
 748                 return 0;
 749
 750         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 751         txq->pool = NULL;
 752         ret = nicvf_qset_sq_config(nic, qidx, txq);
 753         if (ret) {
 754                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 755                              nic->vf_id, qidx, ret);
 756                 goto config_sq_error;
 757         }
 758
 759         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 760                 RTE_ETH_QUEUE_STATE_STARTED;
 761         return ret;
 762
 763 config_sq_error:
 764         nicvf_qset_sq_reclaim(nic, qidx);
 765         return ret;
 766 }
 767
 768 static inline int
 769 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 770                        uint16_t qidx)
 771 {
 772         struct nicvf_txq *txq;
 773         int ret;
 774
 775         assert(qidx < MAX_SND_QUEUES_PER_QS);
 776
 777         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 778                 RTE_ETH_QUEUE_STATE_STOPPED)
 779                 return 0;
 780
 781         ret = nicvf_qset_sq_reclaim(nic, qidx);
 782         if (ret)
 783                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 784                              nic->vf_id, qidx, ret);
 785
 786         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 787         nicvf_tx_queue_release_mbufs(txq);
 788         nicvf_tx_queue_reset(txq);
 789
 790         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 791                 RTE_ETH_QUEUE_STATE_STOPPED;
 792         return ret;
 793 }
 794
 795 static inline int
 796 nicvf_configure_cpi(struct rte_eth_dev *dev)
 797 {
 798         struct nicvf *nic = nicvf_pmd_priv(dev);
 799         uint16_t qidx, qcnt;
 800         int ret;
 801
 802         /* Count started rx queues */
 803         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 804                 if (dev->data->rx_queue_state[qidx] ==
 805                     RTE_ETH_QUEUE_STATE_STARTED)
 806                         qcnt++;
 807
 808         nic->cpi_alg = CPI_ALG_NONE;
 809         ret = nicvf_mbox_config_cpi(nic, qcnt);
 810         if (ret)
 811                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 812
 813         return ret;
 814 }
 815
 816 static inline int
 817 nicvf_configure_rss(struct rte_eth_dev *dev)
 818 {
 819         struct nicvf *nic = nicvf_pmd_priv(dev);
 820         uint64_t rsshf;
 821         int ret = -EINVAL;
 822
 823         rsshf = nicvf_rss_ethdev_to_nic(nic,
 824                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 825         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 826                     dev->data->dev_conf.rxmode.mq_mode,
 827                     dev->data->nb_rx_queues,
 828                     dev->data->dev_conf.lpbk_mode, rsshf);
 829
 830         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 831                 ret = nicvf_rss_term(nic);
 832         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 833                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 834         if (ret)
 835                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 836
 837         return ret;
 838 }
 839
 840 static int
 841 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 842 {
 843         struct nicvf *nic = nicvf_pmd_priv(dev);
 844         unsigned int idx, qmap_size;
 845         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 846         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 847
 848         if (nic->cpi_alg != CPI_ALG_NONE)
 849                 return -EINVAL;
 850
 851         /* Prepare queue map */
 852         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 853                 if (dev->data->rx_queue_state[idx] ==
 854                                 RTE_ETH_QUEUE_STATE_STARTED)
 855                         qmap[qmap_size++] = idx;
 856         }
 857
 858         /* Update default RSS RETA */
 859         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 860                 default_reta[idx] = qmap[idx % qmap_size];
 861
 862         return nicvf_rss_reta_update(nic, default_reta,
 863                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 864 }
 865
 866 static void
 867 nicvf_dev_tx_queue_release(void *sq)
 868 {
 869         struct nicvf_txq *txq;
 870
 871         PMD_INIT_FUNC_TRACE();
 872
 873         txq = (struct nicvf_txq *)sq;
 874         if (txq) {
 875                 if (txq->txbuffs != NULL) {
 876                         nicvf_tx_queue_release_mbufs(txq);
 877                         rte_free(txq->txbuffs);
 878                         txq->txbuffs = NULL;
 879                 }
 880                 rte_free(txq);
 881         }
 882 }
 883
 884 static void
 885 nicvf_set_tx_function(struct rte_eth_dev *dev)
 886 {
 887         struct nicvf_txq *txq = NULL;
 888         size_t i;
 889         bool multiseg = false;
 890
 891         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 892                 txq = dev->data->tx_queues[i];
 893                 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
 894                         multiseg = true;
 895                         break;
 896                 }
 897         }
 898
 899         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 900         if (multiseg) {
 901                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 902                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 903         } else {
 904                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 905                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 906         }
 907
 908         if (!txq)
 909                 return;
 910
 911         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 912                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 913         else
 914                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 915 }
 916
 917 static void
 918 nicvf_set_rx_function(struct rte_eth_dev *dev)
 919 {
 920         struct nicvf *nic = nicvf_pmd_priv(dev);
 921
 922         const eth_rx_burst_t rx_burst_func[2][2][2] = {
 923         /* [NORMAL/SCATTER] [CKSUM/NO_CKSUM] [VLAN_STRIP/NO_VLAN_STRIP] */
 924                 [0][0][0] = nicvf_recv_pkts_no_offload,
 925                 [0][0][1] = nicvf_recv_pkts_vlan_strip,
 926                 [0][1][0] = nicvf_recv_pkts_cksum,
 927                 [0][1][1] = nicvf_recv_pkts_cksum_vlan_strip,
 928                 [1][0][0] = nicvf_recv_pkts_multiseg_no_offload,
 929                 [1][0][1] = nicvf_recv_pkts_multiseg_vlan_strip,
 930                 [1][1][0] = nicvf_recv_pkts_multiseg_cksum,
 931                 [1][1][1] = nicvf_recv_pkts_multiseg_cksum_vlan_strip,
 932         };
 933
 934         dev->rx_pkt_burst =
 935                 rx_burst_func[dev->data->scattered_rx]
 936                         [nic->offload_cksum][nic->vlan_strip];
 937 }
 938
 939 static int
 940 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 941                          uint16_t nb_desc, unsigned int socket_id,
 942                          const struct rte_eth_txconf *tx_conf)
 943 {
 944         uint16_t tx_free_thresh;
 945         bool is_single_pool;
 946         struct nicvf_txq *txq;
 947         struct nicvf *nic = nicvf_pmd_priv(dev);
 948         uint64_t offloads;
 949
 950         PMD_INIT_FUNC_TRACE();
 951
 952         if (qidx >= MAX_SND_QUEUES_PER_QS)
 953                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 954
 955         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 956
 957         /* Socket id check */
 958         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 959                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 960                 socket_id, nic->node);
 961
 962         /* Tx deferred start is not supported */
 963         if (tx_conf->tx_deferred_start) {
 964                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 965                 return -EINVAL;
 966         }
 967
 968         /* Roundup nb_desc to available qsize and validate max number of desc */
 969         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 970         if (nb_desc == 0) {
 971                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 972                 return -EINVAL;
 973         }
 974
 975         /* Validate tx_free_thresh */
 976         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 977                                 tx_conf->tx_free_thresh :
 978                                 NICVF_DEFAULT_TX_FREE_THRESH);
 979
 980         if (tx_free_thresh > (nb_desc) ||
 981                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 982                 PMD_INIT_LOG(ERR,
 983                         "tx_free_thresh must be less than the number of TX "
 984                         "descriptors. (tx_free_thresh=%u port=%d "
 985                         "queue=%d)", (unsigned int)tx_free_thresh,
 986                         (int)dev->data->port_id, (int)qidx);
 987                 return -EINVAL;
 988         }
 989
 990         /* Free memory prior to re-allocation if needed. */
 991         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 992                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 993                                 nicvf_netdev_qidx(nic, qidx));
 994                 nicvf_dev_tx_queue_release(
 995                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 996                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 997         }
 998
 999         /* Allocating tx queue data structure */
1000         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
1001                                         RTE_CACHE_LINE_SIZE, nic->node);
1002         if (txq == NULL) {
1003                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
1004                              nicvf_netdev_qidx(nic, qidx));
1005                 return -ENOMEM;
1006         }
1007
1008         txq->nic = nic;
1009         txq->queue_id = qidx;
1010         txq->tx_free_thresh = tx_free_thresh;
1011         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1012         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1013         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1014         txq->offloads = offloads;
1015
1016         is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);
1017
1018         /* Choose optimum free threshold value for multipool case */
1019         if (!is_single_pool) {
1020                 txq->tx_free_thresh = (uint16_t)
1021                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1022                                 NICVF_TX_FREE_MPOOL_THRESH :
1023                                 tx_conf->tx_free_thresh);
1024                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1025         } else {
1026                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1027         }
1028
1029         /* Allocate software ring */
1030         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1031                                 nb_desc * sizeof(struct rte_mbuf *),
1032                                 RTE_CACHE_LINE_SIZE, nic->node);
1033
1034         if (txq->txbuffs == NULL) {
1035                 nicvf_dev_tx_queue_release(txq);
1036                 return -ENOMEM;
1037         }
1038
1039         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1040                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1041                 nicvf_dev_tx_queue_release(txq);
1042                 return -ENOMEM;
1043         }
1044
1045         nicvf_tx_queue_reset(txq);
1046
1047         PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p"
1048                         " phys=0x%" PRIx64 " offloads=0x%" PRIx64,
1049                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1050                         txq->phys, txq->offloads);
1051
1052         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1053         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1054                 RTE_ETH_QUEUE_STATE_STOPPED;
1055         return 0;
1056 }
1057
1058 static inline void
1059 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1060 {
1061         uint32_t rxq_cnt;
1062         uint32_t nb_pkts, released_pkts = 0;
1063         uint32_t refill_cnt = 0;
1064         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1065
1066         if (dev->rx_pkt_burst == NULL)
1067                 return;
1068
1069         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1070                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1071                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1072                                         NICVF_MAX_RX_FREE_THRESH);
1073                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1074                 while (nb_pkts) {
1075                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1076                         released_pkts++;
1077                 }
1078         }
1079
1080
1081         refill_cnt += nicvf_dev_rbdr_refill(dev,
1082                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1083
1084         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1085                     released_pkts, refill_cnt);
1086 }
1087
1088 static void
1089 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1090 {
1091         rxq->head = 0;
1092         rxq->available_space = 0;
1093         rxq->recv_buffers = 0;
1094 }
1095
1096 static inline int
1097 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1098                         uint16_t qidx)
1099 {
1100         struct nicvf_rxq *rxq;
1101         int ret;
1102
1103         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1104
1105         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1106                 RTE_ETH_QUEUE_STATE_STARTED)
1107                 return 0;
1108
1109         /* Update rbdr pointer to all rxq */
1110         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1111         rxq->shared_rbdr = nic->rbdr;
1112
1113         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1114         if (ret) {
1115                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1116                              nic->vf_id, qidx, ret);
1117                 goto config_rq_error;
1118         }
1119         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1120         if (ret) {
1121                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1122                              nic->vf_id, qidx, ret);
1123                 goto config_cq_error;
1124         }
1125
1126         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1127                 RTE_ETH_QUEUE_STATE_STARTED;
1128         return 0;
1129
1130 config_cq_error:
1131         nicvf_qset_cq_reclaim(nic, qidx);
1132 config_rq_error:
1133         nicvf_qset_rq_reclaim(nic, qidx);
1134         return ret;
1135 }
1136
1137 static inline int
1138 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1139                        uint16_t qidx)
1140 {
1141         struct nicvf_rxq *rxq;
1142         int ret, other_error;
1143
1144         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1145                 RTE_ETH_QUEUE_STATE_STOPPED)
1146                 return 0;
1147
1148         ret = nicvf_qset_rq_reclaim(nic, qidx);
1149         if (ret)
1150                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1151                              nic->vf_id, qidx, ret);
1152
1153         other_error = ret;
1154         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1155         nicvf_rx_queue_release_mbufs(dev, rxq);
1156         nicvf_rx_queue_reset(rxq);
1157
1158         ret = nicvf_qset_cq_reclaim(nic, qidx);
1159         if (ret)
1160                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1161                              nic->vf_id, qidx, ret);
1162
1163         other_error |= ret;
1164         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1165                 RTE_ETH_QUEUE_STATE_STOPPED;
1166         return other_error;
1167 }
1168
1169 static void
1170 nicvf_dev_rx_queue_release(void *rx_queue)
1171 {
1172         PMD_INIT_FUNC_TRACE();
1173
1174         rte_free(rx_queue);
1175 }
1176
1177 static int
1178 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1179 {
1180         struct nicvf *nic = nicvf_pmd_priv(dev);
1181         int ret;
1182
1183         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1184                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1185
1186         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1187
1188         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1189         if (ret)
1190                 return ret;
1191
1192         ret = nicvf_configure_cpi(dev);
1193         if (ret)
1194                 return ret;
1195
1196         return nicvf_configure_rss_reta(dev);
1197 }
1198
1199 static int
1200 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1201 {
1202         int ret;
1203         struct nicvf *nic = nicvf_pmd_priv(dev);
1204
1205         if (qidx >= MAX_SND_QUEUES_PER_QS)
1206                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1207
1208         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1209
1210         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1211         ret |= nicvf_configure_cpi(dev);
1212         ret |= nicvf_configure_rss_reta(dev);
1213         return ret;
1214 }
1215
1216 static int
1217 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1218 {
1219         struct nicvf *nic = nicvf_pmd_priv(dev);
1220
1221         if (qidx >= MAX_SND_QUEUES_PER_QS)
1222                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1223
1224         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1225
1226         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1227 }
1228
1229 static int
1230 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1231 {
1232         struct nicvf *nic = nicvf_pmd_priv(dev);
1233
1234         if (qidx >= MAX_SND_QUEUES_PER_QS)
1235                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1236
1237         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1238
1239         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1240 }
1241
1242 static inline void
1243 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1244 {
1245         uintptr_t p;
1246         struct rte_mbuf mb_def;
1247         struct nicvf *nic = rxq->nic;
1248
1249         RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1250         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1251         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1252                                 offsetof(struct rte_mbuf, data_off) != 2);
1253         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1254                                 offsetof(struct rte_mbuf, data_off) != 4);
1255         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1256                                 offsetof(struct rte_mbuf, data_off) != 6);
1257         RTE_BUILD_BUG_ON(offsetof(struct nicvf_rxq, rxq_fastpath_data_end) -
1258                                 offsetof(struct nicvf_rxq,
1259                                         rxq_fastpath_data_start) > 128);
1260         mb_def.nb_segs = 1;
1261         mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes);
1262         mb_def.port = rxq->port_id;
1263         rte_mbuf_refcnt_set(&mb_def, 1);
1264
1265         /* Prevent compiler reordering: rearm_data covers previous fields */
1266         rte_compiler_barrier();
1267         p = (uintptr_t)&mb_def.rearm_data;
1268         rxq->mbuf_initializer.value = *(uint64_t *)p;
1269 }
1270
1271 static int
1272 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1273                          uint16_t nb_desc, unsigned int socket_id,
1274                          const struct rte_eth_rxconf *rx_conf,
1275                          struct rte_mempool *mp)
1276 {
1277         uint16_t rx_free_thresh;
1278         struct nicvf_rxq *rxq;
1279         struct nicvf *nic = nicvf_pmd_priv(dev);
1280         uint64_t offloads;
1281         uint32_t buffsz;
1282         struct rte_pktmbuf_pool_private *mbp_priv;
1283
1284         PMD_INIT_FUNC_TRACE();
1285
1286         /* First skip check */
1287         mbp_priv = rte_mempool_get_priv(mp);
1288         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1289         if (buffsz < (uint32_t)(nic->skip_bytes)) {
1290                 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size");
1291                 return -EINVAL;
1292         }
1293
1294         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1295                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1296
1297         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1298
1299         /* Socket id check */
1300         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1301                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1302                 socket_id, nic->node);
1303
1304         /* Mempool memory must be contiguous, so must be one memory segment*/
1305         if (mp->nb_mem_chunks != 1) {
1306                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1307                 return -EINVAL;
1308         }
1309
1310         /* Mempool memory must be physically contiguous */
1311         if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) {
1312                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1313                 return -EINVAL;
1314         }
1315
1316         /* Rx deferred start is not supported */
1317         if (rx_conf->rx_deferred_start) {
1318                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1319                 return -EINVAL;
1320         }
1321
1322         /* Roundup nb_desc to available qsize and validate max number of desc */
1323         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1324         if (nb_desc == 0) {
1325                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1326                 return -EINVAL;
1327         }
1328
1329
1330         /* Check rx_free_thresh upper bound */
1331         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1332                                 rx_conf->rx_free_thresh :
1333                                 NICVF_DEFAULT_RX_FREE_THRESH);
1334         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1335                 rx_free_thresh >= nb_desc * .75) {
1336                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1337                                 rx_free_thresh);
1338                 return -EINVAL;
1339         }
1340
1341         /* Free memory prior to re-allocation if needed */
1342         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1343                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1344                                 nicvf_netdev_qidx(nic, qidx));
1345                 nicvf_dev_rx_queue_release(
1346                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1347                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1348         }
1349
1350         /* Allocate rxq memory */
1351         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1352                                         RTE_CACHE_LINE_SIZE, nic->node);
1353         if (rxq == NULL) {
1354                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1355                              nicvf_netdev_qidx(nic, qidx));
1356                 return -ENOMEM;
1357         }
1358
1359         rxq->nic = nic;
1360         rxq->pool = mp;
1361         rxq->queue_id = qidx;
1362         rxq->port_id = dev->data->port_id;
1363         rxq->rx_free_thresh = rx_free_thresh;
1364         rxq->rx_drop_en = rx_conf->rx_drop_en;
1365         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1366         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1367         rxq->precharge_cnt = 0;
1368
1369         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1370                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1371         else
1372                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1373
1374         nicvf_rxq_mbuf_setup(rxq);
1375
1376         /* Alloc completion queue */
1377         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1378                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1379                 nicvf_dev_rx_queue_release(rxq);
1380                 return -ENOMEM;
1381         }
1382
1383         nicvf_rx_queue_reset(rxq);
1384
1385         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1386         PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)"
1387                         " phy=0x%" PRIx64 " offloads=0x%" PRIx64,
1388                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1389                         rte_mempool_avail_count(mp), rxq->phys, offloads);
1390
1391         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1392         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1393                 RTE_ETH_QUEUE_STATE_STOPPED;
1394         return 0;
1395 }
1396
1397 static int
1398 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1399 {
1400         struct nicvf *nic = nicvf_pmd_priv(dev);
1401         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1402
1403         PMD_INIT_FUNC_TRACE();
1404
1405         /* Autonegotiation may be disabled */
1406         dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1407         dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1408                                  ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1409         if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1410                 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1411
1412         dev_info->min_rx_bufsize = RTE_ETHER_MIN_MTU;
1413         dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + RTE_ETHER_HDR_LEN;
1414         dev_info->max_rx_queues =
1415                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1416         dev_info->max_tx_queues =
1417                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1418         dev_info->max_mac_addrs = 1;
1419         dev_info->max_vfs = pci_dev->max_vfs;
1420
1421         dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1422         dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1423         dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1424         dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1425
1426         dev_info->reta_size = nic->rss_info.rss_size;
1427         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1428         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1429         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1430                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1431
1432         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1433                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1434                 .rx_drop_en = 0,
1435         };
1436
1437         dev_info->default_txconf = (struct rte_eth_txconf) {
1438                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1439                 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE |
1440                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM   |
1441                         DEV_TX_OFFLOAD_UDP_CKSUM          |
1442                         DEV_TX_OFFLOAD_TCP_CKSUM,
1443         };
1444
1445         return 0;
1446 }
1447
1448 static nicvf_iova_addr_t
1449 rbdr_rte_mempool_get(void *dev, void *opaque)
1450 {
1451         uint16_t qidx;
1452         uintptr_t mbuf;
1453         struct nicvf_rxq *rxq;
1454         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1455         struct nicvf *nic = (struct nicvf *)opaque;
1456         uint16_t rx_start, rx_end;
1457
1458         /* Get queue ranges for this VF */
1459         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1460
1461         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1462                 rxq = eth_dev->data->rx_queues[qidx];
1463                 /* Maintain equal buffer count across all pools */
1464                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1465                         continue;
1466                 rxq->precharge_cnt++;
1467                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1468                 if (mbuf)
1469                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1470         }
1471         return 0;
1472 }
1473
1474 static int
1475 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1476 {
1477         int ret;
1478         uint16_t qidx, data_off;
1479         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1480         uint64_t mbuf_phys_off = 0;
1481         struct nicvf_rxq *rxq;
1482         struct rte_mbuf *mbuf;
1483         uint16_t rx_start, rx_end;
1484         uint16_t tx_start, tx_end;
1485         int mask;
1486
1487         PMD_INIT_FUNC_TRACE();
1488
1489         /* Userspace process exited without proper shutdown in last run */
1490         if (nicvf_qset_rbdr_active(nic, 0))
1491                 nicvf_vf_stop(dev, nic, false);
1492
1493         /* Get queue ranges for this VF */
1494         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1495
1496         /*
1497          * Thunderx nicvf PMD can support more than one pool per port only when
1498          * 1) Data payload size is same across all the pools in given port
1499          * AND
1500          * 2) All mbuffs in the pools are from the same hugepage
1501          * AND
1502          * 3) Mbuff metadata size is same across all the pools in given port
1503          *
1504          * This is to support existing application that uses multiple pool/port.
1505          * But, the purpose of using multipool for QoS will not be addressed.
1506          *
1507          */
1508
1509         /* Validate mempool attributes */
1510         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1511                 rxq = dev->data->rx_queues[qidx];
1512                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1513                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1514                 if (mbuf == NULL) {
1515                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1516                                      "pool=%s",
1517                                      nic->vf_id, qidx, rxq->pool->name);
1518                         return -ENOMEM;
1519                 }
1520                 data_off = nicvf_mbuff_meta_length(mbuf);
1521                 data_off += RTE_PKTMBUF_HEADROOM;
1522                 rte_pktmbuf_free(mbuf);
1523
1524                 if (data_off % RTE_CACHE_LINE_SIZE) {
1525                         PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1526                                 rxq->pool->name, data_off,
1527                                 data_off % RTE_CACHE_LINE_SIZE);
1528                         return -EINVAL;
1529                 }
1530                 rxq->mbuf_phys_off -= data_off;
1531                 rxq->mbuf_phys_off -= nic->skip_bytes;
1532
1533                 if (mbuf_phys_off == 0)
1534                         mbuf_phys_off = rxq->mbuf_phys_off;
1535                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1536                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1537                                      PRIx64, rxq->pool->name, nic->vf_id,
1538                                      mbuf_phys_off);
1539                         return -EINVAL;
1540                 }
1541         }
1542
1543         /* Check the level of buffers in the pool */
1544         total_rxq_desc = 0;
1545         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1546                 rxq = dev->data->rx_queues[qidx];
1547                 /* Count total numbers of rxq descs */
1548                 total_rxq_desc += rxq->qlen_mask + 1;
1549                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1550                 exp_buffs *= dev->data->nb_rx_queues;
1551                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1552                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1553                                      rxq->pool->name,
1554                                      rte_mempool_avail_count(rxq->pool),
1555                                      exp_buffs);
1556                         return -ENOENT;
1557                 }
1558         }
1559
1560         /* Check RBDR desc overflow */
1561         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1562         if (ret == 0) {
1563                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1564                              "VF%d", nic->vf_id);
1565                 return -ENOMEM;
1566         }
1567
1568         /* Enable qset */
1569         ret = nicvf_qset_config(nic);
1570         if (ret) {
1571                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1572                              nic->vf_id);
1573                 return ret;
1574         }
1575
1576         /* Allocate RBDR and RBDR ring desc */
1577         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1578         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1579         if (ret) {
1580                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1581                              "VF%d", nic->vf_id);
1582                 goto qset_reclaim;
1583         }
1584
1585         /* Enable and configure RBDR registers */
1586         ret = nicvf_qset_rbdr_config(nic, 0);
1587         if (ret) {
1588                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1589                              nic->vf_id);
1590                 goto qset_rbdr_free;
1591         }
1592
1593         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1594         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1595                                         total_rxq_desc);
1596         if (ret) {
1597                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1598                              nic->vf_id);
1599                 goto qset_rbdr_reclaim;
1600         }
1601
1602         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1603                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1604
1605         /* Configure VLAN Strip */
1606         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1607                 ETH_VLAN_EXTEND_MASK;
1608         ret = nicvf_vlan_offload_config(dev, mask);
1609
1610         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1611          * to the 64bit memory address.
1612          * The alignment creates a hole in mbuf(between the end of headroom and
1613          * packet data start). The new revision of the HW provides an option to
1614          * disable the L3 alignment feature and make mbuf layout looks
1615          * more like other NICs. For better application compatibility, disabling
1616          * l3 alignment feature on the hardware revisions it supports
1617          */
1618         nicvf_apad_config(nic, false);
1619
1620         /* Get queue ranges for this VF */
1621         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1622
1623         /* Configure TX queues */
1624         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1625                 ret = nicvf_vf_start_tx_queue(dev, nic,
1626                         qidx % MAX_SND_QUEUES_PER_QS);
1627                 if (ret)
1628                         goto start_txq_error;
1629         }
1630
1631         /* Configure RX queues */
1632         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1633                 ret = nicvf_vf_start_rx_queue(dev, nic,
1634                         qidx % MAX_RCV_QUEUES_PER_QS);
1635                 if (ret)
1636                         goto start_rxq_error;
1637         }
1638
1639         if (!nic->sqs_mode) {
1640                 /* Configure CPI algorithm */
1641                 ret = nicvf_configure_cpi(dev);
1642                 if (ret)
1643                         goto start_txq_error;
1644
1645                 ret = nicvf_mbox_get_rss_size(nic);
1646                 if (ret) {
1647                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1648                         goto qset_rss_error;
1649                 }
1650
1651                 /* Configure RSS */
1652                 ret = nicvf_configure_rss(dev);
1653                 if (ret)
1654                         goto qset_rss_error;
1655         }
1656
1657         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1658         nicvf_mbox_cfg_done(nic);
1659         return 0;
1660
1661 qset_rss_error:
1662         nicvf_rss_term(nic);
1663 start_rxq_error:
1664         for (qidx = rx_start; qidx <= rx_end; qidx++)
1665                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1666 start_txq_error:
1667         for (qidx = tx_start; qidx <= tx_end; qidx++)
1668                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1669 qset_rbdr_reclaim:
1670         nicvf_qset_rbdr_reclaim(nic, 0);
1671         nicvf_rbdr_release_mbufs(dev, nic);
1672 qset_rbdr_free:
1673         if (nic->rbdr) {
1674                 rte_free(nic->rbdr);
1675                 nic->rbdr = NULL;
1676         }
1677 qset_reclaim:
1678         nicvf_qset_reclaim(nic);
1679         return ret;
1680 }
1681
1682 static int
1683 nicvf_dev_start(struct rte_eth_dev *dev)
1684 {
1685         uint16_t qidx;
1686         int ret;
1687         size_t i;
1688         struct nicvf *nic = nicvf_pmd_priv(dev);
1689         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1690         uint16_t mtu;
1691         uint32_t buffsz = 0, rbdrsz = 0;
1692         struct rte_pktmbuf_pool_private *mbp_priv;
1693         struct nicvf_rxq *rxq;
1694
1695         PMD_INIT_FUNC_TRACE();
1696
1697         /* This function must be called for a primary device */
1698         assert_primary(nic);
1699
1700         /* Validate RBDR buff size */
1701         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1702                 rxq = dev->data->rx_queues[qidx];
1703                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1704                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1705                 if (buffsz % 128) {
1706                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1707                         return -EINVAL;
1708                 }
1709                 if (rbdrsz == 0)
1710                         rbdrsz = buffsz;
1711                 if (rbdrsz != buffsz) {
1712                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1713                                      qidx, rbdrsz, buffsz);
1714                         return -EINVAL;
1715                 }
1716         }
1717
1718         /* Configure loopback */
1719         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1720         if (ret) {
1721                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1722                 return ret;
1723         }
1724
1725         /* Reset all statistics counters attached to this port */
1726         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1727         if (ret) {
1728                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1729                 return ret;
1730         }
1731
1732         /* Setup scatter mode if needed by jumbo */
1733         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1734                                             2 * VLAN_TAG_SIZE > buffsz)
1735                 dev->data->scattered_rx = 1;
1736         if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0)
1737                 dev->data->scattered_rx = 1;
1738
1739         /* Setup MTU based on max_rx_pkt_len or default */
1740         mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ?
1741                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1742                         -  RTE_ETHER_HDR_LEN : RTE_ETHER_MTU;
1743
1744         if (nicvf_dev_set_mtu(dev, mtu)) {
1745                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1746                 return -EBUSY;
1747         }
1748
1749         ret = nicvf_vf_start(dev, nic, rbdrsz);
1750         if (ret != 0)
1751                 return ret;
1752
1753         for (i = 0; i < nic->sqs_count; i++) {
1754                 assert(nic->snicvf[i]);
1755
1756                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1757                 if (ret != 0)
1758                         return ret;
1759         }
1760
1761         /* Configure callbacks based on offloads */
1762         nicvf_set_tx_function(dev);
1763         nicvf_set_rx_function(dev);
1764
1765         return 0;
1766 }
1767
1768 static void
1769 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1770 {
1771         size_t i;
1772         int ret;
1773         struct nicvf *nic = nicvf_pmd_priv(dev);
1774
1775         PMD_INIT_FUNC_TRACE();
1776
1777         /* Teardown secondary vf first */
1778         for (i = 0; i < nic->sqs_count; i++) {
1779                 if (!nic->snicvf[i])
1780                         continue;
1781
1782                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1783         }
1784
1785         /* Stop the primary VF now */
1786         nicvf_vf_stop(dev, nic, cleanup);
1787
1788         /* Disable loopback */
1789         ret = nicvf_loopback_config(nic, 0);
1790         if (ret)
1791                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1792
1793         /* Reclaim CPI configuration */
1794         ret = nicvf_mbox_config_cpi(nic, 0);
1795         if (ret)
1796                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1797 }
1798
1799 static void
1800 nicvf_dev_stop(struct rte_eth_dev *dev)
1801 {
1802         PMD_INIT_FUNC_TRACE();
1803
1804         nicvf_dev_stop_cleanup(dev, false);
1805 }
1806
1807 static void
1808 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1809 {
1810         int ret;
1811         uint16_t qidx;
1812         uint16_t tx_start, tx_end;
1813         uint16_t rx_start, rx_end;
1814
1815         PMD_INIT_FUNC_TRACE();
1816
1817         if (cleanup) {
1818                 /* Let PF make the BGX's RX and TX switches to OFF position */
1819                 nicvf_mbox_shutdown(nic);
1820         }
1821
1822         /* Disable VLAN Strip */
1823         nicvf_vlan_hw_strip(nic, 0);
1824
1825         /* Get queue ranges for this VF */
1826         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1827
1828         for (qidx = tx_start; qidx <= tx_end; qidx++)
1829                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1830
1831         /* Get queue ranges for this VF */
1832         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1833
1834         /* Reclaim rq */
1835         for (qidx = rx_start; qidx <= rx_end; qidx++)
1836                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1837
1838         /* Reclaim RBDR */
1839         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1840         if (ret)
1841                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1842
1843         /* Move all charged buffers in RBDR back to pool */
1844         if (nic->rbdr != NULL)
1845                 nicvf_rbdr_release_mbufs(dev, nic);
1846
1847         /* Disable qset */
1848         ret = nicvf_qset_reclaim(nic);
1849         if (ret)
1850                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1851
1852         /* Disable all interrupts */
1853         nicvf_disable_all_interrupts(nic);
1854
1855         /* Free RBDR SW structure */
1856         if (nic->rbdr) {
1857                 rte_free(nic->rbdr);
1858                 nic->rbdr = NULL;
1859         }
1860 }
1861
1862 static void
1863 nicvf_dev_close(struct rte_eth_dev *dev)
1864 {
1865         size_t i;
1866         struct nicvf *nic = nicvf_pmd_priv(dev);
1867
1868         PMD_INIT_FUNC_TRACE();
1869
1870         nicvf_dev_stop_cleanup(dev, true);
1871         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1872
1873         for (i = 0; i < nic->sqs_count; i++) {
1874                 if (!nic->snicvf[i])
1875                         continue;
1876
1877                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1878         }
1879 }
1880
1881 static int
1882 nicvf_request_sqs(struct nicvf *nic)
1883 {
1884         size_t i;
1885
1886         assert_primary(nic);
1887         assert(nic->sqs_count > 0);
1888         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1889
1890         /* Set no of Rx/Tx queues in each of the SQsets */
1891         for (i = 0; i < nic->sqs_count; i++) {
1892                 if (nicvf_svf_empty())
1893                         rte_panic("Cannot assign sufficient number of "
1894                                   "secondary queues to primary VF%" PRIu8 "\n",
1895                                   nic->vf_id);
1896
1897                 nic->snicvf[i] = nicvf_svf_pop();
1898                 nic->snicvf[i]->sqs_id = i;
1899         }
1900
1901         return nicvf_mbox_request_sqs(nic);
1902 }
1903
1904 static int
1905 nicvf_dev_configure(struct rte_eth_dev *dev)
1906 {
1907         struct rte_eth_dev_data *data = dev->data;
1908         struct rte_eth_conf *conf = &data->dev_conf;
1909         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1910         struct rte_eth_txmode *txmode = &conf->txmode;
1911         struct nicvf *nic = nicvf_pmd_priv(dev);
1912         uint8_t cqcount;
1913
1914         PMD_INIT_FUNC_TRACE();
1915
1916         if (!rte_eal_has_hugepages()) {
1917                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1918                 return -EINVAL;
1919         }
1920
1921         if (txmode->mq_mode) {
1922                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1923                 return -EINVAL;
1924         }
1925
1926         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1927                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1928                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1929                 return -EINVAL;
1930         }
1931
1932         if (rxmode->split_hdr_size) {
1933                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1934                 return -EINVAL;
1935         }
1936
1937         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1938                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1939                 return -EINVAL;
1940         }
1941
1942         if (conf->dcb_capability_en) {
1943                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1944                 return -EINVAL;
1945         }
1946
1947         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1948                 PMD_INIT_LOG(INFO, "Flow director not supported");
1949                 return -EINVAL;
1950         }
1951
1952         assert_primary(nic);
1953         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1954         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1955         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1956                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1957                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1958         } else {
1959                 nic->sqs_count = 0;
1960         }
1961
1962         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1963
1964         if (nic->sqs_count > 0) {
1965                 if (nicvf_request_sqs(nic)) {
1966                         rte_panic("Cannot assign sufficient number of "
1967                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1968                                   dev->data->port_id, nic->vf_id);
1969                 }
1970         }
1971
1972         if (rxmode->offloads & DEV_RX_OFFLOAD_CHECKSUM)
1973                 nic->offload_cksum = 1;
1974
1975         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1976                 dev->data->port_id, nicvf_hw_cap(nic));
1977
1978         return 0;
1979 }
1980
1981 /* Initialize and register driver with DPDK Application */
1982 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1983         .dev_configure            = nicvf_dev_configure,
1984         .dev_start                = nicvf_dev_start,
1985         .dev_stop                 = nicvf_dev_stop,
1986         .link_update              = nicvf_dev_link_update,
1987         .dev_close                = nicvf_dev_close,
1988         .stats_get                = nicvf_dev_stats_get,
1989         .stats_reset              = nicvf_dev_stats_reset,
1990         .promiscuous_enable       = nicvf_dev_promisc_enable,
1991         .dev_infos_get            = nicvf_dev_info_get,
1992         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1993         .mtu_set                  = nicvf_dev_set_mtu,
1994         .vlan_offload_set         = nicvf_vlan_offload_set,
1995         .reta_update              = nicvf_dev_reta_update,
1996         .reta_query               = nicvf_dev_reta_query,
1997         .rss_hash_update          = nicvf_dev_rss_hash_update,
1998         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1999         .rx_queue_start           = nicvf_dev_rx_queue_start,
2000         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
2001         .tx_queue_start           = nicvf_dev_tx_queue_start,
2002         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
2003         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
2004         .rx_queue_release         = nicvf_dev_rx_queue_release,
2005         .rx_queue_count           = nicvf_dev_rx_queue_count,
2006         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
2007         .tx_queue_release         = nicvf_dev_tx_queue_release,
2008         .get_reg                  = nicvf_dev_get_regs,
2009 };
2010
2011 static int
2012 nicvf_vlan_offload_config(struct rte_eth_dev *dev, int mask)
2013 {
2014         struct rte_eth_rxmode *rxmode;
2015         struct nicvf *nic = nicvf_pmd_priv(dev);
2016         rxmode = &dev->data->dev_conf.rxmode;
2017         if (mask & ETH_VLAN_STRIP_MASK) {
2018                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2019                         nicvf_vlan_hw_strip(nic, true);
2020                 else
2021                         nicvf_vlan_hw_strip(nic, false);
2022         }
2023
2024         return 0;
2025 }
2026
2027 static int
2028 nicvf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2029 {
2030         nicvf_vlan_offload_config(dev, mask);
2031
2032         return 0;
2033 }
2034
2035 static inline int
2036 nicvf_set_first_skip(struct rte_eth_dev *dev)
2037 {
2038         int bytes_to_skip = 0;
2039         int ret = 0;
2040         unsigned int i;
2041         struct rte_kvargs *kvlist;
2042         static const char *const skip[] = {
2043                 SKIP_DATA_BYTES,
2044                 NULL};
2045         struct nicvf *nic = nicvf_pmd_priv(dev);
2046
2047         if (!dev->device->devargs) {
2048                 nicvf_first_skip_config(nic, 0);
2049                 return ret;
2050         }
2051
2052         kvlist = rte_kvargs_parse(dev->device->devargs->args, skip);
2053         if (!kvlist)
2054                 return -EINVAL;
2055
2056         if (kvlist->count == 0)
2057                 goto exit;
2058
2059         for (i = 0; i != kvlist->count; ++i) {
2060                 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
2061
2062                 if (!strcmp(pair->key, SKIP_DATA_BYTES))
2063                         bytes_to_skip = atoi(pair->value);
2064         }
2065
2066         /*128 bytes amounts to one cache line*/
2067         if (bytes_to_skip >= 0 && bytes_to_skip < 128) {
2068                 if (!(bytes_to_skip % 8)) {
2069                         nicvf_first_skip_config(nic, (bytes_to_skip / 8));
2070                         nic->skip_bytes = bytes_to_skip;
2071                         goto kvlist_free;
2072                 } else {
2073                         PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8");
2074                         ret = -EINVAL;
2075                         goto exit;
2076                 }
2077         } else {
2078                 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128");
2079                 ret = -EINVAL;
2080                 goto exit;
2081         }
2082 exit:
2083         nicvf_first_skip_config(nic, 0);
2084 kvlist_free:
2085         rte_kvargs_free(kvlist);
2086         return ret;
2087 }
2088 static int
2089 nicvf_eth_dev_uninit(struct rte_eth_dev *dev)
2090 {
2091         PMD_INIT_FUNC_TRACE();
2092
2093         if (rte_eal_process_type() == RTE_PROC_PRIMARY)
2094                 nicvf_dev_close(dev);
2095
2096         return 0;
2097 }
2098 static int
2099 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2100 {
2101         int ret;
2102         struct rte_pci_device *pci_dev;
2103         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2104
2105         PMD_INIT_FUNC_TRACE();
2106
2107         eth_dev->dev_ops = &nicvf_eth_dev_ops;
2108
2109         /* For secondary processes, the primary has done all the work */
2110         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2111                 if (nic) {
2112                         /* Setup callbacks for secondary process */
2113                         nicvf_set_tx_function(eth_dev);
2114                         nicvf_set_rx_function(eth_dev);
2115                         return 0;
2116                 } else {
2117                         /* If nic == NULL than it is secondary function
2118                          * so ethdev need to be released by caller */
2119                         return ENOTSUP;
2120                 }
2121         }
2122
2123         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2124         rte_eth_copy_pci_info(eth_dev, pci_dev);
2125
2126         nic->device_id = pci_dev->id.device_id;
2127         nic->vendor_id = pci_dev->id.vendor_id;
2128         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2129         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2130
2131         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2132                         pci_dev->id.vendor_id, pci_dev->id.device_id,
2133                         pci_dev->addr.domain, pci_dev->addr.bus,
2134                         pci_dev->addr.devid, pci_dev->addr.function);
2135
2136         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2137         if (!nic->reg_base) {
2138                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2139                 ret = -ENODEV;
2140                 goto fail;
2141         }
2142
2143         nicvf_disable_all_interrupts(nic);
2144
2145         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2146         if (ret) {
2147                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2148                 goto fail;
2149         }
2150
2151         ret = nicvf_mbox_check_pf_ready(nic);
2152         if (ret) {
2153                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2154                 goto alarm_fail;
2155         } else {
2156                 PMD_INIT_LOG(INFO,
2157                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2158                         nic->node, nic->vf_id,
2159                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2160                         nic->sqs_mode ? "true" : "false",
2161                         nic->loopback_supported ? "true" : "false"
2162                         );
2163         }
2164
2165         ret = nicvf_base_init(nic);
2166         if (ret) {
2167                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2168                 goto malloc_fail;
2169         }
2170
2171         if (nic->sqs_mode) {
2172                 /* Push nic to stack of secondary vfs */
2173                 nicvf_svf_push(nic);
2174
2175                 /* Steal nic pointer from the device for further reuse */
2176                 eth_dev->data->dev_private = NULL;
2177
2178                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2179                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2180                 if (ret) {
2181                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2182                         goto fail;
2183                 }
2184
2185                 /* Detach port by returning positive error number */
2186                 return ENOTSUP;
2187         }
2188
2189         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr",
2190                                         RTE_ETHER_ADDR_LEN, 0);
2191         if (eth_dev->data->mac_addrs == NULL) {
2192                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2193                 ret = -ENOMEM;
2194                 goto alarm_fail;
2195         }
2196         if (rte_is_zero_ether_addr((struct rte_ether_addr *)nic->mac_addr))
2197                 rte_eth_random_addr(&nic->mac_addr[0]);
2198
2199         rte_ether_addr_copy((struct rte_ether_addr *)nic->mac_addr,
2200                         &eth_dev->data->mac_addrs[0]);
2201
2202         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2203         if (ret) {
2204                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2205                 goto malloc_fail;
2206         }
2207
2208         ret = nicvf_set_first_skip(eth_dev);
2209         if (ret) {
2210                 PMD_INIT_LOG(ERR, "Failed to configure first skip");
2211                 goto malloc_fail;
2212         }
2213         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2214                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2215                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2216                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2217
2218         return 0;
2219
2220 malloc_fail:
2221         rte_free(eth_dev->data->mac_addrs);
2222         eth_dev->data->mac_addrs = NULL;
2223 alarm_fail:
2224         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2225 fail:
2226         return ret;
2227 }
2228
2229 static const struct rte_pci_id pci_id_nicvf_map[] = {
2230         {
2231                 .class_id = RTE_CLASS_ANY_ID,
2232                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2233                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2234                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2235                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2236         },
2237         {
2238                 .class_id = RTE_CLASS_ANY_ID,
2239                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2240                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2241                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2242                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2243         },
2244         {
2245                 .class_id = RTE_CLASS_ANY_ID,
2246                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2247                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2248                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2249                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2250         },
2251         {
2252                 .class_id = RTE_CLASS_ANY_ID,
2253                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2254                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2255                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2256                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2257         },
2258         {
2259                 .vendor_id = 0,
2260         },
2261 };
2262
2263 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2264         struct rte_pci_device *pci_dev)
2265 {
2266         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2267                 nicvf_eth_dev_init);
2268 }
2269
2270 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2271 {
2272         return rte_eth_dev_pci_generic_remove(pci_dev, nicvf_eth_dev_uninit);
2273 }
2274
2275 static struct rte_pci_driver rte_nicvf_pmd = {
2276         .id_table = pci_id_nicvf_map,
2277         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2278                         RTE_PCI_DRV_INTR_LSC,
2279         .probe = nicvf_eth_pci_probe,
2280         .remove = nicvf_eth_pci_remove,
2281 };
2282
2283 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2284 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2285 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");
2286 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>");