drivers/net/thunderx/nicvf_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016 Cavium, Inc
   3  */
   4
   5 #include <assert.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15 #include <sys/queue.h>
  16
  17 #include <rte_alarm.h>
  18 #include <rte_atomic.h>
  19 #include <rte_branch_prediction.h>
  20 #include <rte_byteorder.h>
  21 #include <rte_common.h>
  22 #include <rte_cycles.h>
  23 #include <rte_debug.h>
  24 #include <rte_dev.h>
  25 #include <rte_eal.h>
  26 #include <rte_ether.h>
  27 #include <rte_ethdev.h>
  28 #include <rte_ethdev_pci.h>
  29 #include <rte_interrupts.h>
  30 #include <rte_log.h>
  31 #include <rte_memory.h>
  32 #include <rte_memzone.h>
  33 #include <rte_malloc.h>
  34 #include <rte_random.h>
  35 #include <rte_pci.h>
  36 #include <rte_bus_pci.h>
  37 #include <rte_tailq.h>
  38
  39 #include "base/nicvf_plat.h"
  40
  41 #include "nicvf_ethdev.h"
  42 #include "nicvf_rxtx.h"
  43 #include "nicvf_svf.h"
  44 #include "nicvf_logs.h"
  45
  46 int nicvf_logtype_mbox;
  47 int nicvf_logtype_init;
  48 int nicvf_logtype_driver;
  49
  50 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  51 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  52 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  53                           bool cleanup);
  54
  55 RTE_INIT(nicvf_init_log);
  56 static void
  57 nicvf_init_log(void)
  58 {
  59         nicvf_logtype_mbox = rte_log_register("pmd.nicvf.mbox");
  60         if (nicvf_logtype_mbox >= 0)
  61                 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
  62
  63         nicvf_logtype_init = rte_log_register("pmd.nicvf.init");
  64         if (nicvf_logtype_init >= 0)
  65                 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
  66
  67         nicvf_logtype_driver = rte_log_register("pmd.nicvf.driver");
  68         if (nicvf_logtype_driver >= 0)
  69                 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
  70 }
  71
  72 static inline int
  73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  74                                struct rte_eth_link *link)
  75 {
  76         struct rte_eth_link *dst = &dev->data->dev_link;
  77         struct rte_eth_link *src = link;
  78
  79         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  80                 *(uint64_t *)src) == 0)
  81                 return -1;
  82
  83         return 0;
  84 }
  85
  86 static inline void
  87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  88 {
  89         link->link_status = nic->link_up;
  90         link->link_duplex = ETH_LINK_AUTONEG;
  91         if (nic->duplex == NICVF_HALF_DUPLEX)
  92                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  93         else if (nic->duplex == NICVF_FULL_DUPLEX)
  94                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  95         link->link_speed = nic->speed;
  96         link->link_autoneg = ETH_LINK_AUTONEG;
  97 }
  98
  99 static void
 100 nicvf_interrupt(void *arg)
 101 {
 102         struct rte_eth_dev *dev = arg;
 103         struct nicvf *nic = nicvf_pmd_priv(dev);
 104
 105         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 106                 if (dev->data->dev_conf.intr_conf.lsc)
 107                         nicvf_set_eth_link_status(nic, &dev->data->dev_link);
 108                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
 109                                               NULL, NULL);
 110         }
 111
 112         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 113                                 nicvf_interrupt, dev);
 114 }
 115
 116 static void
 117 nicvf_vf_interrupt(void *arg)
 118 {
 119         struct nicvf *nic = arg;
 120
 121         nicvf_reg_poll_interrupts(nic);
 122
 123         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 124                                 nicvf_vf_interrupt, nic);
 125 }
 126
 127 static int
 128 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 129 {
 130         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 131 }
 132
 133 static int
 134 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 135 {
 136         return rte_eal_alarm_cancel(fn, arg);
 137 }
 138
 139 /*
 140  * Return 0 means link status changed, -1 means not changed
 141  */
 142 static int
 143 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 144 {
 145 #define CHECK_INTERVAL 100  /* 100ms */
 146 #define MAX_CHECK_TIME 90   /* 9s (90 * 100ms) in total */
 147         struct rte_eth_link link;
 148         struct nicvf *nic = nicvf_pmd_priv(dev);
 149         int i;
 150
 151         PMD_INIT_FUNC_TRACE();
 152
 153         if (wait_to_complete) {
 154                 /* rte_eth_link_get() might need to wait up to 9 seconds */
 155                 for (i = 0; i < MAX_CHECK_TIME; i++) {
 156                         memset(&link, 0, sizeof(link));
 157                         nicvf_set_eth_link_status(nic, &link);
 158                         if (link.link_status)
 159                                 break;
 160                         rte_delay_ms(CHECK_INTERVAL);
 161                 }
 162         } else {
 163                 memset(&link, 0, sizeof(link));
 164                 nicvf_set_eth_link_status(nic, &link);
 165         }
 166         return nicvf_atomic_write_link_status(dev, &link);
 167 }
 168
 169 static int
 170 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 171 {
 172         struct nicvf *nic = nicvf_pmd_priv(dev);
 173         uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 174         size_t i;
 175
 176         PMD_INIT_FUNC_TRACE();
 177
 178         if (frame_size > NIC_HW_MAX_FRS)
 179                 return -EINVAL;
 180
 181         if (frame_size < NIC_HW_MIN_FRS)
 182                 return -EINVAL;
 183
 184         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 185
 186         /*
 187          * Refuse mtu that requires the support of scattered packets
 188          * when this feature has not been enabled before.
 189          */
 190         if (!dev->data->scattered_rx &&
 191                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 192                 return -EINVAL;
 193
 194         /* check <seg size> * <max_seg>  >= max_frame */
 195         if (dev->data->scattered_rx &&
 196                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 197                 return -EINVAL;
 198
 199         if (frame_size > ETHER_MAX_LEN)
 200                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 201         else
 202                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 203
 204         if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
 205                 return -EINVAL;
 206
 207         /* Update max frame size */
 208         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
 209         nic->mtu = mtu;
 210
 211         for (i = 0; i < nic->sqs_count; i++)
 212                 nic->snicvf[i]->mtu = mtu;
 213
 214         return 0;
 215 }
 216
 217 static int
 218 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 219 {
 220         uint64_t *data = regs->data;
 221         struct nicvf *nic = nicvf_pmd_priv(dev);
 222
 223         if (data == NULL) {
 224                 regs->length = nicvf_reg_get_count();
 225                 regs->width = THUNDERX_REG_BYTES;
 226                 return 0;
 227         }
 228
 229         /* Support only full register dump */
 230         if ((regs->length == 0) ||
 231                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 232                 regs->version = nic->vendor_id << 16 | nic->device_id;
 233                 nicvf_reg_dump(nic, data);
 234                 return 0;
 235         }
 236         return -ENOTSUP;
 237 }
 238
 239 static int
 240 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 241 {
 242         uint16_t qidx;
 243         struct nicvf_hw_rx_qstats rx_qstats;
 244         struct nicvf_hw_tx_qstats tx_qstats;
 245         struct nicvf_hw_stats port_stats;
 246         struct nicvf *nic = nicvf_pmd_priv(dev);
 247         uint16_t rx_start, rx_end;
 248         uint16_t tx_start, tx_end;
 249         size_t i;
 250
 251         /* RX queue indices for the first VF */
 252         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 253
 254         /* Reading per RX ring stats */
 255         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 256                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 257                         break;
 258
 259                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 260                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 261                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 262         }
 263
 264         /* TX queue indices for the first VF */
 265         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 266
 267         /* Reading per TX ring stats */
 268         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 269                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 270                         break;
 271
 272                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 273                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 274                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 275         }
 276
 277         for (i = 0; i < nic->sqs_count; i++) {
 278                 struct nicvf *snic = nic->snicvf[i];
 279
 280                 if (snic == NULL)
 281                         break;
 282
 283                 /* RX queue indices for a secondary VF */
 284                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 285
 286                 /* Reading per RX ring stats */
 287                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 288                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 289                                 break;
 290
 291                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 292                                                qidx % MAX_RCV_QUEUES_PER_QS);
 293                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 294                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 295                 }
 296
 297                 /* TX queue indices for a secondary VF */
 298                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 299                 /* Reading per TX ring stats */
 300                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 301                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 302                                 break;
 303
 304                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 305                                                qidx % MAX_SND_QUEUES_PER_QS);
 306                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 307                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 308                 }
 309         }
 310
 311         nicvf_hw_get_stats(nic, &port_stats);
 312         stats->ibytes = port_stats.rx_bytes;
 313         stats->ipackets = port_stats.rx_ucast_frames;
 314         stats->ipackets += port_stats.rx_bcast_frames;
 315         stats->ipackets += port_stats.rx_mcast_frames;
 316         stats->ierrors = port_stats.rx_l2_errors;
 317         stats->imissed = port_stats.rx_drop_red;
 318         stats->imissed += port_stats.rx_drop_overrun;
 319         stats->imissed += port_stats.rx_drop_bcast;
 320         stats->imissed += port_stats.rx_drop_mcast;
 321         stats->imissed += port_stats.rx_drop_l3_bcast;
 322         stats->imissed += port_stats.rx_drop_l3_mcast;
 323
 324         stats->obytes = port_stats.tx_bytes_ok;
 325         stats->opackets = port_stats.tx_ucast_frames_ok;
 326         stats->opackets += port_stats.tx_bcast_frames_ok;
 327         stats->opackets += port_stats.tx_mcast_frames_ok;
 328         stats->oerrors = port_stats.tx_drops;
 329
 330         return 0;
 331 }
 332
 333 static const uint32_t *
 334 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 335 {
 336         size_t copied;
 337         static uint32_t ptypes[32];
 338         struct nicvf *nic = nicvf_pmd_priv(dev);
 339         static const uint32_t ptypes_common[] = {
 340                 RTE_PTYPE_L3_IPV4,
 341                 RTE_PTYPE_L3_IPV4_EXT,
 342                 RTE_PTYPE_L3_IPV6,
 343                 RTE_PTYPE_L3_IPV6_EXT,
 344                 RTE_PTYPE_L4_TCP,
 345                 RTE_PTYPE_L4_UDP,
 346                 RTE_PTYPE_L4_FRAG,
 347         };
 348         static const uint32_t ptypes_tunnel[] = {
 349                 RTE_PTYPE_TUNNEL_GRE,
 350                 RTE_PTYPE_TUNNEL_GENEVE,
 351                 RTE_PTYPE_TUNNEL_VXLAN,
 352                 RTE_PTYPE_TUNNEL_NVGRE,
 353         };
 354         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 355
 356         copied = sizeof(ptypes_common);
 357         memcpy(ptypes, ptypes_common, copied);
 358         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 359                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 360                         sizeof(ptypes_tunnel));
 361                 copied += sizeof(ptypes_tunnel);
 362         }
 363
 364         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 365         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 366                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 367                 return ptypes;
 368
 369         return NULL;
 370 }
 371
 372 static void
 373 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 374 {
 375         int i;
 376         uint16_t rxqs = 0, txqs = 0;
 377         struct nicvf *nic = nicvf_pmd_priv(dev);
 378         uint16_t rx_start, rx_end;
 379         uint16_t tx_start, tx_end;
 380
 381         /* Reset all primary nic counters */
 382         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 383         for (i = rx_start; i <= rx_end; i++)
 384                 rxqs |= (0x3 << (i * 2));
 385
 386         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 387         for (i = tx_start; i <= tx_end; i++)
 388                 txqs |= (0x3 << (i * 2));
 389
 390         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 391
 392         /* Reset secondary nic queue counters */
 393         for (i = 0; i < nic->sqs_count; i++) {
 394                 struct nicvf *snic = nic->snicvf[i];
 395                 if (snic == NULL)
 396                         break;
 397
 398                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 399                 for (i = rx_start; i <= rx_end; i++)
 400                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 401
 402                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 403                 for (i = tx_start; i <= tx_end; i++)
 404                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 405
 406                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 407         }
 408 }
 409
 410 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 411 static void
 412 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 413 {
 414 }
 415
 416 static inline uint64_t
 417 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 418 {
 419         uint64_t nic_rss = 0;
 420
 421         if (ethdev_rss & ETH_RSS_IPV4)
 422                 nic_rss |= RSS_IP_ENA;
 423
 424         if (ethdev_rss & ETH_RSS_IPV6)
 425                 nic_rss |= RSS_IP_ENA;
 426
 427         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 428                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 429
 430         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 431                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 432
 433         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 434                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 435
 436         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 437                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 438
 439         if (ethdev_rss & ETH_RSS_PORT)
 440                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 441
 442         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 443                 if (ethdev_rss & ETH_RSS_VXLAN)
 444                         nic_rss |= RSS_TUN_VXLAN_ENA;
 445
 446                 if (ethdev_rss & ETH_RSS_GENEVE)
 447                         nic_rss |= RSS_TUN_GENEVE_ENA;
 448
 449                 if (ethdev_rss & ETH_RSS_NVGRE)
 450                         nic_rss |= RSS_TUN_NVGRE_ENA;
 451         }
 452
 453         return nic_rss;
 454 }
 455
 456 static inline uint64_t
 457 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 458 {
 459         uint64_t ethdev_rss = 0;
 460
 461         if (nic_rss & RSS_IP_ENA)
 462                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 463
 464         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 465                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 466                                 ETH_RSS_NONFRAG_IPV6_TCP);
 467
 468         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 469                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 470                                 ETH_RSS_NONFRAG_IPV6_UDP);
 471
 472         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 473                 ethdev_rss |= ETH_RSS_PORT;
 474
 475         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 476                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 477                         ethdev_rss |= ETH_RSS_VXLAN;
 478
 479                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 480                         ethdev_rss |= ETH_RSS_GENEVE;
 481
 482                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 483                         ethdev_rss |= ETH_RSS_NVGRE;
 484         }
 485         return ethdev_rss;
 486 }
 487
 488 static int
 489 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 490                      struct rte_eth_rss_reta_entry64 *reta_conf,
 491                      uint16_t reta_size)
 492 {
 493         struct nicvf *nic = nicvf_pmd_priv(dev);
 494         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 495         int ret, i, j;
 496
 497         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 498                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 499                         "(%d) doesn't match the number hardware can supported "
 500                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 501                 return -EINVAL;
 502         }
 503
 504         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 505         if (ret)
 506                 return ret;
 507
 508         /* Copy RETA table */
 509         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 510                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 511                         if ((reta_conf[i].mask >> j) & 0x01)
 512                                 reta_conf[i].reta[j] = tbl[j];
 513         }
 514
 515         return 0;
 516 }
 517
 518 static int
 519 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 520                       struct rte_eth_rss_reta_entry64 *reta_conf,
 521                       uint16_t reta_size)
 522 {
 523         struct nicvf *nic = nicvf_pmd_priv(dev);
 524         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 525         int ret, i, j;
 526
 527         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 528                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 529                         "(%d) doesn't match the number hardware can supported "
 530                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 531                 return -EINVAL;
 532         }
 533
 534         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 535         if (ret)
 536                 return ret;
 537
 538         /* Copy RETA table */
 539         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 540                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 541                         if ((reta_conf[i].mask >> j) & 0x01)
 542                                 tbl[j] = reta_conf[i].reta[j];
 543         }
 544
 545         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 546 }
 547
 548 static int
 549 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 550                             struct rte_eth_rss_conf *rss_conf)
 551 {
 552         struct nicvf *nic = nicvf_pmd_priv(dev);
 553
 554         if (rss_conf->rss_key)
 555                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 556
 557         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 558         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 559         return 0;
 560 }
 561
 562 static int
 563 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 564                           struct rte_eth_rss_conf *rss_conf)
 565 {
 566         struct nicvf *nic = nicvf_pmd_priv(dev);
 567         uint64_t nic_rss;
 568
 569         if (rss_conf->rss_key &&
 570                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 571                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 572                                 rss_conf->rss_key_len);
 573                 return -EINVAL;
 574         }
 575
 576         if (rss_conf->rss_key)
 577                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 578
 579         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 580         nicvf_rss_set_cfg(nic, nic_rss);
 581         return 0;
 582 }
 583
 584 static int
 585 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 586                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 587 {
 588         const struct rte_memzone *rz;
 589         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 590
 591         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 592                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 593                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 594         if (rz == NULL) {
 595                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 596                 return -ENOMEM;
 597         }
 598
 599         memset(rz->addr, 0, ring_size);
 600
 601         rxq->phys = rz->iova;
 602         rxq->desc = rz->addr;
 603         rxq->qlen_mask = desc_cnt - 1;
 604
 605         return 0;
 606 }
 607
 608 static int
 609 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 610                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 611 {
 612         const struct rte_memzone *rz;
 613         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 614
 615         rz = rte_eth_dma_zone_reserve(dev, "sq",
 616                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 617                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 618         if (rz == NULL) {
 619                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 620                 return -ENOMEM;
 621         }
 622
 623         memset(rz->addr, 0, ring_size);
 624
 625         sq->phys = rz->iova;
 626         sq->desc = rz->addr;
 627         sq->qlen_mask = desc_cnt - 1;
 628
 629         return 0;
 630 }
 631
 632 static int
 633 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 634                       uint32_t desc_cnt, uint32_t buffsz)
 635 {
 636         struct nicvf_rbdr *rbdr;
 637         const struct rte_memzone *rz;
 638         uint32_t ring_size;
 639
 640         assert(nic->rbdr == NULL);
 641         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 642                                   RTE_CACHE_LINE_SIZE, nic->node);
 643         if (rbdr == NULL) {
 644                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 645                 return -ENOMEM;
 646         }
 647
 648         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 649         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 650                                       nicvf_netdev_qidx(nic, 0), ring_size,
 651                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 652         if (rz == NULL) {
 653                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 654                 return -ENOMEM;
 655         }
 656
 657         memset(rz->addr, 0, ring_size);
 658
 659         rbdr->phys = rz->iova;
 660         rbdr->tail = 0;
 661         rbdr->next_tail = 0;
 662         rbdr->desc = rz->addr;
 663         rbdr->buffsz = buffsz;
 664         rbdr->qlen_mask = desc_cnt - 1;
 665         rbdr->rbdr_status =
 666                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 667         rbdr->rbdr_door =
 668                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 669
 670         nic->rbdr = rbdr;
 671         return 0;
 672 }
 673
 674 static void
 675 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 676                         nicvf_iova_addr_t phy)
 677 {
 678         uint16_t qidx;
 679         void *obj;
 680         struct nicvf_rxq *rxq;
 681         uint16_t rx_start, rx_end;
 682
 683         /* Get queue ranges for this VF */
 684         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 685
 686         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 687                 rxq = dev->data->rx_queues[qidx];
 688                 if (rxq->precharge_cnt) {
 689                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 690                                                            rxq->mbuf_phys_off);
 691                         rte_mempool_put(rxq->pool, obj);
 692                         rxq->precharge_cnt--;
 693                         break;
 694                 }
 695         }
 696 }
 697
 698 static inline void
 699 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 700 {
 701         uint32_t qlen_mask, head;
 702         struct rbdr_entry_t *entry;
 703         struct nicvf_rbdr *rbdr = nic->rbdr;
 704
 705         qlen_mask = rbdr->qlen_mask;
 706         head = rbdr->head;
 707         while (head != rbdr->tail) {
 708                 entry = rbdr->desc + head;
 709                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 710                 head++;
 711                 head = head & qlen_mask;
 712         }
 713 }
 714
 715 static inline void
 716 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 717 {
 718         uint32_t head;
 719
 720         head = txq->head;
 721         while (head != txq->tail) {
 722                 if (txq->txbuffs[head]) {
 723                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 724                         txq->txbuffs[head] = NULL;
 725                 }
 726                 head++;
 727                 head = head & txq->qlen_mask;
 728         }
 729 }
 730
 731 static void
 732 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 733 {
 734         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 735
 736         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 737         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 738         txq->tail = 0;
 739         txq->head = 0;
 740         txq->xmit_bufs = 0;
 741 }
 742
 743 static inline int
 744 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 745                         uint16_t qidx)
 746 {
 747         struct nicvf_txq *txq;
 748         int ret;
 749
 750         assert(qidx < MAX_SND_QUEUES_PER_QS);
 751
 752         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 753                 RTE_ETH_QUEUE_STATE_STARTED)
 754                 return 0;
 755
 756         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 757         txq->pool = NULL;
 758         ret = nicvf_qset_sq_config(nic, qidx, txq);
 759         if (ret) {
 760                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 761                              nic->vf_id, qidx, ret);
 762                 goto config_sq_error;
 763         }
 764
 765         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 766                 RTE_ETH_QUEUE_STATE_STARTED;
 767         return ret;
 768
 769 config_sq_error:
 770         nicvf_qset_sq_reclaim(nic, qidx);
 771         return ret;
 772 }
 773
 774 static inline int
 775 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 776                        uint16_t qidx)
 777 {
 778         struct nicvf_txq *txq;
 779         int ret;
 780
 781         assert(qidx < MAX_SND_QUEUES_PER_QS);
 782
 783         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 784                 RTE_ETH_QUEUE_STATE_STOPPED)
 785                 return 0;
 786
 787         ret = nicvf_qset_sq_reclaim(nic, qidx);
 788         if (ret)
 789                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 790                              nic->vf_id, qidx, ret);
 791
 792         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 793         nicvf_tx_queue_release_mbufs(txq);
 794         nicvf_tx_queue_reset(txq);
 795
 796         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 797                 RTE_ETH_QUEUE_STATE_STOPPED;
 798         return ret;
 799 }
 800
 801 static inline int
 802 nicvf_configure_cpi(struct rte_eth_dev *dev)
 803 {
 804         struct nicvf *nic = nicvf_pmd_priv(dev);
 805         uint16_t qidx, qcnt;
 806         int ret;
 807
 808         /* Count started rx queues */
 809         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 810                 if (dev->data->rx_queue_state[qidx] ==
 811                     RTE_ETH_QUEUE_STATE_STARTED)
 812                         qcnt++;
 813
 814         nic->cpi_alg = CPI_ALG_NONE;
 815         ret = nicvf_mbox_config_cpi(nic, qcnt);
 816         if (ret)
 817                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 818
 819         return ret;
 820 }
 821
 822 static inline int
 823 nicvf_configure_rss(struct rte_eth_dev *dev)
 824 {
 825         struct nicvf *nic = nicvf_pmd_priv(dev);
 826         uint64_t rsshf;
 827         int ret = -EINVAL;
 828
 829         rsshf = nicvf_rss_ethdev_to_nic(nic,
 830                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 831         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 832                     dev->data->dev_conf.rxmode.mq_mode,
 833                     dev->data->nb_rx_queues,
 834                     dev->data->dev_conf.lpbk_mode, rsshf);
 835
 836         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 837                 ret = nicvf_rss_term(nic);
 838         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 839                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 840         if (ret)
 841                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 842
 843         return ret;
 844 }
 845
 846 static int
 847 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 848 {
 849         struct nicvf *nic = nicvf_pmd_priv(dev);
 850         unsigned int idx, qmap_size;
 851         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 852         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 853
 854         if (nic->cpi_alg != CPI_ALG_NONE)
 855                 return -EINVAL;
 856
 857         /* Prepare queue map */
 858         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 859                 if (dev->data->rx_queue_state[idx] ==
 860                                 RTE_ETH_QUEUE_STATE_STARTED)
 861                         qmap[qmap_size++] = idx;
 862         }
 863
 864         /* Update default RSS RETA */
 865         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 866                 default_reta[idx] = qmap[idx % qmap_size];
 867
 868         return nicvf_rss_reta_update(nic, default_reta,
 869                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 870 }
 871
 872 static void
 873 nicvf_dev_tx_queue_release(void *sq)
 874 {
 875         struct nicvf_txq *txq;
 876
 877         PMD_INIT_FUNC_TRACE();
 878
 879         txq = (struct nicvf_txq *)sq;
 880         if (txq) {
 881                 if (txq->txbuffs != NULL) {
 882                         nicvf_tx_queue_release_mbufs(txq);
 883                         rte_free(txq->txbuffs);
 884                         txq->txbuffs = NULL;
 885                 }
 886                 rte_free(txq);
 887         }
 888 }
 889
 890 static void
 891 nicvf_set_tx_function(struct rte_eth_dev *dev)
 892 {
 893         struct nicvf_txq *txq;
 894         size_t i;
 895         bool multiseg = false;
 896
 897         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 898                 txq = dev->data->tx_queues[i];
 899                 if ((txq->txq_flags & ETH_TXQ_FLAGS_NOMULTSEGS) == 0) {
 900                         multiseg = true;
 901                         break;
 902                 }
 903         }
 904
 905         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 906         if (multiseg) {
 907                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 908                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 909         } else {
 910                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 911                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 912         }
 913
 914         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 915                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 916         else
 917                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 918 }
 919
 920 static void
 921 nicvf_set_rx_function(struct rte_eth_dev *dev)
 922 {
 923         if (dev->data->scattered_rx) {
 924                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 925                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 926         } else {
 927                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 928                 dev->rx_pkt_burst = nicvf_recv_pkts;
 929         }
 930 }
 931
 932 static int
 933 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 934                          uint16_t nb_desc, unsigned int socket_id,
 935                          const struct rte_eth_txconf *tx_conf)
 936 {
 937         uint16_t tx_free_thresh;
 938         uint8_t is_single_pool;
 939         struct nicvf_txq *txq;
 940         struct nicvf *nic = nicvf_pmd_priv(dev);
 941
 942         PMD_INIT_FUNC_TRACE();
 943
 944         if (qidx >= MAX_SND_QUEUES_PER_QS)
 945                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 946
 947         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 948
 949         /* Socket id check */
 950         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 951                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 952                 socket_id, nic->node);
 953
 954         /* Tx deferred start is not supported */
 955         if (tx_conf->tx_deferred_start) {
 956                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 957                 return -EINVAL;
 958         }
 959
 960         /* Roundup nb_desc to available qsize and validate max number of desc */
 961         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 962         if (nb_desc == 0) {
 963                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 964                 return -EINVAL;
 965         }
 966
 967         /* Validate tx_free_thresh */
 968         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 969                                 tx_conf->tx_free_thresh :
 970                                 NICVF_DEFAULT_TX_FREE_THRESH);
 971
 972         if (tx_free_thresh > (nb_desc) ||
 973                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 974                 PMD_INIT_LOG(ERR,
 975                         "tx_free_thresh must be less than the number of TX "
 976                         "descriptors. (tx_free_thresh=%u port=%d "
 977                         "queue=%d)", (unsigned int)tx_free_thresh,
 978                         (int)dev->data->port_id, (int)qidx);
 979                 return -EINVAL;
 980         }
 981
 982         /* Free memory prior to re-allocation if needed. */
 983         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 984                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 985                                 nicvf_netdev_qidx(nic, qidx));
 986                 nicvf_dev_tx_queue_release(
 987                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 988                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 989         }
 990
 991         /* Allocating tx queue data structure */
 992         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 993                                         RTE_CACHE_LINE_SIZE, nic->node);
 994         if (txq == NULL) {
 995                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
 996                              nicvf_netdev_qidx(nic, qidx));
 997                 return -ENOMEM;
 998         }
 999
1000         txq->nic = nic;
1001         txq->queue_id = qidx;
1002         txq->tx_free_thresh = tx_free_thresh;
1003         txq->txq_flags = tx_conf->txq_flags;
1004         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1005         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1006         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
1007                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
1008
1009         /* Choose optimum free threshold value for multipool case */
1010         if (!is_single_pool) {
1011                 txq->tx_free_thresh = (uint16_t)
1012                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1013                                 NICVF_TX_FREE_MPOOL_THRESH :
1014                                 tx_conf->tx_free_thresh);
1015                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1016         } else {
1017                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1018         }
1019
1020         /* Allocate software ring */
1021         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1022                                 nb_desc * sizeof(struct rte_mbuf *),
1023                                 RTE_CACHE_LINE_SIZE, nic->node);
1024
1025         if (txq->txbuffs == NULL) {
1026                 nicvf_dev_tx_queue_release(txq);
1027                 return -ENOMEM;
1028         }
1029
1030         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1031                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1032                 nicvf_dev_tx_queue_release(txq);
1033                 return -ENOMEM;
1034         }
1035
1036         nicvf_tx_queue_reset(txq);
1037
1038         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
1039                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1040                         txq->phys);
1041
1042         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1043         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1044                 RTE_ETH_QUEUE_STATE_STOPPED;
1045         return 0;
1046 }
1047
1048 static inline void
1049 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1050 {
1051         uint32_t rxq_cnt;
1052         uint32_t nb_pkts, released_pkts = 0;
1053         uint32_t refill_cnt = 0;
1054         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1055
1056         if (dev->rx_pkt_burst == NULL)
1057                 return;
1058
1059         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1060                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1061                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1062                                         NICVF_MAX_RX_FREE_THRESH);
1063                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1064                 while (nb_pkts) {
1065                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1066                         released_pkts++;
1067                 }
1068         }
1069
1070
1071         refill_cnt += nicvf_dev_rbdr_refill(dev,
1072                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1073
1074         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1075                     released_pkts, refill_cnt);
1076 }
1077
1078 static void
1079 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1080 {
1081         rxq->head = 0;
1082         rxq->available_space = 0;
1083         rxq->recv_buffers = 0;
1084 }
1085
1086 static inline int
1087 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1088                         uint16_t qidx)
1089 {
1090         struct nicvf_rxq *rxq;
1091         int ret;
1092
1093         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1094
1095         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1096                 RTE_ETH_QUEUE_STATE_STARTED)
1097                 return 0;
1098
1099         /* Update rbdr pointer to all rxq */
1100         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1101         rxq->shared_rbdr = nic->rbdr;
1102
1103         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1104         if (ret) {
1105                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1106                              nic->vf_id, qidx, ret);
1107                 goto config_rq_error;
1108         }
1109         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1110         if (ret) {
1111                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1112                              nic->vf_id, qidx, ret);
1113                 goto config_cq_error;
1114         }
1115
1116         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1117                 RTE_ETH_QUEUE_STATE_STARTED;
1118         return 0;
1119
1120 config_cq_error:
1121         nicvf_qset_cq_reclaim(nic, qidx);
1122 config_rq_error:
1123         nicvf_qset_rq_reclaim(nic, qidx);
1124         return ret;
1125 }
1126
1127 static inline int
1128 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1129                        uint16_t qidx)
1130 {
1131         struct nicvf_rxq *rxq;
1132         int ret, other_error;
1133
1134         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1135                 RTE_ETH_QUEUE_STATE_STOPPED)
1136                 return 0;
1137
1138         ret = nicvf_qset_rq_reclaim(nic, qidx);
1139         if (ret)
1140                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1141                              nic->vf_id, qidx, ret);
1142
1143         other_error = ret;
1144         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1145         nicvf_rx_queue_release_mbufs(dev, rxq);
1146         nicvf_rx_queue_reset(rxq);
1147
1148         ret = nicvf_qset_cq_reclaim(nic, qidx);
1149         if (ret)
1150                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1151                              nic->vf_id, qidx, ret);
1152
1153         other_error |= ret;
1154         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1155                 RTE_ETH_QUEUE_STATE_STOPPED;
1156         return other_error;
1157 }
1158
1159 static void
1160 nicvf_dev_rx_queue_release(void *rx_queue)
1161 {
1162         PMD_INIT_FUNC_TRACE();
1163
1164         rte_free(rx_queue);
1165 }
1166
1167 static int
1168 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1169 {
1170         struct nicvf *nic = nicvf_pmd_priv(dev);
1171         int ret;
1172
1173         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1174                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1175
1176         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1177
1178         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1179         if (ret)
1180                 return ret;
1181
1182         ret = nicvf_configure_cpi(dev);
1183         if (ret)
1184                 return ret;
1185
1186         return nicvf_configure_rss_reta(dev);
1187 }
1188
1189 static int
1190 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1191 {
1192         int ret;
1193         struct nicvf *nic = nicvf_pmd_priv(dev);
1194
1195         if (qidx >= MAX_SND_QUEUES_PER_QS)
1196                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1197
1198         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1199
1200         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1201         ret |= nicvf_configure_cpi(dev);
1202         ret |= nicvf_configure_rss_reta(dev);
1203         return ret;
1204 }
1205
1206 static int
1207 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1208 {
1209         struct nicvf *nic = nicvf_pmd_priv(dev);
1210
1211         if (qidx >= MAX_SND_QUEUES_PER_QS)
1212                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1213
1214         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1215
1216         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1217 }
1218
1219 static int
1220 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1221 {
1222         struct nicvf *nic = nicvf_pmd_priv(dev);
1223
1224         if (qidx >= MAX_SND_QUEUES_PER_QS)
1225                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1226
1227         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1228
1229         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1230 }
1231
1232 static inline void
1233 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1234 {
1235         uintptr_t p;
1236         struct rte_mbuf mb_def;
1237
1238         RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1239         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1240         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1241                                 offsetof(struct rte_mbuf, data_off) != 2);
1242         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1243                                 offsetof(struct rte_mbuf, data_off) != 4);
1244         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1245                                 offsetof(struct rte_mbuf, data_off) != 6);
1246         mb_def.nb_segs = 1;
1247         mb_def.data_off = RTE_PKTMBUF_HEADROOM;
1248         mb_def.port = rxq->port_id;
1249         rte_mbuf_refcnt_set(&mb_def, 1);
1250
1251         /* Prevent compiler reordering: rearm_data covers previous fields */
1252         rte_compiler_barrier();
1253         p = (uintptr_t)&mb_def.rearm_data;
1254         rxq->mbuf_initializer.value = *(uint64_t *)p;
1255 }
1256
1257 static int
1258 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1259                          uint16_t nb_desc, unsigned int socket_id,
1260                          const struct rte_eth_rxconf *rx_conf,
1261                          struct rte_mempool *mp)
1262 {
1263         uint16_t rx_free_thresh;
1264         struct nicvf_rxq *rxq;
1265         struct nicvf *nic = nicvf_pmd_priv(dev);
1266
1267         PMD_INIT_FUNC_TRACE();
1268
1269         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1270                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1271
1272         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1273
1274         /* Socket id check */
1275         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1276                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1277                 socket_id, nic->node);
1278
1279         /* Mempool memory must be contiguous, so must be one memory segment*/
1280         if (mp->nb_mem_chunks != 1) {
1281                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1282                 return -EINVAL;
1283         }
1284
1285         /* Mempool memory must be physically contiguous */
1286         if (mp->flags & MEMPOOL_F_NO_PHYS_CONTIG) {
1287                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1288                 return -EINVAL;
1289         }
1290
1291         /* Rx deferred start is not supported */
1292         if (rx_conf->rx_deferred_start) {
1293                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1294                 return -EINVAL;
1295         }
1296
1297         /* Roundup nb_desc to available qsize and validate max number of desc */
1298         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1299         if (nb_desc == 0) {
1300                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1301                 return -EINVAL;
1302         }
1303
1304         /* Check rx_free_thresh upper bound */
1305         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1306                                 rx_conf->rx_free_thresh :
1307                                 NICVF_DEFAULT_RX_FREE_THRESH);
1308         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1309                 rx_free_thresh >= nb_desc * .75) {
1310                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1311                                 rx_free_thresh);
1312                 return -EINVAL;
1313         }
1314
1315         /* Free memory prior to re-allocation if needed */
1316         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1317                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1318                                 nicvf_netdev_qidx(nic, qidx));
1319                 nicvf_dev_rx_queue_release(
1320                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1321                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1322         }
1323
1324         /* Allocate rxq memory */
1325         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1326                                         RTE_CACHE_LINE_SIZE, nic->node);
1327         if (rxq == NULL) {
1328                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1329                              nicvf_netdev_qidx(nic, qidx));
1330                 return -ENOMEM;
1331         }
1332
1333         rxq->nic = nic;
1334         rxq->pool = mp;
1335         rxq->queue_id = qidx;
1336         rxq->port_id = dev->data->port_id;
1337         rxq->rx_free_thresh = rx_free_thresh;
1338         rxq->rx_drop_en = rx_conf->rx_drop_en;
1339         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1340         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1341         rxq->precharge_cnt = 0;
1342
1343         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1344                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1345         else
1346                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1347
1348         nicvf_rxq_mbuf_setup(rxq);
1349
1350         /* Alloc completion queue */
1351         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1352                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1353                 nicvf_dev_rx_queue_release(rxq);
1354                 return -ENOMEM;
1355         }
1356
1357         nicvf_rx_queue_reset(rxq);
1358
1359         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
1360                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1361                         rte_mempool_avail_count(mp), rxq->phys);
1362
1363         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1364         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1365                 RTE_ETH_QUEUE_STATE_STOPPED;
1366         return 0;
1367 }
1368
1369 static void
1370 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1371 {
1372         struct nicvf *nic = nicvf_pmd_priv(dev);
1373         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1374
1375         PMD_INIT_FUNC_TRACE();
1376
1377         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1378
1379         /* Autonegotiation may be disabled */
1380         dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1381         dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1382                                  ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1383         if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1384                 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1385
1386         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1387         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
1388         dev_info->max_rx_queues =
1389                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1390         dev_info->max_tx_queues =
1391                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1392         dev_info->max_mac_addrs = 1;
1393         dev_info->max_vfs = pci_dev->max_vfs;
1394
1395         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
1396         dev_info->tx_offload_capa =
1397                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
1398                 DEV_TX_OFFLOAD_UDP_CKSUM   |
1399                 DEV_TX_OFFLOAD_TCP_CKSUM   |
1400                 DEV_TX_OFFLOAD_TCP_TSO     |
1401                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
1402
1403         dev_info->reta_size = nic->rss_info.rss_size;
1404         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1405         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1406         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1407                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1408
1409         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1410                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1411                 .rx_drop_en = 0,
1412         };
1413
1414         dev_info->default_txconf = (struct rte_eth_txconf) {
1415                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1416                 .txq_flags =
1417                         ETH_TXQ_FLAGS_NOMULTSEGS  |
1418                         ETH_TXQ_FLAGS_NOREFCOUNT  |
1419                         ETH_TXQ_FLAGS_NOMULTMEMP  |
1420                         ETH_TXQ_FLAGS_NOVLANOFFL  |
1421                         ETH_TXQ_FLAGS_NOXSUMSCTP,
1422         };
1423 }
1424
1425 static nicvf_iova_addr_t
1426 rbdr_rte_mempool_get(void *dev, void *opaque)
1427 {
1428         uint16_t qidx;
1429         uintptr_t mbuf;
1430         struct nicvf_rxq *rxq;
1431         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1432         struct nicvf *nic = (struct nicvf *)opaque;
1433         uint16_t rx_start, rx_end;
1434
1435         /* Get queue ranges for this VF */
1436         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1437
1438         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1439                 rxq = eth_dev->data->rx_queues[qidx];
1440                 /* Maintain equal buffer count across all pools */
1441                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1442                         continue;
1443                 rxq->precharge_cnt++;
1444                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1445                 if (mbuf)
1446                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1447         }
1448         return 0;
1449 }
1450
1451 static int
1452 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1453 {
1454         int ret;
1455         uint16_t qidx, data_off;
1456         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1457         uint64_t mbuf_phys_off = 0;
1458         struct nicvf_rxq *rxq;
1459         struct rte_mbuf *mbuf;
1460         uint16_t rx_start, rx_end;
1461         uint16_t tx_start, tx_end;
1462
1463         PMD_INIT_FUNC_TRACE();
1464
1465         /* Userspace process exited without proper shutdown in last run */
1466         if (nicvf_qset_rbdr_active(nic, 0))
1467                 nicvf_vf_stop(dev, nic, false);
1468
1469         /* Get queue ranges for this VF */
1470         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1471
1472         /*
1473          * Thunderx nicvf PMD can support more than one pool per port only when
1474          * 1) Data payload size is same across all the pools in given port
1475          * AND
1476          * 2) All mbuffs in the pools are from the same hugepage
1477          * AND
1478          * 3) Mbuff metadata size is same across all the pools in given port
1479          *
1480          * This is to support existing application that uses multiple pool/port.
1481          * But, the purpose of using multipool for QoS will not be addressed.
1482          *
1483          */
1484
1485         /* Validate mempool attributes */
1486         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1487                 rxq = dev->data->rx_queues[qidx];
1488                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1489                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1490                 if (mbuf == NULL) {
1491                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1492                                      "pool=%s",
1493                                      nic->vf_id, qidx, rxq->pool->name);
1494                         return -ENOMEM;
1495                 }
1496                 data_off = nicvf_mbuff_meta_length(mbuf);
1497                 data_off += RTE_PKTMBUF_HEADROOM;
1498                 rte_pktmbuf_free(mbuf);
1499
1500                 if (data_off % RTE_CACHE_LINE_SIZE) {
1501                         PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1502                                 rxq->pool->name, data_off,
1503                                 data_off % RTE_CACHE_LINE_SIZE);
1504                         return -EINVAL;
1505                 }
1506                 rxq->mbuf_phys_off -= data_off;
1507
1508                 if (mbuf_phys_off == 0)
1509                         mbuf_phys_off = rxq->mbuf_phys_off;
1510                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1511                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1512                                      PRIx64, rxq->pool->name, nic->vf_id,
1513                                      mbuf_phys_off);
1514                         return -EINVAL;
1515                 }
1516         }
1517
1518         /* Check the level of buffers in the pool */
1519         total_rxq_desc = 0;
1520         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1521                 rxq = dev->data->rx_queues[qidx];
1522                 /* Count total numbers of rxq descs */
1523                 total_rxq_desc += rxq->qlen_mask + 1;
1524                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1525                 exp_buffs *= dev->data->nb_rx_queues;
1526                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1527                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1528                                      rxq->pool->name,
1529                                      rte_mempool_avail_count(rxq->pool),
1530                                      exp_buffs);
1531                         return -ENOENT;
1532                 }
1533         }
1534
1535         /* Check RBDR desc overflow */
1536         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1537         if (ret == 0) {
1538                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1539                              "VF%d", nic->vf_id);
1540                 return -ENOMEM;
1541         }
1542
1543         /* Enable qset */
1544         ret = nicvf_qset_config(nic);
1545         if (ret) {
1546                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1547                              nic->vf_id);
1548                 return ret;
1549         }
1550
1551         /* Allocate RBDR and RBDR ring desc */
1552         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1553         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1554         if (ret) {
1555                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1556                              "VF%d", nic->vf_id);
1557                 goto qset_reclaim;
1558         }
1559
1560         /* Enable and configure RBDR registers */
1561         ret = nicvf_qset_rbdr_config(nic, 0);
1562         if (ret) {
1563                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1564                              nic->vf_id);
1565                 goto qset_rbdr_free;
1566         }
1567
1568         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1569         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1570                                         total_rxq_desc);
1571         if (ret) {
1572                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1573                              nic->vf_id);
1574                 goto qset_rbdr_reclaim;
1575         }
1576
1577         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1578                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1579
1580         /* Configure VLAN Strip */
1581         nicvf_vlan_hw_strip(nic, dev->data->dev_conf.rxmode.hw_vlan_strip);
1582
1583         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1584          * to the 64bit memory address.
1585          * The alignment creates a hole in mbuf(between the end of headroom and
1586          * packet data start). The new revision of the HW provides an option to
1587          * disable the L3 alignment feature and make mbuf layout looks
1588          * more like other NICs. For better application compatibility, disabling
1589          * l3 alignment feature on the hardware revisions it supports
1590          */
1591         nicvf_apad_config(nic, false);
1592
1593         /* Get queue ranges for this VF */
1594         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1595
1596         /* Configure TX queues */
1597         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1598                 ret = nicvf_vf_start_tx_queue(dev, nic,
1599                         qidx % MAX_SND_QUEUES_PER_QS);
1600                 if (ret)
1601                         goto start_txq_error;
1602         }
1603
1604         /* Configure RX queues */
1605         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1606                 ret = nicvf_vf_start_rx_queue(dev, nic,
1607                         qidx % MAX_RCV_QUEUES_PER_QS);
1608                 if (ret)
1609                         goto start_rxq_error;
1610         }
1611
1612         if (!nic->sqs_mode) {
1613                 /* Configure CPI algorithm */
1614                 ret = nicvf_configure_cpi(dev);
1615                 if (ret)
1616                         goto start_txq_error;
1617
1618                 ret = nicvf_mbox_get_rss_size(nic);
1619                 if (ret) {
1620                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1621                         goto qset_rss_error;
1622                 }
1623
1624                 /* Configure RSS */
1625                 ret = nicvf_configure_rss(dev);
1626                 if (ret)
1627                         goto qset_rss_error;
1628         }
1629
1630         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1631         nicvf_mbox_cfg_done(nic);
1632         return 0;
1633
1634 qset_rss_error:
1635         nicvf_rss_term(nic);
1636 start_rxq_error:
1637         for (qidx = rx_start; qidx <= rx_end; qidx++)
1638                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1639 start_txq_error:
1640         for (qidx = tx_start; qidx <= tx_end; qidx++)
1641                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1642 qset_rbdr_reclaim:
1643         nicvf_qset_rbdr_reclaim(nic, 0);
1644         nicvf_rbdr_release_mbufs(dev, nic);
1645 qset_rbdr_free:
1646         if (nic->rbdr) {
1647                 rte_free(nic->rbdr);
1648                 nic->rbdr = NULL;
1649         }
1650 qset_reclaim:
1651         nicvf_qset_reclaim(nic);
1652         return ret;
1653 }
1654
1655 static int
1656 nicvf_dev_start(struct rte_eth_dev *dev)
1657 {
1658         uint16_t qidx;
1659         int ret;
1660         size_t i;
1661         struct nicvf *nic = nicvf_pmd_priv(dev);
1662         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1663         uint16_t mtu;
1664         uint32_t buffsz = 0, rbdrsz = 0;
1665         struct rte_pktmbuf_pool_private *mbp_priv;
1666         struct nicvf_rxq *rxq;
1667
1668         PMD_INIT_FUNC_TRACE();
1669
1670         /* This function must be called for a primary device */
1671         assert_primary(nic);
1672
1673         /* Validate RBDR buff size */
1674         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1675                 rxq = dev->data->rx_queues[qidx];
1676                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1677                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1678                 if (buffsz % 128) {
1679                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1680                         return -EINVAL;
1681                 }
1682                 if (rbdrsz == 0)
1683                         rbdrsz = buffsz;
1684                 if (rbdrsz != buffsz) {
1685                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1686                                      qidx, rbdrsz, buffsz);
1687                         return -EINVAL;
1688                 }
1689         }
1690
1691         /* Configure loopback */
1692         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1693         if (ret) {
1694                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1695                 return ret;
1696         }
1697
1698         /* Reset all statistics counters attached to this port */
1699         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1700         if (ret) {
1701                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1702                 return ret;
1703         }
1704
1705         /* Setup scatter mode if needed by jumbo */
1706         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1707                                             2 * VLAN_TAG_SIZE > buffsz)
1708                 dev->data->scattered_rx = 1;
1709         if (rx_conf->enable_scatter)
1710                 dev->data->scattered_rx = 1;
1711
1712         /* Setup MTU based on max_rx_pkt_len or default */
1713         mtu = dev->data->dev_conf.rxmode.jumbo_frame ?
1714                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1715                         -  ETHER_HDR_LEN - ETHER_CRC_LEN
1716                 : ETHER_MTU;
1717
1718         if (nicvf_dev_set_mtu(dev, mtu)) {
1719                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1720                 return -EBUSY;
1721         }
1722
1723         ret = nicvf_vf_start(dev, nic, rbdrsz);
1724         if (ret != 0)
1725                 return ret;
1726
1727         for (i = 0; i < nic->sqs_count; i++) {
1728                 assert(nic->snicvf[i]);
1729
1730                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1731                 if (ret != 0)
1732                         return ret;
1733         }
1734
1735         /* Configure callbacks based on scatter mode */
1736         nicvf_set_tx_function(dev);
1737         nicvf_set_rx_function(dev);
1738
1739         return 0;
1740 }
1741
1742 static void
1743 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1744 {
1745         size_t i;
1746         int ret;
1747         struct nicvf *nic = nicvf_pmd_priv(dev);
1748
1749         PMD_INIT_FUNC_TRACE();
1750
1751         /* Teardown secondary vf first */
1752         for (i = 0; i < nic->sqs_count; i++) {
1753                 if (!nic->snicvf[i])
1754                         continue;
1755
1756                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1757         }
1758
1759         /* Stop the primary VF now */
1760         nicvf_vf_stop(dev, nic, cleanup);
1761
1762         /* Disable loopback */
1763         ret = nicvf_loopback_config(nic, 0);
1764         if (ret)
1765                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1766
1767         /* Reclaim CPI configuration */
1768         ret = nicvf_mbox_config_cpi(nic, 0);
1769         if (ret)
1770                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1771 }
1772
1773 static void
1774 nicvf_dev_stop(struct rte_eth_dev *dev)
1775 {
1776         PMD_INIT_FUNC_TRACE();
1777
1778         nicvf_dev_stop_cleanup(dev, false);
1779 }
1780
1781 static void
1782 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1783 {
1784         int ret;
1785         uint16_t qidx;
1786         uint16_t tx_start, tx_end;
1787         uint16_t rx_start, rx_end;
1788
1789         PMD_INIT_FUNC_TRACE();
1790
1791         if (cleanup) {
1792                 /* Let PF make the BGX's RX and TX switches to OFF position */
1793                 nicvf_mbox_shutdown(nic);
1794         }
1795
1796         /* Disable VLAN Strip */
1797         nicvf_vlan_hw_strip(nic, 0);
1798
1799         /* Get queue ranges for this VF */
1800         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1801
1802         for (qidx = tx_start; qidx <= tx_end; qidx++)
1803                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1804
1805         /* Get queue ranges for this VF */
1806         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1807
1808         /* Reclaim rq */
1809         for (qidx = rx_start; qidx <= rx_end; qidx++)
1810                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1811
1812         /* Reclaim RBDR */
1813         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1814         if (ret)
1815                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1816
1817         /* Move all charged buffers in RBDR back to pool */
1818         if (nic->rbdr != NULL)
1819                 nicvf_rbdr_release_mbufs(dev, nic);
1820
1821         /* Disable qset */
1822         ret = nicvf_qset_reclaim(nic);
1823         if (ret)
1824                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1825
1826         /* Disable all interrupts */
1827         nicvf_disable_all_interrupts(nic);
1828
1829         /* Free RBDR SW structure */
1830         if (nic->rbdr) {
1831                 rte_free(nic->rbdr);
1832                 nic->rbdr = NULL;
1833         }
1834 }
1835
1836 static void
1837 nicvf_dev_close(struct rte_eth_dev *dev)
1838 {
1839         size_t i;
1840         struct nicvf *nic = nicvf_pmd_priv(dev);
1841
1842         PMD_INIT_FUNC_TRACE();
1843
1844         nicvf_dev_stop_cleanup(dev, true);
1845         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1846
1847         for (i = 0; i < nic->sqs_count; i++) {
1848                 if (!nic->snicvf[i])
1849                         continue;
1850
1851                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1852         }
1853 }
1854
1855 static int
1856 nicvf_request_sqs(struct nicvf *nic)
1857 {
1858         size_t i;
1859
1860         assert_primary(nic);
1861         assert(nic->sqs_count > 0);
1862         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1863
1864         /* Set no of Rx/Tx queues in each of the SQsets */
1865         for (i = 0; i < nic->sqs_count; i++) {
1866                 if (nicvf_svf_empty())
1867                         rte_panic("Cannot assign sufficient number of "
1868                                   "secondary queues to primary VF%" PRIu8 "\n",
1869                                   nic->vf_id);
1870
1871                 nic->snicvf[i] = nicvf_svf_pop();
1872                 nic->snicvf[i]->sqs_id = i;
1873         }
1874
1875         return nicvf_mbox_request_sqs(nic);
1876 }
1877
1878 static int
1879 nicvf_dev_configure(struct rte_eth_dev *dev)
1880 {
1881         struct rte_eth_dev_data *data = dev->data;
1882         struct rte_eth_conf *conf = &data->dev_conf;
1883         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1884         struct rte_eth_txmode *txmode = &conf->txmode;
1885         struct nicvf *nic = nicvf_pmd_priv(dev);
1886         uint8_t cqcount;
1887
1888         PMD_INIT_FUNC_TRACE();
1889
1890         if (!rte_eal_has_hugepages()) {
1891                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1892                 return -EINVAL;
1893         }
1894
1895         if (txmode->mq_mode) {
1896                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1897                 return -EINVAL;
1898         }
1899
1900         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1901                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1902                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1903                 return -EINVAL;
1904         }
1905
1906         if (!rxmode->hw_strip_crc) {
1907                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1908                 rxmode->hw_strip_crc = 1;
1909         }
1910
1911         if (rxmode->hw_ip_checksum) {
1912                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
1913                 rxmode->hw_ip_checksum = 0;
1914         }
1915
1916         if (rxmode->split_hdr_size) {
1917                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1918                 return -EINVAL;
1919         }
1920
1921         if (rxmode->hw_vlan_filter) {
1922                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
1923                 return -EINVAL;
1924         }
1925
1926         if (rxmode->hw_vlan_extend) {
1927                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
1928                 return -EINVAL;
1929         }
1930
1931         if (rxmode->enable_lro) {
1932                 PMD_INIT_LOG(INFO, "LRO not supported");
1933                 return -EINVAL;
1934         }
1935
1936         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1937                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1938                 return -EINVAL;
1939         }
1940
1941         if (conf->dcb_capability_en) {
1942                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1943                 return -EINVAL;
1944         }
1945
1946         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1947                 PMD_INIT_LOG(INFO, "Flow director not supported");
1948                 return -EINVAL;
1949         }
1950
1951         assert_primary(nic);
1952         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1953         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1954         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1955                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1956                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1957         } else {
1958                 nic->sqs_count = 0;
1959         }
1960
1961         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1962
1963         if (nic->sqs_count > 0) {
1964                 if (nicvf_request_sqs(nic)) {
1965                         rte_panic("Cannot assign sufficient number of "
1966                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1967                                   dev->data->port_id, nic->vf_id);
1968                 }
1969         }
1970
1971         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1972                 dev->data->port_id, nicvf_hw_cap(nic));
1973
1974         return 0;
1975 }
1976
1977 /* Initialize and register driver with DPDK Application */
1978 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1979         .dev_configure            = nicvf_dev_configure,
1980         .dev_start                = nicvf_dev_start,
1981         .dev_stop                 = nicvf_dev_stop,
1982         .link_update              = nicvf_dev_link_update,
1983         .dev_close                = nicvf_dev_close,
1984         .stats_get                = nicvf_dev_stats_get,
1985         .stats_reset              = nicvf_dev_stats_reset,
1986         .promiscuous_enable       = nicvf_dev_promisc_enable,
1987         .dev_infos_get            = nicvf_dev_info_get,
1988         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1989         .mtu_set                  = nicvf_dev_set_mtu,
1990         .reta_update              = nicvf_dev_reta_update,
1991         .reta_query               = nicvf_dev_reta_query,
1992         .rss_hash_update          = nicvf_dev_rss_hash_update,
1993         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1994         .rx_queue_start           = nicvf_dev_rx_queue_start,
1995         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1996         .tx_queue_start           = nicvf_dev_tx_queue_start,
1997         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1998         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1999         .rx_queue_release         = nicvf_dev_rx_queue_release,
2000         .rx_queue_count           = nicvf_dev_rx_queue_count,
2001         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
2002         .tx_queue_release         = nicvf_dev_tx_queue_release,
2003         .get_reg                  = nicvf_dev_get_regs,
2004 };
2005
2006 static int
2007 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2008 {
2009         int ret;
2010         struct rte_pci_device *pci_dev;
2011         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2012
2013         PMD_INIT_FUNC_TRACE();
2014
2015         eth_dev->dev_ops = &nicvf_eth_dev_ops;
2016
2017         /* For secondary processes, the primary has done all the work */
2018         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2019                 if (nic) {
2020                         /* Setup callbacks for secondary process */
2021                         nicvf_set_tx_function(eth_dev);
2022                         nicvf_set_rx_function(eth_dev);
2023                         return 0;
2024                 } else {
2025                         /* If nic == NULL than it is secondary function
2026                          * so ethdev need to be released by caller */
2027                         return ENOTSUP;
2028                 }
2029         }
2030
2031         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2032         rte_eth_copy_pci_info(eth_dev, pci_dev);
2033
2034         nic->device_id = pci_dev->id.device_id;
2035         nic->vendor_id = pci_dev->id.vendor_id;
2036         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2037         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2038
2039         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2040                         pci_dev->id.vendor_id, pci_dev->id.device_id,
2041                         pci_dev->addr.domain, pci_dev->addr.bus,
2042                         pci_dev->addr.devid, pci_dev->addr.function);
2043
2044         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2045         if (!nic->reg_base) {
2046                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2047                 ret = -ENODEV;
2048                 goto fail;
2049         }
2050
2051         nicvf_disable_all_interrupts(nic);
2052
2053         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2054         if (ret) {
2055                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2056                 goto fail;
2057         }
2058
2059         ret = nicvf_mbox_check_pf_ready(nic);
2060         if (ret) {
2061                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2062                 goto alarm_fail;
2063         } else {
2064                 PMD_INIT_LOG(INFO,
2065                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2066                         nic->node, nic->vf_id,
2067                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2068                         nic->sqs_mode ? "true" : "false",
2069                         nic->loopback_supported ? "true" : "false"
2070                         );
2071         }
2072
2073         ret = nicvf_base_init(nic);
2074         if (ret) {
2075                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2076                 goto malloc_fail;
2077         }
2078
2079         if (nic->sqs_mode) {
2080                 /* Push nic to stack of secondary vfs */
2081                 nicvf_svf_push(nic);
2082
2083                 /* Steal nic pointer from the device for further reuse */
2084                 eth_dev->data->dev_private = NULL;
2085
2086                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2087                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2088                 if (ret) {
2089                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2090                         goto fail;
2091                 }
2092
2093                 /* Detach port by returning positive error number */
2094                 return ENOTSUP;
2095         }
2096
2097         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2098         if (eth_dev->data->mac_addrs == NULL) {
2099                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2100                 ret = -ENOMEM;
2101                 goto alarm_fail;
2102         }
2103         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2104                 eth_random_addr(&nic->mac_addr[0]);
2105
2106         ether_addr_copy((struct ether_addr *)nic->mac_addr,
2107                         &eth_dev->data->mac_addrs[0]);
2108
2109         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2110         if (ret) {
2111                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2112                 goto malloc_fail;
2113         }
2114
2115         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2116                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2117                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2118                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2119
2120         return 0;
2121
2122 malloc_fail:
2123         rte_free(eth_dev->data->mac_addrs);
2124 alarm_fail:
2125         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2126 fail:
2127         return ret;
2128 }
2129
2130 static const struct rte_pci_id pci_id_nicvf_map[] = {
2131         {
2132                 .class_id = RTE_CLASS_ANY_ID,
2133                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2134                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2135                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2136                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2137         },
2138         {
2139                 .class_id = RTE_CLASS_ANY_ID,
2140                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2141                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2142                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2143                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2144         },
2145         {
2146                 .class_id = RTE_CLASS_ANY_ID,
2147                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2148                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2149                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2150                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2151         },
2152         {
2153                 .class_id = RTE_CLASS_ANY_ID,
2154                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2155                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2156                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2157                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2158         },
2159         {
2160                 .vendor_id = 0,
2161         },
2162 };
2163
2164 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2165         struct rte_pci_device *pci_dev)
2166 {
2167         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2168                 nicvf_eth_dev_init);
2169 }
2170
2171 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2172 {
2173         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2174 }
2175
2176 static struct rte_pci_driver rte_nicvf_pmd = {
2177         .id_table = pci_id_nicvf_map,
2178         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2179                         RTE_PCI_DRV_INTR_LSC,
2180         .probe = nicvf_eth_pci_probe,
2181         .remove = nicvf_eth_pci_remove,
2182 };
2183
2184 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2185 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2186 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");