drivers/net/thunderx/nicvf_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016 Cavium, Inc
   3  */
   4
   5 #include <assert.h>
   6 #include <stdio.h>
   7 #include <stdbool.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <string.h>
  11 #include <unistd.h>
  12 #include <stdarg.h>
  13 #include <inttypes.h>
  14 #include <netinet/in.h>
  15 #include <sys/queue.h>
  16
  17 #include <rte_alarm.h>
  18 #include <rte_branch_prediction.h>
  19 #include <rte_byteorder.h>
  20 #include <rte_common.h>
  21 #include <rte_cycles.h>
  22 #include <rte_debug.h>
  23 #include <rte_dev.h>
  24 #include <rte_eal.h>
  25 #include <rte_ether.h>
  26 #include <rte_ethdev_driver.h>
  27 #include <rte_ethdev_pci.h>
  28 #include <rte_interrupts.h>
  29 #include <rte_log.h>
  30 #include <rte_memory.h>
  31 #include <rte_memzone.h>
  32 #include <rte_malloc.h>
  33 #include <rte_random.h>
  34 #include <rte_pci.h>
  35 #include <rte_bus_pci.h>
  36 #include <rte_tailq.h>
  37 #include <rte_devargs.h>
  38 #include <rte_kvargs.h>
  39
  40 #include "base/nicvf_plat.h"
  41
  42 #include "nicvf_ethdev.h"
  43 #include "nicvf_rxtx.h"
  44 #include "nicvf_svf.h"
  45 #include "nicvf_logs.h"
  46
  47 int nicvf_logtype_mbox;
  48 int nicvf_logtype_init;
  49 int nicvf_logtype_driver;
  50
  51 static void nicvf_dev_stop(struct rte_eth_dev *dev);
  52 static void nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup);
  53 static void nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic,
  54                           bool cleanup);
  55
  56 RTE_INIT(nicvf_init_log);
  57 static void
  58 nicvf_init_log(void)
  59 {
  60         nicvf_logtype_mbox = rte_log_register("pmd.net.thunderx.mbox");
  61         if (nicvf_logtype_mbox >= 0)
  62                 rte_log_set_level(nicvf_logtype_mbox, RTE_LOG_NOTICE);
  63
  64         nicvf_logtype_init = rte_log_register("pmd.net.thunderx.init");
  65         if (nicvf_logtype_init >= 0)
  66                 rte_log_set_level(nicvf_logtype_init, RTE_LOG_NOTICE);
  67
  68         nicvf_logtype_driver = rte_log_register("pmd.net.thunderx.driver");
  69         if (nicvf_logtype_driver >= 0)
  70                 rte_log_set_level(nicvf_logtype_driver, RTE_LOG_NOTICE);
  71 }
  72
  73 static void
  74 nicvf_link_status_update(struct nicvf *nic,
  75                          struct rte_eth_link *link)
  76 {
  77         memset(link, 0, sizeof(*link));
  78
  79         link->link_status = nic->link_up ? ETH_LINK_UP : ETH_LINK_DOWN;
  80
  81         if (nic->duplex == NICVF_HALF_DUPLEX)
  82                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  83         else if (nic->duplex == NICVF_FULL_DUPLEX)
  84                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  85         link->link_speed = nic->speed;
  86         link->link_autoneg = ETH_LINK_AUTONEG;
  87 }
  88
  89 static void
  90 nicvf_interrupt(void *arg)
  91 {
  92         struct rte_eth_dev *dev = arg;
  93         struct nicvf *nic = nicvf_pmd_priv(dev);
  94         struct rte_eth_link link;
  95
  96         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
  97                 if (dev->data->dev_conf.intr_conf.lsc) {
  98                         nicvf_link_status_update(nic, &link);
  99                         rte_eth_linkstatus_set(dev, &link);
 100
 101                         _rte_eth_dev_callback_process(dev,
 102                                                       RTE_ETH_EVENT_INTR_LSC,
 103                                                       NULL);
 104                 }
 105         }
 106
 107         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 108                                 nicvf_interrupt, dev);
 109 }
 110
 111 static void
 112 nicvf_vf_interrupt(void *arg)
 113 {
 114         struct nicvf *nic = arg;
 115
 116         nicvf_reg_poll_interrupts(nic);
 117
 118         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 119                                 nicvf_vf_interrupt, nic);
 120 }
 121
 122 static int
 123 nicvf_periodic_alarm_start(void (fn)(void *), void *arg)
 124 {
 125         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000, fn, arg);
 126 }
 127
 128 static int
 129 nicvf_periodic_alarm_stop(void (fn)(void *), void *arg)
 130 {
 131         return rte_eal_alarm_cancel(fn, arg);
 132 }
 133
 134 /*
 135  * Return 0 means link status changed, -1 means not changed
 136  */
 137 static int
 138 nicvf_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
 139 {
 140 #define CHECK_INTERVAL 100  /* 100ms */
 141 #define MAX_CHECK_TIME 90   /* 9s (90 * 100ms) in total */
 142         struct rte_eth_link link;
 143         struct nicvf *nic = nicvf_pmd_priv(dev);
 144         int i;
 145
 146         PMD_INIT_FUNC_TRACE();
 147
 148         if (wait_to_complete) {
 149                 /* rte_eth_link_get() might need to wait up to 9 seconds */
 150                 for (i = 0; i < MAX_CHECK_TIME; i++) {
 151                         nicvf_link_status_update(nic, &link);
 152                         if (link.link_status == ETH_LINK_UP)
 153                                 break;
 154                         rte_delay_ms(CHECK_INTERVAL);
 155                 }
 156         } else {
 157                 nicvf_link_status_update(nic, &link);
 158         }
 159
 160         return rte_eth_linkstatus_set(dev, &link);
 161 }
 162
 163 static int
 164 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 165 {
 166         struct nicvf *nic = nicvf_pmd_priv(dev);
 167         uint32_t buffsz, frame_size = mtu + NIC_HW_L2_OVERHEAD;
 168         size_t i;
 169         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
 170
 171         PMD_INIT_FUNC_TRACE();
 172
 173         if (frame_size > NIC_HW_MAX_FRS)
 174                 return -EINVAL;
 175
 176         if (frame_size < NIC_HW_MIN_FRS)
 177                 return -EINVAL;
 178
 179         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 180
 181         /*
 182          * Refuse mtu that requires the support of scattered packets
 183          * when this feature has not been enabled before.
 184          */
 185         if (dev->data->dev_started && !dev->data->scattered_rx &&
 186                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 187                 return -EINVAL;
 188
 189         /* check <seg size> * <max_seg>  >= max_frame */
 190         if (dev->data->scattered_rx &&
 191                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 192                 return -EINVAL;
 193
 194         if (frame_size > ETHER_MAX_LEN)
 195                 rxmode->offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME;
 196         else
 197                 rxmode->offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME;
 198
 199         if (nicvf_mbox_update_hw_max_frs(nic, mtu))
 200                 return -EINVAL;
 201
 202         /* Update max_rx_pkt_len */
 203         rxmode->max_rx_pkt_len = mtu + ETHER_HDR_LEN;
 204         nic->mtu = mtu;
 205
 206         for (i = 0; i < nic->sqs_count; i++)
 207                 nic->snicvf[i]->mtu = mtu;
 208
 209         return 0;
 210 }
 211
 212 static int
 213 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 214 {
 215         uint64_t *data = regs->data;
 216         struct nicvf *nic = nicvf_pmd_priv(dev);
 217
 218         if (data == NULL) {
 219                 regs->length = nicvf_reg_get_count();
 220                 regs->width = THUNDERX_REG_BYTES;
 221                 return 0;
 222         }
 223
 224         /* Support only full register dump */
 225         if ((regs->length == 0) ||
 226                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 227                 regs->version = nic->vendor_id << 16 | nic->device_id;
 228                 nicvf_reg_dump(nic, data);
 229                 return 0;
 230         }
 231         return -ENOTSUP;
 232 }
 233
 234 static int
 235 nicvf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 236 {
 237         uint16_t qidx;
 238         struct nicvf_hw_rx_qstats rx_qstats;
 239         struct nicvf_hw_tx_qstats tx_qstats;
 240         struct nicvf_hw_stats port_stats;
 241         struct nicvf *nic = nicvf_pmd_priv(dev);
 242         uint16_t rx_start, rx_end;
 243         uint16_t tx_start, tx_end;
 244         size_t i;
 245
 246         /* RX queue indices for the first VF */
 247         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 248
 249         /* Reading per RX ring stats */
 250         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 251                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 252                         break;
 253
 254                 nicvf_hw_get_rx_qstats(nic, &rx_qstats, qidx);
 255                 stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 256                 stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 257         }
 258
 259         /* TX queue indices for the first VF */
 260         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 261
 262         /* Reading per TX ring stats */
 263         for (qidx = tx_start; qidx <= tx_end; qidx++) {
 264                 if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 265                         break;
 266
 267                 nicvf_hw_get_tx_qstats(nic, &tx_qstats, qidx);
 268                 stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 269                 stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 270         }
 271
 272         for (i = 0; i < nic->sqs_count; i++) {
 273                 struct nicvf *snic = nic->snicvf[i];
 274
 275                 if (snic == NULL)
 276                         break;
 277
 278                 /* RX queue indices for a secondary VF */
 279                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 280
 281                 /* Reading per RX ring stats */
 282                 for (qidx = rx_start; qidx <= rx_end; qidx++) {
 283                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 284                                 break;
 285
 286                         nicvf_hw_get_rx_qstats(snic, &rx_qstats,
 287                                                qidx % MAX_RCV_QUEUES_PER_QS);
 288                         stats->q_ibytes[qidx] = rx_qstats.q_rx_bytes;
 289                         stats->q_ipackets[qidx] = rx_qstats.q_rx_packets;
 290                 }
 291
 292                 /* TX queue indices for a secondary VF */
 293                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 294                 /* Reading per TX ring stats */
 295                 for (qidx = tx_start; qidx <= tx_end; qidx++) {
 296                         if (qidx >= RTE_ETHDEV_QUEUE_STAT_CNTRS)
 297                                 break;
 298
 299                         nicvf_hw_get_tx_qstats(snic, &tx_qstats,
 300                                                qidx % MAX_SND_QUEUES_PER_QS);
 301                         stats->q_obytes[qidx] = tx_qstats.q_tx_bytes;
 302                         stats->q_opackets[qidx] = tx_qstats.q_tx_packets;
 303                 }
 304         }
 305
 306         nicvf_hw_get_stats(nic, &port_stats);
 307         stats->ibytes = port_stats.rx_bytes;
 308         stats->ipackets = port_stats.rx_ucast_frames;
 309         stats->ipackets += port_stats.rx_bcast_frames;
 310         stats->ipackets += port_stats.rx_mcast_frames;
 311         stats->ierrors = port_stats.rx_l2_errors;
 312         stats->imissed = port_stats.rx_drop_red;
 313         stats->imissed += port_stats.rx_drop_overrun;
 314         stats->imissed += port_stats.rx_drop_bcast;
 315         stats->imissed += port_stats.rx_drop_mcast;
 316         stats->imissed += port_stats.rx_drop_l3_bcast;
 317         stats->imissed += port_stats.rx_drop_l3_mcast;
 318
 319         stats->obytes = port_stats.tx_bytes_ok;
 320         stats->opackets = port_stats.tx_ucast_frames_ok;
 321         stats->opackets += port_stats.tx_bcast_frames_ok;
 322         stats->opackets += port_stats.tx_mcast_frames_ok;
 323         stats->oerrors = port_stats.tx_drops;
 324
 325         return 0;
 326 }
 327
 328 static const uint32_t *
 329 nicvf_dev_supported_ptypes_get(struct rte_eth_dev *dev)
 330 {
 331         size_t copied;
 332         static uint32_t ptypes[32];
 333         struct nicvf *nic = nicvf_pmd_priv(dev);
 334         static const uint32_t ptypes_common[] = {
 335                 RTE_PTYPE_L3_IPV4,
 336                 RTE_PTYPE_L3_IPV4_EXT,
 337                 RTE_PTYPE_L3_IPV6,
 338                 RTE_PTYPE_L3_IPV6_EXT,
 339                 RTE_PTYPE_L4_TCP,
 340                 RTE_PTYPE_L4_UDP,
 341                 RTE_PTYPE_L4_FRAG,
 342         };
 343         static const uint32_t ptypes_tunnel[] = {
 344                 RTE_PTYPE_TUNNEL_GRE,
 345                 RTE_PTYPE_TUNNEL_GENEVE,
 346                 RTE_PTYPE_TUNNEL_VXLAN,
 347                 RTE_PTYPE_TUNNEL_NVGRE,
 348         };
 349         static const uint32_t ptypes_end = RTE_PTYPE_UNKNOWN;
 350
 351         copied = sizeof(ptypes_common);
 352         memcpy(ptypes, ptypes_common, copied);
 353         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 354                 memcpy((char *)ptypes + copied, ptypes_tunnel,
 355                         sizeof(ptypes_tunnel));
 356                 copied += sizeof(ptypes_tunnel);
 357         }
 358
 359         memcpy((char *)ptypes + copied, &ptypes_end, sizeof(ptypes_end));
 360         if (dev->rx_pkt_burst == nicvf_recv_pkts ||
 361                 dev->rx_pkt_burst == nicvf_recv_pkts_multiseg)
 362                 return ptypes;
 363
 364         return NULL;
 365 }
 366
 367 static void
 368 nicvf_dev_stats_reset(struct rte_eth_dev *dev)
 369 {
 370         int i;
 371         uint16_t rxqs = 0, txqs = 0;
 372         struct nicvf *nic = nicvf_pmd_priv(dev);
 373         uint16_t rx_start, rx_end;
 374         uint16_t tx_start, tx_end;
 375
 376         /* Reset all primary nic counters */
 377         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 378         for (i = rx_start; i <= rx_end; i++)
 379                 rxqs |= (0x3 << (i * 2));
 380
 381         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
 382         for (i = tx_start; i <= tx_end; i++)
 383                 txqs |= (0x3 << (i * 2));
 384
 385         nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, rxqs, txqs);
 386
 387         /* Reset secondary nic queue counters */
 388         for (i = 0; i < nic->sqs_count; i++) {
 389                 struct nicvf *snic = nic->snicvf[i];
 390                 if (snic == NULL)
 391                         break;
 392
 393                 nicvf_rx_range(dev, snic, &rx_start, &rx_end);
 394                 for (i = rx_start; i <= rx_end; i++)
 395                         rxqs |= (0x3 << ((i % MAX_CMP_QUEUES_PER_QS) * 2));
 396
 397                 nicvf_tx_range(dev, snic, &tx_start, &tx_end);
 398                 for (i = tx_start; i <= tx_end; i++)
 399                         txqs |= (0x3 << ((i % MAX_SND_QUEUES_PER_QS) * 2));
 400
 401                 nicvf_mbox_reset_stat_counters(snic, 0, 0, rxqs, txqs);
 402         }
 403 }
 404
 405 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 406 static void
 407 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 408 {
 409 }
 410
 411 static inline uint64_t
 412 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 413 {
 414         uint64_t nic_rss = 0;
 415
 416         if (ethdev_rss & ETH_RSS_IPV4)
 417                 nic_rss |= RSS_IP_ENA;
 418
 419         if (ethdev_rss & ETH_RSS_IPV6)
 420                 nic_rss |= RSS_IP_ENA;
 421
 422         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 423                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 424
 425         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 426                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 427
 428         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 429                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 430
 431         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 432                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 433
 434         if (ethdev_rss & ETH_RSS_PORT)
 435                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 436
 437         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 438                 if (ethdev_rss & ETH_RSS_VXLAN)
 439                         nic_rss |= RSS_TUN_VXLAN_ENA;
 440
 441                 if (ethdev_rss & ETH_RSS_GENEVE)
 442                         nic_rss |= RSS_TUN_GENEVE_ENA;
 443
 444                 if (ethdev_rss & ETH_RSS_NVGRE)
 445                         nic_rss |= RSS_TUN_NVGRE_ENA;
 446         }
 447
 448         return nic_rss;
 449 }
 450
 451 static inline uint64_t
 452 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 453 {
 454         uint64_t ethdev_rss = 0;
 455
 456         if (nic_rss & RSS_IP_ENA)
 457                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 458
 459         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 460                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 461                                 ETH_RSS_NONFRAG_IPV6_TCP);
 462
 463         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 464                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 465                                 ETH_RSS_NONFRAG_IPV6_UDP);
 466
 467         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 468                 ethdev_rss |= ETH_RSS_PORT;
 469
 470         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 471                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 472                         ethdev_rss |= ETH_RSS_VXLAN;
 473
 474                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 475                         ethdev_rss |= ETH_RSS_GENEVE;
 476
 477                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 478                         ethdev_rss |= ETH_RSS_NVGRE;
 479         }
 480         return ethdev_rss;
 481 }
 482
 483 static int
 484 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 485                      struct rte_eth_rss_reta_entry64 *reta_conf,
 486                      uint16_t reta_size)
 487 {
 488         struct nicvf *nic = nicvf_pmd_priv(dev);
 489         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 490         int ret, i, j;
 491
 492         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 493                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 494                         "(%d) doesn't match the number hardware can supported "
 495                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 496                 return -EINVAL;
 497         }
 498
 499         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 500         if (ret)
 501                 return ret;
 502
 503         /* Copy RETA table */
 504         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 505                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 506                         if ((reta_conf[i].mask >> j) & 0x01)
 507                                 reta_conf[i].reta[j] = tbl[j];
 508         }
 509
 510         return 0;
 511 }
 512
 513 static int
 514 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 515                       struct rte_eth_rss_reta_entry64 *reta_conf,
 516                       uint16_t reta_size)
 517 {
 518         struct nicvf *nic = nicvf_pmd_priv(dev);
 519         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 520         int ret, i, j;
 521
 522         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 523                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 524                         "(%d) doesn't match the number hardware can supported "
 525                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 526                 return -EINVAL;
 527         }
 528
 529         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 530         if (ret)
 531                 return ret;
 532
 533         /* Copy RETA table */
 534         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 535                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 536                         if ((reta_conf[i].mask >> j) & 0x01)
 537                                 tbl[j] = reta_conf[i].reta[j];
 538         }
 539
 540         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 541 }
 542
 543 static int
 544 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 545                             struct rte_eth_rss_conf *rss_conf)
 546 {
 547         struct nicvf *nic = nicvf_pmd_priv(dev);
 548
 549         if (rss_conf->rss_key)
 550                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 551
 552         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 553         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 554         return 0;
 555 }
 556
 557 static int
 558 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 559                           struct rte_eth_rss_conf *rss_conf)
 560 {
 561         struct nicvf *nic = nicvf_pmd_priv(dev);
 562         uint64_t nic_rss;
 563
 564         if (rss_conf->rss_key &&
 565                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 566                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 567                                 rss_conf->rss_key_len);
 568                 return -EINVAL;
 569         }
 570
 571         if (rss_conf->rss_key)
 572                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 573
 574         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 575         nicvf_rss_set_cfg(nic, nic_rss);
 576         return 0;
 577 }
 578
 579 static int
 580 nicvf_qset_cq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 581                     struct nicvf_rxq *rxq, uint16_t qidx, uint32_t desc_cnt)
 582 {
 583         const struct rte_memzone *rz;
 584         uint32_t ring_size = CMP_QUEUE_SZ_MAX * sizeof(union cq_entry_t);
 585
 586         rz = rte_eth_dma_zone_reserve(dev, "cq_ring",
 587                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 588                                       NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 589         if (rz == NULL) {
 590                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 591                 return -ENOMEM;
 592         }
 593
 594         memset(rz->addr, 0, ring_size);
 595
 596         rxq->phys = rz->iova;
 597         rxq->desc = rz->addr;
 598         rxq->qlen_mask = desc_cnt - 1;
 599
 600         return 0;
 601 }
 602
 603 static int
 604 nicvf_qset_sq_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 605                     struct nicvf_txq *sq, uint16_t qidx, uint32_t desc_cnt)
 606 {
 607         const struct rte_memzone *rz;
 608         uint32_t ring_size = SND_QUEUE_SZ_MAX * sizeof(union sq_entry_t);
 609
 610         rz = rte_eth_dma_zone_reserve(dev, "sq",
 611                                       nicvf_netdev_qidx(nic, qidx), ring_size,
 612                                       NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 613         if (rz == NULL) {
 614                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 615                 return -ENOMEM;
 616         }
 617
 618         memset(rz->addr, 0, ring_size);
 619
 620         sq->phys = rz->iova;
 621         sq->desc = rz->addr;
 622         sq->qlen_mask = desc_cnt - 1;
 623
 624         return 0;
 625 }
 626
 627 static int
 628 nicvf_qset_rbdr_alloc(struct rte_eth_dev *dev, struct nicvf *nic,
 629                       uint32_t desc_cnt, uint32_t buffsz)
 630 {
 631         struct nicvf_rbdr *rbdr;
 632         const struct rte_memzone *rz;
 633         uint32_t ring_size;
 634
 635         assert(nic->rbdr == NULL);
 636         rbdr = rte_zmalloc_socket("rbdr", sizeof(struct nicvf_rbdr),
 637                                   RTE_CACHE_LINE_SIZE, nic->node);
 638         if (rbdr == NULL) {
 639                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr");
 640                 return -ENOMEM;
 641         }
 642
 643         ring_size = sizeof(struct rbdr_entry_t) * RBDR_QUEUE_SZ_MAX;
 644         rz = rte_eth_dma_zone_reserve(dev, "rbdr",
 645                                       nicvf_netdev_qidx(nic, 0), ring_size,
 646                                       NICVF_RBDR_BASE_ALIGN_BYTES, nic->node);
 647         if (rz == NULL) {
 648                 PMD_INIT_LOG(ERR, "Failed to allocate mem for rbdr desc ring");
 649                 return -ENOMEM;
 650         }
 651
 652         memset(rz->addr, 0, ring_size);
 653
 654         rbdr->phys = rz->iova;
 655         rbdr->tail = 0;
 656         rbdr->next_tail = 0;
 657         rbdr->desc = rz->addr;
 658         rbdr->buffsz = buffsz;
 659         rbdr->qlen_mask = desc_cnt - 1;
 660         rbdr->rbdr_status =
 661                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_STATUS0;
 662         rbdr->rbdr_door =
 663                 nicvf_qset_base(nic, 0) + NIC_QSET_RBDR_0_1_DOOR;
 664
 665         nic->rbdr = rbdr;
 666         return 0;
 667 }
 668
 669 static void
 670 nicvf_rbdr_release_mbuf(struct rte_eth_dev *dev, struct nicvf *nic,
 671                         nicvf_iova_addr_t phy)
 672 {
 673         uint16_t qidx;
 674         void *obj;
 675         struct nicvf_rxq *rxq;
 676         uint16_t rx_start, rx_end;
 677
 678         /* Get queue ranges for this VF */
 679         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
 680
 681         for (qidx = rx_start; qidx <= rx_end; qidx++) {
 682                 rxq = dev->data->rx_queues[qidx];
 683                 if (rxq->precharge_cnt) {
 684                         obj = (void *)nicvf_mbuff_phy2virt(phy,
 685                                                            rxq->mbuf_phys_off);
 686                         rte_mempool_put(rxq->pool, obj);
 687                         rxq->precharge_cnt--;
 688                         break;
 689                 }
 690         }
 691 }
 692
 693 static inline void
 694 nicvf_rbdr_release_mbufs(struct rte_eth_dev *dev, struct nicvf *nic)
 695 {
 696         uint32_t qlen_mask, head;
 697         struct rbdr_entry_t *entry;
 698         struct nicvf_rbdr *rbdr = nic->rbdr;
 699
 700         qlen_mask = rbdr->qlen_mask;
 701         head = rbdr->head;
 702         while (head != rbdr->tail) {
 703                 entry = rbdr->desc + head;
 704                 nicvf_rbdr_release_mbuf(dev, nic, entry->full_addr);
 705                 head++;
 706                 head = head & qlen_mask;
 707         }
 708 }
 709
 710 static inline void
 711 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 712 {
 713         uint32_t head;
 714
 715         head = txq->head;
 716         while (head != txq->tail) {
 717                 if (txq->txbuffs[head]) {
 718                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 719                         txq->txbuffs[head] = NULL;
 720                 }
 721                 head++;
 722                 head = head & txq->qlen_mask;
 723         }
 724 }
 725
 726 static void
 727 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 728 {
 729         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 730
 731         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 732         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 733         txq->tail = 0;
 734         txq->head = 0;
 735         txq->xmit_bufs = 0;
 736 }
 737
 738 static inline int
 739 nicvf_vf_start_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 740                         uint16_t qidx)
 741 {
 742         struct nicvf_txq *txq;
 743         int ret;
 744
 745         assert(qidx < MAX_SND_QUEUES_PER_QS);
 746
 747         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 748                 RTE_ETH_QUEUE_STATE_STARTED)
 749                 return 0;
 750
 751         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 752         txq->pool = NULL;
 753         ret = nicvf_qset_sq_config(nic, qidx, txq);
 754         if (ret) {
 755                 PMD_INIT_LOG(ERR, "Failed to configure sq VF%d %d %d",
 756                              nic->vf_id, qidx, ret);
 757                 goto config_sq_error;
 758         }
 759
 760         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 761                 RTE_ETH_QUEUE_STATE_STARTED;
 762         return ret;
 763
 764 config_sq_error:
 765         nicvf_qset_sq_reclaim(nic, qidx);
 766         return ret;
 767 }
 768
 769 static inline int
 770 nicvf_vf_stop_tx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
 771                        uint16_t qidx)
 772 {
 773         struct nicvf_txq *txq;
 774         int ret;
 775
 776         assert(qidx < MAX_SND_QUEUES_PER_QS);
 777
 778         if (dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
 779                 RTE_ETH_QUEUE_STATE_STOPPED)
 780                 return 0;
 781
 782         ret = nicvf_qset_sq_reclaim(nic, qidx);
 783         if (ret)
 784                 PMD_INIT_LOG(ERR, "Failed to reclaim sq VF%d %d %d",
 785                              nic->vf_id, qidx, ret);
 786
 787         txq = dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)];
 788         nicvf_tx_queue_release_mbufs(txq);
 789         nicvf_tx_queue_reset(txq);
 790
 791         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
 792                 RTE_ETH_QUEUE_STATE_STOPPED;
 793         return ret;
 794 }
 795
 796 static inline int
 797 nicvf_configure_cpi(struct rte_eth_dev *dev)
 798 {
 799         struct nicvf *nic = nicvf_pmd_priv(dev);
 800         uint16_t qidx, qcnt;
 801         int ret;
 802
 803         /* Count started rx queues */
 804         for (qidx = qcnt = 0; qidx < dev->data->nb_rx_queues; qidx++)
 805                 if (dev->data->rx_queue_state[qidx] ==
 806                     RTE_ETH_QUEUE_STATE_STARTED)
 807                         qcnt++;
 808
 809         nic->cpi_alg = CPI_ALG_NONE;
 810         ret = nicvf_mbox_config_cpi(nic, qcnt);
 811         if (ret)
 812                 PMD_INIT_LOG(ERR, "Failed to configure CPI %d", ret);
 813
 814         return ret;
 815 }
 816
 817 static inline int
 818 nicvf_configure_rss(struct rte_eth_dev *dev)
 819 {
 820         struct nicvf *nic = nicvf_pmd_priv(dev);
 821         uint64_t rsshf;
 822         int ret = -EINVAL;
 823
 824         rsshf = nicvf_rss_ethdev_to_nic(nic,
 825                         dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf);
 826         PMD_DRV_LOG(INFO, "mode=%d rx_queues=%d loopback=%d rsshf=0x%" PRIx64,
 827                     dev->data->dev_conf.rxmode.mq_mode,
 828                     dev->data->nb_rx_queues,
 829                     dev->data->dev_conf.lpbk_mode, rsshf);
 830
 831         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_NONE)
 832                 ret = nicvf_rss_term(nic);
 833         else if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_RSS)
 834                 ret = nicvf_rss_config(nic, dev->data->nb_rx_queues, rsshf);
 835         if (ret)
 836                 PMD_INIT_LOG(ERR, "Failed to configure RSS %d", ret);
 837
 838         return ret;
 839 }
 840
 841 static int
 842 nicvf_configure_rss_reta(struct rte_eth_dev *dev)
 843 {
 844         struct nicvf *nic = nicvf_pmd_priv(dev);
 845         unsigned int idx, qmap_size;
 846         uint8_t qmap[RTE_MAX_QUEUES_PER_PORT];
 847         uint8_t default_reta[NIC_MAX_RSS_IDR_TBL_SIZE];
 848
 849         if (nic->cpi_alg != CPI_ALG_NONE)
 850                 return -EINVAL;
 851
 852         /* Prepare queue map */
 853         for (idx = 0, qmap_size = 0; idx < dev->data->nb_rx_queues; idx++) {
 854                 if (dev->data->rx_queue_state[idx] ==
 855                                 RTE_ETH_QUEUE_STATE_STARTED)
 856                         qmap[qmap_size++] = idx;
 857         }
 858
 859         /* Update default RSS RETA */
 860         for (idx = 0; idx < NIC_MAX_RSS_IDR_TBL_SIZE; idx++)
 861                 default_reta[idx] = qmap[idx % qmap_size];
 862
 863         return nicvf_rss_reta_update(nic, default_reta,
 864                                      NIC_MAX_RSS_IDR_TBL_SIZE);
 865 }
 866
 867 static void
 868 nicvf_dev_tx_queue_release(void *sq)
 869 {
 870         struct nicvf_txq *txq;
 871
 872         PMD_INIT_FUNC_TRACE();
 873
 874         txq = (struct nicvf_txq *)sq;
 875         if (txq) {
 876                 if (txq->txbuffs != NULL) {
 877                         nicvf_tx_queue_release_mbufs(txq);
 878                         rte_free(txq->txbuffs);
 879                         txq->txbuffs = NULL;
 880                 }
 881                 rte_free(txq);
 882         }
 883 }
 884
 885 static void
 886 nicvf_set_tx_function(struct rte_eth_dev *dev)
 887 {
 888         struct nicvf_txq *txq;
 889         size_t i;
 890         bool multiseg = false;
 891
 892         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 893                 txq = dev->data->tx_queues[i];
 894                 if (txq->offloads & DEV_TX_OFFLOAD_MULTI_SEGS) {
 895                         multiseg = true;
 896                         break;
 897                 }
 898         }
 899
 900         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
 901         if (multiseg) {
 902                 PMD_DRV_LOG(DEBUG, "Using multi-segment tx callback");
 903                 dev->tx_pkt_burst = nicvf_xmit_pkts_multiseg;
 904         } else {
 905                 PMD_DRV_LOG(DEBUG, "Using single-segment tx callback");
 906                 dev->tx_pkt_burst = nicvf_xmit_pkts;
 907         }
 908
 909         if (txq->pool_free == nicvf_single_pool_free_xmited_buffers)
 910                 PMD_DRV_LOG(DEBUG, "Using single-mempool tx free method");
 911         else
 912                 PMD_DRV_LOG(DEBUG, "Using multi-mempool tx free method");
 913 }
 914
 915 static void
 916 nicvf_set_rx_function(struct rte_eth_dev *dev)
 917 {
 918         if (dev->data->scattered_rx) {
 919                 PMD_DRV_LOG(DEBUG, "Using multi-segment rx callback");
 920                 dev->rx_pkt_burst = nicvf_recv_pkts_multiseg;
 921         } else {
 922                 PMD_DRV_LOG(DEBUG, "Using single-segment rx callback");
 923                 dev->rx_pkt_burst = nicvf_recv_pkts;
 924         }
 925 }
 926
 927 static int
 928 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 929                          uint16_t nb_desc, unsigned int socket_id,
 930                          const struct rte_eth_txconf *tx_conf)
 931 {
 932         uint16_t tx_free_thresh;
 933         bool is_single_pool;
 934         struct nicvf_txq *txq;
 935         struct nicvf *nic = nicvf_pmd_priv(dev);
 936         uint64_t offloads;
 937
 938         PMD_INIT_FUNC_TRACE();
 939
 940         if (qidx >= MAX_SND_QUEUES_PER_QS)
 941                 nic = nic->snicvf[qidx / MAX_SND_QUEUES_PER_QS - 1];
 942
 943         qidx = qidx % MAX_SND_QUEUES_PER_QS;
 944
 945         /* Socket id check */
 946         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 947                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 948                 socket_id, nic->node);
 949
 950         /* Tx deferred start is not supported */
 951         if (tx_conf->tx_deferred_start) {
 952                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 953                 return -EINVAL;
 954         }
 955
 956         /* Roundup nb_desc to available qsize and validate max number of desc */
 957         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 958         if (nb_desc == 0) {
 959                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 960                 return -EINVAL;
 961         }
 962
 963         /* Validate tx_free_thresh */
 964         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 965                                 tx_conf->tx_free_thresh :
 966                                 NICVF_DEFAULT_TX_FREE_THRESH);
 967
 968         if (tx_free_thresh > (nb_desc) ||
 969                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 970                 PMD_INIT_LOG(ERR,
 971                         "tx_free_thresh must be less than the number of TX "
 972                         "descriptors. (tx_free_thresh=%u port=%d "
 973                         "queue=%d)", (unsigned int)tx_free_thresh,
 974                         (int)dev->data->port_id, (int)qidx);
 975                 return -EINVAL;
 976         }
 977
 978         /* Free memory prior to re-allocation if needed. */
 979         if (dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
 980                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 981                                 nicvf_netdev_qidx(nic, qidx));
 982                 nicvf_dev_tx_queue_release(
 983                         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)]);
 984                 dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
 985         }
 986
 987         /* Allocating tx queue data structure */
 988         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 989                                         RTE_CACHE_LINE_SIZE, nic->node);
 990         if (txq == NULL) {
 991                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d",
 992                              nicvf_netdev_qidx(nic, qidx));
 993                 return -ENOMEM;
 994         }
 995
 996         txq->nic = nic;
 997         txq->queue_id = qidx;
 998         txq->tx_free_thresh = tx_free_thresh;
 999         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
1000         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
1001         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
1002         txq->offloads = offloads;
1003
1004         is_single_pool = !!(offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE);
1005
1006         /* Choose optimum free threshold value for multipool case */
1007         if (!is_single_pool) {
1008                 txq->tx_free_thresh = (uint16_t)
1009                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
1010                                 NICVF_TX_FREE_MPOOL_THRESH :
1011                                 tx_conf->tx_free_thresh);
1012                 txq->pool_free = nicvf_multi_pool_free_xmited_buffers;
1013         } else {
1014                 txq->pool_free = nicvf_single_pool_free_xmited_buffers;
1015         }
1016
1017         /* Allocate software ring */
1018         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
1019                                 nb_desc * sizeof(struct rte_mbuf *),
1020                                 RTE_CACHE_LINE_SIZE, nic->node);
1021
1022         if (txq->txbuffs == NULL) {
1023                 nicvf_dev_tx_queue_release(txq);
1024                 return -ENOMEM;
1025         }
1026
1027         if (nicvf_qset_sq_alloc(dev, nic, txq, qidx, nb_desc)) {
1028                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
1029                 nicvf_dev_tx_queue_release(txq);
1030                 return -ENOMEM;
1031         }
1032
1033         nicvf_tx_queue_reset(txq);
1034
1035         PMD_INIT_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p"
1036                         " phys=0x%" PRIx64 " offloads=0x%" PRIx64,
1037                         nicvf_netdev_qidx(nic, qidx), txq, nb_desc, txq->desc,
1038                         txq->phys, txq->offloads);
1039
1040         dev->data->tx_queues[nicvf_netdev_qidx(nic, qidx)] = txq;
1041         dev->data->tx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1042                 RTE_ETH_QUEUE_STATE_STOPPED;
1043         return 0;
1044 }
1045
1046 static inline void
1047 nicvf_rx_queue_release_mbufs(struct rte_eth_dev *dev, struct nicvf_rxq *rxq)
1048 {
1049         uint32_t rxq_cnt;
1050         uint32_t nb_pkts, released_pkts = 0;
1051         uint32_t refill_cnt = 0;
1052         struct rte_mbuf *rx_pkts[NICVF_MAX_RX_FREE_THRESH];
1053
1054         if (dev->rx_pkt_burst == NULL)
1055                 return;
1056
1057         while ((rxq_cnt = nicvf_dev_rx_queue_count(dev,
1058                                 nicvf_netdev_qidx(rxq->nic, rxq->queue_id)))) {
1059                 nb_pkts = dev->rx_pkt_burst(rxq, rx_pkts,
1060                                         NICVF_MAX_RX_FREE_THRESH);
1061                 PMD_DRV_LOG(INFO, "nb_pkts=%d  rxq_cnt=%d", nb_pkts, rxq_cnt);
1062                 while (nb_pkts) {
1063                         rte_pktmbuf_free_seg(rx_pkts[--nb_pkts]);
1064                         released_pkts++;
1065                 }
1066         }
1067
1068
1069         refill_cnt += nicvf_dev_rbdr_refill(dev,
1070                         nicvf_netdev_qidx(rxq->nic, rxq->queue_id));
1071
1072         PMD_DRV_LOG(INFO, "free_cnt=%d  refill_cnt=%d",
1073                     released_pkts, refill_cnt);
1074 }
1075
1076 static void
1077 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
1078 {
1079         rxq->head = 0;
1080         rxq->available_space = 0;
1081         rxq->recv_buffers = 0;
1082 }
1083
1084 static inline int
1085 nicvf_vf_start_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1086                         uint16_t qidx)
1087 {
1088         struct nicvf_rxq *rxq;
1089         int ret;
1090
1091         assert(qidx < MAX_RCV_QUEUES_PER_QS);
1092
1093         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1094                 RTE_ETH_QUEUE_STATE_STARTED)
1095                 return 0;
1096
1097         /* Update rbdr pointer to all rxq */
1098         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1099         rxq->shared_rbdr = nic->rbdr;
1100
1101         ret = nicvf_qset_rq_config(nic, qidx, rxq);
1102         if (ret) {
1103                 PMD_INIT_LOG(ERR, "Failed to configure rq VF%d %d %d",
1104                              nic->vf_id, qidx, ret);
1105                 goto config_rq_error;
1106         }
1107         ret = nicvf_qset_cq_config(nic, qidx, rxq);
1108         if (ret) {
1109                 PMD_INIT_LOG(ERR, "Failed to configure cq VF%d %d %d",
1110                              nic->vf_id, qidx, ret);
1111                 goto config_cq_error;
1112         }
1113
1114         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1115                 RTE_ETH_QUEUE_STATE_STARTED;
1116         return 0;
1117
1118 config_cq_error:
1119         nicvf_qset_cq_reclaim(nic, qidx);
1120 config_rq_error:
1121         nicvf_qset_rq_reclaim(nic, qidx);
1122         return ret;
1123 }
1124
1125 static inline int
1126 nicvf_vf_stop_rx_queue(struct rte_eth_dev *dev, struct nicvf *nic,
1127                        uint16_t qidx)
1128 {
1129         struct nicvf_rxq *rxq;
1130         int ret, other_error;
1131
1132         if (dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] ==
1133                 RTE_ETH_QUEUE_STATE_STOPPED)
1134                 return 0;
1135
1136         ret = nicvf_qset_rq_reclaim(nic, qidx);
1137         if (ret)
1138                 PMD_INIT_LOG(ERR, "Failed to reclaim rq VF%d %d %d",
1139                              nic->vf_id, qidx, ret);
1140
1141         other_error = ret;
1142         rxq = dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)];
1143         nicvf_rx_queue_release_mbufs(dev, rxq);
1144         nicvf_rx_queue_reset(rxq);
1145
1146         ret = nicvf_qset_cq_reclaim(nic, qidx);
1147         if (ret)
1148                 PMD_INIT_LOG(ERR, "Failed to reclaim cq VF%d %d %d",
1149                              nic->vf_id, qidx, ret);
1150
1151         other_error |= ret;
1152         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1153                 RTE_ETH_QUEUE_STATE_STOPPED;
1154         return other_error;
1155 }
1156
1157 static void
1158 nicvf_dev_rx_queue_release(void *rx_queue)
1159 {
1160         PMD_INIT_FUNC_TRACE();
1161
1162         rte_free(rx_queue);
1163 }
1164
1165 static int
1166 nicvf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1167 {
1168         struct nicvf *nic = nicvf_pmd_priv(dev);
1169         int ret;
1170
1171         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1172                 nic = nic->snicvf[(qidx / MAX_RCV_QUEUES_PER_QS - 1)];
1173
1174         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1175
1176         ret = nicvf_vf_start_rx_queue(dev, nic, qidx);
1177         if (ret)
1178                 return ret;
1179
1180         ret = nicvf_configure_cpi(dev);
1181         if (ret)
1182                 return ret;
1183
1184         return nicvf_configure_rss_reta(dev);
1185 }
1186
1187 static int
1188 nicvf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1189 {
1190         int ret;
1191         struct nicvf *nic = nicvf_pmd_priv(dev);
1192
1193         if (qidx >= MAX_SND_QUEUES_PER_QS)
1194                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1195
1196         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1197
1198         ret = nicvf_vf_stop_rx_queue(dev, nic, qidx);
1199         ret |= nicvf_configure_cpi(dev);
1200         ret |= nicvf_configure_rss_reta(dev);
1201         return ret;
1202 }
1203
1204 static int
1205 nicvf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t qidx)
1206 {
1207         struct nicvf *nic = nicvf_pmd_priv(dev);
1208
1209         if (qidx >= MAX_SND_QUEUES_PER_QS)
1210                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1211
1212         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1213
1214         return nicvf_vf_start_tx_queue(dev, nic, qidx);
1215 }
1216
1217 static int
1218 nicvf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t qidx)
1219 {
1220         struct nicvf *nic = nicvf_pmd_priv(dev);
1221
1222         if (qidx >= MAX_SND_QUEUES_PER_QS)
1223                 nic = nic->snicvf[(qidx / MAX_SND_QUEUES_PER_QS - 1)];
1224
1225         qidx = qidx % MAX_SND_QUEUES_PER_QS;
1226
1227         return nicvf_vf_stop_tx_queue(dev, nic, qidx);
1228 }
1229
1230 static inline void
1231 nicvf_rxq_mbuf_setup(struct nicvf_rxq *rxq)
1232 {
1233         uintptr_t p;
1234         struct rte_mbuf mb_def;
1235         struct nicvf *nic = rxq->nic;
1236
1237         RTE_BUILD_BUG_ON(sizeof(union mbuf_initializer) != 8);
1238         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_off) % 8 != 0);
1239         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, refcnt) -
1240                                 offsetof(struct rte_mbuf, data_off) != 2);
1241         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, nb_segs) -
1242                                 offsetof(struct rte_mbuf, data_off) != 4);
1243         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, port) -
1244                                 offsetof(struct rte_mbuf, data_off) != 6);
1245         mb_def.nb_segs = 1;
1246         mb_def.data_off = RTE_PKTMBUF_HEADROOM + (nic->skip_bytes);
1247         mb_def.port = rxq->port_id;
1248         rte_mbuf_refcnt_set(&mb_def, 1);
1249
1250         /* Prevent compiler reordering: rearm_data covers previous fields */
1251         rte_compiler_barrier();
1252         p = (uintptr_t)&mb_def.rearm_data;
1253         rxq->mbuf_initializer.value = *(uint64_t *)p;
1254 }
1255
1256 static int
1257 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
1258                          uint16_t nb_desc, unsigned int socket_id,
1259                          const struct rte_eth_rxconf *rx_conf,
1260                          struct rte_mempool *mp)
1261 {
1262         uint16_t rx_free_thresh;
1263         struct nicvf_rxq *rxq;
1264         struct nicvf *nic = nicvf_pmd_priv(dev);
1265         uint64_t offloads;
1266         uint32_t buffsz;
1267         struct rte_pktmbuf_pool_private *mbp_priv;
1268
1269         PMD_INIT_FUNC_TRACE();
1270
1271         /* First skip check */
1272         mbp_priv = rte_mempool_get_priv(mp);
1273         buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1274         if (buffsz < (uint32_t)(nic->skip_bytes)) {
1275                 PMD_INIT_LOG(ERR, "First skip is more than configured buffer size");
1276                 return -EINVAL;
1277         }
1278
1279         if (qidx >= MAX_RCV_QUEUES_PER_QS)
1280                 nic = nic->snicvf[qidx / MAX_RCV_QUEUES_PER_QS - 1];
1281
1282         qidx = qidx % MAX_RCV_QUEUES_PER_QS;
1283
1284         /* Socket id check */
1285         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
1286                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
1287                 socket_id, nic->node);
1288
1289         /* Mempool memory must be contiguous, so must be one memory segment*/
1290         if (mp->nb_mem_chunks != 1) {
1291                 PMD_INIT_LOG(ERR, "Non-contiguous mempool, add more huge pages");
1292                 return -EINVAL;
1293         }
1294
1295         /* Mempool memory must be physically contiguous */
1296         if (mp->flags & MEMPOOL_F_NO_IOVA_CONTIG) {
1297                 PMD_INIT_LOG(ERR, "Mempool memory must be physically contiguous");
1298                 return -EINVAL;
1299         }
1300
1301         /* Rx deferred start is not supported */
1302         if (rx_conf->rx_deferred_start) {
1303                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
1304                 return -EINVAL;
1305         }
1306
1307         /* Roundup nb_desc to available qsize and validate max number of desc */
1308         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
1309         if (nb_desc == 0) {
1310                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
1311                 return -EINVAL;
1312         }
1313
1314
1315         /* Check rx_free_thresh upper bound */
1316         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
1317                                 rx_conf->rx_free_thresh :
1318                                 NICVF_DEFAULT_RX_FREE_THRESH);
1319         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
1320                 rx_free_thresh >= nb_desc * .75) {
1321                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
1322                                 rx_free_thresh);
1323                 return -EINVAL;
1324         }
1325
1326         /* Free memory prior to re-allocation if needed */
1327         if (dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] != NULL) {
1328                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
1329                                 nicvf_netdev_qidx(nic, qidx));
1330                 nicvf_dev_rx_queue_release(
1331                         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)]);
1332                 dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = NULL;
1333         }
1334
1335         /* Allocate rxq memory */
1336         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
1337                                         RTE_CACHE_LINE_SIZE, nic->node);
1338         if (rxq == NULL) {
1339                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d",
1340                              nicvf_netdev_qidx(nic, qidx));
1341                 return -ENOMEM;
1342         }
1343
1344         rxq->nic = nic;
1345         rxq->pool = mp;
1346         rxq->queue_id = qidx;
1347         rxq->port_id = dev->data->port_id;
1348         rxq->rx_free_thresh = rx_free_thresh;
1349         rxq->rx_drop_en = rx_conf->rx_drop_en;
1350         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
1351         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
1352         rxq->precharge_cnt = 0;
1353
1354         if (nicvf_hw_cap(nic) & NICVF_CAP_CQE_RX2)
1355                 rxq->rbptr_offset = NICVF_CQE_RX2_RBPTR_WORD;
1356         else
1357                 rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
1358
1359         nicvf_rxq_mbuf_setup(rxq);
1360
1361         /* Alloc completion queue */
1362         if (nicvf_qset_cq_alloc(dev, nic, rxq, rxq->queue_id, nb_desc)) {
1363                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
1364                 nicvf_dev_rx_queue_release(rxq);
1365                 return -ENOMEM;
1366         }
1367
1368         nicvf_rx_queue_reset(rxq);
1369
1370         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1371         PMD_INIT_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d)"
1372                         " phy=0x%" PRIx64 " offloads=0x%" PRIx64,
1373                         nicvf_netdev_qidx(nic, qidx), rxq, mp->name, nb_desc,
1374                         rte_mempool_avail_count(mp), rxq->phys, offloads);
1375
1376         dev->data->rx_queues[nicvf_netdev_qidx(nic, qidx)] = rxq;
1377         dev->data->rx_queue_state[nicvf_netdev_qidx(nic, qidx)] =
1378                 RTE_ETH_QUEUE_STATE_STOPPED;
1379         return 0;
1380 }
1381
1382 static void
1383 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1384 {
1385         struct nicvf *nic = nicvf_pmd_priv(dev);
1386         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1387
1388         PMD_INIT_FUNC_TRACE();
1389
1390         /* Autonegotiation may be disabled */
1391         dev_info->speed_capa = ETH_LINK_SPEED_FIXED;
1392         dev_info->speed_capa |= ETH_LINK_SPEED_10M | ETH_LINK_SPEED_100M |
1393                                  ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
1394         if (nicvf_hw_version(nic) != PCI_SUB_DEVICE_ID_CN81XX_NICVF)
1395                 dev_info->speed_capa |= ETH_LINK_SPEED_40G;
1396
1397         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
1398         dev_info->max_rx_pktlen = NIC_HW_MAX_MTU + ETHER_HDR_LEN;
1399         dev_info->max_rx_queues =
1400                         (uint16_t)MAX_RCV_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1401         dev_info->max_tx_queues =
1402                         (uint16_t)MAX_SND_QUEUES_PER_QS * (MAX_SQS_PER_VF + 1);
1403         dev_info->max_mac_addrs = 1;
1404         dev_info->max_vfs = pci_dev->max_vfs;
1405
1406         dev_info->rx_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1407         dev_info->tx_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1408         dev_info->rx_queue_offload_capa = NICVF_RX_OFFLOAD_CAPA;
1409         dev_info->tx_queue_offload_capa = NICVF_TX_OFFLOAD_CAPA;
1410
1411         dev_info->reta_size = nic->rss_info.rss_size;
1412         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
1413         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
1414         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
1415                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
1416
1417         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1418                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
1419                 .rx_drop_en = 0,
1420                 .offloads = DEV_RX_OFFLOAD_CRC_STRIP,
1421         };
1422
1423         dev_info->default_txconf = (struct rte_eth_txconf) {
1424                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
1425                 .offloads = DEV_TX_OFFLOAD_MBUF_FAST_FREE |
1426                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM   |
1427                         DEV_TX_OFFLOAD_UDP_CKSUM          |
1428                         DEV_TX_OFFLOAD_TCP_CKSUM,
1429         };
1430 }
1431
1432 static nicvf_iova_addr_t
1433 rbdr_rte_mempool_get(void *dev, void *opaque)
1434 {
1435         uint16_t qidx;
1436         uintptr_t mbuf;
1437         struct nicvf_rxq *rxq;
1438         struct rte_eth_dev *eth_dev = (struct rte_eth_dev *)dev;
1439         struct nicvf *nic = (struct nicvf *)opaque;
1440         uint16_t rx_start, rx_end;
1441
1442         /* Get queue ranges for this VF */
1443         nicvf_rx_range(eth_dev, nic, &rx_start, &rx_end);
1444
1445         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1446                 rxq = eth_dev->data->rx_queues[qidx];
1447                 /* Maintain equal buffer count across all pools */
1448                 if (rxq->precharge_cnt >= rxq->qlen_mask)
1449                         continue;
1450                 rxq->precharge_cnt++;
1451                 mbuf = (uintptr_t)rte_pktmbuf_alloc(rxq->pool);
1452                 if (mbuf)
1453                         return nicvf_mbuff_virt2phy(mbuf, rxq->mbuf_phys_off);
1454         }
1455         return 0;
1456 }
1457
1458 static int
1459 nicvf_vf_start(struct rte_eth_dev *dev, struct nicvf *nic, uint32_t rbdrsz)
1460 {
1461         int ret;
1462         uint16_t qidx, data_off;
1463         uint32_t total_rxq_desc, nb_rbdr_desc, exp_buffs;
1464         uint64_t mbuf_phys_off = 0;
1465         struct nicvf_rxq *rxq;
1466         struct rte_mbuf *mbuf;
1467         uint16_t rx_start, rx_end;
1468         uint16_t tx_start, tx_end;
1469         bool vlan_strip;
1470
1471         PMD_INIT_FUNC_TRACE();
1472
1473         /* Userspace process exited without proper shutdown in last run */
1474         if (nicvf_qset_rbdr_active(nic, 0))
1475                 nicvf_vf_stop(dev, nic, false);
1476
1477         /* Get queue ranges for this VF */
1478         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1479
1480         /*
1481          * Thunderx nicvf PMD can support more than one pool per port only when
1482          * 1) Data payload size is same across all the pools in given port
1483          * AND
1484          * 2) All mbuffs in the pools are from the same hugepage
1485          * AND
1486          * 3) Mbuff metadata size is same across all the pools in given port
1487          *
1488          * This is to support existing application that uses multiple pool/port.
1489          * But, the purpose of using multipool for QoS will not be addressed.
1490          *
1491          */
1492
1493         /* Validate mempool attributes */
1494         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1495                 rxq = dev->data->rx_queues[qidx];
1496                 rxq->mbuf_phys_off = nicvf_mempool_phy_offset(rxq->pool);
1497                 mbuf = rte_pktmbuf_alloc(rxq->pool);
1498                 if (mbuf == NULL) {
1499                         PMD_INIT_LOG(ERR, "Failed allocate mbuf VF%d qid=%d "
1500                                      "pool=%s",
1501                                      nic->vf_id, qidx, rxq->pool->name);
1502                         return -ENOMEM;
1503                 }
1504                 data_off = nicvf_mbuff_meta_length(mbuf);
1505                 data_off += RTE_PKTMBUF_HEADROOM;
1506                 rte_pktmbuf_free(mbuf);
1507
1508                 if (data_off % RTE_CACHE_LINE_SIZE) {
1509                         PMD_INIT_LOG(ERR, "%s: unaligned data_off=%d delta=%d",
1510                                 rxq->pool->name, data_off,
1511                                 data_off % RTE_CACHE_LINE_SIZE);
1512                         return -EINVAL;
1513                 }
1514                 rxq->mbuf_phys_off -= data_off;
1515                 rxq->mbuf_phys_off -= nic->skip_bytes;
1516
1517                 if (mbuf_phys_off == 0)
1518                         mbuf_phys_off = rxq->mbuf_phys_off;
1519                 if (mbuf_phys_off != rxq->mbuf_phys_off) {
1520                         PMD_INIT_LOG(ERR, "pool params not same,%s VF%d %"
1521                                      PRIx64, rxq->pool->name, nic->vf_id,
1522                                      mbuf_phys_off);
1523                         return -EINVAL;
1524                 }
1525         }
1526
1527         /* Check the level of buffers in the pool */
1528         total_rxq_desc = 0;
1529         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1530                 rxq = dev->data->rx_queues[qidx];
1531                 /* Count total numbers of rxq descs */
1532                 total_rxq_desc += rxq->qlen_mask + 1;
1533                 exp_buffs = RTE_MEMPOOL_CACHE_MAX_SIZE + rxq->rx_free_thresh;
1534                 exp_buffs *= dev->data->nb_rx_queues;
1535                 if (rte_mempool_avail_count(rxq->pool) < exp_buffs) {
1536                         PMD_INIT_LOG(ERR, "Buff shortage in pool=%s (%d/%d)",
1537                                      rxq->pool->name,
1538                                      rte_mempool_avail_count(rxq->pool),
1539                                      exp_buffs);
1540                         return -ENOENT;
1541                 }
1542         }
1543
1544         /* Check RBDR desc overflow */
1545         ret = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1546         if (ret == 0) {
1547                 PMD_INIT_LOG(ERR, "Reached RBDR desc limit, reduce nr desc "
1548                              "VF%d", nic->vf_id);
1549                 return -ENOMEM;
1550         }
1551
1552         /* Enable qset */
1553         ret = nicvf_qset_config(nic);
1554         if (ret) {
1555                 PMD_INIT_LOG(ERR, "Failed to enable qset %d VF%d", ret,
1556                              nic->vf_id);
1557                 return ret;
1558         }
1559
1560         /* Allocate RBDR and RBDR ring desc */
1561         nb_rbdr_desc = nicvf_qsize_rbdr_roundup(total_rxq_desc);
1562         ret = nicvf_qset_rbdr_alloc(dev, nic, nb_rbdr_desc, rbdrsz);
1563         if (ret) {
1564                 PMD_INIT_LOG(ERR, "Failed to allocate memory for rbdr alloc "
1565                              "VF%d", nic->vf_id);
1566                 goto qset_reclaim;
1567         }
1568
1569         /* Enable and configure RBDR registers */
1570         ret = nicvf_qset_rbdr_config(nic, 0);
1571         if (ret) {
1572                 PMD_INIT_LOG(ERR, "Failed to configure rbdr %d VF%d", ret,
1573                              nic->vf_id);
1574                 goto qset_rbdr_free;
1575         }
1576
1577         /* Fill rte_mempool buffers in RBDR pool and precharge it */
1578         ret = nicvf_qset_rbdr_precharge(dev, nic, 0, rbdr_rte_mempool_get,
1579                                         total_rxq_desc);
1580         if (ret) {
1581                 PMD_INIT_LOG(ERR, "Failed to fill rbdr %d VF%d", ret,
1582                              nic->vf_id);
1583                 goto qset_rbdr_reclaim;
1584         }
1585
1586         PMD_DRV_LOG(INFO, "Filled %d out of %d entries in RBDR VF%d",
1587                      nic->rbdr->tail, nb_rbdr_desc, nic->vf_id);
1588
1589         /* Configure VLAN Strip */
1590         vlan_strip = !!(dev->data->dev_conf.rxmode.offloads &
1591                         DEV_RX_OFFLOAD_VLAN_STRIP);
1592         nicvf_vlan_hw_strip(nic, vlan_strip);
1593
1594         /* Based on the packet type(IPv4 or IPv6), the nicvf HW aligns L3 data
1595          * to the 64bit memory address.
1596          * The alignment creates a hole in mbuf(between the end of headroom and
1597          * packet data start). The new revision of the HW provides an option to
1598          * disable the L3 alignment feature and make mbuf layout looks
1599          * more like other NICs. For better application compatibility, disabling
1600          * l3 alignment feature on the hardware revisions it supports
1601          */
1602         nicvf_apad_config(nic, false);
1603
1604         /* Get queue ranges for this VF */
1605         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1606
1607         /* Configure TX queues */
1608         for (qidx = tx_start; qidx <= tx_end; qidx++) {
1609                 ret = nicvf_vf_start_tx_queue(dev, nic,
1610                         qidx % MAX_SND_QUEUES_PER_QS);
1611                 if (ret)
1612                         goto start_txq_error;
1613         }
1614
1615         /* Configure RX queues */
1616         for (qidx = rx_start; qidx <= rx_end; qidx++) {
1617                 ret = nicvf_vf_start_rx_queue(dev, nic,
1618                         qidx % MAX_RCV_QUEUES_PER_QS);
1619                 if (ret)
1620                         goto start_rxq_error;
1621         }
1622
1623         if (!nic->sqs_mode) {
1624                 /* Configure CPI algorithm */
1625                 ret = nicvf_configure_cpi(dev);
1626                 if (ret)
1627                         goto start_txq_error;
1628
1629                 ret = nicvf_mbox_get_rss_size(nic);
1630                 if (ret) {
1631                         PMD_INIT_LOG(ERR, "Failed to get rss table size");
1632                         goto qset_rss_error;
1633                 }
1634
1635                 /* Configure RSS */
1636                 ret = nicvf_configure_rss(dev);
1637                 if (ret)
1638                         goto qset_rss_error;
1639         }
1640
1641         /* Done; Let PF make the BGX's RX and TX switches to ON position */
1642         nicvf_mbox_cfg_done(nic);
1643         return 0;
1644
1645 qset_rss_error:
1646         nicvf_rss_term(nic);
1647 start_rxq_error:
1648         for (qidx = rx_start; qidx <= rx_end; qidx++)
1649                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1650 start_txq_error:
1651         for (qidx = tx_start; qidx <= tx_end; qidx++)
1652                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1653 qset_rbdr_reclaim:
1654         nicvf_qset_rbdr_reclaim(nic, 0);
1655         nicvf_rbdr_release_mbufs(dev, nic);
1656 qset_rbdr_free:
1657         if (nic->rbdr) {
1658                 rte_free(nic->rbdr);
1659                 nic->rbdr = NULL;
1660         }
1661 qset_reclaim:
1662         nicvf_qset_reclaim(nic);
1663         return ret;
1664 }
1665
1666 static int
1667 nicvf_dev_start(struct rte_eth_dev *dev)
1668 {
1669         uint16_t qidx;
1670         int ret;
1671         size_t i;
1672         struct nicvf *nic = nicvf_pmd_priv(dev);
1673         struct rte_eth_rxmode *rx_conf = &dev->data->dev_conf.rxmode;
1674         uint16_t mtu;
1675         uint32_t buffsz = 0, rbdrsz = 0;
1676         struct rte_pktmbuf_pool_private *mbp_priv;
1677         struct nicvf_rxq *rxq;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         /* This function must be called for a primary device */
1682         assert_primary(nic);
1683
1684         /* Validate RBDR buff size */
1685         for (qidx = 0; qidx < dev->data->nb_rx_queues; qidx++) {
1686                 rxq = dev->data->rx_queues[qidx];
1687                 mbp_priv = rte_mempool_get_priv(rxq->pool);
1688                 buffsz = mbp_priv->mbuf_data_room_size - RTE_PKTMBUF_HEADROOM;
1689                 if (buffsz % 128) {
1690                         PMD_INIT_LOG(ERR, "rxbuf size must be multiply of 128");
1691                         return -EINVAL;
1692                 }
1693                 if (rbdrsz == 0)
1694                         rbdrsz = buffsz;
1695                 if (rbdrsz != buffsz) {
1696                         PMD_INIT_LOG(ERR, "buffsz not same, qidx=%d (%d/%d)",
1697                                      qidx, rbdrsz, buffsz);
1698                         return -EINVAL;
1699                 }
1700         }
1701
1702         /* Configure loopback */
1703         ret = nicvf_loopback_config(nic, dev->data->dev_conf.lpbk_mode);
1704         if (ret) {
1705                 PMD_INIT_LOG(ERR, "Failed to configure loopback %d", ret);
1706                 return ret;
1707         }
1708
1709         /* Reset all statistics counters attached to this port */
1710         ret = nicvf_mbox_reset_stat_counters(nic, 0x3FFF, 0x1F, 0xFFFF, 0xFFFF);
1711         if (ret) {
1712                 PMD_INIT_LOG(ERR, "Failed to reset stat counters %d", ret);
1713                 return ret;
1714         }
1715
1716         /* Setup scatter mode if needed by jumbo */
1717         if (dev->data->dev_conf.rxmode.max_rx_pkt_len +
1718                                             2 * VLAN_TAG_SIZE > buffsz)
1719                 dev->data->scattered_rx = 1;
1720         if ((rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) != 0)
1721                 dev->data->scattered_rx = 1;
1722
1723         /* Setup MTU based on max_rx_pkt_len or default */
1724         mtu = dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME ?
1725                 dev->data->dev_conf.rxmode.max_rx_pkt_len
1726                         -  ETHER_HDR_LEN : ETHER_MTU;
1727
1728         if (nicvf_dev_set_mtu(dev, mtu)) {
1729                 PMD_INIT_LOG(ERR, "Failed to set default mtu size");
1730                 return -EBUSY;
1731         }
1732
1733         ret = nicvf_vf_start(dev, nic, rbdrsz);
1734         if (ret != 0)
1735                 return ret;
1736
1737         for (i = 0; i < nic->sqs_count; i++) {
1738                 assert(nic->snicvf[i]);
1739
1740                 ret = nicvf_vf_start(dev, nic->snicvf[i], rbdrsz);
1741                 if (ret != 0)
1742                         return ret;
1743         }
1744
1745         /* Configure callbacks based on scatter mode */
1746         nicvf_set_tx_function(dev);
1747         nicvf_set_rx_function(dev);
1748
1749         return 0;
1750 }
1751
1752 static void
1753 nicvf_dev_stop_cleanup(struct rte_eth_dev *dev, bool cleanup)
1754 {
1755         size_t i;
1756         int ret;
1757         struct nicvf *nic = nicvf_pmd_priv(dev);
1758
1759         PMD_INIT_FUNC_TRACE();
1760
1761         /* Teardown secondary vf first */
1762         for (i = 0; i < nic->sqs_count; i++) {
1763                 if (!nic->snicvf[i])
1764                         continue;
1765
1766                 nicvf_vf_stop(dev, nic->snicvf[i], cleanup);
1767         }
1768
1769         /* Stop the primary VF now */
1770         nicvf_vf_stop(dev, nic, cleanup);
1771
1772         /* Disable loopback */
1773         ret = nicvf_loopback_config(nic, 0);
1774         if (ret)
1775                 PMD_INIT_LOG(ERR, "Failed to disable loopback %d", ret);
1776
1777         /* Reclaim CPI configuration */
1778         ret = nicvf_mbox_config_cpi(nic, 0);
1779         if (ret)
1780                 PMD_INIT_LOG(ERR, "Failed to reclaim CPI config %d", ret);
1781 }
1782
1783 static void
1784 nicvf_dev_stop(struct rte_eth_dev *dev)
1785 {
1786         PMD_INIT_FUNC_TRACE();
1787
1788         nicvf_dev_stop_cleanup(dev, false);
1789 }
1790
1791 static void
1792 nicvf_vf_stop(struct rte_eth_dev *dev, struct nicvf *nic, bool cleanup)
1793 {
1794         int ret;
1795         uint16_t qidx;
1796         uint16_t tx_start, tx_end;
1797         uint16_t rx_start, rx_end;
1798
1799         PMD_INIT_FUNC_TRACE();
1800
1801         if (cleanup) {
1802                 /* Let PF make the BGX's RX and TX switches to OFF position */
1803                 nicvf_mbox_shutdown(nic);
1804         }
1805
1806         /* Disable VLAN Strip */
1807         nicvf_vlan_hw_strip(nic, 0);
1808
1809         /* Get queue ranges for this VF */
1810         nicvf_tx_range(dev, nic, &tx_start, &tx_end);
1811
1812         for (qidx = tx_start; qidx <= tx_end; qidx++)
1813                 nicvf_vf_stop_tx_queue(dev, nic, qidx % MAX_SND_QUEUES_PER_QS);
1814
1815         /* Get queue ranges for this VF */
1816         nicvf_rx_range(dev, nic, &rx_start, &rx_end);
1817
1818         /* Reclaim rq */
1819         for (qidx = rx_start; qidx <= rx_end; qidx++)
1820                 nicvf_vf_stop_rx_queue(dev, nic, qidx % MAX_RCV_QUEUES_PER_QS);
1821
1822         /* Reclaim RBDR */
1823         ret = nicvf_qset_rbdr_reclaim(nic, 0);
1824         if (ret)
1825                 PMD_INIT_LOG(ERR, "Failed to reclaim RBDR %d", ret);
1826
1827         /* Move all charged buffers in RBDR back to pool */
1828         if (nic->rbdr != NULL)
1829                 nicvf_rbdr_release_mbufs(dev, nic);
1830
1831         /* Disable qset */
1832         ret = nicvf_qset_reclaim(nic);
1833         if (ret)
1834                 PMD_INIT_LOG(ERR, "Failed to disable qset %d", ret);
1835
1836         /* Disable all interrupts */
1837         nicvf_disable_all_interrupts(nic);
1838
1839         /* Free RBDR SW structure */
1840         if (nic->rbdr) {
1841                 rte_free(nic->rbdr);
1842                 nic->rbdr = NULL;
1843         }
1844 }
1845
1846 static void
1847 nicvf_dev_close(struct rte_eth_dev *dev)
1848 {
1849         size_t i;
1850         struct nicvf *nic = nicvf_pmd_priv(dev);
1851
1852         PMD_INIT_FUNC_TRACE();
1853
1854         nicvf_dev_stop_cleanup(dev, true);
1855         nicvf_periodic_alarm_stop(nicvf_interrupt, dev);
1856
1857         for (i = 0; i < nic->sqs_count; i++) {
1858                 if (!nic->snicvf[i])
1859                         continue;
1860
1861                 nicvf_periodic_alarm_stop(nicvf_vf_interrupt, nic->snicvf[i]);
1862         }
1863 }
1864
1865 static int
1866 nicvf_request_sqs(struct nicvf *nic)
1867 {
1868         size_t i;
1869
1870         assert_primary(nic);
1871         assert(nic->sqs_count > 0);
1872         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1873
1874         /* Set no of Rx/Tx queues in each of the SQsets */
1875         for (i = 0; i < nic->sqs_count; i++) {
1876                 if (nicvf_svf_empty())
1877                         rte_panic("Cannot assign sufficient number of "
1878                                   "secondary queues to primary VF%" PRIu8 "\n",
1879                                   nic->vf_id);
1880
1881                 nic->snicvf[i] = nicvf_svf_pop();
1882                 nic->snicvf[i]->sqs_id = i;
1883         }
1884
1885         return nicvf_mbox_request_sqs(nic);
1886 }
1887
1888 static int
1889 nicvf_dev_configure(struct rte_eth_dev *dev)
1890 {
1891         struct rte_eth_dev_data *data = dev->data;
1892         struct rte_eth_conf *conf = &data->dev_conf;
1893         struct rte_eth_rxmode *rxmode = &conf->rxmode;
1894         struct rte_eth_txmode *txmode = &conf->txmode;
1895         struct nicvf *nic = nicvf_pmd_priv(dev);
1896         uint8_t cqcount;
1897
1898         PMD_INIT_FUNC_TRACE();
1899
1900         if (!rte_eal_has_hugepages()) {
1901                 PMD_INIT_LOG(INFO, "Huge page is not configured");
1902                 return -EINVAL;
1903         }
1904
1905         if ((rxmode->offloads & DEV_RX_OFFLOAD_CRC_STRIP) == 0) {
1906                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
1907                 rxmode->offloads |= DEV_RX_OFFLOAD_CRC_STRIP;
1908         }
1909
1910         if (txmode->mq_mode) {
1911                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
1912                 return -EINVAL;
1913         }
1914
1915         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
1916                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
1917                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
1918                 return -EINVAL;
1919         }
1920
1921         if (rxmode->split_hdr_size) {
1922                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
1923                 return -EINVAL;
1924         }
1925
1926         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
1927                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
1928                 return -EINVAL;
1929         }
1930
1931         if (conf->dcb_capability_en) {
1932                 PMD_INIT_LOG(INFO, "DCB enable not supported");
1933                 return -EINVAL;
1934         }
1935
1936         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1937                 PMD_INIT_LOG(INFO, "Flow director not supported");
1938                 return -EINVAL;
1939         }
1940
1941         assert_primary(nic);
1942         NICVF_STATIC_ASSERT(MAX_RCV_QUEUES_PER_QS == MAX_SND_QUEUES_PER_QS);
1943         cqcount = RTE_MAX(data->nb_tx_queues, data->nb_rx_queues);
1944         if (cqcount > MAX_RCV_QUEUES_PER_QS) {
1945                 nic->sqs_count = RTE_ALIGN_CEIL(cqcount, MAX_RCV_QUEUES_PER_QS);
1946                 nic->sqs_count = (nic->sqs_count / MAX_RCV_QUEUES_PER_QS) - 1;
1947         } else {
1948                 nic->sqs_count = 0;
1949         }
1950
1951         assert(nic->sqs_count <= MAX_SQS_PER_VF);
1952
1953         if (nic->sqs_count > 0) {
1954                 if (nicvf_request_sqs(nic)) {
1955                         rte_panic("Cannot assign sufficient number of "
1956                                   "secondary queues to PORT%d VF%" PRIu8 "\n",
1957                                   dev->data->port_id, nic->vf_id);
1958                 }
1959         }
1960
1961         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
1962                 dev->data->port_id, nicvf_hw_cap(nic));
1963
1964         return 0;
1965 }
1966
1967 /* Initialize and register driver with DPDK Application */
1968 static const struct eth_dev_ops nicvf_eth_dev_ops = {
1969         .dev_configure            = nicvf_dev_configure,
1970         .dev_start                = nicvf_dev_start,
1971         .dev_stop                 = nicvf_dev_stop,
1972         .link_update              = nicvf_dev_link_update,
1973         .dev_close                = nicvf_dev_close,
1974         .stats_get                = nicvf_dev_stats_get,
1975         .stats_reset              = nicvf_dev_stats_reset,
1976         .promiscuous_enable       = nicvf_dev_promisc_enable,
1977         .dev_infos_get            = nicvf_dev_info_get,
1978         .dev_supported_ptypes_get = nicvf_dev_supported_ptypes_get,
1979         .mtu_set                  = nicvf_dev_set_mtu,
1980         .reta_update              = nicvf_dev_reta_update,
1981         .reta_query               = nicvf_dev_reta_query,
1982         .rss_hash_update          = nicvf_dev_rss_hash_update,
1983         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
1984         .rx_queue_start           = nicvf_dev_rx_queue_start,
1985         .rx_queue_stop            = nicvf_dev_rx_queue_stop,
1986         .tx_queue_start           = nicvf_dev_tx_queue_start,
1987         .tx_queue_stop            = nicvf_dev_tx_queue_stop,
1988         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
1989         .rx_queue_release         = nicvf_dev_rx_queue_release,
1990         .rx_queue_count           = nicvf_dev_rx_queue_count,
1991         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
1992         .tx_queue_release         = nicvf_dev_tx_queue_release,
1993         .get_reg                  = nicvf_dev_get_regs,
1994 };
1995
1996 static inline int
1997 nicvf_set_first_skip(struct rte_eth_dev *dev)
1998 {
1999         int bytes_to_skip = 0;
2000         int ret = 0;
2001         unsigned int i;
2002         struct rte_kvargs *kvlist;
2003         static const char *const skip[] = {
2004                 SKIP_DATA_BYTES,
2005                 NULL};
2006         struct nicvf *nic = nicvf_pmd_priv(dev);
2007
2008         if (!dev->device->devargs) {
2009                 nicvf_first_skip_config(nic, 0);
2010                 return ret;
2011         }
2012
2013         kvlist = rte_kvargs_parse(dev->device->devargs->args, skip);
2014         if (!kvlist)
2015                 return -EINVAL;
2016
2017         if (kvlist->count == 0)
2018                 goto exit;
2019
2020         for (i = 0; i != kvlist->count; ++i) {
2021                 const struct rte_kvargs_pair *pair = &kvlist->pairs[i];
2022
2023                 if (!strcmp(pair->key, SKIP_DATA_BYTES))
2024                         bytes_to_skip = atoi(pair->value);
2025         }
2026
2027         /*128 bytes amounts to one cache line*/
2028         if (bytes_to_skip >= 0 && bytes_to_skip < 128) {
2029                 if (!(bytes_to_skip % 8)) {
2030                         nicvf_first_skip_config(nic, (bytes_to_skip / 8));
2031                         nic->skip_bytes = bytes_to_skip;
2032                         goto kvlist_free;
2033                 } else {
2034                         PMD_INIT_LOG(ERR, "skip_data_bytes should be multiple of 8");
2035                         ret = -EINVAL;
2036                         goto exit;
2037                 }
2038         } else {
2039                 PMD_INIT_LOG(ERR, "skip_data_bytes should be less than 128");
2040                 ret = -EINVAL;
2041                 goto exit;
2042         }
2043 exit:
2044         nicvf_first_skip_config(nic, 0);
2045 kvlist_free:
2046         rte_kvargs_free(kvlist);
2047         return ret;
2048 }
2049 static int
2050 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
2051 {
2052         int ret;
2053         struct rte_pci_device *pci_dev;
2054         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
2055
2056         PMD_INIT_FUNC_TRACE();
2057
2058         eth_dev->dev_ops = &nicvf_eth_dev_ops;
2059
2060         /* For secondary processes, the primary has done all the work */
2061         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2062                 if (nic) {
2063                         /* Setup callbacks for secondary process */
2064                         nicvf_set_tx_function(eth_dev);
2065                         nicvf_set_rx_function(eth_dev);
2066                         return 0;
2067                 } else {
2068                         /* If nic == NULL than it is secondary function
2069                          * so ethdev need to be released by caller */
2070                         return ENOTSUP;
2071                 }
2072         }
2073
2074         pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
2075         rte_eth_copy_pci_info(eth_dev, pci_dev);
2076
2077         nic->device_id = pci_dev->id.device_id;
2078         nic->vendor_id = pci_dev->id.vendor_id;
2079         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
2080         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2081
2082         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
2083                         pci_dev->id.vendor_id, pci_dev->id.device_id,
2084                         pci_dev->addr.domain, pci_dev->addr.bus,
2085                         pci_dev->addr.devid, pci_dev->addr.function);
2086
2087         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
2088         if (!nic->reg_base) {
2089                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
2090                 ret = -ENODEV;
2091                 goto fail;
2092         }
2093
2094         nicvf_disable_all_interrupts(nic);
2095
2096         ret = nicvf_periodic_alarm_start(nicvf_interrupt, eth_dev);
2097         if (ret) {
2098                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
2099                 goto fail;
2100         }
2101
2102         ret = nicvf_mbox_check_pf_ready(nic);
2103         if (ret) {
2104                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
2105                 goto alarm_fail;
2106         } else {
2107                 PMD_INIT_LOG(INFO,
2108                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
2109                         nic->node, nic->vf_id,
2110                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
2111                         nic->sqs_mode ? "true" : "false",
2112                         nic->loopback_supported ? "true" : "false"
2113                         );
2114         }
2115
2116         ret = nicvf_base_init(nic);
2117         if (ret) {
2118                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
2119                 goto malloc_fail;
2120         }
2121
2122         if (nic->sqs_mode) {
2123                 /* Push nic to stack of secondary vfs */
2124                 nicvf_svf_push(nic);
2125
2126                 /* Steal nic pointer from the device for further reuse */
2127                 eth_dev->data->dev_private = NULL;
2128
2129                 nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2130                 ret = nicvf_periodic_alarm_start(nicvf_vf_interrupt, nic);
2131                 if (ret) {
2132                         PMD_INIT_LOG(ERR, "Failed to start period alarm");
2133                         goto fail;
2134                 }
2135
2136                 /* Detach port by returning positive error number */
2137                 return ENOTSUP;
2138         }
2139
2140         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
2141         if (eth_dev->data->mac_addrs == NULL) {
2142                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
2143                 ret = -ENOMEM;
2144                 goto alarm_fail;
2145         }
2146         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
2147                 eth_random_addr(&nic->mac_addr[0]);
2148
2149         ether_addr_copy((struct ether_addr *)nic->mac_addr,
2150                         &eth_dev->data->mac_addrs[0]);
2151
2152         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
2153         if (ret) {
2154                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
2155                 goto malloc_fail;
2156         }
2157
2158         ret = nicvf_set_first_skip(eth_dev);
2159         if (ret) {
2160                 PMD_INIT_LOG(ERR, "Failed to configure first skip");
2161                 goto malloc_fail;
2162         }
2163         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
2164                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
2165                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
2166                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
2167
2168         return 0;
2169
2170 malloc_fail:
2171         rte_free(eth_dev->data->mac_addrs);
2172 alarm_fail:
2173         nicvf_periodic_alarm_stop(nicvf_interrupt, eth_dev);
2174 fail:
2175         return ret;
2176 }
2177
2178 static const struct rte_pci_id pci_id_nicvf_map[] = {
2179         {
2180                 .class_id = RTE_CLASS_ANY_ID,
2181                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2182                 .device_id = PCI_DEVICE_ID_THUNDERX_CN88XX_PASS1_NICVF,
2183                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2184                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS1_NICVF,
2185         },
2186         {
2187                 .class_id = RTE_CLASS_ANY_ID,
2188                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2189                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2190                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2191                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN88XX_PASS2_NICVF,
2192         },
2193         {
2194                 .class_id = RTE_CLASS_ANY_ID,
2195                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2196                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2197                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2198                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN81XX_NICVF,
2199         },
2200         {
2201                 .class_id = RTE_CLASS_ANY_ID,
2202                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
2203                 .device_id = PCI_DEVICE_ID_THUNDERX_NICVF,
2204                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
2205                 .subsystem_device_id = PCI_SUB_DEVICE_ID_CN83XX_NICVF,
2206         },
2207         {
2208                 .vendor_id = 0,
2209         },
2210 };
2211
2212 static int nicvf_eth_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
2213         struct rte_pci_device *pci_dev)
2214 {
2215         return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct nicvf),
2216                 nicvf_eth_dev_init);
2217 }
2218
2219 static int nicvf_eth_pci_remove(struct rte_pci_device *pci_dev)
2220 {
2221         return rte_eth_dev_pci_generic_remove(pci_dev, NULL);
2222 }
2223
2224 static struct rte_pci_driver rte_nicvf_pmd = {
2225         .id_table = pci_id_nicvf_map,
2226         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_KEEP_MAPPED_RES |
2227                         RTE_PCI_DRV_INTR_LSC,
2228         .probe = nicvf_eth_pci_probe,
2229         .remove = nicvf_eth_pci_remove,
2230 };
2231
2232 RTE_PMD_REGISTER_PCI(net_thunderx, rte_nicvf_pmd);
2233 RTE_PMD_REGISTER_PCI_TABLE(net_thunderx, pci_id_nicvf_map);
2234 RTE_PMD_REGISTER_KMOD_DEP(net_thunderx, "* igb_uio | uio_pci_generic | vfio-pci");
2235 RTE_PMD_REGISTER_PARAM_STRING(net_thunderx, SKIP_DATA_BYTES "=<int>");