drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44 #include <sys/timerfd.h>
  45
  46 #include <rte_alarm.h>
  47 #include <rte_atomic.h>
  48 #include <rte_branch_prediction.h>
  49 #include <rte_byteorder.h>
  50 #include <rte_common.h>
  51 #include <rte_cycles.h>
  52 #include <rte_debug.h>
  53 #include <rte_dev.h>
  54 #include <rte_eal.h>
  55 #include <rte_ether.h>
  56 #include <rte_ethdev.h>
  57 #include <rte_interrupts.h>
  58 #include <rte_log.h>
  59 #include <rte_memory.h>
  60 #include <rte_memzone.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_pci.h>
  64 #include <rte_tailq.h>
  65
  66 #include "base/nicvf_plat.h"
  67
  68 #include "nicvf_ethdev.h"
  69
  70 #include "nicvf_logs.h"
  71
  72 static inline int
  73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  74                                struct rte_eth_link *link)
  75 {
  76         struct rte_eth_link *dst = &dev->data->dev_link;
  77         struct rte_eth_link *src = link;
  78
  79         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  80                 *(uint64_t *)src) == 0)
  81                 return -1;
  82
  83         return 0;
  84 }
  85
  86 static inline void
  87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  88 {
  89         link->link_status = nic->link_up;
  90         link->link_duplex = ETH_LINK_AUTONEG;
  91         if (nic->duplex == NICVF_HALF_DUPLEX)
  92                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  93         else if (nic->duplex == NICVF_FULL_DUPLEX)
  94                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  95         link->link_speed = nic->speed;
  96         link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
  97 }
  98
  99 static void
 100 nicvf_interrupt(void *arg)
 101 {
 102         struct nicvf *nic = arg;
 103
 104         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 105                 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
 106                         nicvf_set_eth_link_status(nic,
 107                                         &nic->eth_dev->data->dev_link);
 108                 _rte_eth_dev_callback_process(nic->eth_dev,
 109                                 RTE_ETH_EVENT_INTR_LSC);
 110         }
 111
 112         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 113                                 nicvf_interrupt, nic);
 114 }
 115
 116 static int
 117 nicvf_periodic_alarm_start(struct nicvf *nic)
 118 {
 119         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 120                                         nicvf_interrupt, nic);
 121 }
 122
 123 static int
 124 nicvf_periodic_alarm_stop(struct nicvf *nic)
 125 {
 126         return rte_eal_alarm_cancel(nicvf_interrupt, nic);
 127 }
 128
 129 /*
 130  * Return 0 means link status changed, -1 means not changed
 131  */
 132 static int
 133 nicvf_dev_link_update(struct rte_eth_dev *dev,
 134                       int wait_to_complete __rte_unused)
 135 {
 136         struct rte_eth_link link;
 137         struct nicvf *nic = nicvf_pmd_priv(dev);
 138
 139         PMD_INIT_FUNC_TRACE();
 140
 141         memset(&link, 0, sizeof(link));
 142         nicvf_set_eth_link_status(nic, &link);
 143         return nicvf_atomic_write_link_status(dev, &link);
 144 }
 145
 146 static int
 147 nicvf_dev_get_reg_length(struct rte_eth_dev *dev  __rte_unused)
 148 {
 149         return nicvf_reg_get_count();
 150 }
 151
 152 static int
 153 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 154 {
 155         uint64_t *data = regs->data;
 156         struct nicvf *nic = nicvf_pmd_priv(dev);
 157
 158         if (data == NULL)
 159                 return -EINVAL;
 160
 161         /* Support only full register dump */
 162         if ((regs->length == 0) ||
 163                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 164                 regs->version = nic->vendor_id << 16 | nic->device_id;
 165                 nicvf_reg_dump(nic, data);
 166                 return 0;
 167         }
 168         return -ENOTSUP;
 169 }
 170
 171 static int
 172 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
 173                     uint32_t desc_cnt)
 174 {
 175         const struct rte_memzone *rz;
 176         uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
 177
 178         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
 179                                         NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 180         if (rz == NULL) {
 181                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 182                 return -ENOMEM;
 183         }
 184
 185         memset(rz->addr, 0, ring_size);
 186
 187         rxq->phys = rz->phys_addr;
 188         rxq->desc = rz->addr;
 189         rxq->qlen_mask = desc_cnt - 1;
 190
 191         return 0;
 192 }
 193
 194 static int
 195 nicvf_qset_sq_alloc(struct nicvf *nic,  struct nicvf_txq *sq, uint16_t qidx,
 196                     uint32_t desc_cnt)
 197 {
 198         const struct rte_memzone *rz;
 199         uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
 200
 201         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
 202                                 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 203         if (rz == NULL) {
 204                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 205                 return -ENOMEM;
 206         }
 207
 208         memset(rz->addr, 0, ring_size);
 209
 210         sq->phys = rz->phys_addr;
 211         sq->desc = rz->addr;
 212         sq->qlen_mask = desc_cnt - 1;
 213
 214         return 0;
 215 }
 216
 217 static inline void
 218 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 219 {
 220         uint32_t head;
 221
 222         head = txq->head;
 223         while (head != txq->tail) {
 224                 if (txq->txbuffs[head]) {
 225                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 226                         txq->txbuffs[head] = NULL;
 227                 }
 228                 head++;
 229                 head = head & txq->qlen_mask;
 230         }
 231 }
 232
 233 static void
 234 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 235 {
 236         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 237
 238         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 239         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 240         txq->tail = 0;
 241         txq->head = 0;
 242         txq->xmit_bufs = 0;
 243 }
 244
 245 static void
 246 nicvf_dev_tx_queue_release(void *sq)
 247 {
 248         struct nicvf_txq *txq;
 249
 250         PMD_INIT_FUNC_TRACE();
 251
 252         txq = (struct nicvf_txq *)sq;
 253         if (txq) {
 254                 if (txq->txbuffs != NULL) {
 255                         nicvf_tx_queue_release_mbufs(txq);
 256                         rte_free(txq->txbuffs);
 257                         txq->txbuffs = NULL;
 258                 }
 259                 rte_free(txq);
 260         }
 261 }
 262
 263 static int
 264 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 265                          uint16_t nb_desc, unsigned int socket_id,
 266                          const struct rte_eth_txconf *tx_conf)
 267 {
 268         uint16_t tx_free_thresh;
 269         uint8_t is_single_pool;
 270         struct nicvf_txq *txq;
 271         struct nicvf *nic = nicvf_pmd_priv(dev);
 272
 273         PMD_INIT_FUNC_TRACE();
 274
 275         /* Socket id check */
 276         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 277                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 278                 socket_id, nic->node);
 279
 280         /* Tx deferred start is not supported */
 281         if (tx_conf->tx_deferred_start) {
 282                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 283                 return -EINVAL;
 284         }
 285
 286         /* Roundup nb_desc to available qsize and validate max number of desc */
 287         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 288         if (nb_desc == 0) {
 289                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 290                 return -EINVAL;
 291         }
 292
 293         /* Validate tx_free_thresh */
 294         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 295                                 tx_conf->tx_free_thresh :
 296                                 NICVF_DEFAULT_TX_FREE_THRESH);
 297
 298         if (tx_free_thresh > (nb_desc) ||
 299                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 300                 PMD_INIT_LOG(ERR,
 301                         "tx_free_thresh must be less than the number of TX "
 302                         "descriptors. (tx_free_thresh=%u port=%d "
 303                         "queue=%d)", (unsigned int)tx_free_thresh,
 304                         (int)dev->data->port_id, (int)qidx);
 305                 return -EINVAL;
 306         }
 307
 308         /* Free memory prior to re-allocation if needed. */
 309         if (dev->data->tx_queues[qidx] != NULL) {
 310                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 311                                 qidx);
 312                 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
 313                 dev->data->tx_queues[qidx] = NULL;
 314         }
 315
 316         /* Allocating tx queue data structure */
 317         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 318                                         RTE_CACHE_LINE_SIZE, nic->node);
 319         if (txq == NULL) {
 320                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
 321                 return -ENOMEM;
 322         }
 323
 324         txq->nic = nic;
 325         txq->queue_id = qidx;
 326         txq->tx_free_thresh = tx_free_thresh;
 327         txq->txq_flags = tx_conf->txq_flags;
 328         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
 329         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
 330         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
 331                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
 332
 333         /* Choose optimum free threshold value for multipool case */
 334         if (!is_single_pool) {
 335                 txq->tx_free_thresh = (uint16_t)
 336                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
 337                                 NICVF_TX_FREE_MPOOL_THRESH :
 338                                 tx_conf->tx_free_thresh);
 339         }
 340
 341         /* Allocate software ring */
 342         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
 343                                 nb_desc * sizeof(struct rte_mbuf *),
 344                                 RTE_CACHE_LINE_SIZE, nic->node);
 345
 346         if (txq->txbuffs == NULL) {
 347                 nicvf_dev_tx_queue_release(txq);
 348                 return -ENOMEM;
 349         }
 350
 351         if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
 352                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
 353                 nicvf_dev_tx_queue_release(txq);
 354                 return -ENOMEM;
 355         }
 356
 357         nicvf_tx_queue_reset(txq);
 358
 359         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
 360                         qidx, txq, nb_desc, txq->desc, txq->phys);
 361
 362         dev->data->tx_queues[qidx] = txq;
 363         dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 364         return 0;
 365 }
 366
 367 static void
 368 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
 369 {
 370         rxq->head = 0;
 371         rxq->available_space = 0;
 372         rxq->recv_buffers = 0;
 373 }
 374
 375 static void
 376 nicvf_dev_rx_queue_release(void *rx_queue)
 377 {
 378         struct nicvf_rxq *rxq = rx_queue;
 379
 380         PMD_INIT_FUNC_TRACE();
 381
 382         if (rxq)
 383                 rte_free(rxq);
 384 }
 385
 386 static int
 387 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 388                          uint16_t nb_desc, unsigned int socket_id,
 389                          const struct rte_eth_rxconf *rx_conf,
 390                          struct rte_mempool *mp)
 391 {
 392         uint16_t rx_free_thresh;
 393         struct nicvf_rxq *rxq;
 394         struct nicvf *nic = nicvf_pmd_priv(dev);
 395
 396         PMD_INIT_FUNC_TRACE();
 397
 398         /* Socket id check */
 399         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 400                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 401                 socket_id, nic->node);
 402
 403         /* Mempool memory should be contiguous */
 404         if (mp->nb_mem_chunks != 1) {
 405                 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
 406                 return -EINVAL;
 407         }
 408
 409         /* Rx deferred start is not supported */
 410         if (rx_conf->rx_deferred_start) {
 411                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
 412                 return -EINVAL;
 413         }
 414
 415         /* Roundup nb_desc to available qsize and validate max number of desc */
 416         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
 417         if (nb_desc == 0) {
 418                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
 419                 return -EINVAL;
 420         }
 421
 422         /* Check rx_free_thresh upper bound */
 423         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
 424                                 rx_conf->rx_free_thresh :
 425                                 NICVF_DEFAULT_RX_FREE_THRESH);
 426         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
 427                 rx_free_thresh >= nb_desc * .75) {
 428                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
 429                                 rx_free_thresh);
 430                 return -EINVAL;
 431         }
 432
 433         /* Free memory prior to re-allocation if needed */
 434         if (dev->data->rx_queues[qidx] != NULL) {
 435                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 436                                 qidx);
 437                 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
 438                 dev->data->rx_queues[qidx] = NULL;
 439         }
 440
 441         /* Allocate rxq memory */
 442         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
 443                                         RTE_CACHE_LINE_SIZE, nic->node);
 444         if (rxq == NULL) {
 445                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
 446                 return -ENOMEM;
 447         }
 448
 449         rxq->nic = nic;
 450         rxq->pool = mp;
 451         rxq->queue_id = qidx;
 452         rxq->port_id = dev->data->port_id;
 453         rxq->rx_free_thresh = rx_free_thresh;
 454         rxq->rx_drop_en = rx_conf->rx_drop_en;
 455         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
 456         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
 457         rxq->precharge_cnt = 0;
 458         rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
 459
 460         /* Alloc completion queue */
 461         if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
 462                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
 463                 nicvf_dev_rx_queue_release(rxq);
 464                 return -ENOMEM;
 465         }
 466
 467         nicvf_rx_queue_reset(rxq);
 468
 469         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
 470                         qidx, rxq, mp->name, nb_desc,
 471                         rte_mempool_count(mp), rxq->phys);
 472
 473         dev->data->rx_queues[qidx] = rxq;
 474         dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 475         return 0;
 476 }
 477
 478 static void
 479 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 480 {
 481         struct nicvf *nic = nicvf_pmd_priv(dev);
 482
 483         PMD_INIT_FUNC_TRACE();
 484
 485         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
 486         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
 487         dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
 488         dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
 489         dev_info->max_mac_addrs = 1;
 490         dev_info->max_vfs = dev->pci_dev->max_vfs;
 491
 492         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
 493         dev_info->tx_offload_capa =
 494                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
 495                 DEV_TX_OFFLOAD_UDP_CKSUM   |
 496                 DEV_TX_OFFLOAD_TCP_CKSUM   |
 497                 DEV_TX_OFFLOAD_TCP_TSO     |
 498                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
 499
 500         dev_info->reta_size = nic->rss_info.rss_size;
 501         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
 502         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
 503         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
 504                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
 505
 506         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 507                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
 508                 .rx_drop_en = 0,
 509         };
 510
 511         dev_info->default_txconf = (struct rte_eth_txconf) {
 512                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
 513                 .txq_flags =
 514                         ETH_TXQ_FLAGS_NOMULTSEGS  |
 515                         ETH_TXQ_FLAGS_NOREFCOUNT  |
 516                         ETH_TXQ_FLAGS_NOMULTMEMP  |
 517                         ETH_TXQ_FLAGS_NOVLANOFFL  |
 518                         ETH_TXQ_FLAGS_NOXSUMSCTP,
 519         };
 520 }
 521
 522 static int
 523 nicvf_dev_configure(struct rte_eth_dev *dev)
 524 {
 525         struct rte_eth_conf *conf = &dev->data->dev_conf;
 526         struct rte_eth_rxmode *rxmode = &conf->rxmode;
 527         struct rte_eth_txmode *txmode = &conf->txmode;
 528         struct nicvf *nic = nicvf_pmd_priv(dev);
 529
 530         PMD_INIT_FUNC_TRACE();
 531
 532         if (!rte_eal_has_hugepages()) {
 533                 PMD_INIT_LOG(INFO, "Huge page is not configured");
 534                 return -EINVAL;
 535         }
 536
 537         if (txmode->mq_mode) {
 538                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
 539                 return -EINVAL;
 540         }
 541
 542         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
 543                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
 544                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
 545                 return -EINVAL;
 546         }
 547
 548         if (!rxmode->hw_strip_crc) {
 549                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
 550                 rxmode->hw_strip_crc = 1;
 551         }
 552
 553         if (rxmode->hw_ip_checksum) {
 554                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
 555                 rxmode->hw_ip_checksum = 0;
 556         }
 557
 558         if (rxmode->split_hdr_size) {
 559                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
 560                 return -EINVAL;
 561         }
 562
 563         if (rxmode->hw_vlan_filter) {
 564                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 565                 return -EINVAL;
 566         }
 567
 568         if (rxmode->hw_vlan_extend) {
 569                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 570                 return -EINVAL;
 571         }
 572
 573         if (rxmode->enable_lro) {
 574                 PMD_INIT_LOG(INFO, "LRO not supported");
 575                 return -EINVAL;
 576         }
 577
 578         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 579                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
 580                 return -EINVAL;
 581         }
 582
 583         if (conf->dcb_capability_en) {
 584                 PMD_INIT_LOG(INFO, "DCB enable not supported");
 585                 return -EINVAL;
 586         }
 587
 588         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
 589                 PMD_INIT_LOG(INFO, "Flow director not supported");
 590                 return -EINVAL;
 591         }
 592
 593         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
 594                 dev->data->port_id, nicvf_hw_cap(nic));
 595
 596         return 0;
 597 }
 598
 599 /* Initialize and register driver with DPDK Application */
 600 static const struct eth_dev_ops nicvf_eth_dev_ops = {
 601         .dev_configure            = nicvf_dev_configure,
 602         .link_update              = nicvf_dev_link_update,
 603         .dev_infos_get            = nicvf_dev_info_get,
 604         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
 605         .rx_queue_release         = nicvf_dev_rx_queue_release,
 606         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
 607         .tx_queue_release         = nicvf_dev_tx_queue_release,
 608         .get_reg_length           = nicvf_dev_get_reg_length,
 609         .get_reg                  = nicvf_dev_get_regs,
 610 };
 611
 612 static int
 613 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
 614 {
 615         int ret;
 616         struct rte_pci_device *pci_dev;
 617         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
 618
 619         PMD_INIT_FUNC_TRACE();
 620
 621         eth_dev->dev_ops = &nicvf_eth_dev_ops;
 622
 623         pci_dev = eth_dev->pci_dev;
 624         rte_eth_copy_pci_info(eth_dev, pci_dev);
 625
 626         nic->device_id = pci_dev->id.device_id;
 627         nic->vendor_id = pci_dev->id.vendor_id;
 628         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
 629         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 630         nic->eth_dev = eth_dev;
 631
 632         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
 633                         pci_dev->id.vendor_id, pci_dev->id.device_id,
 634                         pci_dev->addr.domain, pci_dev->addr.bus,
 635                         pci_dev->addr.devid, pci_dev->addr.function);
 636
 637         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
 638         if (!nic->reg_base) {
 639                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
 640                 ret = -ENODEV;
 641                 goto fail;
 642         }
 643
 644         nicvf_disable_all_interrupts(nic);
 645
 646         ret = nicvf_periodic_alarm_start(nic);
 647         if (ret) {
 648                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
 649                 goto fail;
 650         }
 651
 652         ret = nicvf_mbox_check_pf_ready(nic);
 653         if (ret) {
 654                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
 655                 goto alarm_fail;
 656         } else {
 657                 PMD_INIT_LOG(INFO,
 658                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
 659                         nic->node, nic->vf_id,
 660                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
 661                         nic->sqs_mode ? "true" : "false",
 662                         nic->loopback_supported ? "true" : "false"
 663                         );
 664         }
 665
 666         if (nic->sqs_mode) {
 667                 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
 668                 /* Detach port by returning Positive error number */
 669                 ret = ENOTSUP;
 670                 goto alarm_fail;
 671         }
 672
 673         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
 674         if (eth_dev->data->mac_addrs == NULL) {
 675                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
 676                 ret = -ENOMEM;
 677                 goto alarm_fail;
 678         }
 679         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
 680                 eth_random_addr(&nic->mac_addr[0]);
 681
 682         ether_addr_copy((struct ether_addr *)nic->mac_addr,
 683                         &eth_dev->data->mac_addrs[0]);
 684
 685         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
 686         if (ret) {
 687                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
 688                 goto malloc_fail;
 689         }
 690
 691         ret = nicvf_base_init(nic);
 692         if (ret) {
 693                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
 694                 goto malloc_fail;
 695         }
 696
 697         ret = nicvf_mbox_get_rss_size(nic);
 698         if (ret) {
 699                 PMD_INIT_LOG(ERR, "Failed to get rss table size");
 700                 goto malloc_fail;
 701         }
 702
 703         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
 704                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
 705                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
 706                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
 707
 708         return 0;
 709
 710 malloc_fail:
 711         rte_free(eth_dev->data->mac_addrs);
 712 alarm_fail:
 713         nicvf_periodic_alarm_stop(nic);
 714 fail:
 715         return ret;
 716 }
 717
 718 static const struct rte_pci_id pci_id_nicvf_map[] = {
 719         {
 720                 .class_id = RTE_CLASS_ANY_ID,
 721                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
 722                 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
 723                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 724                 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
 725         },
 726         {
 727                 .class_id = RTE_CLASS_ANY_ID,
 728                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
 729                 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
 730                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 731                 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
 732         },
 733         {
 734                 .vendor_id = 0,
 735         },
 736 };
 737
 738 static struct eth_driver rte_nicvf_pmd = {
 739         .pci_drv = {
 740                 .name = "rte_nicvf_pmd",
 741                 .id_table = pci_id_nicvf_map,
 742                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 743         },
 744         .eth_dev_init = nicvf_eth_dev_init,
 745         .dev_private_size = sizeof(struct nicvf),
 746 };
 747
 748 static int
 749 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
 750 {
 751         PMD_INIT_FUNC_TRACE();
 752         PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
 753                         THUNDERX_NICVF_PMD_VERSION);
 754
 755         rte_eth_driver_register(&rte_nicvf_pmd);
 756         return 0;
 757 }
 758
 759 static struct rte_driver rte_nicvf_driver = {
 760         .name = "nicvf_driver",
 761         .type = PMD_PDEV,
 762         .init = rte_nicvf_pmd_init,
 763 };
 764
 765 PMD_REGISTER_DRIVER(rte_nicvf_driver);