drivers/net/thunderx/nicvf_ethdev.c

   1 /*
   2  *   BSD LICENSE
   3  *
   4  *   Copyright (C) Cavium networks Ltd. 2016.
   5  *
   6  *   Redistribution and use in source and binary forms, with or without
   7  *   modification, are permitted provided that the following conditions
   8  *   are met:
   9  *
  10  *     * Redistributions of source code must retain the above copyright
  11  *       notice, this list of conditions and the following disclaimer.
  12  *     * Redistributions in binary form must reproduce the above copyright
  13  *       notice, this list of conditions and the following disclaimer in
  14  *       the documentation and/or other materials provided with the
  15  *       distribution.
  16  *     * Neither the name of Cavium networks nor the names of its
  17  *       contributors may be used to endorse or promote products derived
  18  *       from this software without specific prior written permission.
  19  *
  20  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  21  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  22  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  23  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  24  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  25  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  26  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  27  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  28  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  30  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32
  33 #include <assert.h>
  34 #include <stdio.h>
  35 #include <stdbool.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <netinet/in.h>
  43 #include <sys/queue.h>
  44 #include <sys/timerfd.h>
  45
  46 #include <rte_alarm.h>
  47 #include <rte_atomic.h>
  48 #include <rte_branch_prediction.h>
  49 #include <rte_byteorder.h>
  50 #include <rte_common.h>
  51 #include <rte_cycles.h>
  52 #include <rte_debug.h>
  53 #include <rte_dev.h>
  54 #include <rte_eal.h>
  55 #include <rte_ether.h>
  56 #include <rte_ethdev.h>
  57 #include <rte_interrupts.h>
  58 #include <rte_log.h>
  59 #include <rte_memory.h>
  60 #include <rte_memzone.h>
  61 #include <rte_malloc.h>
  62 #include <rte_random.h>
  63 #include <rte_pci.h>
  64 #include <rte_tailq.h>
  65
  66 #include "base/nicvf_plat.h"
  67
  68 #include "nicvf_ethdev.h"
  69
  70 #include "nicvf_logs.h"
  71
  72 static inline int
  73 nicvf_atomic_write_link_status(struct rte_eth_dev *dev,
  74                                struct rte_eth_link *link)
  75 {
  76         struct rte_eth_link *dst = &dev->data->dev_link;
  77         struct rte_eth_link *src = link;
  78
  79         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
  80                 *(uint64_t *)src) == 0)
  81                 return -1;
  82
  83         return 0;
  84 }
  85
  86 static inline void
  87 nicvf_set_eth_link_status(struct nicvf *nic, struct rte_eth_link *link)
  88 {
  89         link->link_status = nic->link_up;
  90         link->link_duplex = ETH_LINK_AUTONEG;
  91         if (nic->duplex == NICVF_HALF_DUPLEX)
  92                 link->link_duplex = ETH_LINK_HALF_DUPLEX;
  93         else if (nic->duplex == NICVF_FULL_DUPLEX)
  94                 link->link_duplex = ETH_LINK_FULL_DUPLEX;
  95         link->link_speed = nic->speed;
  96         link->link_autoneg = ETH_LINK_SPEED_AUTONEG;
  97 }
  98
  99 static void
 100 nicvf_interrupt(void *arg)
 101 {
 102         struct nicvf *nic = arg;
 103
 104         if (nicvf_reg_poll_interrupts(nic) == NIC_MBOX_MSG_BGX_LINK_CHANGE) {
 105                 if (nic->eth_dev->data->dev_conf.intr_conf.lsc)
 106                         nicvf_set_eth_link_status(nic,
 107                                         &nic->eth_dev->data->dev_link);
 108                 _rte_eth_dev_callback_process(nic->eth_dev,
 109                                 RTE_ETH_EVENT_INTR_LSC);
 110         }
 111
 112         rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 113                                 nicvf_interrupt, nic);
 114 }
 115
 116 static int
 117 nicvf_periodic_alarm_start(struct nicvf *nic)
 118 {
 119         return rte_eal_alarm_set(NICVF_INTR_POLL_INTERVAL_MS * 1000,
 120                                         nicvf_interrupt, nic);
 121 }
 122
 123 static int
 124 nicvf_periodic_alarm_stop(struct nicvf *nic)
 125 {
 126         return rte_eal_alarm_cancel(nicvf_interrupt, nic);
 127 }
 128
 129 /*
 130  * Return 0 means link status changed, -1 means not changed
 131  */
 132 static int
 133 nicvf_dev_link_update(struct rte_eth_dev *dev,
 134                       int wait_to_complete __rte_unused)
 135 {
 136         struct rte_eth_link link;
 137         struct nicvf *nic = nicvf_pmd_priv(dev);
 138
 139         PMD_INIT_FUNC_TRACE();
 140
 141         memset(&link, 0, sizeof(link));
 142         nicvf_set_eth_link_status(nic, &link);
 143         return nicvf_atomic_write_link_status(dev, &link);
 144 }
 145
 146 static int
 147 nicvf_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
 148 {
 149         struct nicvf *nic = nicvf_pmd_priv(dev);
 150         uint32_t buffsz, frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
 151
 152         PMD_INIT_FUNC_TRACE();
 153
 154         if (frame_size > NIC_HW_MAX_FRS)
 155                 return -EINVAL;
 156
 157         if (frame_size < NIC_HW_MIN_FRS)
 158                 return -EINVAL;
 159
 160         buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM;
 161
 162         /*
 163          * Refuse mtu that requires the support of scattered packets
 164          * when this feature has not been enabled before.
 165          */
 166         if (!dev->data->scattered_rx &&
 167                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz))
 168                 return -EINVAL;
 169
 170         /* check <seg size> * <max_seg>  >= max_frame */
 171         if (dev->data->scattered_rx &&
 172                 (frame_size + 2 * VLAN_TAG_SIZE > buffsz * NIC_HW_MAX_SEGS))
 173                 return -EINVAL;
 174
 175         if (frame_size > ETHER_MAX_LEN)
 176                 dev->data->dev_conf.rxmode.jumbo_frame = 1;
 177         else
 178                 dev->data->dev_conf.rxmode.jumbo_frame = 0;
 179
 180         if (nicvf_mbox_update_hw_max_frs(nic, frame_size))
 181                 return -EINVAL;
 182
 183         /* Update max frame size */
 184         dev->data->dev_conf.rxmode.max_rx_pkt_len = (uint32_t)frame_size;
 185         nic->mtu = mtu;
 186         return 0;
 187 }
 188
 189 static int
 190 nicvf_dev_get_reg_length(struct rte_eth_dev *dev  __rte_unused)
 191 {
 192         return nicvf_reg_get_count();
 193 }
 194
 195 static int
 196 nicvf_dev_get_regs(struct rte_eth_dev *dev, struct rte_dev_reg_info *regs)
 197 {
 198         uint64_t *data = regs->data;
 199         struct nicvf *nic = nicvf_pmd_priv(dev);
 200
 201         if (data == NULL)
 202                 return -EINVAL;
 203
 204         /* Support only full register dump */
 205         if ((regs->length == 0) ||
 206                 (regs->length == (uint32_t)nicvf_reg_get_count())) {
 207                 regs->version = nic->vendor_id << 16 | nic->device_id;
 208                 nicvf_reg_dump(nic, data);
 209                 return 0;
 210         }
 211         return -ENOTSUP;
 212 }
 213
 214 /* Promiscuous mode enabled by default in LMAC to VF 1:1 map configuration */
 215 static void
 216 nicvf_dev_promisc_enable(struct rte_eth_dev *dev __rte_unused)
 217 {
 218 }
 219
 220 static inline uint64_t
 221 nicvf_rss_ethdev_to_nic(struct nicvf *nic, uint64_t ethdev_rss)
 222 {
 223         uint64_t nic_rss = 0;
 224
 225         if (ethdev_rss & ETH_RSS_IPV4)
 226                 nic_rss |= RSS_IP_ENA;
 227
 228         if (ethdev_rss & ETH_RSS_IPV6)
 229                 nic_rss |= RSS_IP_ENA;
 230
 231         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_UDP)
 232                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 233
 234         if (ethdev_rss & ETH_RSS_NONFRAG_IPV4_TCP)
 235                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 236
 237         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_UDP)
 238                 nic_rss |= (RSS_IP_ENA | RSS_UDP_ENA);
 239
 240         if (ethdev_rss & ETH_RSS_NONFRAG_IPV6_TCP)
 241                 nic_rss |= (RSS_IP_ENA | RSS_TCP_ENA);
 242
 243         if (ethdev_rss & ETH_RSS_PORT)
 244                 nic_rss |= RSS_L2_EXTENDED_HASH_ENA;
 245
 246         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 247                 if (ethdev_rss & ETH_RSS_VXLAN)
 248                         nic_rss |= RSS_TUN_VXLAN_ENA;
 249
 250                 if (ethdev_rss & ETH_RSS_GENEVE)
 251                         nic_rss |= RSS_TUN_GENEVE_ENA;
 252
 253                 if (ethdev_rss & ETH_RSS_NVGRE)
 254                         nic_rss |= RSS_TUN_NVGRE_ENA;
 255         }
 256
 257         return nic_rss;
 258 }
 259
 260 static inline uint64_t
 261 nicvf_rss_nic_to_ethdev(struct nicvf *nic,  uint64_t nic_rss)
 262 {
 263         uint64_t ethdev_rss = 0;
 264
 265         if (nic_rss & RSS_IP_ENA)
 266                 ethdev_rss |= (ETH_RSS_IPV4 | ETH_RSS_IPV6);
 267
 268         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_TCP_ENA))
 269                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_TCP |
 270                                 ETH_RSS_NONFRAG_IPV6_TCP);
 271
 272         if ((nic_rss & RSS_IP_ENA) && (nic_rss & RSS_UDP_ENA))
 273                 ethdev_rss |= (ETH_RSS_NONFRAG_IPV4_UDP |
 274                                 ETH_RSS_NONFRAG_IPV6_UDP);
 275
 276         if (nic_rss & RSS_L2_EXTENDED_HASH_ENA)
 277                 ethdev_rss |= ETH_RSS_PORT;
 278
 279         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING) {
 280                 if (nic_rss & RSS_TUN_VXLAN_ENA)
 281                         ethdev_rss |= ETH_RSS_VXLAN;
 282
 283                 if (nic_rss & RSS_TUN_GENEVE_ENA)
 284                         ethdev_rss |= ETH_RSS_GENEVE;
 285
 286                 if (nic_rss & RSS_TUN_NVGRE_ENA)
 287                         ethdev_rss |= ETH_RSS_NVGRE;
 288         }
 289         return ethdev_rss;
 290 }
 291
 292 static int
 293 nicvf_dev_reta_query(struct rte_eth_dev *dev,
 294                      struct rte_eth_rss_reta_entry64 *reta_conf,
 295                      uint16_t reta_size)
 296 {
 297         struct nicvf *nic = nicvf_pmd_priv(dev);
 298         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 299         int ret, i, j;
 300
 301         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 302                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 303                         "(%d) doesn't match the number hardware can supported "
 304                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 305                 return -EINVAL;
 306         }
 307
 308         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 309         if (ret)
 310                 return ret;
 311
 312         /* Copy RETA table */
 313         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 314                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 315                         if ((reta_conf[i].mask >> j) & 0x01)
 316                                 reta_conf[i].reta[j] = tbl[j];
 317         }
 318
 319         return 0;
 320 }
 321
 322 static int
 323 nicvf_dev_reta_update(struct rte_eth_dev *dev,
 324                       struct rte_eth_rss_reta_entry64 *reta_conf,
 325                       uint16_t reta_size)
 326 {
 327         struct nicvf *nic = nicvf_pmd_priv(dev);
 328         uint8_t tbl[NIC_MAX_RSS_IDR_TBL_SIZE];
 329         int ret, i, j;
 330
 331         if (reta_size != NIC_MAX_RSS_IDR_TBL_SIZE) {
 332                 RTE_LOG(ERR, PMD, "The size of hash lookup table configured "
 333                         "(%d) doesn't match the number hardware can supported "
 334                         "(%d)", reta_size, NIC_MAX_RSS_IDR_TBL_SIZE);
 335                 return -EINVAL;
 336         }
 337
 338         ret = nicvf_rss_reta_query(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 339         if (ret)
 340                 return ret;
 341
 342         /* Copy RETA table */
 343         for (i = 0; i < (NIC_MAX_RSS_IDR_TBL_SIZE / RTE_RETA_GROUP_SIZE); i++) {
 344                 for (j = 0; j < RTE_RETA_GROUP_SIZE; j++)
 345                         if ((reta_conf[i].mask >> j) & 0x01)
 346                                 tbl[j] = reta_conf[i].reta[j];
 347         }
 348
 349         return nicvf_rss_reta_update(nic, tbl, NIC_MAX_RSS_IDR_TBL_SIZE);
 350 }
 351
 352 static int
 353 nicvf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 354                             struct rte_eth_rss_conf *rss_conf)
 355 {
 356         struct nicvf *nic = nicvf_pmd_priv(dev);
 357
 358         if (rss_conf->rss_key)
 359                 nicvf_rss_get_key(nic, rss_conf->rss_key);
 360
 361         rss_conf->rss_key_len =  RSS_HASH_KEY_BYTE_SIZE;
 362         rss_conf->rss_hf = nicvf_rss_nic_to_ethdev(nic, nicvf_rss_get_cfg(nic));
 363         return 0;
 364 }
 365
 366 static int
 367 nicvf_dev_rss_hash_update(struct rte_eth_dev *dev,
 368                           struct rte_eth_rss_conf *rss_conf)
 369 {
 370         struct nicvf *nic = nicvf_pmd_priv(dev);
 371         uint64_t nic_rss;
 372
 373         if (rss_conf->rss_key &&
 374                 rss_conf->rss_key_len != RSS_HASH_KEY_BYTE_SIZE) {
 375                 RTE_LOG(ERR, PMD, "Hash key size mismatch %d",
 376                                 rss_conf->rss_key_len);
 377                 return -EINVAL;
 378         }
 379
 380         if (rss_conf->rss_key)
 381                 nicvf_rss_set_key(nic, rss_conf->rss_key);
 382
 383         nic_rss = nicvf_rss_ethdev_to_nic(nic, rss_conf->rss_hf);
 384         nicvf_rss_set_cfg(nic, nic_rss);
 385         return 0;
 386 }
 387
 388 static int
 389 nicvf_qset_cq_alloc(struct nicvf *nic, struct nicvf_rxq *rxq, uint16_t qidx,
 390                     uint32_t desc_cnt)
 391 {
 392         const struct rte_memzone *rz;
 393         uint32_t ring_size = desc_cnt * sizeof(union cq_entry_t);
 394
 395         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "cq_ring", qidx, ring_size,
 396                                         NICVF_CQ_BASE_ALIGN_BYTES, nic->node);
 397         if (rz == NULL) {
 398                 PMD_INIT_LOG(ERR, "Failed to allocate mem for cq hw ring");
 399                 return -ENOMEM;
 400         }
 401
 402         memset(rz->addr, 0, ring_size);
 403
 404         rxq->phys = rz->phys_addr;
 405         rxq->desc = rz->addr;
 406         rxq->qlen_mask = desc_cnt - 1;
 407
 408         return 0;
 409 }
 410
 411 static int
 412 nicvf_qset_sq_alloc(struct nicvf *nic,  struct nicvf_txq *sq, uint16_t qidx,
 413                     uint32_t desc_cnt)
 414 {
 415         const struct rte_memzone *rz;
 416         uint32_t ring_size = desc_cnt * sizeof(union sq_entry_t);
 417
 418         rz = rte_eth_dma_zone_reserve(nic->eth_dev, "sq", qidx, ring_size,
 419                                 NICVF_SQ_BASE_ALIGN_BYTES, nic->node);
 420         if (rz == NULL) {
 421                 PMD_INIT_LOG(ERR, "Failed allocate mem for sq hw ring");
 422                 return -ENOMEM;
 423         }
 424
 425         memset(rz->addr, 0, ring_size);
 426
 427         sq->phys = rz->phys_addr;
 428         sq->desc = rz->addr;
 429         sq->qlen_mask = desc_cnt - 1;
 430
 431         return 0;
 432 }
 433
 434 static inline void
 435 nicvf_tx_queue_release_mbufs(struct nicvf_txq *txq)
 436 {
 437         uint32_t head;
 438
 439         head = txq->head;
 440         while (head != txq->tail) {
 441                 if (txq->txbuffs[head]) {
 442                         rte_pktmbuf_free_seg(txq->txbuffs[head]);
 443                         txq->txbuffs[head] = NULL;
 444                 }
 445                 head++;
 446                 head = head & txq->qlen_mask;
 447         }
 448 }
 449
 450 static void
 451 nicvf_tx_queue_reset(struct nicvf_txq *txq)
 452 {
 453         uint32_t txq_desc_cnt = txq->qlen_mask + 1;
 454
 455         memset(txq->desc, 0, sizeof(union sq_entry_t) * txq_desc_cnt);
 456         memset(txq->txbuffs, 0, sizeof(struct rte_mbuf *) * txq_desc_cnt);
 457         txq->tail = 0;
 458         txq->head = 0;
 459         txq->xmit_bufs = 0;
 460 }
 461
 462 static void
 463 nicvf_dev_tx_queue_release(void *sq)
 464 {
 465         struct nicvf_txq *txq;
 466
 467         PMD_INIT_FUNC_TRACE();
 468
 469         txq = (struct nicvf_txq *)sq;
 470         if (txq) {
 471                 if (txq->txbuffs != NULL) {
 472                         nicvf_tx_queue_release_mbufs(txq);
 473                         rte_free(txq->txbuffs);
 474                         txq->txbuffs = NULL;
 475                 }
 476                 rte_free(txq);
 477         }
 478 }
 479
 480 static int
 481 nicvf_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 482                          uint16_t nb_desc, unsigned int socket_id,
 483                          const struct rte_eth_txconf *tx_conf)
 484 {
 485         uint16_t tx_free_thresh;
 486         uint8_t is_single_pool;
 487         struct nicvf_txq *txq;
 488         struct nicvf *nic = nicvf_pmd_priv(dev);
 489
 490         PMD_INIT_FUNC_TRACE();
 491
 492         /* Socket id check */
 493         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 494                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 495                 socket_id, nic->node);
 496
 497         /* Tx deferred start is not supported */
 498         if (tx_conf->tx_deferred_start) {
 499                 PMD_INIT_LOG(ERR, "Tx deferred start not supported");
 500                 return -EINVAL;
 501         }
 502
 503         /* Roundup nb_desc to available qsize and validate max number of desc */
 504         nb_desc = nicvf_qsize_sq_roundup(nb_desc);
 505         if (nb_desc == 0) {
 506                 PMD_INIT_LOG(ERR, "Value of nb_desc beyond available sq qsize");
 507                 return -EINVAL;
 508         }
 509
 510         /* Validate tx_free_thresh */
 511         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 512                                 tx_conf->tx_free_thresh :
 513                                 NICVF_DEFAULT_TX_FREE_THRESH);
 514
 515         if (tx_free_thresh > (nb_desc) ||
 516                 tx_free_thresh > NICVF_MAX_TX_FREE_THRESH) {
 517                 PMD_INIT_LOG(ERR,
 518                         "tx_free_thresh must be less than the number of TX "
 519                         "descriptors. (tx_free_thresh=%u port=%d "
 520                         "queue=%d)", (unsigned int)tx_free_thresh,
 521                         (int)dev->data->port_id, (int)qidx);
 522                 return -EINVAL;
 523         }
 524
 525         /* Free memory prior to re-allocation if needed. */
 526         if (dev->data->tx_queues[qidx] != NULL) {
 527                 PMD_TX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 528                                 qidx);
 529                 nicvf_dev_tx_queue_release(dev->data->tx_queues[qidx]);
 530                 dev->data->tx_queues[qidx] = NULL;
 531         }
 532
 533         /* Allocating tx queue data structure */
 534         txq = rte_zmalloc_socket("ethdev TX queue", sizeof(struct nicvf_txq),
 535                                         RTE_CACHE_LINE_SIZE, nic->node);
 536         if (txq == NULL) {
 537                 PMD_INIT_LOG(ERR, "Failed to allocate txq=%d", qidx);
 538                 return -ENOMEM;
 539         }
 540
 541         txq->nic = nic;
 542         txq->queue_id = qidx;
 543         txq->tx_free_thresh = tx_free_thresh;
 544         txq->txq_flags = tx_conf->txq_flags;
 545         txq->sq_head = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_HEAD;
 546         txq->sq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_SQ_0_7_DOOR;
 547         is_single_pool = (txq->txq_flags & ETH_TXQ_FLAGS_NOREFCOUNT &&
 548                                 txq->txq_flags & ETH_TXQ_FLAGS_NOMULTMEMP);
 549
 550         /* Choose optimum free threshold value for multipool case */
 551         if (!is_single_pool) {
 552                 txq->tx_free_thresh = (uint16_t)
 553                 (tx_conf->tx_free_thresh == NICVF_DEFAULT_TX_FREE_THRESH ?
 554                                 NICVF_TX_FREE_MPOOL_THRESH :
 555                                 tx_conf->tx_free_thresh);
 556         }
 557
 558         /* Allocate software ring */
 559         txq->txbuffs = rte_zmalloc_socket("txq->txbuffs",
 560                                 nb_desc * sizeof(struct rte_mbuf *),
 561                                 RTE_CACHE_LINE_SIZE, nic->node);
 562
 563         if (txq->txbuffs == NULL) {
 564                 nicvf_dev_tx_queue_release(txq);
 565                 return -ENOMEM;
 566         }
 567
 568         if (nicvf_qset_sq_alloc(nic, txq, qidx, nb_desc)) {
 569                 PMD_INIT_LOG(ERR, "Failed to allocate mem for sq %d", qidx);
 570                 nicvf_dev_tx_queue_release(txq);
 571                 return -ENOMEM;
 572         }
 573
 574         nicvf_tx_queue_reset(txq);
 575
 576         PMD_TX_LOG(DEBUG, "[%d] txq=%p nb_desc=%d desc=%p phys=0x%" PRIx64,
 577                         qidx, txq, nb_desc, txq->desc, txq->phys);
 578
 579         dev->data->tx_queues[qidx] = txq;
 580         dev->data->tx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 581         return 0;
 582 }
 583
 584 static void
 585 nicvf_rx_queue_reset(struct nicvf_rxq *rxq)
 586 {
 587         rxq->head = 0;
 588         rxq->available_space = 0;
 589         rxq->recv_buffers = 0;
 590 }
 591
 592 static void
 593 nicvf_dev_rx_queue_release(void *rx_queue)
 594 {
 595         struct nicvf_rxq *rxq = rx_queue;
 596
 597         PMD_INIT_FUNC_TRACE();
 598
 599         if (rxq)
 600                 rte_free(rxq);
 601 }
 602
 603 static int
 604 nicvf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t qidx,
 605                          uint16_t nb_desc, unsigned int socket_id,
 606                          const struct rte_eth_rxconf *rx_conf,
 607                          struct rte_mempool *mp)
 608 {
 609         uint16_t rx_free_thresh;
 610         struct nicvf_rxq *rxq;
 611         struct nicvf *nic = nicvf_pmd_priv(dev);
 612
 613         PMD_INIT_FUNC_TRACE();
 614
 615         /* Socket id check */
 616         if (socket_id != (unsigned int)SOCKET_ID_ANY && socket_id != nic->node)
 617                 PMD_DRV_LOG(WARNING, "socket_id expected %d, configured %d",
 618                 socket_id, nic->node);
 619
 620         /* Mempool memory should be contiguous */
 621         if (mp->nb_mem_chunks != 1) {
 622                 PMD_INIT_LOG(ERR, "Non contiguous mempool, check huge page sz");
 623                 return -EINVAL;
 624         }
 625
 626         /* Rx deferred start is not supported */
 627         if (rx_conf->rx_deferred_start) {
 628                 PMD_INIT_LOG(ERR, "Rx deferred start not supported");
 629                 return -EINVAL;
 630         }
 631
 632         /* Roundup nb_desc to available qsize and validate max number of desc */
 633         nb_desc = nicvf_qsize_cq_roundup(nb_desc);
 634         if (nb_desc == 0) {
 635                 PMD_INIT_LOG(ERR, "Value nb_desc beyond available hw cq qsize");
 636                 return -EINVAL;
 637         }
 638
 639         /* Check rx_free_thresh upper bound */
 640         rx_free_thresh = (uint16_t)((rx_conf->rx_free_thresh) ?
 641                                 rx_conf->rx_free_thresh :
 642                                 NICVF_DEFAULT_RX_FREE_THRESH);
 643         if (rx_free_thresh > NICVF_MAX_RX_FREE_THRESH ||
 644                 rx_free_thresh >= nb_desc * .75) {
 645                 PMD_INIT_LOG(ERR, "rx_free_thresh greater than expected %d",
 646                                 rx_free_thresh);
 647                 return -EINVAL;
 648         }
 649
 650         /* Free memory prior to re-allocation if needed */
 651         if (dev->data->rx_queues[qidx] != NULL) {
 652                 PMD_RX_LOG(DEBUG, "Freeing memory prior to re-allocation %d",
 653                                 qidx);
 654                 nicvf_dev_rx_queue_release(dev->data->rx_queues[qidx]);
 655                 dev->data->rx_queues[qidx] = NULL;
 656         }
 657
 658         /* Allocate rxq memory */
 659         rxq = rte_zmalloc_socket("ethdev rx queue", sizeof(struct nicvf_rxq),
 660                                         RTE_CACHE_LINE_SIZE, nic->node);
 661         if (rxq == NULL) {
 662                 PMD_INIT_LOG(ERR, "Failed to allocate rxq=%d", qidx);
 663                 return -ENOMEM;
 664         }
 665
 666         rxq->nic = nic;
 667         rxq->pool = mp;
 668         rxq->queue_id = qidx;
 669         rxq->port_id = dev->data->port_id;
 670         rxq->rx_free_thresh = rx_free_thresh;
 671         rxq->rx_drop_en = rx_conf->rx_drop_en;
 672         rxq->cq_status = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_STATUS;
 673         rxq->cq_door = nicvf_qset_base(nic, qidx) + NIC_QSET_CQ_0_7_DOOR;
 674         rxq->precharge_cnt = 0;
 675         rxq->rbptr_offset = NICVF_CQE_RBPTR_WORD;
 676
 677         /* Alloc completion queue */
 678         if (nicvf_qset_cq_alloc(nic, rxq, rxq->queue_id, nb_desc)) {
 679                 PMD_INIT_LOG(ERR, "failed to allocate cq %u", rxq->queue_id);
 680                 nicvf_dev_rx_queue_release(rxq);
 681                 return -ENOMEM;
 682         }
 683
 684         nicvf_rx_queue_reset(rxq);
 685
 686         PMD_RX_LOG(DEBUG, "[%d] rxq=%p pool=%s nb_desc=(%d/%d) phy=%" PRIx64,
 687                         qidx, rxq, mp->name, nb_desc,
 688                         rte_mempool_count(mp), rxq->phys);
 689
 690         dev->data->rx_queues[qidx] = rxq;
 691         dev->data->rx_queue_state[qidx] = RTE_ETH_QUEUE_STATE_STOPPED;
 692         return 0;
 693 }
 694
 695 static void
 696 nicvf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
 697 {
 698         struct nicvf *nic = nicvf_pmd_priv(dev);
 699
 700         PMD_INIT_FUNC_TRACE();
 701
 702         dev_info->min_rx_bufsize = ETHER_MIN_MTU;
 703         dev_info->max_rx_pktlen = NIC_HW_MAX_FRS;
 704         dev_info->max_rx_queues = (uint16_t)MAX_RCV_QUEUES_PER_QS;
 705         dev_info->max_tx_queues = (uint16_t)MAX_SND_QUEUES_PER_QS;
 706         dev_info->max_mac_addrs = 1;
 707         dev_info->max_vfs = dev->pci_dev->max_vfs;
 708
 709         dev_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP;
 710         dev_info->tx_offload_capa =
 711                 DEV_TX_OFFLOAD_IPV4_CKSUM  |
 712                 DEV_TX_OFFLOAD_UDP_CKSUM   |
 713                 DEV_TX_OFFLOAD_TCP_CKSUM   |
 714                 DEV_TX_OFFLOAD_TCP_TSO     |
 715                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
 716
 717         dev_info->reta_size = nic->rss_info.rss_size;
 718         dev_info->hash_key_size = RSS_HASH_KEY_BYTE_SIZE;
 719         dev_info->flow_type_rss_offloads = NICVF_RSS_OFFLOAD_PASS1;
 720         if (nicvf_hw_cap(nic) & NICVF_CAP_TUNNEL_PARSING)
 721                 dev_info->flow_type_rss_offloads |= NICVF_RSS_OFFLOAD_TUNNEL;
 722
 723         dev_info->default_rxconf = (struct rte_eth_rxconf) {
 724                 .rx_free_thresh = NICVF_DEFAULT_RX_FREE_THRESH,
 725                 .rx_drop_en = 0,
 726         };
 727
 728         dev_info->default_txconf = (struct rte_eth_txconf) {
 729                 .tx_free_thresh = NICVF_DEFAULT_TX_FREE_THRESH,
 730                 .txq_flags =
 731                         ETH_TXQ_FLAGS_NOMULTSEGS  |
 732                         ETH_TXQ_FLAGS_NOREFCOUNT  |
 733                         ETH_TXQ_FLAGS_NOMULTMEMP  |
 734                         ETH_TXQ_FLAGS_NOVLANOFFL  |
 735                         ETH_TXQ_FLAGS_NOXSUMSCTP,
 736         };
 737 }
 738
 739 static int
 740 nicvf_dev_configure(struct rte_eth_dev *dev)
 741 {
 742         struct rte_eth_conf *conf = &dev->data->dev_conf;
 743         struct rte_eth_rxmode *rxmode = &conf->rxmode;
 744         struct rte_eth_txmode *txmode = &conf->txmode;
 745         struct nicvf *nic = nicvf_pmd_priv(dev);
 746
 747         PMD_INIT_FUNC_TRACE();
 748
 749         if (!rte_eal_has_hugepages()) {
 750                 PMD_INIT_LOG(INFO, "Huge page is not configured");
 751                 return -EINVAL;
 752         }
 753
 754         if (txmode->mq_mode) {
 755                 PMD_INIT_LOG(INFO, "Tx mq_mode DCB or VMDq not supported");
 756                 return -EINVAL;
 757         }
 758
 759         if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
 760                 rxmode->mq_mode != ETH_MQ_RX_RSS) {
 761                 PMD_INIT_LOG(INFO, "Unsupported rx qmode %d", rxmode->mq_mode);
 762                 return -EINVAL;
 763         }
 764
 765         if (!rxmode->hw_strip_crc) {
 766                 PMD_INIT_LOG(NOTICE, "Can't disable hw crc strip");
 767                 rxmode->hw_strip_crc = 1;
 768         }
 769
 770         if (rxmode->hw_ip_checksum) {
 771                 PMD_INIT_LOG(NOTICE, "Rxcksum not supported");
 772                 rxmode->hw_ip_checksum = 0;
 773         }
 774
 775         if (rxmode->split_hdr_size) {
 776                 PMD_INIT_LOG(INFO, "Rxmode does not support split header");
 777                 return -EINVAL;
 778         }
 779
 780         if (rxmode->hw_vlan_filter) {
 781                 PMD_INIT_LOG(INFO, "VLAN filter not supported");
 782                 return -EINVAL;
 783         }
 784
 785         if (rxmode->hw_vlan_extend) {
 786                 PMD_INIT_LOG(INFO, "VLAN extended not supported");
 787                 return -EINVAL;
 788         }
 789
 790         if (rxmode->enable_lro) {
 791                 PMD_INIT_LOG(INFO, "LRO not supported");
 792                 return -EINVAL;
 793         }
 794
 795         if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
 796                 PMD_INIT_LOG(INFO, "Setting link speed/duplex not supported");
 797                 return -EINVAL;
 798         }
 799
 800         if (conf->dcb_capability_en) {
 801                 PMD_INIT_LOG(INFO, "DCB enable not supported");
 802                 return -EINVAL;
 803         }
 804
 805         if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
 806                 PMD_INIT_LOG(INFO, "Flow director not supported");
 807                 return -EINVAL;
 808         }
 809
 810         PMD_INIT_LOG(DEBUG, "Configured ethdev port%d hwcap=0x%" PRIx64,
 811                 dev->data->port_id, nicvf_hw_cap(nic));
 812
 813         return 0;
 814 }
 815
 816 /* Initialize and register driver with DPDK Application */
 817 static const struct eth_dev_ops nicvf_eth_dev_ops = {
 818         .dev_configure            = nicvf_dev_configure,
 819         .link_update              = nicvf_dev_link_update,
 820         .promiscuous_enable       = nicvf_dev_promisc_enable,
 821         .dev_infos_get            = nicvf_dev_info_get,
 822         .mtu_set                  = nicvf_dev_set_mtu,
 823         .reta_update              = nicvf_dev_reta_update,
 824         .reta_query               = nicvf_dev_reta_query,
 825         .rss_hash_update          = nicvf_dev_rss_hash_update,
 826         .rss_hash_conf_get        = nicvf_dev_rss_hash_conf_get,
 827         .rx_queue_setup           = nicvf_dev_rx_queue_setup,
 828         .rx_queue_release         = nicvf_dev_rx_queue_release,
 829         .tx_queue_setup           = nicvf_dev_tx_queue_setup,
 830         .tx_queue_release         = nicvf_dev_tx_queue_release,
 831         .get_reg_length           = nicvf_dev_get_reg_length,
 832         .get_reg                  = nicvf_dev_get_regs,
 833 };
 834
 835 static int
 836 nicvf_eth_dev_init(struct rte_eth_dev *eth_dev)
 837 {
 838         int ret;
 839         struct rte_pci_device *pci_dev;
 840         struct nicvf *nic = nicvf_pmd_priv(eth_dev);
 841
 842         PMD_INIT_FUNC_TRACE();
 843
 844         eth_dev->dev_ops = &nicvf_eth_dev_ops;
 845
 846         pci_dev = eth_dev->pci_dev;
 847         rte_eth_copy_pci_info(eth_dev, pci_dev);
 848
 849         nic->device_id = pci_dev->id.device_id;
 850         nic->vendor_id = pci_dev->id.vendor_id;
 851         nic->subsystem_device_id = pci_dev->id.subsystem_device_id;
 852         nic->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 853         nic->eth_dev = eth_dev;
 854
 855         PMD_INIT_LOG(DEBUG, "nicvf: device (%x:%x) %u:%u:%u:%u",
 856                         pci_dev->id.vendor_id, pci_dev->id.device_id,
 857                         pci_dev->addr.domain, pci_dev->addr.bus,
 858                         pci_dev->addr.devid, pci_dev->addr.function);
 859
 860         nic->reg_base = (uintptr_t)pci_dev->mem_resource[0].addr;
 861         if (!nic->reg_base) {
 862                 PMD_INIT_LOG(ERR, "Failed to map BAR0");
 863                 ret = -ENODEV;
 864                 goto fail;
 865         }
 866
 867         nicvf_disable_all_interrupts(nic);
 868
 869         ret = nicvf_periodic_alarm_start(nic);
 870         if (ret) {
 871                 PMD_INIT_LOG(ERR, "Failed to start period alarm");
 872                 goto fail;
 873         }
 874
 875         ret = nicvf_mbox_check_pf_ready(nic);
 876         if (ret) {
 877                 PMD_INIT_LOG(ERR, "Failed to get ready message from PF");
 878                 goto alarm_fail;
 879         } else {
 880                 PMD_INIT_LOG(INFO,
 881                         "node=%d vf=%d mode=%s sqs=%s loopback_supported=%s",
 882                         nic->node, nic->vf_id,
 883                         nic->tns_mode == NIC_TNS_MODE ? "tns" : "tns-bypass",
 884                         nic->sqs_mode ? "true" : "false",
 885                         nic->loopback_supported ? "true" : "false"
 886                         );
 887         }
 888
 889         if (nic->sqs_mode) {
 890                 PMD_INIT_LOG(INFO, "Unsupported SQS VF detected, Detaching...");
 891                 /* Detach port by returning Positive error number */
 892                 ret = ENOTSUP;
 893                 goto alarm_fail;
 894         }
 895
 896         eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", ETHER_ADDR_LEN, 0);
 897         if (eth_dev->data->mac_addrs == NULL) {
 898                 PMD_INIT_LOG(ERR, "Failed to allocate memory for mac addr");
 899                 ret = -ENOMEM;
 900                 goto alarm_fail;
 901         }
 902         if (is_zero_ether_addr((struct ether_addr *)nic->mac_addr))
 903                 eth_random_addr(&nic->mac_addr[0]);
 904
 905         ether_addr_copy((struct ether_addr *)nic->mac_addr,
 906                         &eth_dev->data->mac_addrs[0]);
 907
 908         ret = nicvf_mbox_set_mac_addr(nic, nic->mac_addr);
 909         if (ret) {
 910                 PMD_INIT_LOG(ERR, "Failed to set mac addr");
 911                 goto malloc_fail;
 912         }
 913
 914         ret = nicvf_base_init(nic);
 915         if (ret) {
 916                 PMD_INIT_LOG(ERR, "Failed to execute nicvf_base_init");
 917                 goto malloc_fail;
 918         }
 919
 920         ret = nicvf_mbox_get_rss_size(nic);
 921         if (ret) {
 922                 PMD_INIT_LOG(ERR, "Failed to get rss table size");
 923                 goto malloc_fail;
 924         }
 925
 926         PMD_INIT_LOG(INFO, "Port %d (%x:%x) mac=%02x:%02x:%02x:%02x:%02x:%02x",
 927                 eth_dev->data->port_id, nic->vendor_id, nic->device_id,
 928                 nic->mac_addr[0], nic->mac_addr[1], nic->mac_addr[2],
 929                 nic->mac_addr[3], nic->mac_addr[4], nic->mac_addr[5]);
 930
 931         return 0;
 932
 933 malloc_fail:
 934         rte_free(eth_dev->data->mac_addrs);
 935 alarm_fail:
 936         nicvf_periodic_alarm_stop(nic);
 937 fail:
 938         return ret;
 939 }
 940
 941 static const struct rte_pci_id pci_id_nicvf_map[] = {
 942         {
 943                 .class_id = RTE_CLASS_ANY_ID,
 944                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
 945                 .device_id = PCI_DEVICE_ID_THUNDERX_PASS1_NICVF,
 946                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 947                 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS1_NICVF,
 948         },
 949         {
 950                 .class_id = RTE_CLASS_ANY_ID,
 951                 .vendor_id = PCI_VENDOR_ID_CAVIUM,
 952                 .device_id = PCI_DEVICE_ID_THUNDERX_PASS2_NICVF,
 953                 .subsystem_vendor_id = PCI_VENDOR_ID_CAVIUM,
 954                 .subsystem_device_id = PCI_SUB_DEVICE_ID_THUNDERX_PASS2_NICVF,
 955         },
 956         {
 957                 .vendor_id = 0,
 958         },
 959 };
 960
 961 static struct eth_driver rte_nicvf_pmd = {
 962         .pci_drv = {
 963                 .name = "rte_nicvf_pmd",
 964                 .id_table = pci_id_nicvf_map,
 965                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 966         },
 967         .eth_dev_init = nicvf_eth_dev_init,
 968         .dev_private_size = sizeof(struct nicvf),
 969 };
 970
 971 static int
 972 rte_nicvf_pmd_init(const char *name __rte_unused, const char *para __rte_unused)
 973 {
 974         PMD_INIT_FUNC_TRACE();
 975         PMD_INIT_LOG(INFO, "librte_pmd_thunderx nicvf version %s",
 976                         THUNDERX_NICVF_PMD_VERSION);
 977
 978         rte_eth_driver_register(&rte_nicvf_pmd);
 979         return 0;
 980 }
 981
 982 static struct rte_driver rte_nicvf_driver = {
 983         .name = "nicvf_driver",
 984         .type = PMD_PDEV,
 985         .init = rte_nicvf_pmd_init,
 986 };
 987
 988 PMD_REGISTER_DRIVER(rte_nicvf_driver);