drivers/net/txgbe/txgbe_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2020 Beijing WangXun Technology Co., Ltd.
   3  * Copyright(c) 2010-2017 Intel Corporation
   4  */
   5
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <rte_common.h>
  11 #include <ethdev_pci.h>
  12
  13 #include <rte_interrupts.h>
  14 #include <rte_log.h>
  15 #include <rte_debug.h>
  16 #include <rte_pci.h>
  17 #include <rte_memory.h>
  18 #include <rte_eal.h>
  19 #include <rte_alarm.h>
  20 #include <rte_kvargs.h>
  21
  22 #include "txgbe_logs.h"
  23 #include "base/txgbe.h"
  24 #include "txgbe_ethdev.h"
  25 #include "txgbe_rxtx.h"
  26 #include "txgbe_regs_group.h"
  27
  28 static const struct reg_info txgbe_regs_general[] = {
  29         {TXGBE_RST, 1, 1, "TXGBE_RST"},
  30         {TXGBE_STAT, 1, 1, "TXGBE_STAT"},
  31         {TXGBE_PORTCTL, 1, 1, "TXGBE_PORTCTL"},
  32         {TXGBE_SDP, 1, 1, "TXGBE_SDP"},
  33         {TXGBE_SDPCTL, 1, 1, "TXGBE_SDPCTL"},
  34         {TXGBE_LEDCTL, 1, 1, "TXGBE_LEDCTL"},
  35         {0, 0, 0, ""}
  36 };
  37
  38 static const struct reg_info txgbe_regs_nvm[] = {
  39         {0, 0, 0, ""}
  40 };
  41
  42 static const struct reg_info txgbe_regs_interrupt[] = {
  43         {0, 0, 0, ""}
  44 };
  45
  46 static const struct reg_info txgbe_regs_fctl_others[] = {
  47         {0, 0, 0, ""}
  48 };
  49
  50 static const struct reg_info txgbe_regs_rxdma[] = {
  51         {0, 0, 0, ""}
  52 };
  53
  54 static const struct reg_info txgbe_regs_rx[] = {
  55         {0, 0, 0, ""}
  56 };
  57
  58 static struct reg_info txgbe_regs_tx[] = {
  59         {0, 0, 0, ""}
  60 };
  61
  62 static const struct reg_info txgbe_regs_wakeup[] = {
  63         {0, 0, 0, ""}
  64 };
  65
  66 static const struct reg_info txgbe_regs_dcb[] = {
  67         {0, 0, 0, ""}
  68 };
  69
  70 static const struct reg_info txgbe_regs_mac[] = {
  71         {0, 0, 0, ""}
  72 };
  73
  74 static const struct reg_info txgbe_regs_diagnostic[] = {
  75         {0, 0, 0, ""},
  76 };
  77
  78 /* PF registers */
  79 static const struct reg_info *txgbe_regs_others[] = {
  80                                 txgbe_regs_general,
  81                                 txgbe_regs_nvm,
  82                                 txgbe_regs_interrupt,
  83                                 txgbe_regs_fctl_others,
  84                                 txgbe_regs_rxdma,
  85                                 txgbe_regs_rx,
  86                                 txgbe_regs_tx,
  87                                 txgbe_regs_wakeup,
  88                                 txgbe_regs_dcb,
  89                                 txgbe_regs_mac,
  90                                 txgbe_regs_diagnostic,
  91                                 NULL};
  92
  93 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev);
  94 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev);
  95 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev);
  96 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev);
  97 static int  txgbe_dev_set_link_up(struct rte_eth_dev *dev);
  98 static int  txgbe_dev_set_link_down(struct rte_eth_dev *dev);
  99 static int txgbe_dev_close(struct rte_eth_dev *dev);
 100 static int txgbe_dev_link_update(struct rte_eth_dev *dev,
 101                                 int wait_to_complete);
 102 static int txgbe_dev_stats_reset(struct rte_eth_dev *dev);
 103 static void txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue);
 104 static void txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev,
 105                                         uint16_t queue);
 106
 107 static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
 108 static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
 109 static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
 110 static int txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev);
 111 static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
 112 static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
 113 static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
 114                                       struct rte_intr_handle *handle);
 115 static void txgbe_dev_interrupt_handler(void *param);
 116 static void txgbe_dev_interrupt_delayed_handler(void *param);
 117 static void txgbe_configure_msix(struct rte_eth_dev *dev);
 118
 119 static int txgbe_filter_restore(struct rte_eth_dev *dev);
 120 static void txgbe_l2_tunnel_conf(struct rte_eth_dev *dev);
 121
 122 #define TXGBE_SET_HWSTRIP(h, q) do {\
 123                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 124                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 125                 (h)->bitmap[idx] |= 1 << bit;\
 126         } while (0)
 127
 128 #define TXGBE_CLEAR_HWSTRIP(h, q) do {\
 129                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 130                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 131                 (h)->bitmap[idx] &= ~(1 << bit);\
 132         } while (0)
 133
 134 #define TXGBE_GET_HWSTRIP(h, q, r) do {\
 135                 uint32_t idx = (q) / (sizeof((h)->bitmap[0]) * NBBY); \
 136                 uint32_t bit = (q) % (sizeof((h)->bitmap[0]) * NBBY); \
 137                 (r) = (h)->bitmap[idx] >> bit & 1;\
 138         } while (0)
 139
 140 /*
 141  * The set of PCI devices this driver supports
 142  */
 143 static const struct rte_pci_id pci_id_txgbe_map[] = {
 144         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_SP1000) },
 145         { RTE_PCI_DEVICE(PCI_VENDOR_ID_WANGXUN, TXGBE_DEV_ID_WX1820) },
 146         { .vendor_id = 0, /* sentinel */ },
 147 };
 148
 149 static const struct rte_eth_desc_lim rx_desc_lim = {
 150         .nb_max = TXGBE_RING_DESC_MAX,
 151         .nb_min = TXGBE_RING_DESC_MIN,
 152         .nb_align = TXGBE_RXD_ALIGN,
 153 };
 154
 155 static const struct rte_eth_desc_lim tx_desc_lim = {
 156         .nb_max = TXGBE_RING_DESC_MAX,
 157         .nb_min = TXGBE_RING_DESC_MIN,
 158         .nb_align = TXGBE_TXD_ALIGN,
 159         .nb_seg_max = TXGBE_TX_MAX_SEG,
 160         .nb_mtu_seg_max = TXGBE_TX_MAX_SEG,
 161 };
 162
 163 static const struct eth_dev_ops txgbe_eth_dev_ops;
 164
 165 #define HW_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, m)}
 166 #define HW_XSTAT_NAME(m, n) {n, offsetof(struct txgbe_hw_stats, m)}
 167 static const struct rte_txgbe_xstats_name_off rte_txgbe_stats_strings[] = {
 168         /* MNG RxTx */
 169         HW_XSTAT(mng_bmc2host_packets),
 170         HW_XSTAT(mng_host2bmc_packets),
 171         /* Basic RxTx */
 172         HW_XSTAT(rx_packets),
 173         HW_XSTAT(tx_packets),
 174         HW_XSTAT(rx_bytes),
 175         HW_XSTAT(tx_bytes),
 176         HW_XSTAT(rx_total_bytes),
 177         HW_XSTAT(rx_total_packets),
 178         HW_XSTAT(tx_total_packets),
 179         HW_XSTAT(rx_total_missed_packets),
 180         HW_XSTAT(rx_broadcast_packets),
 181         HW_XSTAT(rx_multicast_packets),
 182         HW_XSTAT(rx_management_packets),
 183         HW_XSTAT(tx_management_packets),
 184         HW_XSTAT(rx_management_dropped),
 185
 186         /* Basic Error */
 187         HW_XSTAT(rx_crc_errors),
 188         HW_XSTAT(rx_illegal_byte_errors),
 189         HW_XSTAT(rx_error_bytes),
 190         HW_XSTAT(rx_mac_short_packet_dropped),
 191         HW_XSTAT(rx_length_errors),
 192         HW_XSTAT(rx_undersize_errors),
 193         HW_XSTAT(rx_fragment_errors),
 194         HW_XSTAT(rx_oversize_errors),
 195         HW_XSTAT(rx_jabber_errors),
 196         HW_XSTAT(rx_l3_l4_xsum_error),
 197         HW_XSTAT(mac_local_errors),
 198         HW_XSTAT(mac_remote_errors),
 199
 200         /* Flow Director */
 201         HW_XSTAT(flow_director_added_filters),
 202         HW_XSTAT(flow_director_removed_filters),
 203         HW_XSTAT(flow_director_filter_add_errors),
 204         HW_XSTAT(flow_director_filter_remove_errors),
 205         HW_XSTAT(flow_director_matched_filters),
 206         HW_XSTAT(flow_director_missed_filters),
 207
 208         /* FCoE */
 209         HW_XSTAT(rx_fcoe_crc_errors),
 210         HW_XSTAT(rx_fcoe_mbuf_allocation_errors),
 211         HW_XSTAT(rx_fcoe_dropped),
 212         HW_XSTAT(rx_fcoe_packets),
 213         HW_XSTAT(tx_fcoe_packets),
 214         HW_XSTAT(rx_fcoe_bytes),
 215         HW_XSTAT(tx_fcoe_bytes),
 216         HW_XSTAT(rx_fcoe_no_ddp),
 217         HW_XSTAT(rx_fcoe_no_ddp_ext_buff),
 218
 219         /* MACSEC */
 220         HW_XSTAT(tx_macsec_pkts_untagged),
 221         HW_XSTAT(tx_macsec_pkts_encrypted),
 222         HW_XSTAT(tx_macsec_pkts_protected),
 223         HW_XSTAT(tx_macsec_octets_encrypted),
 224         HW_XSTAT(tx_macsec_octets_protected),
 225         HW_XSTAT(rx_macsec_pkts_untagged),
 226         HW_XSTAT(rx_macsec_pkts_badtag),
 227         HW_XSTAT(rx_macsec_pkts_nosci),
 228         HW_XSTAT(rx_macsec_pkts_unknownsci),
 229         HW_XSTAT(rx_macsec_octets_decrypted),
 230         HW_XSTAT(rx_macsec_octets_validated),
 231         HW_XSTAT(rx_macsec_sc_pkts_unchecked),
 232         HW_XSTAT(rx_macsec_sc_pkts_delayed),
 233         HW_XSTAT(rx_macsec_sc_pkts_late),
 234         HW_XSTAT(rx_macsec_sa_pkts_ok),
 235         HW_XSTAT(rx_macsec_sa_pkts_invalid),
 236         HW_XSTAT(rx_macsec_sa_pkts_notvalid),
 237         HW_XSTAT(rx_macsec_sa_pkts_unusedsa),
 238         HW_XSTAT(rx_macsec_sa_pkts_notusingsa),
 239
 240         /* MAC RxTx */
 241         HW_XSTAT(rx_size_64_packets),
 242         HW_XSTAT(rx_size_65_to_127_packets),
 243         HW_XSTAT(rx_size_128_to_255_packets),
 244         HW_XSTAT(rx_size_256_to_511_packets),
 245         HW_XSTAT(rx_size_512_to_1023_packets),
 246         HW_XSTAT(rx_size_1024_to_max_packets),
 247         HW_XSTAT(tx_size_64_packets),
 248         HW_XSTAT(tx_size_65_to_127_packets),
 249         HW_XSTAT(tx_size_128_to_255_packets),
 250         HW_XSTAT(tx_size_256_to_511_packets),
 251         HW_XSTAT(tx_size_512_to_1023_packets),
 252         HW_XSTAT(tx_size_1024_to_max_packets),
 253
 254         /* Flow Control */
 255         HW_XSTAT(tx_xon_packets),
 256         HW_XSTAT(rx_xon_packets),
 257         HW_XSTAT(tx_xoff_packets),
 258         HW_XSTAT(rx_xoff_packets),
 259
 260         HW_XSTAT_NAME(tx_xon_packets, "tx_flow_control_xon_packets"),
 261         HW_XSTAT_NAME(rx_xon_packets, "rx_flow_control_xon_packets"),
 262         HW_XSTAT_NAME(tx_xoff_packets, "tx_flow_control_xoff_packets"),
 263         HW_XSTAT_NAME(rx_xoff_packets, "rx_flow_control_xoff_packets"),
 264 };
 265
 266 #define TXGBE_NB_HW_STATS (sizeof(rte_txgbe_stats_strings) / \
 267                            sizeof(rte_txgbe_stats_strings[0]))
 268
 269 /* Per-priority statistics */
 270 #define UP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, up[0].m)}
 271 static const struct rte_txgbe_xstats_name_off rte_txgbe_up_strings[] = {
 272         UP_XSTAT(rx_up_packets),
 273         UP_XSTAT(tx_up_packets),
 274         UP_XSTAT(rx_up_bytes),
 275         UP_XSTAT(tx_up_bytes),
 276         UP_XSTAT(rx_up_drop_packets),
 277
 278         UP_XSTAT(tx_up_xon_packets),
 279         UP_XSTAT(rx_up_xon_packets),
 280         UP_XSTAT(tx_up_xoff_packets),
 281         UP_XSTAT(rx_up_xoff_packets),
 282         UP_XSTAT(rx_up_dropped),
 283         UP_XSTAT(rx_up_mbuf_alloc_errors),
 284         UP_XSTAT(tx_up_xon2off_packets),
 285 };
 286
 287 #define TXGBE_NB_UP_STATS (sizeof(rte_txgbe_up_strings) / \
 288                            sizeof(rte_txgbe_up_strings[0]))
 289
 290 /* Per-queue statistics */
 291 #define QP_XSTAT(m) {#m, offsetof(struct txgbe_hw_stats, qp[0].m)}
 292 static const struct rte_txgbe_xstats_name_off rte_txgbe_qp_strings[] = {
 293         QP_XSTAT(rx_qp_packets),
 294         QP_XSTAT(tx_qp_packets),
 295         QP_XSTAT(rx_qp_bytes),
 296         QP_XSTAT(tx_qp_bytes),
 297         QP_XSTAT(rx_qp_mc_packets),
 298 };
 299
 300 #define TXGBE_NB_QP_STATS (sizeof(rte_txgbe_qp_strings) / \
 301                            sizeof(rte_txgbe_qp_strings[0]))
 302
 303 static inline int
 304 txgbe_is_sfp(struct txgbe_hw *hw)
 305 {
 306         switch (hw->phy.type) {
 307         case txgbe_phy_sfp_avago:
 308         case txgbe_phy_sfp_ftl:
 309         case txgbe_phy_sfp_intel:
 310         case txgbe_phy_sfp_unknown:
 311         case txgbe_phy_sfp_tyco_passive:
 312         case txgbe_phy_sfp_unknown_passive:
 313                 return 1;
 314         default:
 315                 return 0;
 316         }
 317 }
 318
 319 static inline int32_t
 320 txgbe_pf_reset_hw(struct txgbe_hw *hw)
 321 {
 322         uint32_t ctrl_ext;
 323         int32_t status;
 324
 325         status = hw->mac.reset_hw(hw);
 326
 327         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 328         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 329         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 330         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 331         txgbe_flush(hw);
 332
 333         if (status == TXGBE_ERR_SFP_NOT_PRESENT)
 334                 status = 0;
 335         return status;
 336 }
 337
 338 static inline void
 339 txgbe_enable_intr(struct rte_eth_dev *dev)
 340 {
 341         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
 342         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 343
 344         wr32(hw, TXGBE_IENMISC, intr->mask_misc);
 345         wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
 346         wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
 347         txgbe_flush(hw);
 348 }
 349
 350 static void
 351 txgbe_disable_intr(struct txgbe_hw *hw)
 352 {
 353         PMD_INIT_FUNC_TRACE();
 354
 355         wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
 356         wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
 357         wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
 358         txgbe_flush(hw);
 359 }
 360
 361 static int
 362 txgbe_dev_queue_stats_mapping_set(struct rte_eth_dev *eth_dev,
 363                                   uint16_t queue_id,
 364                                   uint8_t stat_idx,
 365                                   uint8_t is_rx)
 366 {
 367         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 368         struct txgbe_stat_mappings *stat_mappings =
 369                 TXGBE_DEV_STAT_MAPPINGS(eth_dev);
 370         uint32_t qsmr_mask = 0;
 371         uint32_t clearing_mask = QMAP_FIELD_RESERVED_BITS_MASK;
 372         uint32_t q_map;
 373         uint8_t n, offset;
 374
 375         if (hw->mac.type != txgbe_mac_raptor)
 376                 return -ENOSYS;
 377
 378         if (stat_idx & !QMAP_FIELD_RESERVED_BITS_MASK)
 379                 return -EIO;
 380
 381         PMD_INIT_LOG(DEBUG, "Setting port %d, %s queue_id %d to stat index %d",
 382                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 383                      queue_id, stat_idx);
 384
 385         n = (uint8_t)(queue_id / NB_QMAP_FIELDS_PER_QSM_REG);
 386         if (n >= TXGBE_NB_STAT_MAPPING) {
 387                 PMD_INIT_LOG(ERR, "Nb of stat mapping registers exceeded");
 388                 return -EIO;
 389         }
 390         offset = (uint8_t)(queue_id % NB_QMAP_FIELDS_PER_QSM_REG);
 391
 392         /* Now clear any previous stat_idx set */
 393         clearing_mask <<= (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 394         if (!is_rx)
 395                 stat_mappings->tqsm[n] &= ~clearing_mask;
 396         else
 397                 stat_mappings->rqsm[n] &= ~clearing_mask;
 398
 399         q_map = (uint32_t)stat_idx;
 400         q_map &= QMAP_FIELD_RESERVED_BITS_MASK;
 401         qsmr_mask = q_map << (QSM_REG_NB_BITS_PER_QMAP_FIELD * offset);
 402         if (!is_rx)
 403                 stat_mappings->tqsm[n] |= qsmr_mask;
 404         else
 405                 stat_mappings->rqsm[n] |= qsmr_mask;
 406
 407         PMD_INIT_LOG(DEBUG, "Set port %d, %s queue_id %d to stat index %d",
 408                      (int)(eth_dev->data->port_id), is_rx ? "RX" : "TX",
 409                      queue_id, stat_idx);
 410         PMD_INIT_LOG(DEBUG, "%s[%d] = 0x%08x", is_rx ? "RQSMR" : "TQSM", n,
 411                      is_rx ? stat_mappings->rqsm[n] : stat_mappings->tqsm[n]);
 412         return 0;
 413 }
 414
 415 static void
 416 txgbe_dcb_init(struct txgbe_hw *hw, struct txgbe_dcb_config *dcb_config)
 417 {
 418         int i;
 419         u8 bwgp;
 420         struct txgbe_dcb_tc_config *tc;
 421
 422         UNREFERENCED_PARAMETER(hw);
 423
 424         dcb_config->num_tcs.pg_tcs = TXGBE_DCB_TC_MAX;
 425         dcb_config->num_tcs.pfc_tcs = TXGBE_DCB_TC_MAX;
 426         bwgp = (u8)(100 / TXGBE_DCB_TC_MAX);
 427         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 428                 tc = &dcb_config->tc_config[i];
 429                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_id = i;
 430                 tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent = bwgp + (i & 1);
 431                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_id = i;
 432                 tc->path[TXGBE_DCB_RX_CONFIG].bwg_percent = bwgp + (i & 1);
 433                 tc->pfc = txgbe_dcb_pfc_disabled;
 434         }
 435
 436         /* Initialize default user to priority mapping, UPx->TC0 */
 437         tc = &dcb_config->tc_config[0];
 438         tc->path[TXGBE_DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
 439         tc->path[TXGBE_DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
 440         for (i = 0; i < TXGBE_DCB_BWG_MAX; i++) {
 441                 dcb_config->bw_percentage[i][TXGBE_DCB_TX_CONFIG] = 100;
 442                 dcb_config->bw_percentage[i][TXGBE_DCB_RX_CONFIG] = 100;
 443         }
 444         dcb_config->rx_pba_cfg = txgbe_dcb_pba_equal;
 445         dcb_config->pfc_mode_enable = false;
 446         dcb_config->vt_mode = true;
 447         dcb_config->round_robin_enable = false;
 448         /* support all DCB capabilities */
 449         dcb_config->support.capabilities = 0xFF;
 450 }
 451
 452 /*
 453  * Ensure that all locks are released before first NVM or PHY access
 454  */
 455 static void
 456 txgbe_swfw_lock_reset(struct txgbe_hw *hw)
 457 {
 458         uint16_t mask;
 459
 460         /*
 461          * These ones are more tricky since they are common to all ports; but
 462          * swfw_sync retries last long enough (1s) to be almost sure that if
 463          * lock can not be taken it is due to an improper lock of the
 464          * semaphore.
 465          */
 466         mask = TXGBE_MNGSEM_SWPHY |
 467                TXGBE_MNGSEM_SWMBX |
 468                TXGBE_MNGSEM_SWFLASH;
 469         if (hw->mac.acquire_swfw_sync(hw, mask) < 0)
 470                 PMD_DRV_LOG(DEBUG, "SWFW common locks released");
 471
 472         hw->mac.release_swfw_sync(hw, mask);
 473 }
 474
 475 static int
 476 txgbe_handle_devarg(__rte_unused const char *key, const char *value,
 477                   void *extra_args)
 478 {
 479         uint16_t *n = extra_args;
 480
 481         if (value == NULL || extra_args == NULL)
 482                 return -EINVAL;
 483
 484         *n = (uint16_t)strtoul(value, NULL, 10);
 485         if (*n == USHRT_MAX && errno == ERANGE)
 486                 return -1;
 487
 488         return 0;
 489 }
 490
 491 static void
 492 txgbe_parse_devargs(struct txgbe_hw *hw, struct rte_devargs *devargs)
 493 {
 494         struct rte_kvargs *kvlist;
 495         u16 auto_neg = 1;
 496         u16 poll = 0;
 497         u16 present = 1;
 498         u16 sgmii = 0;
 499         u16 ffe_set = 0;
 500         u16 ffe_main = 27;
 501         u16 ffe_pre = 8;
 502         u16 ffe_post = 44;
 503
 504         if (devargs == NULL)
 505                 goto null;
 506
 507         kvlist = rte_kvargs_parse(devargs->args, txgbe_valid_arguments);
 508         if (kvlist == NULL)
 509                 goto null;
 510
 511         rte_kvargs_process(kvlist, TXGBE_DEVARG_BP_AUTO,
 512                            &txgbe_handle_devarg, &auto_neg);
 513         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_POLL,
 514                            &txgbe_handle_devarg, &poll);
 515         rte_kvargs_process(kvlist, TXGBE_DEVARG_KR_PRESENT,
 516                            &txgbe_handle_devarg, &present);
 517         rte_kvargs_process(kvlist, TXGBE_DEVARG_KX_SGMII,
 518                            &txgbe_handle_devarg, &sgmii);
 519         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_SET,
 520                            &txgbe_handle_devarg, &ffe_set);
 521         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_MAIN,
 522                            &txgbe_handle_devarg, &ffe_main);
 523         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_PRE,
 524                            &txgbe_handle_devarg, &ffe_pre);
 525         rte_kvargs_process(kvlist, TXGBE_DEVARG_FFE_POST,
 526                            &txgbe_handle_devarg, &ffe_post);
 527         rte_kvargs_free(kvlist);
 528
 529 null:
 530         hw->devarg.auto_neg = auto_neg;
 531         hw->devarg.poll = poll;
 532         hw->devarg.present = present;
 533         hw->devarg.sgmii = sgmii;
 534         hw->phy.ffe_set = ffe_set;
 535         hw->phy.ffe_main = ffe_main;
 536         hw->phy.ffe_pre = ffe_pre;
 537         hw->phy.ffe_post = ffe_post;
 538 }
 539
 540 static int
 541 eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 542 {
 543         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
 544         struct txgbe_hw *hw = TXGBE_DEV_HW(eth_dev);
 545         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(eth_dev);
 546         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(eth_dev);
 547         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(eth_dev);
 548         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 549         struct txgbe_bw_conf *bw_conf = TXGBE_DEV_BW_CONF(eth_dev);
 550         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 551         const struct rte_memzone *mz;
 552         uint32_t ctrl_ext;
 553         uint16_t csum;
 554         int err, i, ret;
 555
 556         PMD_INIT_FUNC_TRACE();
 557
 558         eth_dev->dev_ops = &txgbe_eth_dev_ops;
 559         eth_dev->rx_queue_count       = txgbe_dev_rx_queue_count;
 560         eth_dev->rx_descriptor_status = txgbe_dev_rx_descriptor_status;
 561         eth_dev->tx_descriptor_status = txgbe_dev_tx_descriptor_status;
 562         eth_dev->rx_pkt_burst = &txgbe_recv_pkts;
 563         eth_dev->tx_pkt_burst = &txgbe_xmit_pkts;
 564         eth_dev->tx_pkt_prepare = &txgbe_prep_pkts;
 565
 566         /*
 567          * For secondary processes, we don't initialise any further as primary
 568          * has already done this work. Only check we don't need a different
 569          * RX and TX function.
 570          */
 571         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 572                 struct txgbe_tx_queue *txq;
 573                 /* TX queue function in primary, set by last queue initialized
 574                  * Tx queue may not initialized by primary process
 575                  */
 576                 if (eth_dev->data->tx_queues) {
 577                         uint16_t nb_tx_queues = eth_dev->data->nb_tx_queues;
 578                         txq = eth_dev->data->tx_queues[nb_tx_queues - 1];
 579                         txgbe_set_tx_function(eth_dev, txq);
 580                 } else {
 581                         /* Use default TX function if we get here */
 582                         PMD_INIT_LOG(NOTICE, "No TX queues configured yet. "
 583                                      "Using default TX function.");
 584                 }
 585
 586                 txgbe_set_rx_function(eth_dev);
 587
 588                 return 0;
 589         }
 590
 591         rte_eth_copy_pci_info(eth_dev, pci_dev);
 592
 593         /* Vendor and Device ID need to be set before init of shared code */
 594         hw->device_id = pci_dev->id.device_id;
 595         hw->vendor_id = pci_dev->id.vendor_id;
 596         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
 597         hw->allow_unsupported_sfp = 1;
 598
 599         /* Reserve memory for interrupt status block */
 600         mz = rte_eth_dma_zone_reserve(eth_dev, "txgbe_driver", -1,
 601                 16, TXGBE_ALIGN, SOCKET_ID_ANY);
 602         if (mz == NULL)
 603                 return -ENOMEM;
 604
 605         hw->isb_dma = TMZ_PADDR(mz);
 606         hw->isb_mem = TMZ_VADDR(mz);
 607
 608         txgbe_parse_devargs(hw, pci_dev->device.devargs);
 609         /* Initialize the shared code (base driver) */
 610         err = txgbe_init_shared_code(hw);
 611         if (err != 0) {
 612                 PMD_INIT_LOG(ERR, "Shared code init failed: %d", err);
 613                 return -EIO;
 614         }
 615
 616         /* Unlock any pending hardware semaphore */
 617         txgbe_swfw_lock_reset(hw);
 618
 619 #ifdef RTE_LIB_SECURITY
 620         /* Initialize security_ctx only for primary process*/
 621         if (txgbe_ipsec_ctx_create(eth_dev))
 622                 return -ENOMEM;
 623 #endif
 624
 625         /* Initialize DCB configuration*/
 626         memset(dcb_config, 0, sizeof(struct txgbe_dcb_config));
 627         txgbe_dcb_init(hw, dcb_config);
 628
 629         /* Get Hardware Flow Control setting */
 630         hw->fc.requested_mode = txgbe_fc_full;
 631         hw->fc.current_mode = txgbe_fc_full;
 632         hw->fc.pause_time = TXGBE_FC_PAUSE_TIME;
 633         for (i = 0; i < TXGBE_DCB_TC_MAX; i++) {
 634                 hw->fc.low_water[i] = TXGBE_FC_XON_LOTH;
 635                 hw->fc.high_water[i] = TXGBE_FC_XOFF_HITH;
 636         }
 637         hw->fc.send_xon = 1;
 638
 639         err = hw->rom.init_params(hw);
 640         if (err != 0) {
 641                 PMD_INIT_LOG(ERR, "The EEPROM init failed: %d", err);
 642                 return -EIO;
 643         }
 644
 645         /* Make sure we have a good EEPROM before we read from it */
 646         err = hw->rom.validate_checksum(hw, &csum);
 647         if (err != 0) {
 648                 PMD_INIT_LOG(ERR, "The EEPROM checksum is not valid: %d", err);
 649                 return -EIO;
 650         }
 651
 652         err = hw->mac.init_hw(hw);
 653
 654         /*
 655          * Devices with copper phys will fail to initialise if txgbe_init_hw()
 656          * is called too soon after the kernel driver unbinding/binding occurs.
 657          * The failure occurs in txgbe_identify_phy() for all devices,
 658          * but for non-copper devies, txgbe_identify_sfp_module() is
 659          * also called. See txgbe_identify_phy(). The reason for the
 660          * failure is not known, and only occuts when virtualisation features
 661          * are disabled in the bios. A delay of 200ms  was found to be enough by
 662          * trial-and-error, and is doubled to be safe.
 663          */
 664         if (err && hw->phy.media_type == txgbe_media_type_copper) {
 665                 rte_delay_ms(200);
 666                 err = hw->mac.init_hw(hw);
 667         }
 668
 669         if (err == TXGBE_ERR_SFP_NOT_PRESENT)
 670                 err = 0;
 671
 672         if (err == TXGBE_ERR_EEPROM_VERSION) {
 673                 PMD_INIT_LOG(ERR, "This device is a pre-production adapter/"
 674                              "LOM.  Please be aware there may be issues associated "
 675                              "with your hardware.");
 676                 PMD_INIT_LOG(ERR, "If you are experiencing problems "
 677                              "please contact your hardware representative "
 678                              "who provided you with this hardware.");
 679         } else if (err == TXGBE_ERR_SFP_NOT_SUPPORTED) {
 680                 PMD_INIT_LOG(ERR, "Unsupported SFP+ Module");
 681         }
 682         if (err) {
 683                 PMD_INIT_LOG(ERR, "Hardware Initialization Failure: %d", err);
 684                 return -EIO;
 685         }
 686
 687         /* Reset the hw statistics */
 688         txgbe_dev_stats_reset(eth_dev);
 689
 690         /* disable interrupt */
 691         txgbe_disable_intr(hw);
 692
 693         /* Allocate memory for storing MAC addresses */
 694         eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
 695                                                hw->mac.num_rar_entries, 0);
 696         if (eth_dev->data->mac_addrs == NULL) {
 697                 PMD_INIT_LOG(ERR,
 698                              "Failed to allocate %u bytes needed to store "
 699                              "MAC addresses",
 700                              RTE_ETHER_ADDR_LEN * hw->mac.num_rar_entries);
 701                 return -ENOMEM;
 702         }
 703
 704         /* Copy the permanent MAC address */
 705         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
 706                         &eth_dev->data->mac_addrs[0]);
 707
 708         /* Allocate memory for storing hash filter MAC addresses */
 709         eth_dev->data->hash_mac_addrs = rte_zmalloc("txgbe",
 710                         RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC, 0);
 711         if (eth_dev->data->hash_mac_addrs == NULL) {
 712                 PMD_INIT_LOG(ERR,
 713                              "Failed to allocate %d bytes needed to store MAC addresses",
 714                              RTE_ETHER_ADDR_LEN * TXGBE_VMDQ_NUM_UC_MAC);
 715                 return -ENOMEM;
 716         }
 717
 718         /* initialize the vfta */
 719         memset(shadow_vfta, 0, sizeof(*shadow_vfta));
 720
 721         /* initialize the hw strip bitmap*/
 722         memset(hwstrip, 0, sizeof(*hwstrip));
 723
 724         /* initialize PF if max_vfs not zero */
 725         ret = txgbe_pf_host_init(eth_dev);
 726         if (ret) {
 727                 rte_free(eth_dev->data->mac_addrs);
 728                 eth_dev->data->mac_addrs = NULL;
 729                 rte_free(eth_dev->data->hash_mac_addrs);
 730                 eth_dev->data->hash_mac_addrs = NULL;
 731                 return ret;
 732         }
 733
 734         ctrl_ext = rd32(hw, TXGBE_PORTCTL);
 735         /* let hardware know driver is loaded */
 736         ctrl_ext |= TXGBE_PORTCTL_DRVLOAD;
 737         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
 738         ctrl_ext |= TXGBE_PORTCTL_RSTDONE;
 739         wr32(hw, TXGBE_PORTCTL, ctrl_ext);
 740         txgbe_flush(hw);
 741
 742         if (txgbe_is_sfp(hw) && hw->phy.sfp_type != txgbe_sfp_type_not_present)
 743                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d, SFP+: %d",
 744                              (int)hw->mac.type, (int)hw->phy.type,
 745                              (int)hw->phy.sfp_type);
 746         else
 747                 PMD_INIT_LOG(DEBUG, "MAC: %d, PHY: %d",
 748                              (int)hw->mac.type, (int)hw->phy.type);
 749
 750         PMD_INIT_LOG(DEBUG, "port %d vendorID=0x%x deviceID=0x%x",
 751                      eth_dev->data->port_id, pci_dev->id.vendor_id,
 752                      pci_dev->id.device_id);
 753
 754         rte_intr_callback_register(intr_handle,
 755                                    txgbe_dev_interrupt_handler, eth_dev);
 756
 757         /* enable uio/vfio intr/eventfd mapping */
 758         rte_intr_enable(intr_handle);
 759
 760         /* enable support intr */
 761         txgbe_enable_intr(eth_dev);
 762
 763         /* initialize filter info */
 764         memset(filter_info, 0,
 765                sizeof(struct txgbe_filter_info));
 766
 767         /* initialize 5tuple filter list */
 768         TAILQ_INIT(&filter_info->fivetuple_list);
 769
 770         /* initialize flow director filter list & hash */
 771         txgbe_fdir_filter_init(eth_dev);
 772
 773         /* initialize l2 tunnel filter list & hash */
 774         txgbe_l2_tn_filter_init(eth_dev);
 775
 776         /* initialize flow filter lists */
 777         txgbe_filterlist_init();
 778
 779         /* initialize bandwidth configuration info */
 780         memset(bw_conf, 0, sizeof(struct txgbe_bw_conf));
 781
 782         /* initialize Traffic Manager configuration */
 783         txgbe_tm_conf_init(eth_dev);
 784
 785         return 0;
 786 }
 787
 788 static int
 789 eth_txgbe_dev_uninit(struct rte_eth_dev *eth_dev)
 790 {
 791         PMD_INIT_FUNC_TRACE();
 792
 793         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 794                 return 0;
 795
 796         txgbe_dev_close(eth_dev);
 797
 798         return 0;
 799 }
 800
 801 static int txgbe_ntuple_filter_uninit(struct rte_eth_dev *eth_dev)
 802 {
 803         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(eth_dev);
 804         struct txgbe_5tuple_filter *p_5tuple;
 805
 806         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list))) {
 807                 TAILQ_REMOVE(&filter_info->fivetuple_list,
 808                              p_5tuple,
 809                              entries);
 810                 rte_free(p_5tuple);
 811         }
 812         memset(filter_info->fivetuple_mask, 0,
 813                sizeof(uint32_t) * TXGBE_5TUPLE_ARRAY_SIZE);
 814
 815         return 0;
 816 }
 817
 818 static int txgbe_fdir_filter_uninit(struct rte_eth_dev *eth_dev)
 819 {
 820         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 821         struct txgbe_fdir_filter *fdir_filter;
 822
 823         if (fdir_info->hash_map)
 824                 rte_free(fdir_info->hash_map);
 825         if (fdir_info->hash_handle)
 826                 rte_hash_free(fdir_info->hash_handle);
 827
 828         while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
 829                 TAILQ_REMOVE(&fdir_info->fdir_list,
 830                              fdir_filter,
 831                              entries);
 832                 rte_free(fdir_filter);
 833         }
 834
 835         return 0;
 836 }
 837
 838 static int txgbe_l2_tn_filter_uninit(struct rte_eth_dev *eth_dev)
 839 {
 840         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 841         struct txgbe_l2_tn_filter *l2_tn_filter;
 842
 843         if (l2_tn_info->hash_map)
 844                 rte_free(l2_tn_info->hash_map);
 845         if (l2_tn_info->hash_handle)
 846                 rte_hash_free(l2_tn_info->hash_handle);
 847
 848         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
 849                 TAILQ_REMOVE(&l2_tn_info->l2_tn_list,
 850                              l2_tn_filter,
 851                              entries);
 852                 rte_free(l2_tn_filter);
 853         }
 854
 855         return 0;
 856 }
 857
 858 static int txgbe_fdir_filter_init(struct rte_eth_dev *eth_dev)
 859 {
 860         struct txgbe_hw_fdir_info *fdir_info = TXGBE_DEV_FDIR(eth_dev);
 861         char fdir_hash_name[RTE_HASH_NAMESIZE];
 862         struct rte_hash_parameters fdir_hash_params = {
 863                 .name = fdir_hash_name,
 864                 .entries = TXGBE_MAX_FDIR_FILTER_NUM,
 865                 .key_len = sizeof(struct txgbe_atr_input),
 866                 .hash_func = rte_hash_crc,
 867                 .hash_func_init_val = 0,
 868                 .socket_id = rte_socket_id(),
 869         };
 870
 871         TAILQ_INIT(&fdir_info->fdir_list);
 872         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
 873                  "fdir_%s", TDEV_NAME(eth_dev));
 874         fdir_info->hash_handle = rte_hash_create(&fdir_hash_params);
 875         if (!fdir_info->hash_handle) {
 876                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
 877                 return -EINVAL;
 878         }
 879         fdir_info->hash_map = rte_zmalloc("txgbe",
 880                                           sizeof(struct txgbe_fdir_filter *) *
 881                                           TXGBE_MAX_FDIR_FILTER_NUM,
 882                                           0);
 883         if (!fdir_info->hash_map) {
 884                 PMD_INIT_LOG(ERR,
 885                              "Failed to allocate memory for fdir hash map!");
 886                 return -ENOMEM;
 887         }
 888         fdir_info->mask_added = FALSE;
 889
 890         return 0;
 891 }
 892
 893 static int txgbe_l2_tn_filter_init(struct rte_eth_dev *eth_dev)
 894 {
 895         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(eth_dev);
 896         char l2_tn_hash_name[RTE_HASH_NAMESIZE];
 897         struct rte_hash_parameters l2_tn_hash_params = {
 898                 .name = l2_tn_hash_name,
 899                 .entries = TXGBE_MAX_L2_TN_FILTER_NUM,
 900                 .key_len = sizeof(struct txgbe_l2_tn_key),
 901                 .hash_func = rte_hash_crc,
 902                 .hash_func_init_val = 0,
 903                 .socket_id = rte_socket_id(),
 904         };
 905
 906         TAILQ_INIT(&l2_tn_info->l2_tn_list);
 907         snprintf(l2_tn_hash_name, RTE_HASH_NAMESIZE,
 908                  "l2_tn_%s", TDEV_NAME(eth_dev));
 909         l2_tn_info->hash_handle = rte_hash_create(&l2_tn_hash_params);
 910         if (!l2_tn_info->hash_handle) {
 911                 PMD_INIT_LOG(ERR, "Failed to create L2 TN hash table!");
 912                 return -EINVAL;
 913         }
 914         l2_tn_info->hash_map = rte_zmalloc("txgbe",
 915                                    sizeof(struct txgbe_l2_tn_filter *) *
 916                                    TXGBE_MAX_L2_TN_FILTER_NUM,
 917                                    0);
 918         if (!l2_tn_info->hash_map) {
 919                 PMD_INIT_LOG(ERR,
 920                         "Failed to allocate memory for L2 TN hash map!");
 921                 return -ENOMEM;
 922         }
 923         l2_tn_info->e_tag_en = FALSE;
 924         l2_tn_info->e_tag_fwd_en = FALSE;
 925         l2_tn_info->e_tag_ether_type = RTE_ETHER_TYPE_ETAG;
 926
 927         return 0;
 928 }
 929
 930 static int
 931 eth_txgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 932                 struct rte_pci_device *pci_dev)
 933 {
 934         return rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 935                         sizeof(struct txgbe_adapter),
 936                         eth_dev_pci_specific_init, pci_dev,
 937                         eth_txgbe_dev_init, NULL);
 938 }
 939
 940 static int eth_txgbe_pci_remove(struct rte_pci_device *pci_dev)
 941 {
 942         struct rte_eth_dev *ethdev;
 943
 944         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 945         if (!ethdev)
 946                 return 0;
 947
 948         return rte_eth_dev_destroy(ethdev, eth_txgbe_dev_uninit);
 949 }
 950
 951 static struct rte_pci_driver rte_txgbe_pmd = {
 952         .id_table = pci_id_txgbe_map,
 953         .drv_flags = RTE_PCI_DRV_NEED_MAPPING |
 954                      RTE_PCI_DRV_INTR_LSC,
 955         .probe = eth_txgbe_pci_probe,
 956         .remove = eth_txgbe_pci_remove,
 957 };
 958
 959 static int
 960 txgbe_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
 961 {
 962         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 963         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
 964         uint32_t vfta;
 965         uint32_t vid_idx;
 966         uint32_t vid_bit;
 967
 968         vid_idx = (uint32_t)((vlan_id >> 5) & 0x7F);
 969         vid_bit = (uint32_t)(1 << (vlan_id & 0x1F));
 970         vfta = rd32(hw, TXGBE_VLANTBL(vid_idx));
 971         if (on)
 972                 vfta |= vid_bit;
 973         else
 974                 vfta &= ~vid_bit;
 975         wr32(hw, TXGBE_VLANTBL(vid_idx), vfta);
 976
 977         /* update local VFTA copy */
 978         shadow_vfta->vfta[vid_idx] = vfta;
 979
 980         return 0;
 981 }
 982
 983 static void
 984 txgbe_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on)
 985 {
 986         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
 987         struct txgbe_rx_queue *rxq;
 988         bool restart;
 989         uint32_t rxcfg, rxbal, rxbah;
 990
 991         if (on)
 992                 txgbe_vlan_hw_strip_enable(dev, queue);
 993         else
 994                 txgbe_vlan_hw_strip_disable(dev, queue);
 995
 996         rxq = dev->data->rx_queues[queue];
 997         rxbal = rd32(hw, TXGBE_RXBAL(rxq->reg_idx));
 998         rxbah = rd32(hw, TXGBE_RXBAH(rxq->reg_idx));
 999         rxcfg = rd32(hw, TXGBE_RXCFG(rxq->reg_idx));
1000         if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP) {
1001                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1002                         !(rxcfg & TXGBE_RXCFG_VLAN);
1003                 rxcfg |= TXGBE_RXCFG_VLAN;
1004         } else {
1005                 restart = (rxcfg & TXGBE_RXCFG_ENA) &&
1006                         (rxcfg & TXGBE_RXCFG_VLAN);
1007                 rxcfg &= ~TXGBE_RXCFG_VLAN;
1008         }
1009         rxcfg &= ~TXGBE_RXCFG_ENA;
1010
1011         if (restart) {
1012                 /* set vlan strip for ring */
1013                 txgbe_dev_rx_queue_stop(dev, queue);
1014                 wr32(hw, TXGBE_RXBAL(rxq->reg_idx), rxbal);
1015                 wr32(hw, TXGBE_RXBAH(rxq->reg_idx), rxbah);
1016                 wr32(hw, TXGBE_RXCFG(rxq->reg_idx), rxcfg);
1017                 txgbe_dev_rx_queue_start(dev, queue);
1018         }
1019 }
1020
1021 static int
1022 txgbe_vlan_tpid_set(struct rte_eth_dev *dev,
1023                     enum rte_vlan_type vlan_type,
1024                     uint16_t tpid)
1025 {
1026         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1027         int ret = 0;
1028         uint32_t portctrl, vlan_ext, qinq;
1029
1030         portctrl = rd32(hw, TXGBE_PORTCTL);
1031
1032         vlan_ext = (portctrl & TXGBE_PORTCTL_VLANEXT);
1033         qinq = vlan_ext && (portctrl & TXGBE_PORTCTL_QINQ);
1034         switch (vlan_type) {
1035         case ETH_VLAN_TYPE_INNER:
1036                 if (vlan_ext) {
1037                         wr32m(hw, TXGBE_VLANCTL,
1038                                 TXGBE_VLANCTL_TPID_MASK,
1039                                 TXGBE_VLANCTL_TPID(tpid));
1040                         wr32m(hw, TXGBE_DMATXCTRL,
1041                                 TXGBE_DMATXCTRL_TPID_MASK,
1042                                 TXGBE_DMATXCTRL_TPID(tpid));
1043                 } else {
1044                         ret = -ENOTSUP;
1045                         PMD_DRV_LOG(ERR, "Inner type is not supported"
1046                                     " by single VLAN");
1047                 }
1048
1049                 if (qinq) {
1050                         wr32m(hw, TXGBE_TAGTPID(0),
1051                                 TXGBE_TAGTPID_LSB_MASK,
1052                                 TXGBE_TAGTPID_LSB(tpid));
1053                 }
1054                 break;
1055         case ETH_VLAN_TYPE_OUTER:
1056                 if (vlan_ext) {
1057                         /* Only the high 16-bits is valid */
1058                         wr32m(hw, TXGBE_EXTAG,
1059                                 TXGBE_EXTAG_VLAN_MASK,
1060                                 TXGBE_EXTAG_VLAN(tpid));
1061                 } else {
1062                         wr32m(hw, TXGBE_VLANCTL,
1063                                 TXGBE_VLANCTL_TPID_MASK,
1064                                 TXGBE_VLANCTL_TPID(tpid));
1065                         wr32m(hw, TXGBE_DMATXCTRL,
1066                                 TXGBE_DMATXCTRL_TPID_MASK,
1067                                 TXGBE_DMATXCTRL_TPID(tpid));
1068                 }
1069
1070                 if (qinq) {
1071                         wr32m(hw, TXGBE_TAGTPID(0),
1072                                 TXGBE_TAGTPID_MSB_MASK,
1073                                 TXGBE_TAGTPID_MSB(tpid));
1074                 }
1075                 break;
1076         default:
1077                 PMD_DRV_LOG(ERR, "Unsupported VLAN type %d", vlan_type);
1078                 return -EINVAL;
1079         }
1080
1081         return ret;
1082 }
1083
1084 void
1085 txgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev)
1086 {
1087         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1088         uint32_t vlnctrl;
1089
1090         PMD_INIT_FUNC_TRACE();
1091
1092         /* Filter Table Disable */
1093         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1094         vlnctrl &= ~TXGBE_VLANCTL_VFE;
1095         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1096 }
1097
1098 void
1099 txgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1100 {
1101         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1102         struct txgbe_vfta *shadow_vfta = TXGBE_DEV_VFTA(dev);
1103         uint32_t vlnctrl;
1104         uint16_t i;
1105
1106         PMD_INIT_FUNC_TRACE();
1107
1108         /* Filter Table Enable */
1109         vlnctrl = rd32(hw, TXGBE_VLANCTL);
1110         vlnctrl &= ~TXGBE_VLANCTL_CFIENA;
1111         vlnctrl |= TXGBE_VLANCTL_VFE;
1112         wr32(hw, TXGBE_VLANCTL, vlnctrl);
1113
1114         /* write whatever is in local vfta copy */
1115         for (i = 0; i < TXGBE_VFTA_SIZE; i++)
1116                 wr32(hw, TXGBE_VLANTBL(i), shadow_vfta->vfta[i]);
1117 }
1118
1119 void
1120 txgbe_vlan_hw_strip_bitmap_set(struct rte_eth_dev *dev, uint16_t queue, bool on)
1121 {
1122         struct txgbe_hwstrip *hwstrip = TXGBE_DEV_HWSTRIP(dev);
1123         struct txgbe_rx_queue *rxq;
1124
1125         if (queue >= TXGBE_MAX_RX_QUEUE_NUM)
1126                 return;
1127
1128         if (on)
1129                 TXGBE_SET_HWSTRIP(hwstrip, queue);
1130         else
1131                 TXGBE_CLEAR_HWSTRIP(hwstrip, queue);
1132
1133         if (queue >= dev->data->nb_rx_queues)
1134                 return;
1135
1136         rxq = dev->data->rx_queues[queue];
1137
1138         if (on) {
1139                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED;
1140                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1141         } else {
1142                 rxq->vlan_flags = RTE_MBUF_F_RX_VLAN;
1143                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1144         }
1145 }
1146
1147 static void
1148 txgbe_vlan_hw_strip_disable(struct rte_eth_dev *dev, uint16_t queue)
1149 {
1150         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1151         uint32_t ctrl;
1152
1153         PMD_INIT_FUNC_TRACE();
1154
1155         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1156         ctrl &= ~TXGBE_RXCFG_VLAN;
1157         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1158
1159         /* record those setting for HW strip per queue */
1160         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 0);
1161 }
1162
1163 static void
1164 txgbe_vlan_hw_strip_enable(struct rte_eth_dev *dev, uint16_t queue)
1165 {
1166         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1167         uint32_t ctrl;
1168
1169         PMD_INIT_FUNC_TRACE();
1170
1171         ctrl = rd32(hw, TXGBE_RXCFG(queue));
1172         ctrl |= TXGBE_RXCFG_VLAN;
1173         wr32(hw, TXGBE_RXCFG(queue), ctrl);
1174
1175         /* record those setting for HW strip per queue */
1176         txgbe_vlan_hw_strip_bitmap_set(dev, queue, 1);
1177 }
1178
1179 static void
1180 txgbe_vlan_hw_extend_disable(struct rte_eth_dev *dev)
1181 {
1182         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1183         uint32_t ctrl;
1184
1185         PMD_INIT_FUNC_TRACE();
1186
1187         ctrl = rd32(hw, TXGBE_PORTCTL);
1188         ctrl &= ~TXGBE_PORTCTL_VLANEXT;
1189         wr32(hw, TXGBE_PORTCTL, ctrl);
1190 }
1191
1192 static void
1193 txgbe_vlan_hw_extend_enable(struct rte_eth_dev *dev)
1194 {
1195         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1196         uint32_t ctrl;
1197
1198         PMD_INIT_FUNC_TRACE();
1199
1200         ctrl  = rd32(hw, TXGBE_PORTCTL);
1201         ctrl |= TXGBE_PORTCTL_VLANEXT;
1202         wr32(hw, TXGBE_PORTCTL, ctrl);
1203 }
1204
1205 static void
1206 txgbe_qinq_hw_strip_disable(struct rte_eth_dev *dev)
1207 {
1208         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1209         uint32_t ctrl;
1210
1211         PMD_INIT_FUNC_TRACE();
1212
1213         ctrl = rd32(hw, TXGBE_PORTCTL);
1214         ctrl &= ~TXGBE_PORTCTL_QINQ;
1215         wr32(hw, TXGBE_PORTCTL, ctrl);
1216 }
1217
1218 static void
1219 txgbe_qinq_hw_strip_enable(struct rte_eth_dev *dev)
1220 {
1221         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1222         uint32_t ctrl;
1223
1224         PMD_INIT_FUNC_TRACE();
1225
1226         ctrl  = rd32(hw, TXGBE_PORTCTL);
1227         ctrl |= TXGBE_PORTCTL_QINQ | TXGBE_PORTCTL_VLANEXT;
1228         wr32(hw, TXGBE_PORTCTL, ctrl);
1229 }
1230
1231 void
1232 txgbe_vlan_hw_strip_config(struct rte_eth_dev *dev)
1233 {
1234         struct txgbe_rx_queue *rxq;
1235         uint16_t i;
1236
1237         PMD_INIT_FUNC_TRACE();
1238
1239         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1240                 rxq = dev->data->rx_queues[i];
1241
1242                 if (rxq->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1243                         txgbe_vlan_strip_queue_set(dev, i, 1);
1244                 else
1245                         txgbe_vlan_strip_queue_set(dev, i, 0);
1246         }
1247 }
1248
1249 void
1250 txgbe_config_vlan_strip_on_all_queues(struct rte_eth_dev *dev, int mask)
1251 {
1252         uint16_t i;
1253         struct rte_eth_rxmode *rxmode;
1254         struct txgbe_rx_queue *rxq;
1255
1256         if (mask & ETH_VLAN_STRIP_MASK) {
1257                 rxmode = &dev->data->dev_conf.rxmode;
1258                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
1259                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1260                                 rxq = dev->data->rx_queues[i];
1261                                 rxq->offloads |= DEV_RX_OFFLOAD_VLAN_STRIP;
1262                         }
1263                 else
1264                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1265                                 rxq = dev->data->rx_queues[i];
1266                                 rxq->offloads &= ~DEV_RX_OFFLOAD_VLAN_STRIP;
1267                         }
1268         }
1269 }
1270
1271 static int
1272 txgbe_vlan_offload_config(struct rte_eth_dev *dev, int mask)
1273 {
1274         struct rte_eth_rxmode *rxmode;
1275         rxmode = &dev->data->dev_conf.rxmode;
1276
1277         if (mask & ETH_VLAN_STRIP_MASK)
1278                 txgbe_vlan_hw_strip_config(dev);
1279
1280         if (mask & ETH_VLAN_FILTER_MASK) {
1281                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
1282                         txgbe_vlan_hw_filter_enable(dev);
1283                 else
1284                         txgbe_vlan_hw_filter_disable(dev);
1285         }
1286
1287         if (mask & ETH_VLAN_EXTEND_MASK) {
1288                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
1289                         txgbe_vlan_hw_extend_enable(dev);
1290                 else
1291                         txgbe_vlan_hw_extend_disable(dev);
1292         }
1293
1294         if (mask & ETH_QINQ_STRIP_MASK) {
1295                 if (rxmode->offloads & DEV_RX_OFFLOAD_QINQ_STRIP)
1296                         txgbe_qinq_hw_strip_enable(dev);
1297                 else
1298                         txgbe_qinq_hw_strip_disable(dev);
1299         }
1300
1301         return 0;
1302 }
1303
1304 static int
1305 txgbe_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1306 {
1307         txgbe_config_vlan_strip_on_all_queues(dev, mask);
1308
1309         txgbe_vlan_offload_config(dev, mask);
1310
1311         return 0;
1312 }
1313
1314 static void
1315 txgbe_vmdq_vlan_hw_filter_enable(struct rte_eth_dev *dev)
1316 {
1317         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1318         /* VLNCTL: enable vlan filtering and allow all vlan tags through */
1319         uint32_t vlanctrl = rd32(hw, TXGBE_VLANCTL);
1320
1321         vlanctrl |= TXGBE_VLANCTL_VFE; /* enable vlan filters */
1322         wr32(hw, TXGBE_VLANCTL, vlanctrl);
1323 }
1324
1325 static int
1326 txgbe_check_vf_rss_rxq_num(struct rte_eth_dev *dev, uint16_t nb_rx_q)
1327 {
1328         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1329
1330         switch (nb_rx_q) {
1331         case 1:
1332         case 2:
1333                 RTE_ETH_DEV_SRIOV(dev).active = ETH_64_POOLS;
1334                 break;
1335         case 4:
1336                 RTE_ETH_DEV_SRIOV(dev).active = ETH_32_POOLS;
1337                 break;
1338         default:
1339                 return -EINVAL;
1340         }
1341
1342         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool =
1343                 TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1344         RTE_ETH_DEV_SRIOV(dev).def_pool_q_idx =
1345                 pci_dev->max_vfs * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1346         return 0;
1347 }
1348
1349 static int
1350 txgbe_check_mq_mode(struct rte_eth_dev *dev)
1351 {
1352         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1353         uint16_t nb_rx_q = dev->data->nb_rx_queues;
1354         uint16_t nb_tx_q = dev->data->nb_tx_queues;
1355
1356         if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
1357                 /* check multi-queue mode */
1358                 switch (dev_conf->rxmode.mq_mode) {
1359                 case ETH_MQ_RX_VMDQ_DCB:
1360                         PMD_INIT_LOG(INFO, "ETH_MQ_RX_VMDQ_DCB mode supported in SRIOV");
1361                         break;
1362                 case ETH_MQ_RX_VMDQ_DCB_RSS:
1363                         /* DCB/RSS VMDQ in SRIOV mode, not implement yet */
1364                         PMD_INIT_LOG(ERR, "SRIOV active,"
1365                                         " unsupported mq_mode rx %d.",
1366                                         dev_conf->rxmode.mq_mode);
1367                         return -EINVAL;
1368                 case ETH_MQ_RX_RSS:
1369                 case ETH_MQ_RX_VMDQ_RSS:
1370                         dev->data->dev_conf.rxmode.mq_mode = ETH_MQ_RX_VMDQ_RSS;
1371                         if (nb_rx_q <= RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)
1372                                 if (txgbe_check_vf_rss_rxq_num(dev, nb_rx_q)) {
1373                                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1374                                                 " invalid queue number"
1375                                                 " for VMDQ RSS, allowed"
1376                                                 " value are 1, 2 or 4.");
1377                                         return -EINVAL;
1378                                 }
1379                         break;
1380                 case ETH_MQ_RX_VMDQ_ONLY:
1381                 case ETH_MQ_RX_NONE:
1382                         /* if nothing mq mode configure, use default scheme */
1383                         dev->data->dev_conf.rxmode.mq_mode =
1384                                 ETH_MQ_RX_VMDQ_ONLY;
1385                         break;
1386                 default: /* ETH_MQ_RX_DCB, ETH_MQ_RX_DCB_RSS or ETH_MQ_TX_DCB*/
1387                         /* SRIOV only works in VMDq enable mode */
1388                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1389                                         " wrong mq_mode rx %d.",
1390                                         dev_conf->rxmode.mq_mode);
1391                         return -EINVAL;
1392                 }
1393
1394                 switch (dev_conf->txmode.mq_mode) {
1395                 case ETH_MQ_TX_VMDQ_DCB:
1396                         PMD_INIT_LOG(INFO, "ETH_MQ_TX_VMDQ_DCB mode supported in SRIOV");
1397                         dev->data->dev_conf.txmode.mq_mode = ETH_MQ_TX_VMDQ_DCB;
1398                         break;
1399                 default: /* ETH_MQ_TX_VMDQ_ONLY or ETH_MQ_TX_NONE */
1400                         dev->data->dev_conf.txmode.mq_mode =
1401                                 ETH_MQ_TX_VMDQ_ONLY;
1402                         break;
1403                 }
1404
1405                 /* check valid queue number */
1406                 if ((nb_rx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool) ||
1407                     (nb_tx_q > RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool)) {
1408                         PMD_INIT_LOG(ERR, "SRIOV is active,"
1409                                         " nb_rx_q=%d nb_tx_q=%d queue number"
1410                                         " must be less than or equal to %d.",
1411                                         nb_rx_q, nb_tx_q,
1412                                         RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool);
1413                         return -EINVAL;
1414                 }
1415         } else {
1416                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB_RSS) {
1417                         PMD_INIT_LOG(ERR, "VMDQ+DCB+RSS mq_mode is"
1418                                           " not supported.");
1419                         return -EINVAL;
1420                 }
1421                 /* check configuration for vmdb+dcb mode */
1422                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_VMDQ_DCB) {
1423                         const struct rte_eth_vmdq_dcb_conf *conf;
1424
1425                         if (nb_rx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1426                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_rx_q != %d.",
1427                                                 TXGBE_VMDQ_DCB_NB_QUEUES);
1428                                 return -EINVAL;
1429                         }
1430                         conf = &dev_conf->rx_adv_conf.vmdq_dcb_conf;
1431                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1432                                conf->nb_queue_pools == ETH_32_POOLS)) {
1433                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1434                                                 " nb_queue_pools must be %d or %d.",
1435                                                 ETH_16_POOLS, ETH_32_POOLS);
1436                                 return -EINVAL;
1437                         }
1438                 }
1439                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_VMDQ_DCB) {
1440                         const struct rte_eth_vmdq_dcb_tx_conf *conf;
1441
1442                         if (nb_tx_q != TXGBE_VMDQ_DCB_NB_QUEUES) {
1443                                 PMD_INIT_LOG(ERR, "VMDQ+DCB, nb_tx_q != %d",
1444                                                  TXGBE_VMDQ_DCB_NB_QUEUES);
1445                                 return -EINVAL;
1446                         }
1447                         conf = &dev_conf->tx_adv_conf.vmdq_dcb_tx_conf;
1448                         if (!(conf->nb_queue_pools == ETH_16_POOLS ||
1449                                conf->nb_queue_pools == ETH_32_POOLS)) {
1450                                 PMD_INIT_LOG(ERR, "VMDQ+DCB selected,"
1451                                                 " nb_queue_pools != %d and"
1452                                                 " nb_queue_pools != %d.",
1453                                                 ETH_16_POOLS, ETH_32_POOLS);
1454                                 return -EINVAL;
1455                         }
1456                 }
1457
1458                 /* For DCB mode check our configuration before we go further */
1459                 if (dev_conf->rxmode.mq_mode == ETH_MQ_RX_DCB) {
1460                         const struct rte_eth_dcb_rx_conf *conf;
1461
1462                         conf = &dev_conf->rx_adv_conf.dcb_rx_conf;
1463                         if (!(conf->nb_tcs == ETH_4_TCS ||
1464                                conf->nb_tcs == ETH_8_TCS)) {
1465                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1466                                                 " and nb_tcs != %d.",
1467                                                 ETH_4_TCS, ETH_8_TCS);
1468                                 return -EINVAL;
1469                         }
1470                 }
1471
1472                 if (dev_conf->txmode.mq_mode == ETH_MQ_TX_DCB) {
1473                         const struct rte_eth_dcb_tx_conf *conf;
1474
1475                         conf = &dev_conf->tx_adv_conf.dcb_tx_conf;
1476                         if (!(conf->nb_tcs == ETH_4_TCS ||
1477                                conf->nb_tcs == ETH_8_TCS)) {
1478                                 PMD_INIT_LOG(ERR, "DCB selected, nb_tcs != %d"
1479                                                 " and nb_tcs != %d.",
1480                                                 ETH_4_TCS, ETH_8_TCS);
1481                                 return -EINVAL;
1482                         }
1483                 }
1484         }
1485         return 0;
1486 }
1487
1488 static int
1489 txgbe_dev_configure(struct rte_eth_dev *dev)
1490 {
1491         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1492         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1493         int ret;
1494
1495         PMD_INIT_FUNC_TRACE();
1496
1497         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1498                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1499
1500         /* multiple queue mode checking */
1501         ret  = txgbe_check_mq_mode(dev);
1502         if (ret != 0) {
1503                 PMD_DRV_LOG(ERR, "txgbe_check_mq_mode fails with %d.",
1504                             ret);
1505                 return ret;
1506         }
1507
1508         /* set flag to update link status after init */
1509         intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
1510
1511         /*
1512          * Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1513          * allocation Rx preconditions we will reset it.
1514          */
1515         adapter->rx_bulk_alloc_allowed = true;
1516
1517         return 0;
1518 }
1519
1520 static void
1521 txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
1522 {
1523         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1524         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
1525         uint32_t gpie;
1526
1527         gpie = rd32(hw, TXGBE_GPIOINTEN);
1528         gpie |= TXGBE_GPIOBIT_6;
1529         wr32(hw, TXGBE_GPIOINTEN, gpie);
1530         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
1531         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
1532 }
1533
1534 int
1535 txgbe_set_vf_rate_limit(struct rte_eth_dev *dev, uint16_t vf,
1536                         uint16_t tx_rate, uint64_t q_msk)
1537 {
1538         struct txgbe_hw *hw;
1539         struct txgbe_vf_info *vfinfo;
1540         struct rte_eth_link link;
1541         uint8_t  nb_q_per_pool;
1542         uint32_t queue_stride;
1543         uint32_t queue_idx, idx = 0, vf_idx;
1544         uint32_t queue_end;
1545         uint16_t total_rate = 0;
1546         struct rte_pci_device *pci_dev;
1547         int ret;
1548
1549         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1550         ret = rte_eth_link_get_nowait(dev->data->port_id, &link);
1551         if (ret < 0)
1552                 return ret;
1553
1554         if (vf >= pci_dev->max_vfs)
1555                 return -EINVAL;
1556
1557         if (tx_rate > link.link_speed)
1558                 return -EINVAL;
1559
1560         if (q_msk == 0)
1561                 return 0;
1562
1563         hw = TXGBE_DEV_HW(dev);
1564         vfinfo = *(TXGBE_DEV_VFDATA(dev));
1565         nb_q_per_pool = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
1566         queue_stride = TXGBE_MAX_RX_QUEUE_NUM / RTE_ETH_DEV_SRIOV(dev).active;
1567         queue_idx = vf * queue_stride;
1568         queue_end = queue_idx + nb_q_per_pool - 1;
1569         if (queue_end >= hw->mac.max_tx_queues)
1570                 return -EINVAL;
1571
1572         if (vfinfo) {
1573                 for (vf_idx = 0; vf_idx < pci_dev->max_vfs; vf_idx++) {
1574                         if (vf_idx == vf)
1575                                 continue;
1576                         for (idx = 0; idx < RTE_DIM(vfinfo[vf_idx].tx_rate);
1577                                 idx++)
1578                                 total_rate += vfinfo[vf_idx].tx_rate[idx];
1579                 }
1580         } else {
1581                 return -EINVAL;
1582         }
1583
1584         /* Store tx_rate for this vf. */
1585         for (idx = 0; idx < nb_q_per_pool; idx++) {
1586                 if (((uint64_t)0x1 << idx) & q_msk) {
1587                         if (vfinfo[vf].tx_rate[idx] != tx_rate)
1588                                 vfinfo[vf].tx_rate[idx] = tx_rate;
1589                         total_rate += tx_rate;
1590                 }
1591         }
1592
1593         if (total_rate > dev->data->dev_link.link_speed) {
1594                 /* Reset stored TX rate of the VF if it causes exceed
1595                  * link speed.
1596                  */
1597                 memset(vfinfo[vf].tx_rate, 0, sizeof(vfinfo[vf].tx_rate));
1598                 return -EINVAL;
1599         }
1600
1601         /* Set ARBTXRATE of each queue/pool for vf X  */
1602         for (; queue_idx <= queue_end; queue_idx++) {
1603                 if (0x1 & q_msk)
1604                         txgbe_set_queue_rate_limit(dev, queue_idx, tx_rate);
1605                 q_msk = q_msk >> 1;
1606         }
1607
1608         return 0;
1609 }
1610
1611 /*
1612  * Configure device link speed and setup link.
1613  * It returns 0 on success.
1614  */
1615 static int
1616 txgbe_dev_start(struct rte_eth_dev *dev)
1617 {
1618         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1619         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
1620         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1621         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1622         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1623         uint32_t intr_vector = 0;
1624         int err;
1625         bool link_up = false, negotiate = 0;
1626         uint32_t speed = 0;
1627         uint32_t allowed_speeds = 0;
1628         int mask = 0;
1629         int status;
1630         uint16_t vf, idx;
1631         uint32_t *link_speeds;
1632         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1633
1634         PMD_INIT_FUNC_TRACE();
1635
1636         /* TXGBE devices don't support:
1637          *    - half duplex (checked afterwards for valid speeds)
1638          *    - fixed speed: TODO implement
1639          */
1640         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
1641                 PMD_INIT_LOG(ERR,
1642                 "Invalid link_speeds for port %u, fix speed not supported",
1643                                 dev->data->port_id);
1644                 return -EINVAL;
1645         }
1646
1647         /* Stop the link setup handler before resetting the HW. */
1648         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1649
1650         /* disable uio/vfio intr/eventfd mapping */
1651         rte_intr_disable(intr_handle);
1652
1653         /* stop adapter */
1654         hw->adapter_stopped = 0;
1655         txgbe_stop_hw(hw);
1656
1657         /* reinitialize adapter
1658          * this calls reset and start
1659          */
1660         hw->nb_rx_queues = dev->data->nb_rx_queues;
1661         hw->nb_tx_queues = dev->data->nb_tx_queues;
1662         status = txgbe_pf_reset_hw(hw);
1663         if (status != 0)
1664                 return -1;
1665         hw->mac.start_hw(hw);
1666         hw->mac.get_link_status = true;
1667
1668         /* configure PF module if SRIOV enabled */
1669         txgbe_pf_host_configure(dev);
1670
1671         txgbe_dev_phy_intr_setup(dev);
1672
1673         /* check and configure queue intr-vector mapping */
1674         if ((rte_intr_cap_multiple(intr_handle) ||
1675              !RTE_ETH_DEV_SRIOV(dev).active) &&
1676             dev->data->dev_conf.intr_conf.rxq != 0) {
1677                 intr_vector = dev->data->nb_rx_queues;
1678                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1679                         return -1;
1680         }
1681
1682         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1683                 intr_handle->intr_vec =
1684                         rte_zmalloc("intr_vec",
1685                                     dev->data->nb_rx_queues * sizeof(int), 0);
1686                 if (intr_handle->intr_vec == NULL) {
1687                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1688                                      " intr_vec", dev->data->nb_rx_queues);
1689                         return -ENOMEM;
1690                 }
1691         }
1692
1693         /* confiugre msix for sleep until rx interrupt */
1694         txgbe_configure_msix(dev);
1695
1696         /* initialize transmission unit */
1697         txgbe_dev_tx_init(dev);
1698
1699         /* This can fail when allocating mbufs for descriptor rings */
1700         err = txgbe_dev_rx_init(dev);
1701         if (err) {
1702                 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
1703                 goto error;
1704         }
1705
1706         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1707                 ETH_VLAN_EXTEND_MASK;
1708         err = txgbe_vlan_offload_config(dev, mask);
1709         if (err) {
1710                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1711                 goto error;
1712         }
1713
1714         if (dev->data->dev_conf.rxmode.mq_mode == ETH_MQ_RX_VMDQ_ONLY) {
1715                 /* Enable vlan filtering for VMDq */
1716                 txgbe_vmdq_vlan_hw_filter_enable(dev);
1717         }
1718
1719         /* Configure DCB hw */
1720         txgbe_configure_pb(dev);
1721         txgbe_configure_port(dev);
1722         txgbe_configure_dcb(dev);
1723
1724         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_NONE) {
1725                 err = txgbe_fdir_configure(dev);
1726                 if (err)
1727                         goto error;
1728         }
1729
1730         /* Restore vf rate limit */
1731         if (vfinfo != NULL) {
1732                 for (vf = 0; vf < pci_dev->max_vfs; vf++)
1733                         for (idx = 0; idx < TXGBE_MAX_QUEUE_NUM_PER_VF; idx++)
1734                                 if (vfinfo[vf].tx_rate[idx] != 0)
1735                                         txgbe_set_vf_rate_limit(dev, vf,
1736                                                 vfinfo[vf].tx_rate[idx],
1737                                                 1 << idx);
1738         }
1739
1740         err = txgbe_dev_rxtx_start(dev);
1741         if (err < 0) {
1742                 PMD_INIT_LOG(ERR, "Unable to start rxtx queues");
1743                 goto error;
1744         }
1745
1746         /* Skip link setup if loopback mode is enabled. */
1747         if (hw->mac.type == txgbe_mac_raptor &&
1748             dev->data->dev_conf.lpbk_mode)
1749                 goto skip_link_setup;
1750
1751         if (txgbe_is_sfp(hw) && hw->phy.multispeed_fiber) {
1752                 err = hw->mac.setup_sfp(hw);
1753                 if (err)
1754                         goto error;
1755         }
1756
1757         if (hw->phy.media_type == txgbe_media_type_copper) {
1758                 /* Turn on the copper */
1759                 hw->phy.set_phy_power(hw, true);
1760         } else {
1761                 /* Turn on the laser */
1762                 hw->mac.enable_tx_laser(hw);
1763         }
1764
1765         if ((hw->subsystem_device_id & 0xFF) != TXGBE_DEV_ID_KR_KX_KX4)
1766                 err = hw->mac.check_link(hw, &speed, &link_up, 0);
1767         if (err)
1768                 goto error;
1769         dev->data->dev_link.link_status = link_up;
1770
1771         err = hw->mac.get_link_capabilities(hw, &speed, &negotiate);
1772         if (err)
1773                 goto error;
1774
1775         allowed_speeds = ETH_LINK_SPEED_100M | ETH_LINK_SPEED_1G |
1776                         ETH_LINK_SPEED_10G;
1777
1778         link_speeds = &dev->data->dev_conf.link_speeds;
1779         if (*link_speeds & ~allowed_speeds) {
1780                 PMD_INIT_LOG(ERR, "Invalid link setting");
1781                 goto error;
1782         }
1783
1784         speed = 0x0;
1785         if (*link_speeds == ETH_LINK_SPEED_AUTONEG) {
1786                 speed = (TXGBE_LINK_SPEED_100M_FULL |
1787                          TXGBE_LINK_SPEED_1GB_FULL |
1788                          TXGBE_LINK_SPEED_10GB_FULL);
1789         } else {
1790                 if (*link_speeds & ETH_LINK_SPEED_10G)
1791                         speed |= TXGBE_LINK_SPEED_10GB_FULL;
1792                 if (*link_speeds & ETH_LINK_SPEED_5G)
1793                         speed |= TXGBE_LINK_SPEED_5GB_FULL;
1794                 if (*link_speeds & ETH_LINK_SPEED_2_5G)
1795                         speed |= TXGBE_LINK_SPEED_2_5GB_FULL;
1796                 if (*link_speeds & ETH_LINK_SPEED_1G)
1797                         speed |= TXGBE_LINK_SPEED_1GB_FULL;
1798                 if (*link_speeds & ETH_LINK_SPEED_100M)
1799                         speed |= TXGBE_LINK_SPEED_100M_FULL;
1800         }
1801
1802         err = hw->mac.setup_link(hw, speed, link_up);
1803         if (err)
1804                 goto error;
1805
1806 skip_link_setup:
1807
1808         if (rte_intr_allow_others(intr_handle)) {
1809                 txgbe_dev_misc_interrupt_setup(dev);
1810                 /* check if lsc interrupt is enabled */
1811                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1812                         txgbe_dev_lsc_interrupt_setup(dev, TRUE);
1813                 else
1814                         txgbe_dev_lsc_interrupt_setup(dev, FALSE);
1815                 txgbe_dev_macsec_interrupt_setup(dev);
1816                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
1817         } else {
1818                 rte_intr_callback_unregister(intr_handle,
1819                                              txgbe_dev_interrupt_handler, dev);
1820                 if (dev->data->dev_conf.intr_conf.lsc != 0)
1821                         PMD_INIT_LOG(INFO, "lsc won't enable because of"
1822                                      " no intr multiplex");
1823         }
1824
1825         /* check if rxq interrupt is enabled */
1826         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
1827             rte_intr_dp_is_en(intr_handle))
1828                 txgbe_dev_rxq_interrupt_setup(dev);
1829
1830         /* enable uio/vfio intr/eventfd mapping */
1831         rte_intr_enable(intr_handle);
1832
1833         /* resume enabled intr since hw reset */
1834         txgbe_enable_intr(dev);
1835         txgbe_l2_tunnel_conf(dev);
1836         txgbe_filter_restore(dev);
1837
1838         if (tm_conf->root && !tm_conf->committed)
1839                 PMD_DRV_LOG(WARNING,
1840                             "please call hierarchy_commit() "
1841                             "before starting the port");
1842
1843         /*
1844          * Update link status right before return, because it may
1845          * start link configuration process in a separate thread.
1846          */
1847         txgbe_dev_link_update(dev, 0);
1848
1849         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_ORD_MASK);
1850
1851         txgbe_read_stats_registers(hw, hw_stats);
1852         hw->offset_loaded = 1;
1853
1854         return 0;
1855
1856 error:
1857         PMD_INIT_LOG(ERR, "failure in dev start: %d", err);
1858         txgbe_dev_clear_queues(dev);
1859         return -EIO;
1860 }
1861
1862 /*
1863  * Stop device: disable rx and tx functions to allow for reconfiguring.
1864  */
1865 static int
1866 txgbe_dev_stop(struct rte_eth_dev *dev)
1867 {
1868         struct rte_eth_link link;
1869         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
1870         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1871         struct txgbe_vf_info *vfinfo = *TXGBE_DEV_VFDATA(dev);
1872         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1873         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1874         int vf;
1875         struct txgbe_tm_conf *tm_conf = TXGBE_DEV_TM_CONF(dev);
1876
1877         if (hw->adapter_stopped)
1878                 return 0;
1879
1880         PMD_INIT_FUNC_TRACE();
1881
1882         rte_eal_alarm_cancel(txgbe_dev_setup_link_alarm_handler, dev);
1883
1884         /* disable interrupts */
1885         txgbe_disable_intr(hw);
1886
1887         /* reset the NIC */
1888         txgbe_pf_reset_hw(hw);
1889         hw->adapter_stopped = 0;
1890
1891         /* stop adapter */
1892         txgbe_stop_hw(hw);
1893
1894         for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
1895                 vfinfo[vf].clear_to_send = false;
1896
1897         if (hw->phy.media_type == txgbe_media_type_copper) {
1898                 /* Turn off the copper */
1899                 hw->phy.set_phy_power(hw, false);
1900         } else {
1901                 /* Turn off the laser */
1902                 hw->mac.disable_tx_laser(hw);
1903         }
1904
1905         txgbe_dev_clear_queues(dev);
1906
1907         /* Clear stored conf */
1908         dev->data->scattered_rx = 0;
1909         dev->data->lro = 0;
1910
1911         /* Clear recorded link status */
1912         memset(&link, 0, sizeof(link));
1913         rte_eth_linkstatus_set(dev, &link);
1914
1915         if (!rte_intr_allow_others(intr_handle))
1916                 /* resume to the default handler */
1917                 rte_intr_callback_register(intr_handle,
1918                                            txgbe_dev_interrupt_handler,
1919                                            (void *)dev);
1920
1921         /* Clean datapath event and queue/vec mapping */
1922         rte_intr_efd_disable(intr_handle);
1923         if (intr_handle->intr_vec != NULL) {
1924                 rte_free(intr_handle->intr_vec);
1925                 intr_handle->intr_vec = NULL;
1926         }
1927
1928         /* reset hierarchy commit */
1929         tm_conf->committed = false;
1930
1931         adapter->rss_reta_updated = 0;
1932         wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK);
1933
1934         hw->adapter_stopped = true;
1935         dev->data->dev_started = 0;
1936
1937         return 0;
1938 }
1939
1940 /*
1941  * Set device link up: enable tx.
1942  */
1943 static int
1944 txgbe_dev_set_link_up(struct rte_eth_dev *dev)
1945 {
1946         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1947
1948         if (hw->phy.media_type == txgbe_media_type_copper) {
1949                 /* Turn on the copper */
1950                 hw->phy.set_phy_power(hw, true);
1951         } else {
1952                 /* Turn on the laser */
1953                 hw->mac.enable_tx_laser(hw);
1954                 txgbe_dev_link_update(dev, 0);
1955         }
1956
1957         return 0;
1958 }
1959
1960 /*
1961  * Set device link down: disable tx.
1962  */
1963 static int
1964 txgbe_dev_set_link_down(struct rte_eth_dev *dev)
1965 {
1966         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1967
1968         if (hw->phy.media_type == txgbe_media_type_copper) {
1969                 /* Turn off the copper */
1970                 hw->phy.set_phy_power(hw, false);
1971         } else {
1972                 /* Turn off the laser */
1973                 hw->mac.disable_tx_laser(hw);
1974                 txgbe_dev_link_update(dev, 0);
1975         }
1976
1977         return 0;
1978 }
1979
1980 /*
1981  * Reset and stop device.
1982  */
1983 static int
1984 txgbe_dev_close(struct rte_eth_dev *dev)
1985 {
1986         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         int retries = 0;
1990         int ret;
1991
1992         PMD_INIT_FUNC_TRACE();
1993
1994         txgbe_pf_reset_hw(hw);
1995
1996         ret = txgbe_dev_stop(dev);
1997
1998         txgbe_dev_free_queues(dev);
1999
2000         /* reprogram the RAR[0] in case user changed it. */
2001         txgbe_set_rar(hw, 0, hw->mac.addr, 0, true);
2002
2003         /* Unlock any pending hardware semaphore */
2004         txgbe_swfw_lock_reset(hw);
2005
2006         /* disable uio intr before callback unregister */
2007         rte_intr_disable(intr_handle);
2008
2009         do {
2010                 ret = rte_intr_callback_unregister(intr_handle,
2011                                 txgbe_dev_interrupt_handler, dev);
2012                 if (ret >= 0 || ret == -ENOENT) {
2013                         break;
2014                 } else if (ret != -EAGAIN) {
2015                         PMD_INIT_LOG(ERR,
2016                                 "intr callback unregister failed: %d",
2017                                 ret);
2018                 }
2019                 rte_delay_ms(100);
2020         } while (retries++ < (10 + TXGBE_LINK_UP_TIME));
2021
2022         /* cancel the delay handler before remove dev */
2023         rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
2024
2025         /* uninitialize PF if max_vfs not zero */
2026         txgbe_pf_host_uninit(dev);
2027
2028         rte_free(dev->data->mac_addrs);
2029         dev->data->mac_addrs = NULL;
2030
2031         rte_free(dev->data->hash_mac_addrs);
2032         dev->data->hash_mac_addrs = NULL;
2033
2034         /* remove all the fdir filters & hash */
2035         txgbe_fdir_filter_uninit(dev);
2036
2037         /* remove all the L2 tunnel filters & hash */
2038         txgbe_l2_tn_filter_uninit(dev);
2039
2040         /* Remove all ntuple filters of the device */
2041         txgbe_ntuple_filter_uninit(dev);
2042
2043         /* clear all the filters list */
2044         txgbe_filterlist_flush();
2045
2046         /* Remove all Traffic Manager configuration */
2047         txgbe_tm_conf_uninit(dev);
2048
2049 #ifdef RTE_LIB_SECURITY
2050         rte_free(dev->security_ctx);
2051 #endif
2052
2053         return ret;
2054 }
2055
2056 /*
2057  * Reset PF device.
2058  */
2059 static int
2060 txgbe_dev_reset(struct rte_eth_dev *dev)
2061 {
2062         int ret;
2063
2064         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2065          * its VF to make them align with it. The detailed notification
2066          * mechanism is PMD specific. As to txgbe PF, it is rather complex.
2067          * To avoid unexpected behavior in VF, currently reset of PF with
2068          * SR-IOV activation is not supported. It might be supported later.
2069          */
2070         if (dev->data->sriov.active)
2071                 return -ENOTSUP;
2072
2073         ret = eth_txgbe_dev_uninit(dev);
2074         if (ret)
2075                 return ret;
2076
2077         ret = eth_txgbe_dev_init(dev, NULL);
2078
2079         return ret;
2080 }
2081
2082 #define UPDATE_QP_COUNTER_32bit(reg, last_counter, counter)     \
2083         {                                                       \
2084                 uint32_t current_counter = rd32(hw, reg);       \
2085                 if (current_counter < last_counter)             \
2086                         current_counter += 0x100000000LL;       \
2087                 if (!hw->offset_loaded)                         \
2088                         last_counter = current_counter;         \
2089                 counter = current_counter - last_counter;       \
2090                 counter &= 0xFFFFFFFFLL;                        \
2091         }
2092
2093 #define UPDATE_QP_COUNTER_36bit(reg_lsb, reg_msb, last_counter, counter) \
2094         {                                                                \
2095                 uint64_t current_counter_lsb = rd32(hw, reg_lsb);        \
2096                 uint64_t current_counter_msb = rd32(hw, reg_msb);        \
2097                 uint64_t current_counter = (current_counter_msb << 32) | \
2098                         current_counter_lsb;                             \
2099                 if (current_counter < last_counter)                      \
2100                         current_counter += 0x1000000000LL;               \
2101                 if (!hw->offset_loaded)                                  \
2102                         last_counter = current_counter;                  \
2103                 counter = current_counter - last_counter;                \
2104                 counter &= 0xFFFFFFFFFLL;                                \
2105         }
2106
2107 void
2108 txgbe_read_stats_registers(struct txgbe_hw *hw,
2109                            struct txgbe_hw_stats *hw_stats)
2110 {
2111         unsigned int i;
2112
2113         /* QP Stats */
2114         for (i = 0; i < hw->nb_rx_queues; i++) {
2115                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXPKT(i),
2116                         hw->qp_last[i].rx_qp_packets,
2117                         hw_stats->qp[i].rx_qp_packets);
2118                 UPDATE_QP_COUNTER_36bit(TXGBE_QPRXOCTL(i), TXGBE_QPRXOCTH(i),
2119                         hw->qp_last[i].rx_qp_bytes,
2120                         hw_stats->qp[i].rx_qp_bytes);
2121                 UPDATE_QP_COUNTER_32bit(TXGBE_QPRXMPKT(i),
2122                         hw->qp_last[i].rx_qp_mc_packets,
2123                         hw_stats->qp[i].rx_qp_mc_packets);
2124         }
2125
2126         for (i = 0; i < hw->nb_tx_queues; i++) {
2127                 UPDATE_QP_COUNTER_32bit(TXGBE_QPTXPKT(i),
2128                         hw->qp_last[i].tx_qp_packets,
2129                         hw_stats->qp[i].tx_qp_packets);
2130                 UPDATE_QP_COUNTER_36bit(TXGBE_QPTXOCTL(i), TXGBE_QPTXOCTH(i),
2131                         hw->qp_last[i].tx_qp_bytes,
2132                         hw_stats->qp[i].tx_qp_bytes);
2133         }
2134         /* PB Stats */
2135         for (i = 0; i < TXGBE_MAX_UP; i++) {
2136                 hw_stats->up[i].rx_up_xon_packets +=
2137                                 rd32(hw, TXGBE_PBRXUPXON(i));
2138                 hw_stats->up[i].rx_up_xoff_packets +=
2139                                 rd32(hw, TXGBE_PBRXUPXOFF(i));
2140                 hw_stats->up[i].tx_up_xon_packets +=
2141                                 rd32(hw, TXGBE_PBTXUPXON(i));
2142                 hw_stats->up[i].tx_up_xoff_packets +=
2143                                 rd32(hw, TXGBE_PBTXUPXOFF(i));
2144                 hw_stats->up[i].tx_up_xon2off_packets +=
2145                                 rd32(hw, TXGBE_PBTXUPOFF(i));
2146                 hw_stats->up[i].rx_up_dropped +=
2147                                 rd32(hw, TXGBE_PBRXMISS(i));
2148         }
2149         hw_stats->rx_xon_packets += rd32(hw, TXGBE_PBRXLNKXON);
2150         hw_stats->rx_xoff_packets += rd32(hw, TXGBE_PBRXLNKXOFF);
2151         hw_stats->tx_xon_packets += rd32(hw, TXGBE_PBTXLNKXON);
2152         hw_stats->tx_xoff_packets += rd32(hw, TXGBE_PBTXLNKXOFF);
2153
2154         /* DMA Stats */
2155         hw_stats->rx_packets += rd32(hw, TXGBE_DMARXPKT);
2156         hw_stats->tx_packets += rd32(hw, TXGBE_DMATXPKT);
2157
2158         hw_stats->rx_bytes += rd64(hw, TXGBE_DMARXOCTL);
2159         hw_stats->tx_bytes += rd64(hw, TXGBE_DMATXOCTL);
2160         hw_stats->rx_dma_drop += rd32(hw, TXGBE_DMARXDROP);
2161         hw_stats->rx_drop_packets += rd32(hw, TXGBE_PBRXDROP);
2162
2163         /* MAC Stats */
2164         hw_stats->rx_crc_errors += rd64(hw, TXGBE_MACRXERRCRCL);
2165         hw_stats->rx_multicast_packets += rd64(hw, TXGBE_MACRXMPKTL);
2166         hw_stats->tx_multicast_packets += rd64(hw, TXGBE_MACTXMPKTL);
2167
2168         hw_stats->rx_total_packets += rd64(hw, TXGBE_MACRXPKTL);
2169         hw_stats->tx_total_packets += rd64(hw, TXGBE_MACTXPKTL);
2170         hw_stats->rx_total_bytes += rd64(hw, TXGBE_MACRXGBOCTL);
2171
2172         hw_stats->rx_broadcast_packets += rd64(hw, TXGBE_MACRXOCTL);
2173         hw_stats->tx_broadcast_packets += rd32(hw, TXGBE_MACTXOCTL);
2174
2175         hw_stats->rx_size_64_packets += rd64(hw, TXGBE_MACRX1TO64L);
2176         hw_stats->rx_size_65_to_127_packets += rd64(hw, TXGBE_MACRX65TO127L);
2177         hw_stats->rx_size_128_to_255_packets += rd64(hw, TXGBE_MACRX128TO255L);
2178         hw_stats->rx_size_256_to_511_packets += rd64(hw, TXGBE_MACRX256TO511L);
2179         hw_stats->rx_size_512_to_1023_packets +=
2180                         rd64(hw, TXGBE_MACRX512TO1023L);
2181         hw_stats->rx_size_1024_to_max_packets +=
2182                         rd64(hw, TXGBE_MACRX1024TOMAXL);
2183         hw_stats->tx_size_64_packets += rd64(hw, TXGBE_MACTX1TO64L);
2184         hw_stats->tx_size_65_to_127_packets += rd64(hw, TXGBE_MACTX65TO127L);
2185         hw_stats->tx_size_128_to_255_packets += rd64(hw, TXGBE_MACTX128TO255L);
2186         hw_stats->tx_size_256_to_511_packets += rd64(hw, TXGBE_MACTX256TO511L);
2187         hw_stats->tx_size_512_to_1023_packets +=
2188                         rd64(hw, TXGBE_MACTX512TO1023L);
2189         hw_stats->tx_size_1024_to_max_packets +=
2190                         rd64(hw, TXGBE_MACTX1024TOMAXL);
2191
2192         hw_stats->rx_undersize_errors += rd64(hw, TXGBE_MACRXERRLENL);
2193         hw_stats->rx_oversize_errors += rd32(hw, TXGBE_MACRXOVERSIZE);
2194         hw_stats->rx_jabber_errors += rd32(hw, TXGBE_MACRXJABBER);
2195
2196         /* MNG Stats */
2197         hw_stats->mng_bmc2host_packets = rd32(hw, TXGBE_MNGBMC2OS);
2198         hw_stats->mng_host2bmc_packets = rd32(hw, TXGBE_MNGOS2BMC);
2199         hw_stats->rx_management_packets = rd32(hw, TXGBE_DMARXMNG);
2200         hw_stats->tx_management_packets = rd32(hw, TXGBE_DMATXMNG);
2201
2202         /* FCoE Stats */
2203         hw_stats->rx_fcoe_crc_errors += rd32(hw, TXGBE_FCOECRC);
2204         hw_stats->rx_fcoe_mbuf_allocation_errors += rd32(hw, TXGBE_FCOELAST);
2205         hw_stats->rx_fcoe_dropped += rd32(hw, TXGBE_FCOERPDC);
2206         hw_stats->rx_fcoe_packets += rd32(hw, TXGBE_FCOEPRC);
2207         hw_stats->tx_fcoe_packets += rd32(hw, TXGBE_FCOEPTC);
2208         hw_stats->rx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWRC);
2209         hw_stats->tx_fcoe_bytes += rd32(hw, TXGBE_FCOEDWTC);
2210
2211         /* Flow Director Stats */
2212         hw_stats->flow_director_matched_filters += rd32(hw, TXGBE_FDIRMATCH);
2213         hw_stats->flow_director_missed_filters += rd32(hw, TXGBE_FDIRMISS);
2214         hw_stats->flow_director_added_filters +=
2215                 TXGBE_FDIRUSED_ADD(rd32(hw, TXGBE_FDIRUSED));
2216         hw_stats->flow_director_removed_filters +=
2217                 TXGBE_FDIRUSED_REM(rd32(hw, TXGBE_FDIRUSED));
2218         hw_stats->flow_director_filter_add_errors +=
2219                 TXGBE_FDIRFAIL_ADD(rd32(hw, TXGBE_FDIRFAIL));
2220         hw_stats->flow_director_filter_remove_errors +=
2221                 TXGBE_FDIRFAIL_REM(rd32(hw, TXGBE_FDIRFAIL));
2222
2223         /* MACsec Stats */
2224         hw_stats->tx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECTX_UTPKT);
2225         hw_stats->tx_macsec_pkts_encrypted +=
2226                         rd32(hw, TXGBE_LSECTX_ENCPKT);
2227         hw_stats->tx_macsec_pkts_protected +=
2228                         rd32(hw, TXGBE_LSECTX_PROTPKT);
2229         hw_stats->tx_macsec_octets_encrypted +=
2230                         rd32(hw, TXGBE_LSECTX_ENCOCT);
2231         hw_stats->tx_macsec_octets_protected +=
2232                         rd32(hw, TXGBE_LSECTX_PROTOCT);
2233         hw_stats->rx_macsec_pkts_untagged += rd32(hw, TXGBE_LSECRX_UTPKT);
2234         hw_stats->rx_macsec_pkts_badtag += rd32(hw, TXGBE_LSECRX_BTPKT);
2235         hw_stats->rx_macsec_pkts_nosci += rd32(hw, TXGBE_LSECRX_NOSCIPKT);
2236         hw_stats->rx_macsec_pkts_unknownsci += rd32(hw, TXGBE_LSECRX_UNSCIPKT);
2237         hw_stats->rx_macsec_octets_decrypted += rd32(hw, TXGBE_LSECRX_DECOCT);
2238         hw_stats->rx_macsec_octets_validated += rd32(hw, TXGBE_LSECRX_VLDOCT);
2239         hw_stats->rx_macsec_sc_pkts_unchecked +=
2240                         rd32(hw, TXGBE_LSECRX_UNCHKPKT);
2241         hw_stats->rx_macsec_sc_pkts_delayed += rd32(hw, TXGBE_LSECRX_DLYPKT);
2242         hw_stats->rx_macsec_sc_pkts_late += rd32(hw, TXGBE_LSECRX_LATEPKT);
2243         for (i = 0; i < 2; i++) {
2244                 hw_stats->rx_macsec_sa_pkts_ok +=
2245                         rd32(hw, TXGBE_LSECRX_OKPKT(i));
2246                 hw_stats->rx_macsec_sa_pkts_invalid +=
2247                         rd32(hw, TXGBE_LSECRX_INVPKT(i));
2248                 hw_stats->rx_macsec_sa_pkts_notvalid +=
2249                         rd32(hw, TXGBE_LSECRX_BADPKT(i));
2250         }
2251         hw_stats->rx_macsec_sa_pkts_unusedsa +=
2252                         rd32(hw, TXGBE_LSECRX_INVSAPKT);
2253         hw_stats->rx_macsec_sa_pkts_notusingsa +=
2254                         rd32(hw, TXGBE_LSECRX_BADSAPKT);
2255
2256         hw_stats->rx_total_missed_packets = 0;
2257         for (i = 0; i < TXGBE_MAX_UP; i++) {
2258                 hw_stats->rx_total_missed_packets +=
2259                         hw_stats->up[i].rx_up_dropped;
2260         }
2261 }
2262
2263 static int
2264 txgbe_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2265 {
2266         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2267         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2268         struct txgbe_stat_mappings *stat_mappings =
2269                         TXGBE_DEV_STAT_MAPPINGS(dev);
2270         uint32_t i, j;
2271
2272         txgbe_read_stats_registers(hw, hw_stats);
2273
2274         if (stats == NULL)
2275                 return -EINVAL;
2276
2277         /* Fill out the rte_eth_stats statistics structure */
2278         stats->ipackets = hw_stats->rx_packets;
2279         stats->ibytes = hw_stats->rx_bytes;
2280         stats->opackets = hw_stats->tx_packets;
2281         stats->obytes = hw_stats->tx_bytes;
2282
2283         memset(&stats->q_ipackets, 0, sizeof(stats->q_ipackets));
2284         memset(&stats->q_opackets, 0, sizeof(stats->q_opackets));
2285         memset(&stats->q_ibytes, 0, sizeof(stats->q_ibytes));
2286         memset(&stats->q_obytes, 0, sizeof(stats->q_obytes));
2287         memset(&stats->q_errors, 0, sizeof(stats->q_errors));
2288         for (i = 0; i < TXGBE_MAX_QP; i++) {
2289                 uint32_t n = i / NB_QMAP_FIELDS_PER_QSM_REG;
2290                 uint32_t offset = (i % NB_QMAP_FIELDS_PER_QSM_REG) * 8;
2291                 uint32_t q_map;
2292
2293                 q_map = (stat_mappings->rqsm[n] >> offset)
2294                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2295                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2296                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2297                 stats->q_ipackets[j] += hw_stats->qp[i].rx_qp_packets;
2298                 stats->q_ibytes[j] += hw_stats->qp[i].rx_qp_bytes;
2299
2300                 q_map = (stat_mappings->tqsm[n] >> offset)
2301                                 & QMAP_FIELD_RESERVED_BITS_MASK;
2302                 j = (q_map < RTE_ETHDEV_QUEUE_STAT_CNTRS
2303                      ? q_map : q_map % RTE_ETHDEV_QUEUE_STAT_CNTRS);
2304                 stats->q_opackets[j] += hw_stats->qp[i].tx_qp_packets;
2305                 stats->q_obytes[j] += hw_stats->qp[i].tx_qp_bytes;
2306         }
2307
2308         /* Rx Errors */
2309         stats->imissed  = hw_stats->rx_total_missed_packets +
2310                           hw_stats->rx_dma_drop;
2311         stats->ierrors  = hw_stats->rx_crc_errors +
2312                           hw_stats->rx_mac_short_packet_dropped +
2313                           hw_stats->rx_length_errors +
2314                           hw_stats->rx_undersize_errors +
2315                           hw_stats->rx_oversize_errors +
2316                           hw_stats->rx_drop_packets +
2317                           hw_stats->rx_illegal_byte_errors +
2318                           hw_stats->rx_error_bytes +
2319                           hw_stats->rx_fragment_errors +
2320                           hw_stats->rx_fcoe_crc_errors +
2321                           hw_stats->rx_fcoe_mbuf_allocation_errors;
2322
2323         /* Tx Errors */
2324         stats->oerrors  = 0;
2325         return 0;
2326 }
2327
2328 static int
2329 txgbe_dev_stats_reset(struct rte_eth_dev *dev)
2330 {
2331         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2332         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2333
2334         /* HW registers are cleared on read */
2335         hw->offset_loaded = 0;
2336         txgbe_dev_stats_get(dev, NULL);
2337         hw->offset_loaded = 1;
2338
2339         /* Reset software totals */
2340         memset(hw_stats, 0, sizeof(*hw_stats));
2341
2342         return 0;
2343 }
2344
2345 /* This function calculates the number of xstats based on the current config */
2346 static unsigned
2347 txgbe_xstats_calc_num(struct rte_eth_dev *dev)
2348 {
2349         int nb_queues = max(dev->data->nb_rx_queues, dev->data->nb_tx_queues);
2350         return TXGBE_NB_HW_STATS +
2351                TXGBE_NB_UP_STATS * TXGBE_MAX_UP +
2352                TXGBE_NB_QP_STATS * nb_queues;
2353 }
2354
2355 static inline int
2356 txgbe_get_name_by_id(uint32_t id, char *name, uint32_t size)
2357 {
2358         int nb, st;
2359
2360         /* Extended stats from txgbe_hw_stats */
2361         if (id < TXGBE_NB_HW_STATS) {
2362                 snprintf(name, size, "[hw]%s",
2363                         rte_txgbe_stats_strings[id].name);
2364                 return 0;
2365         }
2366         id -= TXGBE_NB_HW_STATS;
2367
2368         /* Priority Stats */
2369         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2370                 nb = id / TXGBE_NB_UP_STATS;
2371                 st = id % TXGBE_NB_UP_STATS;
2372                 snprintf(name, size, "[p%u]%s", nb,
2373                         rte_txgbe_up_strings[st].name);
2374                 return 0;
2375         }
2376         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2377
2378         /* Queue Stats */
2379         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2380                 nb = id / TXGBE_NB_QP_STATS;
2381                 st = id % TXGBE_NB_QP_STATS;
2382                 snprintf(name, size, "[q%u]%s", nb,
2383                         rte_txgbe_qp_strings[st].name);
2384                 return 0;
2385         }
2386         id -= TXGBE_NB_QP_STATS * TXGBE_MAX_QP;
2387
2388         return -(int)(id + 1);
2389 }
2390
2391 static inline int
2392 txgbe_get_offset_by_id(uint32_t id, uint32_t *offset)
2393 {
2394         int nb, st;
2395
2396         /* Extended stats from txgbe_hw_stats */
2397         if (id < TXGBE_NB_HW_STATS) {
2398                 *offset = rte_txgbe_stats_strings[id].offset;
2399                 return 0;
2400         }
2401         id -= TXGBE_NB_HW_STATS;
2402
2403         /* Priority Stats */
2404         if (id < TXGBE_NB_UP_STATS * TXGBE_MAX_UP) {
2405                 nb = id / TXGBE_NB_UP_STATS;
2406                 st = id % TXGBE_NB_UP_STATS;
2407                 *offset = rte_txgbe_up_strings[st].offset +
2408                         nb * (TXGBE_NB_UP_STATS * sizeof(uint64_t));
2409                 return 0;
2410         }
2411         id -= TXGBE_NB_UP_STATS * TXGBE_MAX_UP;
2412
2413         /* Queue Stats */
2414         if (id < TXGBE_NB_QP_STATS * TXGBE_MAX_QP) {
2415                 nb = id / TXGBE_NB_QP_STATS;
2416                 st = id % TXGBE_NB_QP_STATS;
2417                 *offset = rte_txgbe_qp_strings[st].offset +
2418                         nb * (TXGBE_NB_QP_STATS * sizeof(uint64_t));
2419                 return 0;
2420         }
2421
2422         return -1;
2423 }
2424
2425 static int txgbe_dev_xstats_get_names(struct rte_eth_dev *dev,
2426         struct rte_eth_xstat_name *xstats_names, unsigned int limit)
2427 {
2428         unsigned int i, count;
2429
2430         count = txgbe_xstats_calc_num(dev);
2431         if (xstats_names == NULL)
2432                 return count;
2433
2434         /* Note: limit >= cnt_stats checked upstream
2435          * in rte_eth_xstats_names()
2436          */
2437         limit = min(limit, count);
2438
2439         /* Extended stats from txgbe_hw_stats */
2440         for (i = 0; i < limit; i++) {
2441                 if (txgbe_get_name_by_id(i, xstats_names[i].name,
2442                         sizeof(xstats_names[i].name))) {
2443                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2444                         break;
2445                 }
2446         }
2447
2448         return i;
2449 }
2450
2451 static int txgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev,
2452         struct rte_eth_xstat_name *xstats_names,
2453         const uint64_t *ids,
2454         unsigned int limit)
2455 {
2456         unsigned int i;
2457
2458         if (ids == NULL)
2459                 return txgbe_dev_xstats_get_names(dev, xstats_names, limit);
2460
2461         for (i = 0; i < limit; i++) {
2462                 if (txgbe_get_name_by_id(ids[i], xstats_names[i].name,
2463                                 sizeof(xstats_names[i].name))) {
2464                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2465                         return -1;
2466                 }
2467         }
2468
2469         return i;
2470 }
2471
2472 static int
2473 txgbe_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
2474                                          unsigned int limit)
2475 {
2476         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2477         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2478         unsigned int i, count;
2479
2480         txgbe_read_stats_registers(hw, hw_stats);
2481
2482         /* If this is a reset xstats is NULL, and we have cleared the
2483          * registers by reading them.
2484          */
2485         count = txgbe_xstats_calc_num(dev);
2486         if (xstats == NULL)
2487                 return count;
2488
2489         limit = min(limit, txgbe_xstats_calc_num(dev));
2490
2491         /* Extended stats from txgbe_hw_stats */
2492         for (i = 0; i < limit; i++) {
2493                 uint32_t offset = 0;
2494
2495                 if (txgbe_get_offset_by_id(i, &offset)) {
2496                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2497                         break;
2498                 }
2499                 xstats[i].value = *(uint64_t *)(((char *)hw_stats) + offset);
2500                 xstats[i].id = i;
2501         }
2502
2503         return i;
2504 }
2505
2506 static int
2507 txgbe_dev_xstats_get_(struct rte_eth_dev *dev, uint64_t *values,
2508                                          unsigned int limit)
2509 {
2510         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2511         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2512         unsigned int i, count;
2513
2514         txgbe_read_stats_registers(hw, hw_stats);
2515
2516         /* If this is a reset xstats is NULL, and we have cleared the
2517          * registers by reading them.
2518          */
2519         count = txgbe_xstats_calc_num(dev);
2520         if (values == NULL)
2521                 return count;
2522
2523         limit = min(limit, txgbe_xstats_calc_num(dev));
2524
2525         /* Extended stats from txgbe_hw_stats */
2526         for (i = 0; i < limit; i++) {
2527                 uint32_t offset;
2528
2529                 if (txgbe_get_offset_by_id(i, &offset)) {
2530                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2531                         break;
2532                 }
2533                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2534         }
2535
2536         return i;
2537 }
2538
2539 static int
2540 txgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids,
2541                 uint64_t *values, unsigned int limit)
2542 {
2543         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2544         unsigned int i;
2545
2546         if (ids == NULL)
2547                 return txgbe_dev_xstats_get_(dev, values, limit);
2548
2549         for (i = 0; i < limit; i++) {
2550                 uint32_t offset;
2551
2552                 if (txgbe_get_offset_by_id(ids[i], &offset)) {
2553                         PMD_INIT_LOG(WARNING, "id value %d isn't valid", i);
2554                         break;
2555                 }
2556                 values[i] = *(uint64_t *)(((char *)hw_stats) + offset);
2557         }
2558
2559         return i;
2560 }
2561
2562 static int
2563 txgbe_dev_xstats_reset(struct rte_eth_dev *dev)
2564 {
2565         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2566         struct txgbe_hw_stats *hw_stats = TXGBE_DEV_STATS(dev);
2567
2568         /* HW registers are cleared on read */
2569         hw->offset_loaded = 0;
2570         txgbe_read_stats_registers(hw, hw_stats);
2571         hw->offset_loaded = 1;
2572
2573         /* Reset software totals */
2574         memset(hw_stats, 0, sizeof(*hw_stats));
2575
2576         return 0;
2577 }
2578
2579 static int
2580 txgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2581 {
2582         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2583         u32 etrack_id;
2584         int ret;
2585
2586         hw->phy.get_fw_version(hw, &etrack_id);
2587
2588         ret = snprintf(fw_version, fw_size, "0x%08x", etrack_id);
2589         if (ret < 0)
2590                 return -EINVAL;
2591
2592         ret += 1; /* add the size of '\0' */
2593         if (fw_size < (size_t)ret)
2594                 return ret;
2595         else
2596                 return 0;
2597 }
2598
2599 static int
2600 txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2601 {
2602         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2603         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2604
2605         dev_info->max_rx_queues = (uint16_t)hw->mac.max_rx_queues;
2606         dev_info->max_tx_queues = (uint16_t)hw->mac.max_tx_queues;
2607         dev_info->min_rx_bufsize = 1024;
2608         dev_info->max_rx_pktlen = 15872;
2609         dev_info->max_mac_addrs = hw->mac.num_rar_entries;
2610         dev_info->max_hash_mac_addrs = TXGBE_VMDQ_NUM_UC_MAC;
2611         dev_info->max_vfs = pci_dev->max_vfs;
2612         dev_info->max_vmdq_pools = ETH_64_POOLS;
2613         dev_info->vmdq_queue_num = dev_info->max_rx_queues;
2614         dev_info->rx_queue_offload_capa = txgbe_get_rx_queue_offloads(dev);
2615         dev_info->rx_offload_capa = (txgbe_get_rx_port_offloads(dev) |
2616                                      dev_info->rx_queue_offload_capa);
2617         dev_info->tx_queue_offload_capa = txgbe_get_tx_queue_offloads(dev);
2618         dev_info->tx_offload_capa = txgbe_get_tx_port_offloads(dev);
2619
2620         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2621                 .rx_thresh = {
2622                         .pthresh = TXGBE_DEFAULT_RX_PTHRESH,
2623                         .hthresh = TXGBE_DEFAULT_RX_HTHRESH,
2624                         .wthresh = TXGBE_DEFAULT_RX_WTHRESH,
2625                 },
2626                 .rx_free_thresh = TXGBE_DEFAULT_RX_FREE_THRESH,
2627                 .rx_drop_en = 0,
2628                 .offloads = 0,
2629         };
2630
2631         dev_info->default_txconf = (struct rte_eth_txconf) {
2632                 .tx_thresh = {
2633                         .pthresh = TXGBE_DEFAULT_TX_PTHRESH,
2634                         .hthresh = TXGBE_DEFAULT_TX_HTHRESH,
2635                         .wthresh = TXGBE_DEFAULT_TX_WTHRESH,
2636                 },
2637                 .tx_free_thresh = TXGBE_DEFAULT_TX_FREE_THRESH,
2638                 .offloads = 0,
2639         };
2640
2641         dev_info->rx_desc_lim = rx_desc_lim;
2642         dev_info->tx_desc_lim = tx_desc_lim;
2643
2644         dev_info->hash_key_size = TXGBE_HKEY_MAX_INDEX * sizeof(uint32_t);
2645         dev_info->reta_size = ETH_RSS_RETA_SIZE_128;
2646         dev_info->flow_type_rss_offloads = TXGBE_RSS_OFFLOAD_ALL;
2647
2648         dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
2649         dev_info->speed_capa |= ETH_LINK_SPEED_100M;
2650
2651         /* Driver-preferred Rx/Tx parameters */
2652         dev_info->default_rxportconf.burst_size = 32;
2653         dev_info->default_txportconf.burst_size = 32;
2654         dev_info->default_rxportconf.nb_queues = 1;
2655         dev_info->default_txportconf.nb_queues = 1;
2656         dev_info->default_rxportconf.ring_size = 256;
2657         dev_info->default_txportconf.ring_size = 256;
2658
2659         return 0;
2660 }
2661
2662 const uint32_t *
2663 txgbe_dev_supported_ptypes_get(struct rte_eth_dev *dev)
2664 {
2665         if (dev->rx_pkt_burst == txgbe_recv_pkts ||
2666             dev->rx_pkt_burst == txgbe_recv_pkts_lro_single_alloc ||
2667             dev->rx_pkt_burst == txgbe_recv_pkts_lro_bulk_alloc ||
2668             dev->rx_pkt_burst == txgbe_recv_pkts_bulk_alloc)
2669                 return txgbe_get_supported_ptypes();
2670
2671         return NULL;
2672 }
2673
2674 void
2675 txgbe_dev_setup_link_alarm_handler(void *param)
2676 {
2677         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
2678         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2679         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2680         u32 speed;
2681         bool autoneg = false;
2682
2683         speed = hw->phy.autoneg_advertised;
2684         if (!speed)
2685                 hw->mac.get_link_capabilities(hw, &speed, &autoneg);
2686
2687         hw->mac.setup_link(hw, speed, true);
2688
2689         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2690 }
2691
2692 /* return 0 means link status changed, -1 means not changed */
2693 int
2694 txgbe_dev_link_update_share(struct rte_eth_dev *dev,
2695                             int wait_to_complete)
2696 {
2697         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2698         struct rte_eth_link link;
2699         u32 link_speed = TXGBE_LINK_SPEED_UNKNOWN;
2700         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2701         bool link_up;
2702         int err;
2703         int wait = 1;
2704
2705         memset(&link, 0, sizeof(link));
2706         link.link_status = ETH_LINK_DOWN;
2707         link.link_speed = ETH_SPEED_NUM_NONE;
2708         link.link_duplex = ETH_LINK_HALF_DUPLEX;
2709         link.link_autoneg = ETH_LINK_AUTONEG;
2710
2711         hw->mac.get_link_status = true;
2712
2713         if (intr->flags & TXGBE_FLAG_NEED_LINK_CONFIG)
2714                 return rte_eth_linkstatus_set(dev, &link);
2715
2716         /* check if it needs to wait to complete, if lsc interrupt is enabled */
2717         if (wait_to_complete == 0 || dev->data->dev_conf.intr_conf.lsc != 0)
2718                 wait = 0;
2719
2720         err = hw->mac.check_link(hw, &link_speed, &link_up, wait);
2721
2722         if (err != 0) {
2723                 link.link_speed = ETH_SPEED_NUM_100M;
2724                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2725                 return rte_eth_linkstatus_set(dev, &link);
2726         }
2727
2728         if (link_up == 0) {
2729                 if ((hw->subsystem_device_id & 0xFF) ==
2730                                 TXGBE_DEV_ID_KR_KX_KX4) {
2731                         hw->mac.bp_down_event(hw);
2732                 } else if (hw->phy.media_type == txgbe_media_type_fiber) {
2733                         intr->flags |= TXGBE_FLAG_NEED_LINK_CONFIG;
2734                         rte_eal_alarm_set(10,
2735                                 txgbe_dev_setup_link_alarm_handler, dev);
2736                 }
2737                 return rte_eth_linkstatus_set(dev, &link);
2738         }
2739
2740         intr->flags &= ~TXGBE_FLAG_NEED_LINK_CONFIG;
2741         link.link_status = ETH_LINK_UP;
2742         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2743
2744         switch (link_speed) {
2745         default:
2746         case TXGBE_LINK_SPEED_UNKNOWN:
2747                 link.link_duplex = ETH_LINK_FULL_DUPLEX;
2748                 link.link_speed = ETH_SPEED_NUM_100M;
2749                 break;
2750
2751         case TXGBE_LINK_SPEED_100M_FULL:
2752                 link.link_speed = ETH_SPEED_NUM_100M;
2753                 break;
2754
2755         case TXGBE_LINK_SPEED_1GB_FULL:
2756                 link.link_speed = ETH_SPEED_NUM_1G;
2757                 break;
2758
2759         case TXGBE_LINK_SPEED_2_5GB_FULL:
2760                 link.link_speed = ETH_SPEED_NUM_2_5G;
2761                 break;
2762
2763         case TXGBE_LINK_SPEED_5GB_FULL:
2764                 link.link_speed = ETH_SPEED_NUM_5G;
2765                 break;
2766
2767         case TXGBE_LINK_SPEED_10GB_FULL:
2768                 link.link_speed = ETH_SPEED_NUM_10G;
2769                 break;
2770         }
2771
2772         return rte_eth_linkstatus_set(dev, &link);
2773 }
2774
2775 static int
2776 txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2777 {
2778         return txgbe_dev_link_update_share(dev, wait_to_complete);
2779 }
2780
2781 static int
2782 txgbe_dev_promiscuous_enable(struct rte_eth_dev *dev)
2783 {
2784         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2785         uint32_t fctrl;
2786
2787         fctrl = rd32(hw, TXGBE_PSRCTL);
2788         fctrl |= (TXGBE_PSRCTL_UCP | TXGBE_PSRCTL_MCP);
2789         wr32(hw, TXGBE_PSRCTL, fctrl);
2790
2791         return 0;
2792 }
2793
2794 static int
2795 txgbe_dev_promiscuous_disable(struct rte_eth_dev *dev)
2796 {
2797         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2798         uint32_t fctrl;
2799
2800         fctrl = rd32(hw, TXGBE_PSRCTL);
2801         fctrl &= (~TXGBE_PSRCTL_UCP);
2802         if (dev->data->all_multicast == 1)
2803                 fctrl |= TXGBE_PSRCTL_MCP;
2804         else
2805                 fctrl &= (~TXGBE_PSRCTL_MCP);
2806         wr32(hw, TXGBE_PSRCTL, fctrl);
2807
2808         return 0;
2809 }
2810
2811 static int
2812 txgbe_dev_allmulticast_enable(struct rte_eth_dev *dev)
2813 {
2814         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2815         uint32_t fctrl;
2816
2817         fctrl = rd32(hw, TXGBE_PSRCTL);
2818         fctrl |= TXGBE_PSRCTL_MCP;
2819         wr32(hw, TXGBE_PSRCTL, fctrl);
2820
2821         return 0;
2822 }
2823
2824 static int
2825 txgbe_dev_allmulticast_disable(struct rte_eth_dev *dev)
2826 {
2827         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2828         uint32_t fctrl;
2829
2830         if (dev->data->promiscuous == 1)
2831                 return 0; /* must remain in all_multicast mode */
2832
2833         fctrl = rd32(hw, TXGBE_PSRCTL);
2834         fctrl &= (~TXGBE_PSRCTL_MCP);
2835         wr32(hw, TXGBE_PSRCTL, fctrl);
2836
2837         return 0;
2838 }
2839
2840 /**
2841  * It clears the interrupt causes and enables the interrupt.
2842  * It will be called once only during nic initialized.
2843  *
2844  * @param dev
2845  *  Pointer to struct rte_eth_dev.
2846  * @param on
2847  *  Enable or Disable.
2848  *
2849  * @return
2850  *  - On success, zero.
2851  *  - On failure, a negative value.
2852  */
2853 static int
2854 txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
2855 {
2856         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2857
2858         txgbe_dev_link_status_print(dev);
2859         if (on)
2860                 intr->mask_misc |= TXGBE_ICRMISC_LSC;
2861         else
2862                 intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
2863
2864         return 0;
2865 }
2866
2867 static int
2868 txgbe_dev_misc_interrupt_setup(struct rte_eth_dev *dev)
2869 {
2870         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2871         u64 mask;
2872
2873         mask = TXGBE_ICR_MASK;
2874         mask &= (1ULL << TXGBE_MISC_VEC_ID);
2875         intr->mask |= mask;
2876         intr->mask_misc |= TXGBE_ICRMISC_GPIO;
2877         intr->mask_misc |= TXGBE_ICRMISC_ANDONE;
2878         return 0;
2879 }
2880
2881 /**
2882  * It clears the interrupt causes and enables the interrupt.
2883  * It will be called once only during nic initialized.
2884  *
2885  * @param dev
2886  *  Pointer to struct rte_eth_dev.
2887  *
2888  * @return
2889  *  - On success, zero.
2890  *  - On failure, a negative value.
2891  */
2892 static int
2893 txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
2894 {
2895         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2896         u64 mask;
2897
2898         mask = TXGBE_ICR_MASK;
2899         mask &= ~((1ULL << TXGBE_RX_VEC_START) - 1);
2900         intr->mask |= mask;
2901
2902         return 0;
2903 }
2904
2905 /**
2906  * It clears the interrupt causes and enables the interrupt.
2907  * It will be called once only during nic initialized.
2908  *
2909  * @param dev
2910  *  Pointer to struct rte_eth_dev.
2911  *
2912  * @return
2913  *  - On success, zero.
2914  *  - On failure, a negative value.
2915  */
2916 static int
2917 txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
2918 {
2919         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2920
2921         intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
2922
2923         return 0;
2924 }
2925
2926 /*
2927  * It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
2928  *
2929  * @param dev
2930  *  Pointer to struct rte_eth_dev.
2931  *
2932  * @return
2933  *  - On success, zero.
2934  *  - On failure, a negative value.
2935  */
2936 static int
2937 txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
2938 {
2939         uint32_t eicr;
2940         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
2941         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
2942
2943         /* clear all cause mask */
2944         txgbe_disable_intr(hw);
2945
2946         /* read-on-clear nic registers here */
2947         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
2948         PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
2949
2950         intr->flags = 0;
2951
2952         /* set flag for async link update */
2953         if (eicr & TXGBE_ICRMISC_LSC)
2954                 intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
2955
2956         if (eicr & TXGBE_ICRMISC_ANDONE)
2957                 intr->flags |= TXGBE_FLAG_NEED_AN_CONFIG;
2958
2959         if (eicr & TXGBE_ICRMISC_VFMBX)
2960                 intr->flags |= TXGBE_FLAG_MAILBOX;
2961
2962         if (eicr & TXGBE_ICRMISC_LNKSEC)
2963                 intr->flags |= TXGBE_FLAG_MACSEC;
2964
2965         if (eicr & TXGBE_ICRMISC_GPIO)
2966                 intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
2967
2968         return 0;
2969 }
2970
2971 /**
2972  * It gets and then prints the link status.
2973  *
2974  * @param dev
2975  *  Pointer to struct rte_eth_dev.
2976  *
2977  * @return
2978  *  - On success, zero.
2979  *  - On failure, a negative value.
2980  */
2981 static void
2982 txgbe_dev_link_status_print(struct rte_eth_dev *dev)
2983 {
2984         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2985         struct rte_eth_link link;
2986
2987         rte_eth_linkstatus_get(dev, &link);
2988
2989         if (link.link_status) {
2990                 PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
2991                                         (int)(dev->data->port_id),
2992                                         (unsigned int)link.link_speed,
2993                         link.link_duplex == ETH_LINK_FULL_DUPLEX ?
2994                                         "full-duplex" : "half-duplex");
2995         } else {
2996                 PMD_INIT_LOG(INFO, " Port %d: Link Down",
2997                                 (int)(dev->data->port_id));
2998         }
2999         PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
3000                                 pci_dev->addr.domain,
3001                                 pci_dev->addr.bus,
3002                                 pci_dev->addr.devid,
3003                                 pci_dev->addr.function);
3004 }
3005
3006 /*
3007  * It executes link_update after knowing an interrupt occurred.
3008  *
3009  * @param dev
3010  *  Pointer to struct rte_eth_dev.
3011  *
3012  * @return
3013  *  - On success, zero.
3014  *  - On failure, a negative value.
3015  */
3016 static int
3017 txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
3018                            struct rte_intr_handle *intr_handle)
3019 {
3020         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3021         int64_t timeout;
3022         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3023
3024         PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
3025
3026         if (intr->flags & TXGBE_FLAG_MAILBOX) {
3027                 txgbe_pf_mbx_process(dev);
3028                 intr->flags &= ~TXGBE_FLAG_MAILBOX;
3029         }
3030
3031         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3032                 hw->phy.handle_lasi(hw);
3033                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3034         }
3035
3036         if (intr->flags & TXGBE_FLAG_NEED_AN_CONFIG) {
3037                 if (hw->devarg.auto_neg == 1 && hw->devarg.poll == 0) {
3038                         hw->mac.kr_handle(hw);
3039                         intr->flags &= ~TXGBE_FLAG_NEED_AN_CONFIG;
3040                 }
3041         }
3042
3043         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3044                 struct rte_eth_link link;
3045
3046                 /*get the link status before link update, for predicting later*/
3047                 rte_eth_linkstatus_get(dev, &link);
3048
3049                 txgbe_dev_link_update(dev, 0);
3050
3051                 /* likely to up */
3052                 if (!link.link_status)
3053                         /* handle it 1 sec later, wait it being stable */
3054                         timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
3055                 /* likely to down */
3056                 else if ((hw->subsystem_device_id & 0xFF) ==
3057                                 TXGBE_DEV_ID_KR_KX_KX4 &&
3058                                 hw->devarg.auto_neg == 1)
3059                         /* handle it 2 sec later for backplane AN73 */
3060                         timeout = 2000;
3061                 else
3062                         /* handle it 4 sec later, wait it being stable */
3063                         timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
3064
3065                 txgbe_dev_link_status_print(dev);
3066                 if (rte_eal_alarm_set(timeout * 1000,
3067                                       txgbe_dev_interrupt_delayed_handler,
3068                                       (void *)dev) < 0) {
3069                         PMD_DRV_LOG(ERR, "Error setting alarm");
3070                 } else {
3071                         /* only disable lsc interrupt */
3072                         intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
3073
3074                         intr->mask_orig = intr->mask;
3075                         /* only disable all misc interrupts */
3076                         intr->mask &= ~(1ULL << TXGBE_MISC_VEC_ID);
3077                 }
3078         }
3079
3080         PMD_DRV_LOG(DEBUG, "enable intr immediately");
3081         txgbe_enable_intr(dev);
3082         rte_intr_enable(intr_handle);
3083
3084         return 0;
3085 }
3086
3087 /**
3088  * Interrupt handler which shall be registered for alarm callback for delayed
3089  * handling specific interrupt to wait for the stable nic state. As the
3090  * NIC interrupt state is not stable for txgbe after link is just down,
3091  * it needs to wait 4 seconds to get the stable status.
3092  *
3093  * @param handle
3094  *  Pointer to interrupt handle.
3095  * @param param
3096  *  The address of parameter (struct rte_eth_dev *) registered before.
3097  *
3098  * @return
3099  *  void
3100  */
3101 static void
3102 txgbe_dev_interrupt_delayed_handler(void *param)
3103 {
3104         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3105         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3106         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3107         struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
3108         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3109         uint32_t eicr;
3110
3111         txgbe_disable_intr(hw);
3112
3113         eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
3114         if (eicr & TXGBE_ICRMISC_VFMBX)
3115                 txgbe_pf_mbx_process(dev);
3116
3117         if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
3118                 hw->phy.handle_lasi(hw);
3119                 intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
3120         }
3121
3122         if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
3123                 txgbe_dev_link_update(dev, 0);
3124                 intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
3125                 txgbe_dev_link_status_print(dev);
3126                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
3127                                               NULL);
3128         }
3129
3130         if (intr->flags & TXGBE_FLAG_MACSEC) {
3131                 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
3132                                               NULL);
3133                 intr->flags &= ~TXGBE_FLAG_MACSEC;
3134         }
3135
3136         /* restore original mask */
3137         intr->mask_misc |= TXGBE_ICRMISC_LSC;
3138
3139         intr->mask = intr->mask_orig;
3140         intr->mask_orig = 0;
3141
3142         PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
3143         txgbe_enable_intr(dev);
3144         rte_intr_enable(intr_handle);
3145 }
3146
3147 /**
3148  * Interrupt handler triggered by NIC  for handling
3149  * specific interrupt.
3150  *
3151  * @param handle
3152  *  Pointer to interrupt handle.
3153  * @param param
3154  *  The address of parameter (struct rte_eth_dev *) registered before.
3155  *
3156  * @return
3157  *  void
3158  */
3159 static void
3160 txgbe_dev_interrupt_handler(void *param)
3161 {
3162         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
3163
3164         txgbe_dev_interrupt_get_status(dev);
3165         txgbe_dev_interrupt_action(dev, dev->intr_handle);
3166 }
3167
3168 static int
3169 txgbe_dev_led_on(struct rte_eth_dev *dev)
3170 {
3171         struct txgbe_hw *hw;
3172
3173         hw = TXGBE_DEV_HW(dev);
3174         return txgbe_led_on(hw, 4) == 0 ? 0 : -ENOTSUP;
3175 }
3176
3177 static int
3178 txgbe_dev_led_off(struct rte_eth_dev *dev)
3179 {
3180         struct txgbe_hw *hw;
3181
3182         hw = TXGBE_DEV_HW(dev);
3183         return txgbe_led_off(hw, 4) == 0 ? 0 : -ENOTSUP;
3184 }
3185
3186 static int
3187 txgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3188 {
3189         struct txgbe_hw *hw;
3190         uint32_t mflcn_reg;
3191         uint32_t fccfg_reg;
3192         int rx_pause;
3193         int tx_pause;
3194
3195         hw = TXGBE_DEV_HW(dev);
3196
3197         fc_conf->pause_time = hw->fc.pause_time;
3198         fc_conf->high_water = hw->fc.high_water[0];
3199         fc_conf->low_water = hw->fc.low_water[0];
3200         fc_conf->send_xon = hw->fc.send_xon;
3201         fc_conf->autoneg = !hw->fc.disable_fc_autoneg;
3202
3203         /*
3204          * Return rx_pause status according to actual setting of
3205          * RXFCCFG register.
3206          */
3207         mflcn_reg = rd32(hw, TXGBE_RXFCCFG);
3208         if (mflcn_reg & (TXGBE_RXFCCFG_FC | TXGBE_RXFCCFG_PFC))
3209                 rx_pause = 1;
3210         else
3211                 rx_pause = 0;
3212
3213         /*
3214          * Return tx_pause status according to actual setting of
3215          * TXFCCFG register.
3216          */
3217         fccfg_reg = rd32(hw, TXGBE_TXFCCFG);
3218         if (fccfg_reg & (TXGBE_TXFCCFG_FC | TXGBE_TXFCCFG_PFC))
3219                 tx_pause = 1;
3220         else
3221                 tx_pause = 0;
3222
3223         if (rx_pause && tx_pause)
3224                 fc_conf->mode = RTE_FC_FULL;
3225         else if (rx_pause)
3226                 fc_conf->mode = RTE_FC_RX_PAUSE;
3227         else if (tx_pause)
3228                 fc_conf->mode = RTE_FC_TX_PAUSE;
3229         else
3230                 fc_conf->mode = RTE_FC_NONE;
3231
3232         return 0;
3233 }
3234
3235 static int
3236 txgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3237 {
3238         struct txgbe_hw *hw;
3239         int err;
3240         uint32_t rx_buf_size;
3241         uint32_t max_high_water;
3242         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3243                 txgbe_fc_none,
3244                 txgbe_fc_rx_pause,
3245                 txgbe_fc_tx_pause,
3246                 txgbe_fc_full
3247         };
3248
3249         PMD_INIT_FUNC_TRACE();
3250
3251         hw = TXGBE_DEV_HW(dev);
3252         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(0));
3253         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3254
3255         /*
3256          * At least reserve one Ethernet frame for watermark
3257          * high_water/low_water in kilo bytes for txgbe
3258          */
3259         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3260         if (fc_conf->high_water > max_high_water ||
3261             fc_conf->high_water < fc_conf->low_water) {
3262                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3263                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3264                 return -EINVAL;
3265         }
3266
3267         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[fc_conf->mode];
3268         hw->fc.pause_time     = fc_conf->pause_time;
3269         hw->fc.high_water[0]  = fc_conf->high_water;
3270         hw->fc.low_water[0]   = fc_conf->low_water;
3271         hw->fc.send_xon       = fc_conf->send_xon;
3272         hw->fc.disable_fc_autoneg = !fc_conf->autoneg;
3273
3274         err = txgbe_fc_enable(hw);
3275
3276         /* Not negotiated is not an error case */
3277         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED) {
3278                 wr32m(hw, TXGBE_MACRXFLT, TXGBE_MACRXFLT_CTL_MASK,
3279                       (fc_conf->mac_ctrl_frame_fwd
3280                        ? TXGBE_MACRXFLT_CTL_NOPS : TXGBE_MACRXFLT_CTL_DROP));
3281                 txgbe_flush(hw);
3282
3283                 return 0;
3284         }
3285
3286         PMD_INIT_LOG(ERR, "txgbe_fc_enable = 0x%x", err);
3287         return -EIO;
3288 }
3289
3290 static int
3291 txgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev,
3292                 struct rte_eth_pfc_conf *pfc_conf)
3293 {
3294         int err;
3295         uint32_t rx_buf_size;
3296         uint32_t max_high_water;
3297         uint8_t tc_num;
3298         uint8_t  map[TXGBE_DCB_UP_MAX] = { 0 };
3299         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3300         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
3301
3302         enum txgbe_fc_mode rte_fcmode_2_txgbe_fcmode[] = {
3303                 txgbe_fc_none,
3304                 txgbe_fc_rx_pause,
3305                 txgbe_fc_tx_pause,
3306                 txgbe_fc_full
3307         };
3308
3309         PMD_INIT_FUNC_TRACE();
3310
3311         txgbe_dcb_unpack_map_cee(dcb_config, TXGBE_DCB_RX_CONFIG, map);
3312         tc_num = map[pfc_conf->priority];
3313         rx_buf_size = rd32(hw, TXGBE_PBRXSIZE(tc_num));
3314         PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x", rx_buf_size);
3315         /*
3316          * At least reserve one Ethernet frame for watermark
3317          * high_water/low_water in kilo bytes for txgbe
3318          */
3319         max_high_water = (rx_buf_size - RTE_ETHER_MAX_LEN) >> 10;
3320         if (pfc_conf->fc.high_water > max_high_water ||
3321             pfc_conf->fc.high_water <= pfc_conf->fc.low_water) {
3322                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB");
3323                 PMD_INIT_LOG(ERR, "High_water must <= 0x%x", max_high_water);
3324                 return -EINVAL;
3325         }
3326
3327         hw->fc.requested_mode = rte_fcmode_2_txgbe_fcmode[pfc_conf->fc.mode];
3328         hw->fc.pause_time = pfc_conf->fc.pause_time;
3329         hw->fc.send_xon = pfc_conf->fc.send_xon;
3330         hw->fc.low_water[tc_num] =  pfc_conf->fc.low_water;
3331         hw->fc.high_water[tc_num] = pfc_conf->fc.high_water;
3332
3333         err = txgbe_dcb_pfc_enable(hw, tc_num);
3334
3335         /* Not negotiated is not an error case */
3336         if (err == 0 || err == TXGBE_ERR_FC_NOT_NEGOTIATED)
3337                 return 0;
3338
3339         PMD_INIT_LOG(ERR, "txgbe_dcb_pfc_enable = 0x%x", err);
3340         return -EIO;
3341 }
3342
3343 int
3344 txgbe_dev_rss_reta_update(struct rte_eth_dev *dev,
3345                           struct rte_eth_rss_reta_entry64 *reta_conf,
3346                           uint16_t reta_size)
3347 {
3348         uint8_t i, j, mask;
3349         uint32_t reta;
3350         uint16_t idx, shift;
3351         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
3352         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3353
3354         PMD_INIT_FUNC_TRACE();
3355
3356         if (!txgbe_rss_update_sp(hw->mac.type)) {
3357                 PMD_DRV_LOG(ERR, "RSS reta update is not supported on this "
3358                         "NIC.");
3359                 return -ENOTSUP;
3360         }
3361
3362         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3363                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3364                         "(%d) doesn't match the number hardware can supported "
3365                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3366                 return -EINVAL;
3367         }
3368
3369         for (i = 0; i < reta_size; i += 4) {
3370                 idx = i / RTE_RETA_GROUP_SIZE;
3371                 shift = i % RTE_RETA_GROUP_SIZE;
3372                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3373                 if (!mask)
3374                         continue;
3375
3376                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3377                 for (j = 0; j < 4; j++) {
3378                         if (RS8(mask, j, 0x1)) {
3379                                 reta  &= ~(MS32(8 * j, 0xFF));
3380                                 reta |= LS32(reta_conf[idx].reta[shift + j],
3381                                                 8 * j, 0xFF);
3382                         }
3383                 }
3384                 wr32at(hw, TXGBE_REG_RSSTBL, i >> 2, reta);
3385         }
3386         adapter->rss_reta_updated = 1;
3387
3388         return 0;
3389 }
3390
3391 int
3392 txgbe_dev_rss_reta_query(struct rte_eth_dev *dev,
3393                          struct rte_eth_rss_reta_entry64 *reta_conf,
3394                          uint16_t reta_size)
3395 {
3396         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3397         uint8_t i, j, mask;
3398         uint32_t reta;
3399         uint16_t idx, shift;
3400
3401         PMD_INIT_FUNC_TRACE();
3402
3403         if (reta_size != ETH_RSS_RETA_SIZE_128) {
3404                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
3405                         "(%d) doesn't match the number hardware can supported "
3406                         "(%d)", reta_size, ETH_RSS_RETA_SIZE_128);
3407                 return -EINVAL;
3408         }
3409
3410         for (i = 0; i < reta_size; i += 4) {
3411                 idx = i / RTE_RETA_GROUP_SIZE;
3412                 shift = i % RTE_RETA_GROUP_SIZE;
3413                 mask = (uint8_t)RS64(reta_conf[idx].mask, shift, 0xF);
3414                 if (!mask)
3415                         continue;
3416
3417                 reta = rd32at(hw, TXGBE_REG_RSSTBL, i >> 2);
3418                 for (j = 0; j < 4; j++) {
3419                         if (RS8(mask, j, 0x1))
3420                                 reta_conf[idx].reta[shift + j] =
3421                                         (uint16_t)RS32(reta, 8 * j, 0xFF);
3422                 }
3423         }
3424
3425         return 0;
3426 }
3427
3428 static int
3429 txgbe_add_rar(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr,
3430                                 uint32_t index, uint32_t pool)
3431 {
3432         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3433         uint32_t enable_addr = 1;
3434
3435         return txgbe_set_rar(hw, index, mac_addr->addr_bytes,
3436                              pool, enable_addr);
3437 }
3438
3439 static void
3440 txgbe_remove_rar(struct rte_eth_dev *dev, uint32_t index)
3441 {
3442         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3443
3444         txgbe_clear_rar(hw, index);
3445 }
3446
3447 static int
3448 txgbe_set_default_mac_addr(struct rte_eth_dev *dev, struct rte_ether_addr *addr)
3449 {
3450         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3451
3452         txgbe_remove_rar(dev, 0);
3453         txgbe_add_rar(dev, addr, 0, pci_dev->max_vfs);
3454
3455         return 0;
3456 }
3457
3458 static int
3459 txgbe_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3460 {
3461         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3462         struct rte_eth_dev_info dev_info;
3463         uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN;
3464         struct rte_eth_dev_data *dev_data = dev->data;
3465         int ret;
3466
3467         ret = txgbe_dev_info_get(dev, &dev_info);
3468         if (ret != 0)
3469                 return ret;
3470
3471         /* check that mtu is within the allowed range */
3472         if (mtu < RTE_ETHER_MIN_MTU || frame_size > dev_info.max_rx_pktlen)
3473                 return -EINVAL;
3474
3475         /* If device is started, refuse mtu that requires the support of
3476          * scattered packets when this feature has not been enabled before.
3477          */
3478         if (dev_data->dev_started && !dev_data->scattered_rx &&
3479             (frame_size + 2 * TXGBE_VLAN_TAG_SIZE >
3480              dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) {
3481                 PMD_INIT_LOG(ERR, "Stop port first.");
3482                 return -EINVAL;
3483         }
3484
3485         /* update max frame size */
3486         dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3487
3488         if (hw->mode)
3489                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3490                         TXGBE_FRAME_SIZE_MAX);
3491         else
3492                 wr32m(hw, TXGBE_FRMSZ, TXGBE_FRMSZ_MAX_MASK,
3493                         TXGBE_FRMSZ_MAX(frame_size));
3494
3495         return 0;
3496 }
3497
3498 static uint32_t
3499 txgbe_uta_vector(struct txgbe_hw *hw, struct rte_ether_addr *uc_addr)
3500 {
3501         uint32_t vector = 0;
3502
3503         switch (hw->mac.mc_filter_type) {
3504         case 0:   /* use bits [47:36] of the address */
3505                 vector = ((uc_addr->addr_bytes[4] >> 4) |
3506                         (((uint16_t)uc_addr->addr_bytes[5]) << 4));
3507                 break;
3508         case 1:   /* use bits [46:35] of the address */
3509                 vector = ((uc_addr->addr_bytes[4] >> 3) |
3510                         (((uint16_t)uc_addr->addr_bytes[5]) << 5));
3511                 break;
3512         case 2:   /* use bits [45:34] of the address */
3513                 vector = ((uc_addr->addr_bytes[4] >> 2) |
3514                         (((uint16_t)uc_addr->addr_bytes[5]) << 6));
3515                 break;
3516         case 3:   /* use bits [43:32] of the address */
3517                 vector = ((uc_addr->addr_bytes[4]) |
3518                         (((uint16_t)uc_addr->addr_bytes[5]) << 8));
3519                 break;
3520         default:  /* Invalid mc_filter_type */
3521                 break;
3522         }
3523
3524         /* vector can only be 12-bits or boundary will be exceeded */
3525         vector &= 0xFFF;
3526         return vector;
3527 }
3528
3529 static int
3530 txgbe_uc_hash_table_set(struct rte_eth_dev *dev,
3531                         struct rte_ether_addr *mac_addr, uint8_t on)
3532 {
3533         uint32_t vector;
3534         uint32_t uta_idx;
3535         uint32_t reg_val;
3536         uint32_t uta_mask;
3537         uint32_t psrctl;
3538
3539         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3540         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3541
3542         /* The UTA table only exists on pf hardware */
3543         if (hw->mac.type < txgbe_mac_raptor)
3544                 return -ENOTSUP;
3545
3546         vector = txgbe_uta_vector(hw, mac_addr);
3547         uta_idx = (vector >> 5) & 0x7F;
3548         uta_mask = 0x1UL << (vector & 0x1F);
3549
3550         if (!!on == !!(uta_info->uta_shadow[uta_idx] & uta_mask))
3551                 return 0;
3552
3553         reg_val = rd32(hw, TXGBE_UCADDRTBL(uta_idx));
3554         if (on) {
3555                 uta_info->uta_in_use++;
3556                 reg_val |= uta_mask;
3557                 uta_info->uta_shadow[uta_idx] |= uta_mask;
3558         } else {
3559                 uta_info->uta_in_use--;
3560                 reg_val &= ~uta_mask;
3561                 uta_info->uta_shadow[uta_idx] &= ~uta_mask;
3562         }
3563
3564         wr32(hw, TXGBE_UCADDRTBL(uta_idx), reg_val);
3565
3566         psrctl = rd32(hw, TXGBE_PSRCTL);
3567         if (uta_info->uta_in_use > 0)
3568                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3569         else
3570                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3571
3572         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3573         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3574         wr32(hw, TXGBE_PSRCTL, psrctl);
3575
3576         return 0;
3577 }
3578
3579 static int
3580 txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on)
3581 {
3582         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3583         struct txgbe_uta_info *uta_info = TXGBE_DEV_UTA_INFO(dev);
3584         uint32_t psrctl;
3585         int i;
3586
3587         /* The UTA table only exists on pf hardware */
3588         if (hw->mac.type < txgbe_mac_raptor)
3589                 return -ENOTSUP;
3590
3591         if (on) {
3592                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3593                         uta_info->uta_shadow[i] = ~0;
3594                         wr32(hw, TXGBE_UCADDRTBL(i), ~0);
3595                 }
3596         } else {
3597                 for (i = 0; i < ETH_VMDQ_NUM_UC_HASH_ARRAY; i++) {
3598                         uta_info->uta_shadow[i] = 0;
3599                         wr32(hw, TXGBE_UCADDRTBL(i), 0);
3600                 }
3601         }
3602
3603         psrctl = rd32(hw, TXGBE_PSRCTL);
3604         if (on)
3605                 psrctl |= TXGBE_PSRCTL_UCHFENA;
3606         else
3607                 psrctl &= ~TXGBE_PSRCTL_UCHFENA;
3608
3609         psrctl &= ~TXGBE_PSRCTL_ADHF12_MASK;
3610         psrctl |= TXGBE_PSRCTL_ADHF12(hw->mac.mc_filter_type);
3611         wr32(hw, TXGBE_PSRCTL, psrctl);
3612
3613         return 0;
3614 }
3615
3616 uint32_t
3617 txgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val)
3618 {
3619         uint32_t new_val = orig_val;
3620
3621         if (rx_mask & ETH_VMDQ_ACCEPT_UNTAG)
3622                 new_val |= TXGBE_POOLETHCTL_UTA;
3623         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_MC)
3624                 new_val |= TXGBE_POOLETHCTL_MCHA;
3625         if (rx_mask & ETH_VMDQ_ACCEPT_HASH_UC)
3626                 new_val |= TXGBE_POOLETHCTL_UCHA;
3627         if (rx_mask & ETH_VMDQ_ACCEPT_BROADCAST)
3628                 new_val |= TXGBE_POOLETHCTL_BCA;
3629         if (rx_mask & ETH_VMDQ_ACCEPT_MULTICAST)
3630                 new_val |= TXGBE_POOLETHCTL_MCP;
3631
3632         return new_val;
3633 }
3634
3635 static int
3636 txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
3637 {
3638         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3639         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3640         uint32_t mask;
3641         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3642
3643         if (queue_id < 32) {
3644                 mask = rd32(hw, TXGBE_IMS(0));
3645                 mask &= (1 << queue_id);
3646                 wr32(hw, TXGBE_IMS(0), mask);
3647         } else if (queue_id < 64) {
3648                 mask = rd32(hw, TXGBE_IMS(1));
3649                 mask &= (1 << (queue_id - 32));
3650                 wr32(hw, TXGBE_IMS(1), mask);
3651         }
3652         rte_intr_enable(intr_handle);
3653
3654         return 0;
3655 }
3656
3657 static int
3658 txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
3659 {
3660         uint32_t mask;
3661         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3662
3663         if (queue_id < 32) {
3664                 mask = rd32(hw, TXGBE_IMS(0));
3665                 mask &= ~(1 << queue_id);
3666                 wr32(hw, TXGBE_IMS(0), mask);
3667         } else if (queue_id < 64) {
3668                 mask = rd32(hw, TXGBE_IMS(1));
3669                 mask &= ~(1 << (queue_id - 32));
3670                 wr32(hw, TXGBE_IMS(1), mask);
3671         }
3672
3673         return 0;
3674 }
3675
3676 /**
3677  * set the IVAR registers, mapping interrupt causes to vectors
3678  * @param hw
3679  *  pointer to txgbe_hw struct
3680  * @direction
3681  *  0 for Rx, 1 for Tx, -1 for other causes
3682  * @queue
3683  *  queue to map the corresponding interrupt to
3684  * @msix_vector
3685  *  the vector to map to the corresponding queue
3686  */
3687 void
3688 txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
3689                    uint8_t queue, uint8_t msix_vector)
3690 {
3691         uint32_t tmp, idx;
3692
3693         if (direction == -1) {
3694                 /* other causes */
3695                 msix_vector |= TXGBE_IVARMISC_VLD;
3696                 idx = 0;
3697                 tmp = rd32(hw, TXGBE_IVARMISC);
3698                 tmp &= ~(0xFF << idx);
3699                 tmp |= (msix_vector << idx);
3700                 wr32(hw, TXGBE_IVARMISC, tmp);
3701         } else {
3702                 /* rx or tx causes */
3703                 /* Workround for ICR lost */
3704                 idx = ((16 * (queue & 1)) + (8 * direction));
3705                 tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
3706                 tmp &= ~(0xFF << idx);
3707                 tmp |= (msix_vector << idx);
3708                 wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
3709         }
3710 }
3711
3712 /**
3713  * Sets up the hardware to properly generate MSI-X interrupts
3714  * @hw
3715  *  board private structure
3716  */
3717 static void
3718 txgbe_configure_msix(struct rte_eth_dev *dev)
3719 {
3720         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3721         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3722         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3723         uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
3724         uint32_t vec = TXGBE_MISC_VEC_ID;
3725         uint32_t gpie;
3726
3727         /* won't configure msix register if no mapping is done
3728          * between intr vector and event fd
3729          * but if misx has been enabled already, need to configure
3730          * auto clean, auto mask and throttling.
3731          */
3732         gpie = rd32(hw, TXGBE_GPIE);
3733         if (!rte_intr_dp_is_en(intr_handle) &&
3734             !(gpie & TXGBE_GPIE_MSIX))
3735                 return;
3736
3737         if (rte_intr_allow_others(intr_handle)) {
3738                 base = TXGBE_RX_VEC_START;
3739                 vec = base;
3740         }
3741
3742         /* setup GPIE for MSI-x mode */
3743         gpie = rd32(hw, TXGBE_GPIE);
3744         gpie |= TXGBE_GPIE_MSIX;
3745         wr32(hw, TXGBE_GPIE, gpie);
3746
3747         /* Populate the IVAR table and set the ITR values to the
3748          * corresponding register.
3749          */
3750         if (rte_intr_dp_is_en(intr_handle)) {
3751                 for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
3752                         queue_id++) {
3753                         /* by default, 1:1 mapping */
3754                         txgbe_set_ivar_map(hw, 0, queue_id, vec);
3755                         intr_handle->intr_vec[queue_id] = vec;
3756                         if (vec < base + intr_handle->nb_efd - 1)
3757                                 vec++;
3758                 }
3759
3760                 txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
3761         }
3762         wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
3763                         TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
3764                         | TXGBE_ITR_WRDSA);
3765 }
3766
3767 int
3768 txgbe_set_queue_rate_limit(struct rte_eth_dev *dev,
3769                            uint16_t queue_idx, uint16_t tx_rate)
3770 {
3771         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3772         uint32_t bcnrc_val;
3773
3774         if (queue_idx >= hw->mac.max_tx_queues)
3775                 return -EINVAL;
3776
3777         if (tx_rate != 0) {
3778                 bcnrc_val = TXGBE_ARBTXRATE_MAX(tx_rate);
3779                 bcnrc_val |= TXGBE_ARBTXRATE_MIN(tx_rate / 2);
3780         } else {
3781                 bcnrc_val = 0;
3782         }
3783
3784         /*
3785          * Set global transmit compensation time to the MMW_SIZE in ARBTXMMW
3786          * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
3787          */
3788         wr32(hw, TXGBE_ARBTXMMW, 0x14);
3789
3790         /* Set ARBTXRATE of queue X */
3791         wr32(hw, TXGBE_ARBPOOLIDX, queue_idx);
3792         wr32(hw, TXGBE_ARBTXRATE, bcnrc_val);
3793         txgbe_flush(hw);
3794
3795         return 0;
3796 }
3797
3798 int
3799 txgbe_syn_filter_set(struct rte_eth_dev *dev,
3800                         struct rte_eth_syn_filter *filter,
3801                         bool add)
3802 {
3803         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3804         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3805         uint32_t syn_info;
3806         uint32_t synqf;
3807
3808         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
3809                 return -EINVAL;
3810
3811         syn_info = filter_info->syn_info;
3812
3813         if (add) {
3814                 if (syn_info & TXGBE_SYNCLS_ENA)
3815                         return -EINVAL;
3816                 synqf = (uint32_t)TXGBE_SYNCLS_QPID(filter->queue);
3817                 synqf |= TXGBE_SYNCLS_ENA;
3818
3819                 if (filter->hig_pri)
3820                         synqf |= TXGBE_SYNCLS_HIPRIO;
3821                 else
3822                         synqf &= ~TXGBE_SYNCLS_HIPRIO;
3823         } else {
3824                 synqf = rd32(hw, TXGBE_SYNCLS);
3825                 if (!(syn_info & TXGBE_SYNCLS_ENA))
3826                         return -ENOENT;
3827                 synqf &= ~(TXGBE_SYNCLS_QPID_MASK | TXGBE_SYNCLS_ENA);
3828         }
3829
3830         filter_info->syn_info = synqf;
3831         wr32(hw, TXGBE_SYNCLS, synqf);
3832         txgbe_flush(hw);
3833         return 0;
3834 }
3835
3836 static inline enum txgbe_5tuple_protocol
3837 convert_protocol_type(uint8_t protocol_value)
3838 {
3839         if (protocol_value == IPPROTO_TCP)
3840                 return TXGBE_5TF_PROT_TCP;
3841         else if (protocol_value == IPPROTO_UDP)
3842                 return TXGBE_5TF_PROT_UDP;
3843         else if (protocol_value == IPPROTO_SCTP)
3844                 return TXGBE_5TF_PROT_SCTP;
3845         else
3846                 return TXGBE_5TF_PROT_NONE;
3847 }
3848
3849 /* inject a 5-tuple filter to HW */
3850 static inline void
3851 txgbe_inject_5tuple_filter(struct rte_eth_dev *dev,
3852                            struct txgbe_5tuple_filter *filter)
3853 {
3854         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3855         int i;
3856         uint32_t ftqf, sdpqf;
3857         uint32_t l34timir = 0;
3858         uint32_t mask = TXGBE_5TFCTL0_MASK;
3859
3860         i = filter->index;
3861         sdpqf = TXGBE_5TFPORT_DST(be_to_le16(filter->filter_info.dst_port));
3862         sdpqf |= TXGBE_5TFPORT_SRC(be_to_le16(filter->filter_info.src_port));
3863
3864         ftqf = TXGBE_5TFCTL0_PROTO(filter->filter_info.proto);
3865         ftqf |= TXGBE_5TFCTL0_PRI(filter->filter_info.priority);
3866         if (filter->filter_info.src_ip_mask == 0) /* 0 means compare. */
3867                 mask &= ~TXGBE_5TFCTL0_MSADDR;
3868         if (filter->filter_info.dst_ip_mask == 0)
3869                 mask &= ~TXGBE_5TFCTL0_MDADDR;
3870         if (filter->filter_info.src_port_mask == 0)
3871                 mask &= ~TXGBE_5TFCTL0_MSPORT;
3872         if (filter->filter_info.dst_port_mask == 0)
3873                 mask &= ~TXGBE_5TFCTL0_MDPORT;
3874         if (filter->filter_info.proto_mask == 0)
3875                 mask &= ~TXGBE_5TFCTL0_MPROTO;
3876         ftqf |= mask;
3877         ftqf |= TXGBE_5TFCTL0_MPOOL;
3878         ftqf |= TXGBE_5TFCTL0_ENA;
3879
3880         wr32(hw, TXGBE_5TFDADDR(i), be_to_le32(filter->filter_info.dst_ip));
3881         wr32(hw, TXGBE_5TFSADDR(i), be_to_le32(filter->filter_info.src_ip));
3882         wr32(hw, TXGBE_5TFPORT(i), sdpqf);
3883         wr32(hw, TXGBE_5TFCTL0(i), ftqf);
3884
3885         l34timir |= TXGBE_5TFCTL1_QP(filter->queue);
3886         wr32(hw, TXGBE_5TFCTL1(i), l34timir);
3887 }
3888
3889 /*
3890  * add a 5tuple filter
3891  *
3892  * @param
3893  * dev: Pointer to struct rte_eth_dev.
3894  * index: the index the filter allocates.
3895  * filter: pointer to the filter that will be added.
3896  * rx_queue: the queue id the filter assigned to.
3897  *
3898  * @return
3899  *    - On success, zero.
3900  *    - On failure, a negative value.
3901  */
3902 static int
3903 txgbe_add_5tuple_filter(struct rte_eth_dev *dev,
3904                         struct txgbe_5tuple_filter *filter)
3905 {
3906         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3907         int i, idx, shift;
3908
3909         /*
3910          * look for an unused 5tuple filter index,
3911          * and insert the filter to list.
3912          */
3913         for (i = 0; i < TXGBE_MAX_FTQF_FILTERS; i++) {
3914                 idx = i / (sizeof(uint32_t) * NBBY);
3915                 shift = i % (sizeof(uint32_t) * NBBY);
3916                 if (!(filter_info->fivetuple_mask[idx] & (1 << shift))) {
3917                         filter_info->fivetuple_mask[idx] |= 1 << shift;
3918                         filter->index = i;
3919                         TAILQ_INSERT_TAIL(&filter_info->fivetuple_list,
3920                                           filter,
3921                                           entries);
3922                         break;
3923                 }
3924         }
3925         if (i >= TXGBE_MAX_FTQF_FILTERS) {
3926                 PMD_DRV_LOG(ERR, "5tuple filters are full.");
3927                 return -ENOSYS;
3928         }
3929
3930         txgbe_inject_5tuple_filter(dev, filter);
3931
3932         return 0;
3933 }
3934
3935 /*
3936  * remove a 5tuple filter
3937  *
3938  * @param
3939  * dev: Pointer to struct rte_eth_dev.
3940  * filter: the pointer of the filter will be removed.
3941  */
3942 static void
3943 txgbe_remove_5tuple_filter(struct rte_eth_dev *dev,
3944                         struct txgbe_5tuple_filter *filter)
3945 {
3946         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
3947         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
3948         uint16_t index = filter->index;
3949
3950         filter_info->fivetuple_mask[index / (sizeof(uint32_t) * NBBY)] &=
3951                                 ~(1 << (index % (sizeof(uint32_t) * NBBY)));
3952         TAILQ_REMOVE(&filter_info->fivetuple_list, filter, entries);
3953         rte_free(filter);
3954
3955         wr32(hw, TXGBE_5TFDADDR(index), 0);
3956         wr32(hw, TXGBE_5TFSADDR(index), 0);
3957         wr32(hw, TXGBE_5TFPORT(index), 0);
3958         wr32(hw, TXGBE_5TFCTL0(index), 0);
3959         wr32(hw, TXGBE_5TFCTL1(index), 0);
3960 }
3961
3962 static inline struct txgbe_5tuple_filter *
3963 txgbe_5tuple_filter_lookup(struct txgbe_5tuple_filter_list *filter_list,
3964                         struct txgbe_5tuple_filter_info *key)
3965 {
3966         struct txgbe_5tuple_filter *it;
3967
3968         TAILQ_FOREACH(it, filter_list, entries) {
3969                 if (memcmp(key, &it->filter_info,
3970                         sizeof(struct txgbe_5tuple_filter_info)) == 0) {
3971                         return it;
3972                 }
3973         }
3974         return NULL;
3975 }
3976
3977 /* translate elements in struct rte_eth_ntuple_filter
3978  * to struct txgbe_5tuple_filter_info
3979  */
3980 static inline int
3981 ntuple_filter_to_5tuple(struct rte_eth_ntuple_filter *filter,
3982                         struct txgbe_5tuple_filter_info *filter_info)
3983 {
3984         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM ||
3985                 filter->priority > TXGBE_5TUPLE_MAX_PRI ||
3986                 filter->priority < TXGBE_5TUPLE_MIN_PRI)
3987                 return -EINVAL;
3988
3989         switch (filter->dst_ip_mask) {
3990         case UINT32_MAX:
3991                 filter_info->dst_ip_mask = 0;
3992                 filter_info->dst_ip = filter->dst_ip;
3993                 break;
3994         case 0:
3995                 filter_info->dst_ip_mask = 1;
3996                 break;
3997         default:
3998                 PMD_DRV_LOG(ERR, "invalid dst_ip mask.");
3999                 return -EINVAL;
4000         }
4001
4002         switch (filter->src_ip_mask) {
4003         case UINT32_MAX:
4004                 filter_info->src_ip_mask = 0;
4005                 filter_info->src_ip = filter->src_ip;
4006                 break;
4007         case 0:
4008                 filter_info->src_ip_mask = 1;
4009                 break;
4010         default:
4011                 PMD_DRV_LOG(ERR, "invalid src_ip mask.");
4012                 return -EINVAL;
4013         }
4014
4015         switch (filter->dst_port_mask) {
4016         case UINT16_MAX:
4017                 filter_info->dst_port_mask = 0;
4018                 filter_info->dst_port = filter->dst_port;
4019                 break;
4020         case 0:
4021                 filter_info->dst_port_mask = 1;
4022                 break;
4023         default:
4024                 PMD_DRV_LOG(ERR, "invalid dst_port mask.");
4025                 return -EINVAL;
4026         }
4027
4028         switch (filter->src_port_mask) {
4029         case UINT16_MAX:
4030                 filter_info->src_port_mask = 0;
4031                 filter_info->src_port = filter->src_port;
4032                 break;
4033         case 0:
4034                 filter_info->src_port_mask = 1;
4035                 break;
4036         default:
4037                 PMD_DRV_LOG(ERR, "invalid src_port mask.");
4038                 return -EINVAL;
4039         }
4040
4041         switch (filter->proto_mask) {
4042         case UINT8_MAX:
4043                 filter_info->proto_mask = 0;
4044                 filter_info->proto =
4045                         convert_protocol_type(filter->proto);
4046                 break;
4047         case 0:
4048                 filter_info->proto_mask = 1;
4049                 break;
4050         default:
4051                 PMD_DRV_LOG(ERR, "invalid protocol mask.");
4052                 return -EINVAL;
4053         }
4054
4055         filter_info->priority = (uint8_t)filter->priority;
4056         return 0;
4057 }
4058
4059 /*
4060  * add or delete a ntuple filter
4061  *
4062  * @param
4063  * dev: Pointer to struct rte_eth_dev.
4064  * ntuple_filter: Pointer to struct rte_eth_ntuple_filter
4065  * add: if true, add filter, if false, remove filter
4066  *
4067  * @return
4068  *    - On success, zero.
4069  *    - On failure, a negative value.
4070  */
4071 int
4072 txgbe_add_del_ntuple_filter(struct rte_eth_dev *dev,
4073                         struct rte_eth_ntuple_filter *ntuple_filter,
4074                         bool add)
4075 {
4076         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4077         struct txgbe_5tuple_filter_info filter_5tuple;
4078         struct txgbe_5tuple_filter *filter;
4079         int ret;
4080
4081         if (ntuple_filter->flags != RTE_5TUPLE_FLAGS) {
4082                 PMD_DRV_LOG(ERR, "only 5tuple is supported.");
4083                 return -EINVAL;
4084         }
4085
4086         memset(&filter_5tuple, 0, sizeof(struct txgbe_5tuple_filter_info));
4087         ret = ntuple_filter_to_5tuple(ntuple_filter, &filter_5tuple);
4088         if (ret < 0)
4089                 return ret;
4090
4091         filter = txgbe_5tuple_filter_lookup(&filter_info->fivetuple_list,
4092                                          &filter_5tuple);
4093         if (filter != NULL && add) {
4094                 PMD_DRV_LOG(ERR, "filter exists.");
4095                 return -EEXIST;
4096         }
4097         if (filter == NULL && !add) {
4098                 PMD_DRV_LOG(ERR, "filter doesn't exist.");
4099                 return -ENOENT;
4100         }
4101
4102         if (add) {
4103                 filter = rte_zmalloc("txgbe_5tuple_filter",
4104                                 sizeof(struct txgbe_5tuple_filter), 0);
4105                 if (filter == NULL)
4106                         return -ENOMEM;
4107                 rte_memcpy(&filter->filter_info,
4108                                  &filter_5tuple,
4109                                  sizeof(struct txgbe_5tuple_filter_info));
4110                 filter->queue = ntuple_filter->queue;
4111                 ret = txgbe_add_5tuple_filter(dev, filter);
4112                 if (ret < 0) {
4113                         rte_free(filter);
4114                         return ret;
4115                 }
4116         } else {
4117                 txgbe_remove_5tuple_filter(dev, filter);
4118         }
4119
4120         return 0;
4121 }
4122
4123 int
4124 txgbe_add_del_ethertype_filter(struct rte_eth_dev *dev,
4125                         struct rte_eth_ethertype_filter *filter,
4126                         bool add)
4127 {
4128         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4129         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
4130         uint32_t etqf = 0;
4131         uint32_t etqs = 0;
4132         int ret;
4133         struct txgbe_ethertype_filter ethertype_filter;
4134
4135         if (filter->queue >= TXGBE_MAX_RX_QUEUE_NUM)
4136                 return -EINVAL;
4137
4138         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
4139             filter->ether_type == RTE_ETHER_TYPE_IPV6) {
4140                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
4141                         " ethertype filter.", filter->ether_type);
4142                 return -EINVAL;
4143         }
4144
4145         if (filter->flags & RTE_ETHTYPE_FLAGS_MAC) {
4146                 PMD_DRV_LOG(ERR, "mac compare is unsupported.");
4147                 return -EINVAL;
4148         }
4149         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP) {
4150                 PMD_DRV_LOG(ERR, "drop option is unsupported.");
4151                 return -EINVAL;
4152         }
4153
4154         ret = txgbe_ethertype_filter_lookup(filter_info, filter->ether_type);
4155         if (ret >= 0 && add) {
4156                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter exists.",
4157                             filter->ether_type);
4158                 return -EEXIST;
4159         }
4160         if (ret < 0 && !add) {
4161                 PMD_DRV_LOG(ERR, "ethertype (0x%04x) filter doesn't exist.",
4162                             filter->ether_type);
4163                 return -ENOENT;
4164         }
4165
4166         if (add) {
4167                 etqf = TXGBE_ETFLT_ENA;
4168                 etqf |= TXGBE_ETFLT_ETID(filter->ether_type);
4169                 etqs |= TXGBE_ETCLS_QPID(filter->queue);
4170                 etqs |= TXGBE_ETCLS_QENA;
4171
4172                 ethertype_filter.ethertype = filter->ether_type;
4173                 ethertype_filter.etqf = etqf;
4174                 ethertype_filter.etqs = etqs;
4175                 ethertype_filter.conf = FALSE;
4176                 ret = txgbe_ethertype_filter_insert(filter_info,
4177                                                     &ethertype_filter);
4178                 if (ret < 0) {
4179                         PMD_DRV_LOG(ERR, "ethertype filters are full.");
4180                         return -ENOSPC;
4181                 }
4182         } else {
4183                 ret = txgbe_ethertype_filter_remove(filter_info, (uint8_t)ret);
4184                 if (ret < 0)
4185                         return -ENOSYS;
4186         }
4187         wr32(hw, TXGBE_ETFLT(ret), etqf);
4188         wr32(hw, TXGBE_ETCLS(ret), etqs);
4189         txgbe_flush(hw);
4190
4191         return 0;
4192 }
4193
4194 static int
4195 txgbe_dev_flow_ops_get(__rte_unused struct rte_eth_dev *dev,
4196                        const struct rte_flow_ops **ops)
4197 {
4198         *ops = &txgbe_flow_ops;
4199         return 0;
4200 }
4201
4202 static u8 *
4203 txgbe_dev_addr_list_itr(__rte_unused struct txgbe_hw *hw,
4204                         u8 **mc_addr_ptr, u32 *vmdq)
4205 {
4206         u8 *mc_addr;
4207
4208         *vmdq = 0;
4209         mc_addr = *mc_addr_ptr;
4210         *mc_addr_ptr = (mc_addr + sizeof(struct rte_ether_addr));
4211         return mc_addr;
4212 }
4213
4214 int
4215 txgbe_dev_set_mc_addr_list(struct rte_eth_dev *dev,
4216                           struct rte_ether_addr *mc_addr_set,
4217                           uint32_t nb_mc_addr)
4218 {
4219         struct txgbe_hw *hw;
4220         u8 *mc_addr_list;
4221
4222         hw = TXGBE_DEV_HW(dev);
4223         mc_addr_list = (u8 *)mc_addr_set;
4224         return hw->mac.update_mc_addr_list(hw, mc_addr_list, nb_mc_addr,
4225                                          txgbe_dev_addr_list_itr, TRUE);
4226 }
4227
4228 static uint64_t
4229 txgbe_read_systime_cyclecounter(struct rte_eth_dev *dev)
4230 {
4231         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4232         uint64_t systime_cycles;
4233
4234         systime_cycles = (uint64_t)rd32(hw, TXGBE_TSTIMEL);
4235         systime_cycles |= (uint64_t)rd32(hw, TXGBE_TSTIMEH) << 32;
4236
4237         return systime_cycles;
4238 }
4239
4240 static uint64_t
4241 txgbe_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4242 {
4243         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4244         uint64_t rx_tstamp_cycles;
4245
4246         /* TSRXSTMPL stores ns and TSRXSTMPH stores seconds. */
4247         rx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSRXSTMPL);
4248         rx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSRXSTMPH) << 32;
4249
4250         return rx_tstamp_cycles;
4251 }
4252
4253 static uint64_t
4254 txgbe_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
4255 {
4256         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4257         uint64_t tx_tstamp_cycles;
4258
4259         /* TSTXSTMPL stores ns and TSTXSTMPH stores seconds. */
4260         tx_tstamp_cycles = (uint64_t)rd32(hw, TXGBE_TSTXSTMPL);
4261         tx_tstamp_cycles |= (uint64_t)rd32(hw, TXGBE_TSTXSTMPH) << 32;
4262
4263         return tx_tstamp_cycles;
4264 }
4265
4266 static void
4267 txgbe_start_timecounters(struct rte_eth_dev *dev)
4268 {
4269         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4270         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4271         struct rte_eth_link link;
4272         uint32_t incval = 0;
4273         uint32_t shift = 0;
4274
4275         /* Get current link speed. */
4276         txgbe_dev_link_update(dev, 1);
4277         rte_eth_linkstatus_get(dev, &link);
4278
4279         switch (link.link_speed) {
4280         case ETH_SPEED_NUM_100M:
4281                 incval = TXGBE_INCVAL_100;
4282                 shift = TXGBE_INCVAL_SHIFT_100;
4283                 break;
4284         case ETH_SPEED_NUM_1G:
4285                 incval = TXGBE_INCVAL_1GB;
4286                 shift = TXGBE_INCVAL_SHIFT_1GB;
4287                 break;
4288         case ETH_SPEED_NUM_10G:
4289         default:
4290                 incval = TXGBE_INCVAL_10GB;
4291                 shift = TXGBE_INCVAL_SHIFT_10GB;
4292                 break;
4293         }
4294
4295         wr32(hw, TXGBE_TSTIMEINC, TXGBE_TSTIMEINC_VP(incval, 2));
4296
4297         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
4298         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4299         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
4300
4301         adapter->systime_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4302         adapter->systime_tc.cc_shift = shift;
4303         adapter->systime_tc.nsec_mask = (1ULL << shift) - 1;
4304
4305         adapter->rx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4306         adapter->rx_tstamp_tc.cc_shift = shift;
4307         adapter->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4308
4309         adapter->tx_tstamp_tc.cc_mask = TXGBE_CYCLECOUNTER_MASK;
4310         adapter->tx_tstamp_tc.cc_shift = shift;
4311         adapter->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1;
4312 }
4313
4314 static int
4315 txgbe_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
4316 {
4317         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4318
4319         adapter->systime_tc.nsec += delta;
4320         adapter->rx_tstamp_tc.nsec += delta;
4321         adapter->tx_tstamp_tc.nsec += delta;
4322
4323         return 0;
4324 }
4325
4326 static int
4327 txgbe_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
4328 {
4329         uint64_t ns;
4330         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4331
4332         ns = rte_timespec_to_ns(ts);
4333         /* Set the timecounters to a new value. */
4334         adapter->systime_tc.nsec = ns;
4335         adapter->rx_tstamp_tc.nsec = ns;
4336         adapter->tx_tstamp_tc.nsec = ns;
4337
4338         return 0;
4339 }
4340
4341 static int
4342 txgbe_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
4343 {
4344         uint64_t ns, systime_cycles;
4345         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4346
4347         systime_cycles = txgbe_read_systime_cyclecounter(dev);
4348         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
4349         *ts = rte_ns_to_timespec(ns);
4350
4351         return 0;
4352 }
4353
4354 static int
4355 txgbe_timesync_enable(struct rte_eth_dev *dev)
4356 {
4357         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4358         uint32_t tsync_ctl;
4359
4360         /* Stop the timesync system time. */
4361         wr32(hw, TXGBE_TSTIMEINC, 0x0);
4362         /* Reset the timesync system time value. */
4363         wr32(hw, TXGBE_TSTIMEL, 0x0);
4364         wr32(hw, TXGBE_TSTIMEH, 0x0);
4365
4366         txgbe_start_timecounters(dev);
4367
4368         /* Enable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4369         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588),
4370                 RTE_ETHER_TYPE_1588 | TXGBE_ETFLT_ENA | TXGBE_ETFLT_1588);
4371
4372         /* Enable timestamping of received PTP packets. */
4373         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4374         tsync_ctl |= TXGBE_TSRXCTL_ENA;
4375         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4376
4377         /* Enable timestamping of transmitted PTP packets. */
4378         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4379         tsync_ctl |= TXGBE_TSTXCTL_ENA;
4380         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4381
4382         txgbe_flush(hw);
4383
4384         return 0;
4385 }
4386
4387 static int
4388 txgbe_timesync_disable(struct rte_eth_dev *dev)
4389 {
4390         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4391         uint32_t tsync_ctl;
4392
4393         /* Disable timestamping of transmitted PTP packets. */
4394         tsync_ctl = rd32(hw, TXGBE_TSTXCTL);
4395         tsync_ctl &= ~TXGBE_TSTXCTL_ENA;
4396         wr32(hw, TXGBE_TSTXCTL, tsync_ctl);
4397
4398         /* Disable timestamping of received PTP packets. */
4399         tsync_ctl = rd32(hw, TXGBE_TSRXCTL);
4400         tsync_ctl &= ~TXGBE_TSRXCTL_ENA;
4401         wr32(hw, TXGBE_TSRXCTL, tsync_ctl);
4402
4403         /* Disable L2 filtering of IEEE1588/802.1AS Ethernet frame types. */
4404         wr32(hw, TXGBE_ETFLT(TXGBE_ETF_ID_1588), 0);
4405
4406         /* Stop incrementating the System Time registers. */
4407         wr32(hw, TXGBE_TSTIMEINC, 0);
4408
4409         return 0;
4410 }
4411
4412 static int
4413 txgbe_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
4414                                  struct timespec *timestamp,
4415                                  uint32_t flags __rte_unused)
4416 {
4417         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4418         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4419         uint32_t tsync_rxctl;
4420         uint64_t rx_tstamp_cycles;
4421         uint64_t ns;
4422
4423         tsync_rxctl = rd32(hw, TXGBE_TSRXCTL);
4424         if ((tsync_rxctl & TXGBE_TSRXCTL_VLD) == 0)
4425                 return -EINVAL;
4426
4427         rx_tstamp_cycles = txgbe_read_rx_tstamp_cyclecounter(dev);
4428         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
4429         *timestamp = rte_ns_to_timespec(ns);
4430
4431         return  0;
4432 }
4433
4434 static int
4435 txgbe_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
4436                                  struct timespec *timestamp)
4437 {
4438         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4439         struct txgbe_adapter *adapter = TXGBE_DEV_ADAPTER(dev);
4440         uint32_t tsync_txctl;
4441         uint64_t tx_tstamp_cycles;
4442         uint64_t ns;
4443
4444         tsync_txctl = rd32(hw, TXGBE_TSTXCTL);
4445         if ((tsync_txctl & TXGBE_TSTXCTL_VLD) == 0)
4446                 return -EINVAL;
4447
4448         tx_tstamp_cycles = txgbe_read_tx_tstamp_cyclecounter(dev);
4449         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
4450         *timestamp = rte_ns_to_timespec(ns);
4451
4452         return 0;
4453 }
4454
4455 static int
4456 txgbe_get_reg_length(struct rte_eth_dev *dev __rte_unused)
4457 {
4458         int count = 0;
4459         int g_ind = 0;
4460         const struct reg_info *reg_group;
4461         const struct reg_info **reg_set = txgbe_regs_others;
4462
4463         while ((reg_group = reg_set[g_ind++]))
4464                 count += txgbe_regs_group_count(reg_group);
4465
4466         return count;
4467 }
4468
4469 static int
4470 txgbe_get_regs(struct rte_eth_dev *dev,
4471               struct rte_dev_reg_info *regs)
4472 {
4473         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4474         uint32_t *data = regs->data;
4475         int g_ind = 0;
4476         int count = 0;
4477         const struct reg_info *reg_group;
4478         const struct reg_info **reg_set = txgbe_regs_others;
4479
4480         if (data == NULL) {
4481                 regs->length = txgbe_get_reg_length(dev);
4482                 regs->width = sizeof(uint32_t);
4483                 return 0;
4484         }
4485
4486         /* Support only full register dump */
4487         if (regs->length == 0 ||
4488             regs->length == (uint32_t)txgbe_get_reg_length(dev)) {
4489                 regs->version = hw->mac.type << 24 |
4490                                 hw->revision_id << 16 |
4491                                 hw->device_id;
4492                 while ((reg_group = reg_set[g_ind++]))
4493                         count += txgbe_read_regs_group(dev, &data[count],
4494                                                       reg_group);
4495                 return 0;
4496         }
4497
4498         return -ENOTSUP;
4499 }
4500
4501 static int
4502 txgbe_get_eeprom_length(struct rte_eth_dev *dev)
4503 {
4504         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4505
4506         /* Return unit is byte count */
4507         return hw->rom.word_size * 2;
4508 }
4509
4510 static int
4511 txgbe_get_eeprom(struct rte_eth_dev *dev,
4512                 struct rte_dev_eeprom_info *in_eeprom)
4513 {
4514         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4515         struct txgbe_rom_info *eeprom = &hw->rom;
4516         uint16_t *data = in_eeprom->data;
4517         int first, length;
4518
4519         first = in_eeprom->offset >> 1;
4520         length = in_eeprom->length >> 1;
4521         if (first > hw->rom.word_size ||
4522             ((first + length) > hw->rom.word_size))
4523                 return -EINVAL;
4524
4525         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4526
4527         return eeprom->readw_buffer(hw, first, length, data);
4528 }
4529
4530 static int
4531 txgbe_set_eeprom(struct rte_eth_dev *dev,
4532                 struct rte_dev_eeprom_info *in_eeprom)
4533 {
4534         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4535         struct txgbe_rom_info *eeprom = &hw->rom;
4536         uint16_t *data = in_eeprom->data;
4537         int first, length;
4538
4539         first = in_eeprom->offset >> 1;
4540         length = in_eeprom->length >> 1;
4541         if (first > hw->rom.word_size ||
4542             ((first + length) > hw->rom.word_size))
4543                 return -EINVAL;
4544
4545         in_eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4546
4547         return eeprom->writew_buffer(hw,  first, length, data);
4548 }
4549
4550 static int
4551 txgbe_get_module_info(struct rte_eth_dev *dev,
4552                       struct rte_eth_dev_module_info *modinfo)
4553 {
4554         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4555         uint32_t status;
4556         uint8_t sff8472_rev, addr_mode;
4557         bool page_swap = false;
4558
4559         /* Check whether we support SFF-8472 or not */
4560         status = hw->phy.read_i2c_eeprom(hw,
4561                                              TXGBE_SFF_SFF_8472_COMP,
4562                                              &sff8472_rev);
4563         if (status != 0)
4564                 return -EIO;
4565
4566         /* addressing mode is not supported */
4567         status = hw->phy.read_i2c_eeprom(hw,
4568                                              TXGBE_SFF_SFF_8472_SWAP,
4569                                              &addr_mode);
4570         if (status != 0)
4571                 return -EIO;
4572
4573         if (addr_mode & TXGBE_SFF_ADDRESSING_MODE) {
4574                 PMD_DRV_LOG(ERR,
4575                             "Address change required to access page 0xA2, "
4576                             "but not supported. Please report the module "
4577                             "type to the driver maintainers.");
4578                 page_swap = true;
4579         }
4580
4581         if (sff8472_rev == TXGBE_SFF_SFF_8472_UNSUP || page_swap) {
4582                 /* We have a SFP, but it does not support SFF-8472 */
4583                 modinfo->type = RTE_ETH_MODULE_SFF_8079;
4584                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
4585         } else {
4586                 /* We have a SFP which supports a revision of SFF-8472. */
4587                 modinfo->type = RTE_ETH_MODULE_SFF_8472;
4588                 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
4589         }
4590
4591         return 0;
4592 }
4593
4594 static int
4595 txgbe_get_module_eeprom(struct rte_eth_dev *dev,
4596                         struct rte_dev_eeprom_info *info)
4597 {
4598         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4599         uint32_t status = TXGBE_ERR_PHY_ADDR_INVALID;
4600         uint8_t databyte = 0xFF;
4601         uint8_t *data = info->data;
4602         uint32_t i = 0;
4603
4604         if (info->length == 0)
4605                 return -EINVAL;
4606
4607         for (i = info->offset; i < info->offset + info->length; i++) {
4608                 if (i < RTE_ETH_MODULE_SFF_8079_LEN)
4609                         status = hw->phy.read_i2c_eeprom(hw, i, &databyte);
4610                 else
4611                         status = hw->phy.read_i2c_sff8472(hw, i, &databyte);
4612
4613                 if (status != 0)
4614                         return -EIO;
4615
4616                 data[i - info->offset] = databyte;
4617         }
4618
4619         return 0;
4620 }
4621
4622 bool
4623 txgbe_rss_update_sp(enum txgbe_mac_type mac_type)
4624 {
4625         switch (mac_type) {
4626         case txgbe_mac_raptor:
4627         case txgbe_mac_raptor_vf:
4628                 return 1;
4629         default:
4630                 return 0;
4631         }
4632 }
4633
4634 static int
4635 txgbe_dev_get_dcb_info(struct rte_eth_dev *dev,
4636                         struct rte_eth_dcb_info *dcb_info)
4637 {
4638         struct txgbe_dcb_config *dcb_config = TXGBE_DEV_DCB_CONFIG(dev);
4639         struct txgbe_dcb_tc_config *tc;
4640         struct rte_eth_dcb_tc_queue_mapping *tc_queue;
4641         uint8_t nb_tcs;
4642         uint8_t i, j;
4643
4644         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
4645                 dcb_info->nb_tcs = dcb_config->num_tcs.pg_tcs;
4646         else
4647                 dcb_info->nb_tcs = 1;
4648
4649         tc_queue = &dcb_info->tc_queue;
4650         nb_tcs = dcb_info->nb_tcs;
4651
4652         if (dcb_config->vt_mode) { /* vt is enabled */
4653                 struct rte_eth_vmdq_dcb_conf *vmdq_rx_conf =
4654                                 &dev->data->dev_conf.rx_adv_conf.vmdq_dcb_conf;
4655                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4656                         dcb_info->prio_tc[i] = vmdq_rx_conf->dcb_tc[i];
4657                 if (RTE_ETH_DEV_SRIOV(dev).active > 0) {
4658                         for (j = 0; j < nb_tcs; j++) {
4659                                 tc_queue->tc_rxq[0][j].base = j;
4660                                 tc_queue->tc_rxq[0][j].nb_queue = 1;
4661                                 tc_queue->tc_txq[0][j].base = j;
4662                                 tc_queue->tc_txq[0][j].nb_queue = 1;
4663                         }
4664                 } else {
4665                         for (i = 0; i < vmdq_rx_conf->nb_queue_pools; i++) {
4666                                 for (j = 0; j < nb_tcs; j++) {
4667                                         tc_queue->tc_rxq[i][j].base =
4668                                                 i * nb_tcs + j;
4669                                         tc_queue->tc_rxq[i][j].nb_queue = 1;
4670                                         tc_queue->tc_txq[i][j].base =
4671                                                 i * nb_tcs + j;
4672                                         tc_queue->tc_txq[i][j].nb_queue = 1;
4673                                 }
4674                         }
4675                 }
4676         } else { /* vt is disabled */
4677                 struct rte_eth_dcb_rx_conf *rx_conf =
4678                                 &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
4679                 for (i = 0; i < ETH_DCB_NUM_USER_PRIORITIES; i++)
4680                         dcb_info->prio_tc[i] = rx_conf->dcb_tc[i];
4681                 if (dcb_info->nb_tcs == ETH_4_TCS) {
4682                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4683                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 32;
4684                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4685                         }
4686                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4687                         dcb_info->tc_queue.tc_txq[0][1].base = 64;
4688                         dcb_info->tc_queue.tc_txq[0][2].base = 96;
4689                         dcb_info->tc_queue.tc_txq[0][3].base = 112;
4690                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 64;
4691                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4692                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4693                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4694                 } else if (dcb_info->nb_tcs == ETH_8_TCS) {
4695                         for (i = 0; i < dcb_info->nb_tcs; i++) {
4696                                 dcb_info->tc_queue.tc_rxq[0][i].base = i * 16;
4697                                 dcb_info->tc_queue.tc_rxq[0][i].nb_queue = 16;
4698                         }
4699                         dcb_info->tc_queue.tc_txq[0][0].base = 0;
4700                         dcb_info->tc_queue.tc_txq[0][1].base = 32;
4701                         dcb_info->tc_queue.tc_txq[0][2].base = 64;
4702                         dcb_info->tc_queue.tc_txq[0][3].base = 80;
4703                         dcb_info->tc_queue.tc_txq[0][4].base = 96;
4704                         dcb_info->tc_queue.tc_txq[0][5].base = 104;
4705                         dcb_info->tc_queue.tc_txq[0][6].base = 112;
4706                         dcb_info->tc_queue.tc_txq[0][7].base = 120;
4707                         dcb_info->tc_queue.tc_txq[0][0].nb_queue = 32;
4708                         dcb_info->tc_queue.tc_txq[0][1].nb_queue = 32;
4709                         dcb_info->tc_queue.tc_txq[0][2].nb_queue = 16;
4710                         dcb_info->tc_queue.tc_txq[0][3].nb_queue = 16;
4711                         dcb_info->tc_queue.tc_txq[0][4].nb_queue = 8;
4712                         dcb_info->tc_queue.tc_txq[0][5].nb_queue = 8;
4713                         dcb_info->tc_queue.tc_txq[0][6].nb_queue = 8;
4714                         dcb_info->tc_queue.tc_txq[0][7].nb_queue = 8;
4715                 }
4716         }
4717         for (i = 0; i < dcb_info->nb_tcs; i++) {
4718                 tc = &dcb_config->tc_config[i];
4719                 dcb_info->tc_bws[i] = tc->path[TXGBE_DCB_TX_CONFIG].bwg_percent;
4720         }
4721         return 0;
4722 }
4723
4724 /* Update e-tag ether type */
4725 static int
4726 txgbe_update_e_tag_eth_type(struct txgbe_hw *hw,
4727                             uint16_t ether_type)
4728 {
4729         uint32_t etag_etype;
4730
4731         etag_etype = rd32(hw, TXGBE_EXTAG);
4732         etag_etype &= ~TXGBE_EXTAG_ETAG_MASK;
4733         etag_etype |= ether_type;
4734         wr32(hw, TXGBE_EXTAG, etag_etype);
4735         txgbe_flush(hw);
4736
4737         return 0;
4738 }
4739
4740 /* Enable e-tag tunnel */
4741 static int
4742 txgbe_e_tag_enable(struct txgbe_hw *hw)
4743 {
4744         uint32_t etag_etype;
4745
4746         etag_etype = rd32(hw, TXGBE_PORTCTL);
4747         etag_etype |= TXGBE_PORTCTL_ETAG;
4748         wr32(hw, TXGBE_PORTCTL, etag_etype);
4749         txgbe_flush(hw);
4750
4751         return 0;
4752 }
4753
4754 static int
4755 txgbe_e_tag_filter_del(struct rte_eth_dev *dev,
4756                        struct txgbe_l2_tunnel_conf  *l2_tunnel)
4757 {
4758         int ret = 0;
4759         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4760         uint32_t i, rar_entries;
4761         uint32_t rar_low, rar_high;
4762
4763         rar_entries = hw->mac.num_rar_entries;
4764
4765         for (i = 1; i < rar_entries; i++) {
4766                 wr32(hw, TXGBE_ETHADDRIDX, i);
4767                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4768                 rar_low  = rd32(hw, TXGBE_ETHADDRL);
4769                 if ((rar_high & TXGBE_ETHADDRH_VLD) &&
4770                     (rar_high & TXGBE_ETHADDRH_ETAG) &&
4771                     (TXGBE_ETHADDRL_ETAG(rar_low) ==
4772                      l2_tunnel->tunnel_id)) {
4773                         wr32(hw, TXGBE_ETHADDRL, 0);
4774                         wr32(hw, TXGBE_ETHADDRH, 0);
4775
4776                         txgbe_clear_vmdq(hw, i, BIT_MASK32);
4777
4778                         return ret;
4779                 }
4780         }
4781
4782         return ret;
4783 }
4784
4785 static int
4786 txgbe_e_tag_filter_add(struct rte_eth_dev *dev,
4787                        struct txgbe_l2_tunnel_conf *l2_tunnel)
4788 {
4789         int ret = 0;
4790         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4791         uint32_t i, rar_entries;
4792         uint32_t rar_low, rar_high;
4793
4794         /* One entry for one tunnel. Try to remove potential existing entry. */
4795         txgbe_e_tag_filter_del(dev, l2_tunnel);
4796
4797         rar_entries = hw->mac.num_rar_entries;
4798
4799         for (i = 1; i < rar_entries; i++) {
4800                 wr32(hw, TXGBE_ETHADDRIDX, i);
4801                 rar_high = rd32(hw, TXGBE_ETHADDRH);
4802                 if (rar_high & TXGBE_ETHADDRH_VLD) {
4803                         continue;
4804                 } else {
4805                         txgbe_set_vmdq(hw, i, l2_tunnel->pool);
4806                         rar_high = TXGBE_ETHADDRH_VLD | TXGBE_ETHADDRH_ETAG;
4807                         rar_low = l2_tunnel->tunnel_id;
4808
4809                         wr32(hw, TXGBE_ETHADDRL, rar_low);
4810                         wr32(hw, TXGBE_ETHADDRH, rar_high);
4811
4812                         return ret;
4813                 }
4814         }
4815
4816         PMD_INIT_LOG(NOTICE, "The table of E-tag forwarding rule is full."
4817                      " Please remove a rule before adding a new one.");
4818         return -EINVAL;
4819 }
4820
4821 static inline struct txgbe_l2_tn_filter *
4822 txgbe_l2_tn_filter_lookup(struct txgbe_l2_tn_info *l2_tn_info,
4823                           struct txgbe_l2_tn_key *key)
4824 {
4825         int ret;
4826
4827         ret = rte_hash_lookup(l2_tn_info->hash_handle, (const void *)key);
4828         if (ret < 0)
4829                 return NULL;
4830
4831         return l2_tn_info->hash_map[ret];
4832 }
4833
4834 static inline int
4835 txgbe_insert_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4836                           struct txgbe_l2_tn_filter *l2_tn_filter)
4837 {
4838         int ret;
4839
4840         ret = rte_hash_add_key(l2_tn_info->hash_handle,
4841                                &l2_tn_filter->key);
4842
4843         if (ret < 0) {
4844                 PMD_DRV_LOG(ERR,
4845                             "Failed to insert L2 tunnel filter"
4846                             " to hash table %d!",
4847                             ret);
4848                 return ret;
4849         }
4850
4851         l2_tn_info->hash_map[ret] = l2_tn_filter;
4852
4853         TAILQ_INSERT_TAIL(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4854
4855         return 0;
4856 }
4857
4858 static inline int
4859 txgbe_remove_l2_tn_filter(struct txgbe_l2_tn_info *l2_tn_info,
4860                           struct txgbe_l2_tn_key *key)
4861 {
4862         int ret;
4863         struct txgbe_l2_tn_filter *l2_tn_filter;
4864
4865         ret = rte_hash_del_key(l2_tn_info->hash_handle, key);
4866
4867         if (ret < 0) {
4868                 PMD_DRV_LOG(ERR,
4869                             "No such L2 tunnel filter to delete %d!",
4870                             ret);
4871                 return ret;
4872         }
4873
4874         l2_tn_filter = l2_tn_info->hash_map[ret];
4875         l2_tn_info->hash_map[ret] = NULL;
4876
4877         TAILQ_REMOVE(&l2_tn_info->l2_tn_list, l2_tn_filter, entries);
4878         rte_free(l2_tn_filter);
4879
4880         return 0;
4881 }
4882
4883 /* Add l2 tunnel filter */
4884 int
4885 txgbe_dev_l2_tunnel_filter_add(struct rte_eth_dev *dev,
4886                                struct txgbe_l2_tunnel_conf *l2_tunnel,
4887                                bool restore)
4888 {
4889         int ret;
4890         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4891         struct txgbe_l2_tn_key key;
4892         struct txgbe_l2_tn_filter *node;
4893
4894         if (!restore) {
4895                 key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4896                 key.tn_id = l2_tunnel->tunnel_id;
4897
4898                 node = txgbe_l2_tn_filter_lookup(l2_tn_info, &key);
4899
4900                 if (node) {
4901                         PMD_DRV_LOG(ERR,
4902                                     "The L2 tunnel filter already exists!");
4903                         return -EINVAL;
4904                 }
4905
4906                 node = rte_zmalloc("txgbe_l2_tn",
4907                                    sizeof(struct txgbe_l2_tn_filter),
4908                                    0);
4909                 if (!node)
4910                         return -ENOMEM;
4911
4912                 rte_memcpy(&node->key,
4913                                  &key,
4914                                  sizeof(struct txgbe_l2_tn_key));
4915                 node->pool = l2_tunnel->pool;
4916                 ret = txgbe_insert_l2_tn_filter(l2_tn_info, node);
4917                 if (ret < 0) {
4918                         rte_free(node);
4919                         return ret;
4920                 }
4921         }
4922
4923         switch (l2_tunnel->l2_tunnel_type) {
4924         case RTE_L2_TUNNEL_TYPE_E_TAG:
4925                 ret = txgbe_e_tag_filter_add(dev, l2_tunnel);
4926                 break;
4927         default:
4928                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4929                 ret = -EINVAL;
4930                 break;
4931         }
4932
4933         if (!restore && ret < 0)
4934                 (void)txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4935
4936         return ret;
4937 }
4938
4939 /* Delete l2 tunnel filter */
4940 int
4941 txgbe_dev_l2_tunnel_filter_del(struct rte_eth_dev *dev,
4942                                struct txgbe_l2_tunnel_conf *l2_tunnel)
4943 {
4944         int ret;
4945         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
4946         struct txgbe_l2_tn_key key;
4947
4948         key.l2_tn_type = l2_tunnel->l2_tunnel_type;
4949         key.tn_id = l2_tunnel->tunnel_id;
4950         ret = txgbe_remove_l2_tn_filter(l2_tn_info, &key);
4951         if (ret < 0)
4952                 return ret;
4953
4954         switch (l2_tunnel->l2_tunnel_type) {
4955         case RTE_L2_TUNNEL_TYPE_E_TAG:
4956                 ret = txgbe_e_tag_filter_del(dev, l2_tunnel);
4957                 break;
4958         default:
4959                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
4960                 ret = -EINVAL;
4961                 break;
4962         }
4963
4964         return ret;
4965 }
4966
4967 static int
4968 txgbe_e_tag_forwarding_en_dis(struct rte_eth_dev *dev, bool en)
4969 {
4970         int ret = 0;
4971         uint32_t ctrl;
4972         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4973
4974         ctrl = rd32(hw, TXGBE_POOLCTL);
4975         ctrl &= ~TXGBE_POOLCTL_MODE_MASK;
4976         if (en)
4977                 ctrl |= TXGBE_PSRPOOL_MODE_ETAG;
4978         wr32(hw, TXGBE_POOLCTL, ctrl);
4979
4980         return ret;
4981 }
4982
4983 /* Add UDP tunneling port */
4984 static int
4985 txgbe_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
4986                               struct rte_eth_udp_tunnel *udp_tunnel)
4987 {
4988         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
4989         int ret = 0;
4990
4991         if (udp_tunnel == NULL)
4992                 return -EINVAL;
4993
4994         switch (udp_tunnel->prot_type) {
4995         case RTE_TUNNEL_TYPE_VXLAN:
4996                 if (udp_tunnel->udp_port == 0) {
4997                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
4998                         ret = -EINVAL;
4999                         break;
5000                 }
5001                 wr32(hw, TXGBE_VXLANPORT, udp_tunnel->udp_port);
5002                 break;
5003         case RTE_TUNNEL_TYPE_GENEVE:
5004                 if (udp_tunnel->udp_port == 0) {
5005                         PMD_DRV_LOG(ERR, "Add Geneve port 0 is not allowed.");
5006                         ret = -EINVAL;
5007                         break;
5008                 }
5009                 wr32(hw, TXGBE_GENEVEPORT, udp_tunnel->udp_port);
5010                 break;
5011         case RTE_TUNNEL_TYPE_TEREDO:
5012                 if (udp_tunnel->udp_port == 0) {
5013                         PMD_DRV_LOG(ERR, "Add Teredo port 0 is not allowed.");
5014                         ret = -EINVAL;
5015                         break;
5016                 }
5017                 wr32(hw, TXGBE_TEREDOPORT, udp_tunnel->udp_port);
5018                 break;
5019         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5020                 if (udp_tunnel->udp_port == 0) {
5021                         PMD_DRV_LOG(ERR, "Add VxLAN port 0 is not allowed.");
5022                         ret = -EINVAL;
5023                         break;
5024                 }
5025                 wr32(hw, TXGBE_VXLANPORTGPE, udp_tunnel->udp_port);
5026                 break;
5027         default:
5028                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5029                 ret = -EINVAL;
5030                 break;
5031         }
5032
5033         txgbe_flush(hw);
5034
5035         return ret;
5036 }
5037
5038 /* Remove UDP tunneling port */
5039 static int
5040 txgbe_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5041                               struct rte_eth_udp_tunnel *udp_tunnel)
5042 {
5043         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5044         int ret = 0;
5045         uint16_t cur_port;
5046
5047         if (udp_tunnel == NULL)
5048                 return -EINVAL;
5049
5050         switch (udp_tunnel->prot_type) {
5051         case RTE_TUNNEL_TYPE_VXLAN:
5052                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORT);
5053                 if (cur_port != udp_tunnel->udp_port) {
5054                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5055                                         udp_tunnel->udp_port);
5056                         ret = -EINVAL;
5057                         break;
5058                 }
5059                 wr32(hw, TXGBE_VXLANPORT, 0);
5060                 break;
5061         case RTE_TUNNEL_TYPE_GENEVE:
5062                 cur_port = (uint16_t)rd32(hw, TXGBE_GENEVEPORT);
5063                 if (cur_port != udp_tunnel->udp_port) {
5064                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5065                                         udp_tunnel->udp_port);
5066                         ret = -EINVAL;
5067                         break;
5068                 }
5069                 wr32(hw, TXGBE_GENEVEPORT, 0);
5070                 break;
5071         case RTE_TUNNEL_TYPE_TEREDO:
5072                 cur_port = (uint16_t)rd32(hw, TXGBE_TEREDOPORT);
5073                 if (cur_port != udp_tunnel->udp_port) {
5074                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5075                                         udp_tunnel->udp_port);
5076                         ret = -EINVAL;
5077                         break;
5078                 }
5079                 wr32(hw, TXGBE_TEREDOPORT, 0);
5080                 break;
5081         case RTE_TUNNEL_TYPE_VXLAN_GPE:
5082                 cur_port = (uint16_t)rd32(hw, TXGBE_VXLANPORTGPE);
5083                 if (cur_port != udp_tunnel->udp_port) {
5084                         PMD_DRV_LOG(ERR, "Port %u does not exist.",
5085                                         udp_tunnel->udp_port);
5086                         ret = -EINVAL;
5087                         break;
5088                 }
5089                 wr32(hw, TXGBE_VXLANPORTGPE, 0);
5090                 break;
5091         default:
5092                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5093                 ret = -EINVAL;
5094                 break;
5095         }
5096
5097         txgbe_flush(hw);
5098
5099         return ret;
5100 }
5101
5102 /* restore n-tuple filter */
5103 static inline void
5104 txgbe_ntuple_filter_restore(struct rte_eth_dev *dev)
5105 {
5106         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5107         struct txgbe_5tuple_filter *node;
5108
5109         TAILQ_FOREACH(node, &filter_info->fivetuple_list, entries) {
5110                 txgbe_inject_5tuple_filter(dev, node);
5111         }
5112 }
5113
5114 /* restore ethernet type filter */
5115 static inline void
5116 txgbe_ethertype_filter_restore(struct rte_eth_dev *dev)
5117 {
5118         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5119         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5120         int i;
5121
5122         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5123                 if (filter_info->ethertype_mask & (1 << i)) {
5124                         wr32(hw, TXGBE_ETFLT(i),
5125                                         filter_info->ethertype_filters[i].etqf);
5126                         wr32(hw, TXGBE_ETCLS(i),
5127                                         filter_info->ethertype_filters[i].etqs);
5128                         txgbe_flush(hw);
5129                 }
5130         }
5131 }
5132
5133 /* restore SYN filter */
5134 static inline void
5135 txgbe_syn_filter_restore(struct rte_eth_dev *dev)
5136 {
5137         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5138         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5139         uint32_t synqf;
5140
5141         synqf = filter_info->syn_info;
5142
5143         if (synqf & TXGBE_SYNCLS_ENA) {
5144                 wr32(hw, TXGBE_SYNCLS, synqf);
5145                 txgbe_flush(hw);
5146         }
5147 }
5148
5149 /* restore L2 tunnel filter */
5150 static inline void
5151 txgbe_l2_tn_filter_restore(struct rte_eth_dev *dev)
5152 {
5153         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5154         struct txgbe_l2_tn_filter *node;
5155         struct txgbe_l2_tunnel_conf l2_tn_conf;
5156
5157         TAILQ_FOREACH(node, &l2_tn_info->l2_tn_list, entries) {
5158                 l2_tn_conf.l2_tunnel_type = node->key.l2_tn_type;
5159                 l2_tn_conf.tunnel_id      = node->key.tn_id;
5160                 l2_tn_conf.pool           = node->pool;
5161                 (void)txgbe_dev_l2_tunnel_filter_add(dev, &l2_tn_conf, TRUE);
5162         }
5163 }
5164
5165 /* restore rss filter */
5166 static inline void
5167 txgbe_rss_filter_restore(struct rte_eth_dev *dev)
5168 {
5169         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5170
5171         if (filter_info->rss_info.conf.queue_num)
5172                 txgbe_config_rss_filter(dev,
5173                         &filter_info->rss_info, TRUE);
5174 }
5175
5176 static int
5177 txgbe_filter_restore(struct rte_eth_dev *dev)
5178 {
5179         txgbe_ntuple_filter_restore(dev);
5180         txgbe_ethertype_filter_restore(dev);
5181         txgbe_syn_filter_restore(dev);
5182         txgbe_fdir_filter_restore(dev);
5183         txgbe_l2_tn_filter_restore(dev);
5184         txgbe_rss_filter_restore(dev);
5185
5186         return 0;
5187 }
5188
5189 static void
5190 txgbe_l2_tunnel_conf(struct rte_eth_dev *dev)
5191 {
5192         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5193         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5194
5195         if (l2_tn_info->e_tag_en)
5196                 (void)txgbe_e_tag_enable(hw);
5197
5198         if (l2_tn_info->e_tag_fwd_en)
5199                 (void)txgbe_e_tag_forwarding_en_dis(dev, 1);
5200
5201         (void)txgbe_update_e_tag_eth_type(hw, l2_tn_info->e_tag_ether_type);
5202 }
5203
5204 /* remove all the n-tuple filters */
5205 void
5206 txgbe_clear_all_ntuple_filter(struct rte_eth_dev *dev)
5207 {
5208         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5209         struct txgbe_5tuple_filter *p_5tuple;
5210
5211         while ((p_5tuple = TAILQ_FIRST(&filter_info->fivetuple_list)))
5212                 txgbe_remove_5tuple_filter(dev, p_5tuple);
5213 }
5214
5215 /* remove all the ether type filters */
5216 void
5217 txgbe_clear_all_ethertype_filter(struct rte_eth_dev *dev)
5218 {
5219         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5220         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5221         int i;
5222
5223         for (i = 0; i < TXGBE_ETF_ID_MAX; i++) {
5224                 if (filter_info->ethertype_mask & (1 << i) &&
5225                     !filter_info->ethertype_filters[i].conf) {
5226                         (void)txgbe_ethertype_filter_remove(filter_info,
5227                                                             (uint8_t)i);
5228                         wr32(hw, TXGBE_ETFLT(i), 0);
5229                         wr32(hw, TXGBE_ETCLS(i), 0);
5230                         txgbe_flush(hw);
5231                 }
5232         }
5233 }
5234
5235 /* remove the SYN filter */
5236 void
5237 txgbe_clear_syn_filter(struct rte_eth_dev *dev)
5238 {
5239         struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
5240         struct txgbe_filter_info *filter_info = TXGBE_DEV_FILTER(dev);
5241
5242         if (filter_info->syn_info & TXGBE_SYNCLS_ENA) {
5243                 filter_info->syn_info = 0;
5244
5245                 wr32(hw, TXGBE_SYNCLS, 0);
5246                 txgbe_flush(hw);
5247         }
5248 }
5249
5250 /* remove all the L2 tunnel filters */
5251 int
5252 txgbe_clear_all_l2_tn_filter(struct rte_eth_dev *dev)
5253 {
5254         struct txgbe_l2_tn_info *l2_tn_info = TXGBE_DEV_L2_TN(dev);
5255         struct txgbe_l2_tn_filter *l2_tn_filter;
5256         struct txgbe_l2_tunnel_conf l2_tn_conf;
5257         int ret = 0;
5258
5259         while ((l2_tn_filter = TAILQ_FIRST(&l2_tn_info->l2_tn_list))) {
5260                 l2_tn_conf.l2_tunnel_type = l2_tn_filter->key.l2_tn_type;
5261                 l2_tn_conf.tunnel_id      = l2_tn_filter->key.tn_id;
5262                 l2_tn_conf.pool           = l2_tn_filter->pool;
5263                 ret = txgbe_dev_l2_tunnel_filter_del(dev, &l2_tn_conf);
5264                 if (ret < 0)
5265                         return ret;
5266         }
5267
5268         return 0;
5269 }
5270
5271 static const struct eth_dev_ops txgbe_eth_dev_ops = {
5272         .dev_configure              = txgbe_dev_configure,
5273         .dev_infos_get              = txgbe_dev_info_get,
5274         .dev_start                  = txgbe_dev_start,
5275         .dev_stop                   = txgbe_dev_stop,
5276         .dev_set_link_up            = txgbe_dev_set_link_up,
5277         .dev_set_link_down          = txgbe_dev_set_link_down,
5278         .dev_close                  = txgbe_dev_close,
5279         .dev_reset                  = txgbe_dev_reset,
5280         .promiscuous_enable         = txgbe_dev_promiscuous_enable,
5281         .promiscuous_disable        = txgbe_dev_promiscuous_disable,
5282         .allmulticast_enable        = txgbe_dev_allmulticast_enable,
5283         .allmulticast_disable       = txgbe_dev_allmulticast_disable,
5284         .link_update                = txgbe_dev_link_update,
5285         .stats_get                  = txgbe_dev_stats_get,
5286         .xstats_get                 = txgbe_dev_xstats_get,
5287         .xstats_get_by_id           = txgbe_dev_xstats_get_by_id,
5288         .stats_reset                = txgbe_dev_stats_reset,
5289         .xstats_reset               = txgbe_dev_xstats_reset,
5290         .xstats_get_names           = txgbe_dev_xstats_get_names,
5291         .xstats_get_names_by_id     = txgbe_dev_xstats_get_names_by_id,
5292         .queue_stats_mapping_set    = txgbe_dev_queue_stats_mapping_set,
5293         .fw_version_get             = txgbe_fw_version_get,
5294         .dev_supported_ptypes_get   = txgbe_dev_supported_ptypes_get,
5295         .mtu_set                    = txgbe_dev_mtu_set,
5296         .vlan_filter_set            = txgbe_vlan_filter_set,
5297         .vlan_tpid_set              = txgbe_vlan_tpid_set,
5298         .vlan_offload_set           = txgbe_vlan_offload_set,
5299         .vlan_strip_queue_set       = txgbe_vlan_strip_queue_set,
5300         .rx_queue_start             = txgbe_dev_rx_queue_start,
5301         .rx_queue_stop              = txgbe_dev_rx_queue_stop,
5302         .tx_queue_start             = txgbe_dev_tx_queue_start,
5303         .tx_queue_stop              = txgbe_dev_tx_queue_stop,
5304         .rx_queue_setup             = txgbe_dev_rx_queue_setup,
5305         .rx_queue_intr_enable       = txgbe_dev_rx_queue_intr_enable,
5306         .rx_queue_intr_disable      = txgbe_dev_rx_queue_intr_disable,
5307         .rx_queue_release           = txgbe_dev_rx_queue_release,
5308         .tx_queue_setup             = txgbe_dev_tx_queue_setup,
5309         .tx_queue_release           = txgbe_dev_tx_queue_release,
5310         .dev_led_on                 = txgbe_dev_led_on,
5311         .dev_led_off                = txgbe_dev_led_off,
5312         .flow_ctrl_get              = txgbe_flow_ctrl_get,
5313         .flow_ctrl_set              = txgbe_flow_ctrl_set,
5314         .priority_flow_ctrl_set     = txgbe_priority_flow_ctrl_set,
5315         .mac_addr_add               = txgbe_add_rar,
5316         .mac_addr_remove            = txgbe_remove_rar,
5317         .mac_addr_set               = txgbe_set_default_mac_addr,
5318         .uc_hash_table_set          = txgbe_uc_hash_table_set,
5319         .uc_all_hash_table_set      = txgbe_uc_all_hash_table_set,
5320         .set_queue_rate_limit       = txgbe_set_queue_rate_limit,
5321         .reta_update                = txgbe_dev_rss_reta_update,
5322         .reta_query                 = txgbe_dev_rss_reta_query,
5323         .rss_hash_update            = txgbe_dev_rss_hash_update,
5324         .rss_hash_conf_get          = txgbe_dev_rss_hash_conf_get,
5325         .flow_ops_get               = txgbe_dev_flow_ops_get,
5326         .set_mc_addr_list           = txgbe_dev_set_mc_addr_list,
5327         .rxq_info_get               = txgbe_rxq_info_get,
5328         .txq_info_get               = txgbe_txq_info_get,
5329         .timesync_enable            = txgbe_timesync_enable,
5330         .timesync_disable           = txgbe_timesync_disable,
5331         .timesync_read_rx_timestamp = txgbe_timesync_read_rx_timestamp,
5332         .timesync_read_tx_timestamp = txgbe_timesync_read_tx_timestamp,
5333         .get_reg                    = txgbe_get_regs,
5334         .get_eeprom_length          = txgbe_get_eeprom_length,
5335         .get_eeprom                 = txgbe_get_eeprom,
5336         .set_eeprom                 = txgbe_set_eeprom,
5337         .get_module_info            = txgbe_get_module_info,
5338         .get_module_eeprom          = txgbe_get_module_eeprom,
5339         .get_dcb_info               = txgbe_dev_get_dcb_info,
5340         .timesync_adjust_time       = txgbe_timesync_adjust_time,
5341         .timesync_read_time         = txgbe_timesync_read_time,
5342         .timesync_write_time        = txgbe_timesync_write_time,
5343         .udp_tunnel_port_add        = txgbe_dev_udp_tunnel_port_add,
5344         .udp_tunnel_port_del        = txgbe_dev_udp_tunnel_port_del,
5345         .tm_ops_get                 = txgbe_tm_ops_get,
5346         .tx_done_cleanup            = txgbe_dev_tx_done_cleanup,
5347 };
5348
5349 RTE_PMD_REGISTER_PCI(net_txgbe, rte_txgbe_pmd);
5350 RTE_PMD_REGISTER_PCI_TABLE(net_txgbe, pci_id_txgbe_map);
5351 RTE_PMD_REGISTER_KMOD_DEP(net_txgbe, "* igb_uio | uio_pci_generic | vfio-pci");
5352 RTE_PMD_REGISTER_PARAM_STRING(net_txgbe,
5353                               TXGBE_DEVARG_BP_AUTO "=<0|1>"
5354                               TXGBE_DEVARG_KR_POLL "=<0|1>"
5355                               TXGBE_DEVARG_KR_PRESENT "=<0|1>"
5356                               TXGBE_DEVARG_KX_SGMII "=<0|1>"
5357                               TXGBE_DEVARG_FFE_SET "=<0-4>"
5358                               TXGBE_DEVARG_FFE_MAIN "=<uint16>"
5359                               TXGBE_DEVARG_FFE_PRE "=<uint16>"
5360                               TXGBE_DEVARG_FFE_POST "=<uint16>");
5361
5362 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_init, init, NOTICE);
5363 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_driver, driver, NOTICE);
5364 RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_bp, bp, NOTICE);
5365
5366 #ifdef RTE_LIBRTE_TXGBE_DEBUG_RX
5367         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_rx, rx, DEBUG);
5368 #endif
5369 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX
5370         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx, tx, DEBUG);
5371 #endif
5372
5373 #ifdef RTE_LIBRTE_TXGBE_DEBUG_TX_FREE
5374         RTE_LOG_REGISTER_SUFFIX(txgbe_logtype_tx_free, tx_free, DEBUG);
5375 #endif