drivers/net/vmxnet3/vmxnet3_ethdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2014 Intel Corporation
   3  */
   4
   5 #ifndef _VMXNET3_ETHDEV_H_
   6 #define _VMXNET3_ETHDEV_H_
   7
   8 #include <rte_io.h>
   9
  10 #define VMXNET3_MAX_MAC_ADDRS 1
  11
  12 /* UPT feature to negotiate */
  13 #define VMXNET3_F_RXCSUM      0x0001
  14 #define VMXNET3_F_RSS         0x0002
  15 #define VMXNET3_F_RXVLAN      0x0004
  16 #define VMXNET3_F_LRO         0x0008
  17
  18 /* Hash Types supported by device */
  19 #define VMXNET3_RSS_HASH_TYPE_NONE      0x0
  20 #define VMXNET3_RSS_HASH_TYPE_IPV4      0x01
  21 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV4  0x02
  22 #define VMXNET3_RSS_HASH_TYPE_IPV6      0x04
  23 #define VMXNET3_RSS_HASH_TYPE_TCP_IPV6  0x08
  24
  25 #define VMXNET3_RSS_HASH_FUNC_NONE      0x0
  26 #define VMXNET3_RSS_HASH_FUNC_TOEPLITZ  0x01
  27
  28 #define VMXNET3_RSS_MAX_KEY_SIZE        40
  29 #define VMXNET3_RSS_MAX_IND_TABLE_SIZE  128
  30
  31 #define VMXNET3_RSS_OFFLOAD_ALL ( \
  32         ETH_RSS_IPV4 | \
  33         ETH_RSS_NONFRAG_IPV4_TCP | \
  34         ETH_RSS_IPV6 | \
  35         ETH_RSS_NONFRAG_IPV6_TCP)
  36
  37 #define VMXNET3_V4_RSS_MASK ( \
  38         ETH_RSS_NONFRAG_IPV4_UDP | \
  39         ETH_RSS_NONFRAG_IPV6_UDP)
  40
  41 /* RSS configuration structure - shared with device through GPA */
  42 typedef struct VMXNET3_RSSConf {
  43         uint16_t   hashType;
  44         uint16_t   hashFunc;
  45         uint16_t   hashKeySize;
  46         uint16_t   indTableSize;
  47         uint8_t    hashKey[VMXNET3_RSS_MAX_KEY_SIZE];
  48         /*
  49          * indTable is only element that can be changed without
  50          * device quiesce-reset-update-activation cycle
  51          */
  52         uint8_t    indTable[VMXNET3_RSS_MAX_IND_TABLE_SIZE];
  53 } VMXNET3_RSSConf;
  54
  55 typedef struct vmxnet3_mf_table {
  56         void          *mfTableBase; /* Multicast addresses list */
  57         uint64_t      mfTablePA;    /* Physical address of the list */
  58         uint16_t      num_addrs;    /* number of multicast addrs */
  59 } vmxnet3_mf_table_t;
  60
  61 struct vmxnet3_hw {
  62         uint8_t *hw_addr0;      /* BAR0: PT-Passthrough Regs    */
  63         uint8_t *hw_addr1;      /* BAR1: VD-Virtual Device Regs */
  64         /* BAR2: MSI-X Regs */
  65         /* BAR3: Port IO    */
  66         void *back;
  67
  68         uint16_t device_id;
  69         uint16_t vendor_id;
  70         uint16_t subsystem_device_id;
  71         uint16_t subsystem_vendor_id;
  72         bool adapter_stopped;
  73
  74         uint8_t perm_addr[RTE_ETHER_ADDR_LEN];
  75         uint8_t num_tx_queues;
  76         uint8_t num_rx_queues;
  77         uint8_t bufs_per_pkt;
  78
  79         uint8_t version;
  80
  81         uint16_t txdata_desc_size; /* tx data ring buffer size */
  82         uint16_t rxdata_desc_size; /* rx data ring buffer size */
  83
  84         uint8_t num_intrs;
  85
  86         Vmxnet3_TxQueueDesc   *tqd_start;       /* start address of all tx queue desc */
  87         Vmxnet3_RxQueueDesc   *rqd_start;       /* start address of all rx queue desc */
  88
  89         Vmxnet3_DriverShared  *shared;
  90         uint64_t              sharedPA;
  91
  92         uint64_t              queueDescPA;
  93         uint16_t              queue_desc_len;
  94         uint16_t              mtu;
  95
  96         VMXNET3_RSSConf       *rss_conf;
  97         uint64_t              rss_confPA;
  98         vmxnet3_mf_table_t    *mf_table;
  99         uint32_t              shadow_vfta[VMXNET3_VFT_SIZE];
 100         Vmxnet3_MemRegs       *memRegs;
 101         uint64_t              memRegsPA;
 102 #define VMXNET3_VFT_TABLE_SIZE     (VMXNET3_VFT_SIZE * sizeof(uint32_t))
 103         UPT1_TxStats          saved_tx_stats[VMXNET3_MAX_TX_QUEUES];
 104         UPT1_RxStats          saved_rx_stats[VMXNET3_MAX_RX_QUEUES];
 105
 106         UPT1_TxStats          snapshot_tx_stats[VMXNET3_MAX_TX_QUEUES];
 107         UPT1_RxStats          snapshot_rx_stats[VMXNET3_MAX_RX_QUEUES];
 108 };
 109
 110 #define VMXNET3_REV_4           3               /* Vmxnet3 Rev. 4 */
 111 #define VMXNET3_REV_3           2               /* Vmxnet3 Rev. 3 */
 112 #define VMXNET3_REV_2           1               /* Vmxnet3 Rev. 2 */
 113 #define VMXNET3_REV_1           0               /* Vmxnet3 Rev. 1 */
 114
 115 #define VMXNET3_VERSION_GE_4(hw) ((hw)->version >= VMXNET3_REV_4 + 1)
 116 #define VMXNET3_VERSION_GE_3(hw) ((hw)->version >= VMXNET3_REV_3 + 1)
 117 #define VMXNET3_VERSION_GE_2(hw) ((hw)->version >= VMXNET3_REV_2 + 1)
 118
 119 #define VMXNET3_GET_ADDR_LO(reg)   ((uint32_t)(reg))
 120 #define VMXNET3_GET_ADDR_HI(reg)   ((uint32_t)(((uint64_t)(reg)) >> 32))
 121
 122 /* Config space read/writes */
 123
 124 #define VMXNET3_PCI_REG(reg) rte_read32(reg)
 125
 126 static inline uint32_t
 127 vmxnet3_read_addr(volatile void *addr)
 128 {
 129         return VMXNET3_PCI_REG(addr);
 130 }
 131
 132 #define VMXNET3_PCI_REG_WRITE(reg, value) rte_write32((value), (reg))
 133
 134 #define VMXNET3_PCI_BAR0_REG_ADDR(hw, reg) \
 135         ((volatile uint32_t *)((char *)(hw)->hw_addr0 + (reg)))
 136 #define VMXNET3_READ_BAR0_REG(hw, reg) \
 137         vmxnet3_read_addr(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)))
 138 #define VMXNET3_WRITE_BAR0_REG(hw, reg, value) \
 139         VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR0_REG_ADDR((hw), (reg)), (value))
 140
 141 #define VMXNET3_PCI_BAR1_REG_ADDR(hw, reg) \
 142         ((volatile uint32_t *)((char *)(hw)->hw_addr1 + (reg)))
 143 #define VMXNET3_READ_BAR1_REG(hw, reg) \
 144         vmxnet3_read_addr(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)))
 145 #define VMXNET3_WRITE_BAR1_REG(hw, reg, value) \
 146         VMXNET3_PCI_REG_WRITE(VMXNET3_PCI_BAR1_REG_ADDR((hw), (reg)), (value))
 147
 148 static inline uint8_t
 149 vmxnet3_get_ring_idx(struct vmxnet3_hw *hw, uint32 rqID)
 150 {
 151         return (rqID >= hw->num_rx_queues &&
 152                 rqID < 2 * hw->num_rx_queues) ? 1 : 0;
 153 }
 154
 155 static inline bool
 156 vmxnet3_rx_data_ring(struct vmxnet3_hw *hw, uint32 rqID)
 157 {
 158         return (rqID >= 2 * hw->num_rx_queues &&
 159                 rqID < 3 * hw->num_rx_queues);
 160 }
 161
 162 /*
 163  * RX/TX function prototypes
 164  */
 165
 166 void vmxnet3_dev_clear_queues(struct rte_eth_dev *dev);
 167
 168 void vmxnet3_dev_rx_queue_release(void *rxq);
 169 void vmxnet3_dev_tx_queue_release(void *txq);
 170
 171 int vmxnet3_v4_rss_configure(struct rte_eth_dev *dev);
 172
 173 int  vmxnet3_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
 174                                 uint16_t nb_rx_desc, unsigned int socket_id,
 175                                 const struct rte_eth_rxconf *rx_conf,
 176                                 struct rte_mempool *mb_pool);
 177 int  vmxnet3_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
 178                                 uint16_t nb_tx_desc, unsigned int socket_id,
 179                                 const struct rte_eth_txconf *tx_conf);
 180
 181 int vmxnet3_dev_rxtx_init(struct rte_eth_dev *dev);
 182
 183 int vmxnet3_rss_configure(struct rte_eth_dev *dev);
 184
 185 uint16_t vmxnet3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
 186                            uint16_t nb_pkts);
 187 uint16_t vmxnet3_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 188                            uint16_t nb_pkts);
 189 uint16_t vmxnet3_prep_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
 190                         uint16_t nb_pkts);
 191
 192 #endif /* _VMXNET3_ETHDEV_H_ */